ECE 7250/4250 (328) Design of a Complicated Machine using SM Chart:

Digital Systems Design: State Machine Flow Chart

VHDL and PLD Acrobat Document

Components:
State box: Rectangular
Decision box: Diamond
Part 7: SM Chart, Conditional output box: Ellipse.
Microprogramming, Design of a
Game SM chart is equivalent to state transition
diagram.

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 SM Chart: Binary Multiplier
State Transition diagram and SM Chart: Acrobat Document

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SM Chart: Binary to BCD Converter
Design of a Complicated Machine using SM Chart:

Roll Dice game

Roll dice once,

Win: sum= 7 or 11
Lose: sum = 2 3 or 12

If sum does equal to any of those numbers,

Then memorize the sum and roll dice
again.
Win: sum equals the first sum
Lose: sum = 7
Roll dice until one either wins or loses.

Goal: to design a game machine

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 Design of a Complicated Machine using SM Chart:
Roll Dice game
Design of a Complicated Machine using SM Chart: Flow chart
Roll Dice game

Design steps:
1. Construct a flow chart for describing the
game.
2. Refine the flow chart into a SM chart
3. Use the SM chart to develop the VHDL
model.
4. Implement the model into digital
hardware.

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Design of a Complicated Machine using SM Chart: Design of a Complicated Machine using SM Chart:
Roll Dice game Roll Dice game
SM chart:
The flow chart shows the steps: Acrobat Document

Roll dice, compare the sum with numbers,

decide next step, …..

Refine into an SM chart:

Check each step in the flow chart, decide the
detail steps for each action, expand into SM
chart.

For example, for “roll the dice”, a push button is

required for implementation. At first, there
should be an IDLE state waiting for the button
to be pressed. Once it is detected, the machine
may send a “Roll” signal to two counters
simulating the dice. The signal will be stopped
when the pressed button is released.

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 Design of a Complicated Machine using SM Chart: Design of a Complicated Machine using SM Chart:
Roll Dice game Roll Dice game
Datapath
Necessary Conditions in the game:
reset Acrobat Document

Rb D711: Sum = 7 or 11
D2312: sum = 2, 3 or 12
Done Roll Counter (dice) Counter (dice) D7: Sum = 7
Win Eq: Sum = Point?
Lose Reset: Game been reset
Control Adder
section Other status (not explicit):
Point register
Rb: input signal for rolling the dice
Sp

Comparator to check “win” & “lose”

D7 Eq
D711 D2312

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SM Chart: One possible model:

Define control signals Adder and counters are outside of the model

Roll: internal signal to enable the counters

Sp: To store sum to point register
Counters and Adder

Other outputs: sum roll

Win:
Lose: Control section win
Rb (to be modelled)
lose
reset

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 VHDL Program for the Game (2-process model):
VHDL Program for the Game (2-process model):
entity DiceGame is when 2 => Win <= '1';
port (Rb, Reset, CLK: in bit; Sum: in integer if Reset = '1' then Nextstate <= 0; end if;
range 2 to 12; Roll, Win, Lose: out bit); when 3 => Lose <= '1';
end DiceGame; if Reset = '1' then Nextstate <= 0; end if;
when 4 => if Rb = '1' then Nextstate <= 5; end if;
library BITLIB; when 5 =>
use BITLIB.bit_pack.all; if Rb = '1' then Roll <= '1';
elsif Sum = Point then Nextstate <= 2;
architecture DiceBehave of DiceGame is elsif Sum = 7 then Nextstate <= 3;
signal State, Nextstate: integer range 0 to 5; else Nextstate <= 4;
signal Point: integer range 2 to 12; end if;
signal Sp: bit; end case;
begin end process;
process(Rb, Reset, Sum, State) process(CLK)
begin begin
______________________________________; if rising_edge(CLK) then
case State is State <= ______________;
when 0 => if Rb = '1' then Nextstate <= 1; end if; if _______________________; end if;
when 1 => if _________ then Roll <= '1'; end if;
elsif _________________ then Nextstate <= 2; end process;
elsif Sum = 2 or Sum = 3 or Sum =12 then end DiceBehave;
Nextstate <= 3; else Sp <= '1'; Nextstate <= 4;
end if;
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VHDL Program for the Game (2-process model): VHDL Program for the Game (2-process model):
Counters and Adder Complete game (include dicegame and counter)

entity Counter is entity Game is

port(Clk, Roll: in bit; port (Rb, Reset, Clk: in bit;
Sum: out integer range 2 to 12); Win, Lose: out bit);
end Counter; end Game;

architecture Count of Counter is architecture Play1 of Game is

signal Cnt1,Cnt2: integer range 1 to 6 := 1; component ___________
begin port(Clk, Roll: in bit;
process (Clk) Sum: out integer range 2 to 12);
begin end component;
if Clk='1' then component ______________
if Roll='1' then port (Rb, Reset, CLK: in bit;
if Cnt1=6 then _______; else Cnt1 <= ______ ; Sum: in integer range 2 to 12;
end if; Roll, Win, Lose: out bit);
if Cnt1=6 then end component;
if Cnt2=6 then Cnt2 <= 1; else Cnt2 <= Cnt2+1; signal roll1: bit;
end if; signal sum1: integer range 2 to 12;
end if; begin
end if; Dice: __________
end if; port map(Rb,Reset,Clk,sum1,roll1,Win,Lose);
end process; Count: ___________ port map(Clk,roll1,sum1);
Sum <= _______________ ; -- adder; end Play1;
end Count; ECE 4250/7250 Part 7: Microprogramming 17 ECE 4250/7250 Part 7: Microprogramming 18
Test Bench Test Bench

Simulate data section. Game Test

Receive control signals from Dicegame. Acrobat Document

Generate simulation test sequence for 1. Supply the Rb signal

DiceGame. 2. When the DiceGame responds with a
Roll signal, supply a sum signal.
DiceGame: Model (behavior or dataflow 3. If no Win/lose result, roll again.
model) for game control. 4. When a win/lose result is seen, generate
reset signal.
GameTest: Model for generate simulation data
for the game machine.

Tester: Connecting the above two parts together

for simulation test.

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Test Bench Test Bench
Corresponding states in two charts (Dicegame
and GameTest) Function among two modules Dice Game and
T0(Rb = 1) <= => S0, _________ Game Test:
T1(Rb=0) <= => S0, _________
T2 <= => ____________ Rb set to 1 in T0. Make the transition from
S0 to S1 and T0 to T0

Roll becomes 1 and make S1 to S1 and T0 to

T1.

Rb goes to zero when the state goes to T1.

Then in the next cycle, DiceGame will get to
S2, S3 or S4 when Game test has the state go
to T2.

If there is no win/lose result (state S4), another

roll is necessary.

If there is a result, reset by having reset = ‘1’.

Two models should interact adequately!!!!

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Test Bench Test Bench

entity GameTest is elsif Roll = '1' then

port(Rb, Reset: out bit; Sum <= ____________ ;
Sum: out integer range 2 to 12; i:=_________;
CLK: inout bit; Tnext <= 1;
Roll, Win, Lose: in bit); end if;
end GameTest; when 1 => Rb <= '0'; Tnext <= 2;
when 2 => Tnext <= 0;
library BITLIB; Trig1 <= not Trig1; -- toggle Trig1
use BITLIB.bit_pack.all; if (Win or Lose) = '1' then
Reset <= '1';
architecture dicetest of GameTest is end if;
signal Tstate, Tnext: integer range 0 to 3; when 3 => null; -- Stop state
signal Trig1: bit; end case;
type arr is array(0 to 11) of integer; end process;
constant Sumarray:arr := (7,11,2,4,7,5,6,7,6,8,9,6); process(CLK)
begin begin
CLK <= ____________ after 20 ns; if CLK = '1' then
process(Roll, Win, Lose, Tstate) Tstate <= Tnext;
variable i: natural; -- i is initialized to 0 end if;
begin end process;
case Tstate is end dicetest;
when 0 => Rb <= '1'; --wait for Roll
Reset <='0';
if i>=______ then Tnext <= 3;
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Test Bench Test Bench

entity tester is
end tester;

architecture test of tester is

component GameTest
port(Rb, Reset: out bit;
Sum: out integer range 2 to 12;
CLK: inout bit;
Roll, Win, Lose: in bit);
end component;
component DiceGame
port (Rb, Reset, CLK: in bit;
Sum: in integer range 2 to 12 ;
Roll, Win, Lose: out bit); Acrobat Document
end component;
signal rb1, reset1, clk1, roll1, win1, lose1: bit;
signal sum1: integer range 2 to 12;
begin
Dice: Dicegame
port map(rb1,reset1,clk1,sum1,roll1,win1,lose1);
Dicetest: GameTest
port map(rb1,reset1,sum1,clk1,roll1,win1,lose1);
end test;

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Microprogramming Microprogramming

Microprogramming There can be only two possible addresses for

the next “instruction”.
• Use programming concept;
• Use memory to store “instructions” Steps in the design:
• Program the flow in the SM chart
• Next “instruction”: controlled by a • Construct an SM chart.
condition • Revise the SM chart such that there is at
most only one condition at the exit of each
Two ways state. Add states when necessary.
• Obtain the ROM table
Jump to one address if the condition is true and
another address if the condition is false

Continue to the next address if the condition is

true and a specified address if the condition is
false

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Microprogramming

Example Microprogramming
State0/A
Store the control signals in a memory.
0 1
Cond1 Two ways:
1. Execute one “instruction” - test some
Z1 Cond2 condition, branch to one location if the
0
1 condition is true and branch to another location
State1 State2 State3 if the condition is false.

Instruction word

Addr test NSF NST Control signals

(P. S.) cond. (N. S.) (Outputs)
State0/A --------------------------------------------------------
000 101 001 101 0 1 1 0 0
0 1
Cond1 State01 (Present state 000; test condition 5; next state
001 if the condition is false and 101 if the
State02/Z Cond2 condition is true; 5 output values 0 1 1 0 0.)
1 0
1
(TABLE) Figure 5-9: Multiplier control
State1/Z State2 State3 Acrobat Document

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Microprogramming Microprogramming

Figure 5-26 2. Execute one “instruction” - test some

condition, branch to one location if the
Next instruction address condition is true and continue to the next
instruction if the condition is false.

Register Test NSF NST Output Instruction word

Addr test NST Control signals

True
: MUX MUX (P. S.) (N. S.)
false --------------------------------------------------------
000 101 011 0 1 1 0 0
(Present state 000; test condition 5; next state
001 if the condition is false and 011 if the
condition is true; 5 output values 0 1 1 0 0.)

(TABLE)

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Microprogramming Microprogramming

Figure 5-29 For either way, the first step is to modify the SM
chart to meet the microprogramming scheme.

Some conditions:
Next instruction address
Only one condition can be tested in each step

Output must associate with a state, not a

Counter Test NST Output transition

For the second way, the code of next state with

: MUX
the test condition false must be one plus the code
of the present state.
True or
Modifications: Add states to make sure that the
Load, count’ false above conditions are satisfied.

Example using figure 5-9: Multiplier control

Acrobat Document

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Microprogramming Examples Microprogramming Examples
Original SM Charrt
Original SM Charrt
Acrobat Document

Example: Dice Game

Structure 1
Figure 5-27, 28 & Table 5.3: one test per state, no
output alone transition.
Acrobat Document
(To be explained in class)

Structure 2
Figure 5-30, 31 & Table 5.4: Add state to make the
transition to state
(CURRENT STATE + 1) if the condition is false.

(To be explained in class)

Acrobat Document

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Microprogramming Examples Microprogramming Examples
Dice Game: Structure 1 Dice Game: Structure 1

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Microprogramming Examples Microprogramming Examples
Dice Game: Structure 2 Dice Game: Structure 2

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