Analysis of Clocked Sequential Circuits

• Analysis describes behavior under certain conditions

• Determined through inputs, outputs and state of FF
obtaining a table or a diagram for the time sequence of
inputs, outputs, and internal states
• The State x
D Q A
– State = Values of all Flip-Flops
Q

Example D Q B

AB=00 CLK Q

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Analysis of Clocked Sequential Circuits
• State Equations
x
D Q A
A(t+1) = DA
= A(t) x(t)+B(t) x(t) Q
=Ax+Bx
B(t+1) = DB D Q B
= A’(t) x(t)
= A’ x CLK Q

y(t) = [A(t)+ B(t)] x’(t) y

= (A + B) x’

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Analysis of Clocked Sequential Circuits
• State Table (Transition Table)
Present Next x
Input Output D Q A
State State
A B x A B y Q

0 0 0 0 0 0
0 0 1 0 1 0 D Q B

0 1 0 0 0 1 CLK Q
0 1 1 1 1 0
y
1 0 0 0 0 1
1 0 1 1 0 0
1 1 0 0 0 1 A(t+1) = A x + B x
1 1 1 1 0 0 B(t+1) = A’ x
y(t) = (A + B) x’
t
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 Analysis of Clocked Sequential
Circuits
• State Table (Transition Table)
Present Next State Output
State x=0 x=1 x=0 x=1
A B A B A B y y
0 0 0 0 0 1 0 0
0 1 0 0 1 1 1 0
1 0 0 0 1 0 1 0
1 1 0 0 1 0 1 0

t t+1 t A(t+1) = A x + B x
B(t+1) = A’ x
y(t) = (A + B) x’
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 Analysis of Clocked Sequential
Circuits
• State Diagram Present Next State Output
State x=0 x=1 x=0 x=1
A B A B A B y y
AB input/output
0 0 0 0 0 1 0 0
0 1 0 0 1 1 1 0
0/0 1/0 1 0 0 0 1 0 1 0
0/1 1 1 0 0 1 0 1 0

00 10
x
D Q A
0/1 Q
1/0 0/1 1/0
D Q B

CLK Q
01 11
y

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 Analysis of Clocked Sequential
Circuits
• D Flip-Flops
Example: x D Q A
Present Next y
Input
State State CLK Q
A x y A
0 0 0 0
0 0 1 1 A(t+1) = DA = A  x  y
0 1 0 1
0 1 1 0
1 0 0 1 01,10
1 0 1 0
00,11 0 1 00,11
1 1 0 0
1 1 1 1 01,10
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 Analysis of Clocked Sequential
Circuits
• JK Flip-Flops J Q A

Example: x K Q

Present Next Flip-Flop

I/P J Q B
State State Inputs
A B x A B JA K A J B K B K Q
0 0 0 0 1 0 0 1 0 CLK
0 0 1 0 0 0 0 0 1
JA = B KA = B x’
0 1 0 1 1 1 1 1 0
JB = x’ KB = A  x
0 1 1 1 0 1 0 0 1
1 0 0 1 1 0 0 1 1 A(t+1) = JA Q’A + K’A QA
1 0 1 1 0 0 0 0 0 = A’B + AB’ + Ax
1 1 0 0 0 1 1 1 1 B(t+1) = JB Q’B + K’B QB
1 1 1 1 1 1 0 0 0 = B’x’ + ABx + A’Bx’
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 Analysis of Clocked Sequential
Circuits
• JK Flip-Flops J Q A

x
Example: K Q

Present Next Flip-Flop J Q B

I/P
State State Inputs
A B x A B JA K A J B K B K Q

0 0 0 0 1 0 0 1 0 CLK

0 0 1 0 0 0 0 0 1 1 0 1
0 1 0 1 1 1 1 1 0 00 11
0 1 1 1 0 1 0 0 1
0
1 0 0 1 1 0 0 1 1 0 0
1 0 1 1 0 0 0 0 0
1 1 0 0 0 1 1 1 1 01 10
1 1 1 1 1 1 0 0 0 1
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 Analysis of Clocked Sequential
Circuits
• T Flip-Flops
Example:
Present Next F.F
I/P O/P
State State Inputs
A B x A B TA TB y
0 0 0 0 0 0 0 0
0 0 1 0 1 0 1 0
0 1 0 0 1 0 0 0
TA = B x TB = x
0 1 1 1 0 1 1 0
y =AB
1 0 0 1 0 0 0 0
1 0 1 1 1 0 1 0
A(t+1) = TA Q’A + T’A QA
= AB’ + Ax’ + A’Bx
1 1 0 1 1 0 0 1
1 1
B(t+1) = TB Q’B + T’B QB
1 1 1 0 0 1
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 Analysis of Clocked Sequential
Circuits
• T Flip-Flops
Example:
Present Next F.F
I/P O/P
State State Inputs
A B x A B TA TB y
0 0 0 0 0 0 0 0
0 0 1 0 1 0 1 0
0 1 0 0 1 0 0 0 0/0 0/0
0 1 1 1 0 1 1 0 00 1/0 01
1 0 0 1 0 0 0 0
1 0 1 1 1 0 1 0 1/1 1/0
1 1 0 1 1 0 0 1 11 10
1 1 1 0 0 1 1 1 0/1 0/0
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 Mealy and Moore Models
Mealy Moore
Present Next Present Next
I/P O/P I/P O/P
State State State State
A B x A B y A B x A B y
0 0 0 0 0 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 1 0 1 0
0 1 0 0 0 1 0 1 0 0 1 0
0 1 1 1 1 0 0 1 1 1 0 0
1 0 0 0 0 1 1 0 0 1 0 0
1 0 1 1 0 0 1 0 1 1 1 0
1 1 0 0 0 1 1 1 0 1 1 1
1 1 1 1 0 0 1 1 1 0 0 1

For the same state, For the same state,

the output changes with the input the output does not change with the input

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 Moore State Diagram
State / Output

0 0
1
00/0 01/0

1 1

11/1 10/0
1
0 0
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 Timing Diagram
0 1 0
A 00/0 01/0
x y
B 0 0 1

11/1 10/0
No effect 1 1
CLK
x
A 0 0 1 0 0 0
State
B 0 1 0 0 1 1

y
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 Timing Diagram
0/0 1/0 0/0
A 00 01
x y
B 0/0 0/0 1/0

11 10
1/1
1/1
CLK
x
A 1
State
B 0

y
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