Intelligent Frequency Synthesizers

Preliminary Data Sheet PNP-1090-P22

FEATURES: DESCRIPTION:
The PNP-1090-P22 is a complete low noise frequency syn-
∗ 1500-2500 MHz Frequency thesizer, comprised of VCO, PLL, loop filter and data inter-
face. The PNP family of RF signal sources is the world’s
Range first truly configurable frequency synthesizer module. PNP
∗ Programmable Step Size technology offers the designer the ability to configure all of
∗ Low Integrated Phase Noise the synthesizer’s vital functions ‘on the fly’ with simple
strings of code that contain the commands of START,
∗ Simplified Programming STOP, STEP, CHANNEL and REF. When new data is re-
ceived, the PNP module optimizes its internal settings for
best overall integrated phase noise, switching speed and
APPLICATIONS: spurious suppression, all automatically and in less than 100
µS. Therefore, if the system requires 100 kHz steps in
mode #1 and 1 MHz step size in mode #2, these smart syn-
∗ Wireless Infrastructure thesizers can make quick adjustments with amazing accu-
∗ Test Equipment racy, speed and performance.
∗ Wireless LAN Control of the internal registers is accomplished through a
serial data interface. Many industry standard protocols are
supported, including I2C, SPI, and MICROWIRE Serial In-
MICROWIRE is a trademark of National Semiconductor Corp. terfaces. The PNP-1090-P22 is powered from +3V and
SPI is a trademark of Motorola, Inc. +12.5V supplies delivering +7 dBm of RF output power.
I2C is a trademark of Philips Corp.

Package Drawing all dimensions in inches

TOP SIDE BOTTOM

0.000

0.100

0.180

0.260

0.340

0.420
0.500

0.600

GND

GND

GND

GND

GND

GND

0.600 0.600

UMC
0.460 0.460 GND DA0

0.380 0.380 REF DA1

PNP-1090-P22 V2 DA2
0.300 0.300
1500-2500 MHz
0.220 0.220 V1 LD
4205
0.140 0.140 RF N/C

0.000 0.000
GND

GND

GND

GND

GND

GND
0.000

0.220
0.000

0.100

0.180

0.260

0.340

0.420
0.500

0.600

Universal Microwave Corporation, 2339 Destiny Way, Odessa, FL 33556

UMC Worldwide Customer Support Center: 4703 S. Lakeshore Drive, Suite 2, Tempe, AZ 85282
1.877.UMC.Xtreme / Fax 480.756.6026
PNP-1090-P22 Specifications V1 = +12.5V, V2 = +3.0V, REF =20.0 MHz, -40 to +85C

Parameter Min Typ Max Units

RF OUT Characteristics
Frequency Range 1500 2500 MHz
Output Power +5 +7 +9 dBm
Harmonics -20 -10 dBc
Noise Characteristics

1 kHz offset ∅ Noise -100 -95 dBc/Hz

10 kHz offset ∅ Noise -100 -95 dBc/Hz

100 kHz offset ∅ Noise -100 -95 dBc/Hz

1 MHz offset ∅ Noise -130 -125 dBc/Hz

Spurious Signals
STEP = 5000 kHz -70 -601 dBc
dBc
dBc
REF Feed-through -80 -70 dBc
REF IN Characteristics
REF Input Frequency 10 20 250 MHz
2
REF Input Sensitivity -5 0 +5 dBm
REF Input Current +/-100 µA
Logic Inputs
VINH, Input High Voltage 1.35 Vdc
VINL, Input Low Voltage 0.6 Vdc
IINH, IINL, Input Current +/- 1 µA
CIN, Input Capacitance 10 pF
Logic Outputs
VOH, Output High Voltage V2 - 0.4 Vdc
VOL, Output Low Voltage 0.4 Vdc
IOH, IOL, Output Current 500 µA
Power Supplies
Supply Voltage, V1 12.3 12.5 12.7 Vdc
Supply Voltage, V2 2.7 3.0 3.3 Vdc
Supply Current, I1 50 60 mA
Supply Current, I2 25 35 mA

NOTES: 1. Max STEP spurious are degraded by an additional 10 dB at integer multiples of the Reference Frequency
within a +/-100 kHz bandwidth 2. AC coupled. For DC coupled, 0 - V2 max.
Pin Descriptions PNP-1090-P22

Mnemonic FUNCTION
RF RF Output. This pin is AC coupled and should be connected to a non-reflective 50 ohm load.
V1 Supply Input. Decoupling capacitors to the ground plane should be placed as close as possi-
ble to this pin. Use an ultra low-noise regulator followed by an RC filter for best noise.
V2 Supply Input. Decoupling capacitors to the ground plane should be placed as close as possi-
ble to this pin. Use an ultra low-noise regulator followed by an RC filter for best noise.
REF Reference Input. This is a CMOS input with a nominal threshold of V2/2 and a dc equivalent
input resistance of 100K ohms. This input can be driven from a CMOS or TTL crystal clock
oscillator or it can be ac coupled.
GND Analog and RF Ground.
DA0 Serial Interface. This input functions as CS in MICROWIRE/SPI Bus mode. This input func-
tions as SDA in I2C BUS mode.
DA1 Serial Interface. This input functions as DATA in MICROWIRE/SPI BUS mode. This input
functions as SCL in I2C BUS mode.
DA2 Serial Interface. This input functions as CLOCK in MICROWIRE/SPI BUS mode. This input
must be connected to the DIGITAL GROUND in I2C BUS mode.
LD Lock Detect. This output is active high and provides a continuous digital lock status.

Absolute Maximum Ratings

V1 to Ground -0.3 to +12.7 Vdc Operating Temperature -40° to +85°C
V2 to Ground -0.3 to +3.6 Vdc Storage Temperature -55° to +100°C
REF IN to Ground -0.3 to (V2 + 0.3) Vdc
Stress above those listed under “Absolute Maximum Ratings”
RF OUT to Ground +/- 25 Vdc may cause permanent damage to the device. This is a stress
rating only. Operation of the device above the conditions listed
Digital I/O to Ground -0.3 to (V2 + 0.3) Vdc in the operational sections of this specification is not implied.

Ordering Guide PNP-1090-P22

Model I2C Address Type Code
PNP-1090-P22 Default P003
PNP-1090A-P22 Default + 1 P003
PNP-1090B-P22 Default + 2 P003
PNP-1090C-P22 Default + 3 P003

CAUTION!
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as
4000V readily accumulate on the human body and test equipment and can dis-
charge without detection. Although the PNP family of synthesizers feature ESD
protection circuitry, permanent damage may occur on devices subjected to high-
energy electrostatic discharges. Therefore, proper ESD precautions are recom-
mended to avoid performance degradation or loss of functionality
Digital Interface PNP-1090-P22

Overview Bus for control of the PNP synthesizer module, the DA2
line (see Package Drawing, Page 1) must be tied to Digi-
The PNP family of intelligent Frequency Synthesizers can tal Ground. Additionally, the SDA and SCL lines must be
be controlled through the use of a microprocessor inter- pulled up to Dvdd using external resistors.
face or Bus. Several protocols are supported by PNP Multiple PNP devices can reside on the same two wire
devices, although this specification will focus on SPI Bus, Bus without the danger of corrupted data or data colli-
MICROWIRE-Interface and I2C Bus implementations. sions. Device selection is accomplished by sending a
For SPI and MICROWIRE applications, PNP devices re- slave address preceding each string of data. If only one
quire a single 32 bit string of serial data to set frequency PNP device will be used on the I2C Bus, then the factory
or to change its internal settings (Figure 1). I2C Bus util- pre-set base address will operate properly. If more than
izes some unique control bits and requires the addition of one PNP device will reside on the same I2C Bus, then
an ADDRESS byte, increasing the serial bit-stream for modules with unique address locations must be used.
this protocol to 40 bits per command (Figure 2). This should be specified when ordering (see Ordering
Guide on page 3). For additional information refer to the
The PNP device is programmed at the factory with pre- I2C Bus specification (copyright Philips Corp).
sets for the START, STOP, STEP and REFERENCE
registers. It is not necessary to re-load any of these reg- I2C Implementation
isters if the factory values are acceptable. If the applica-
tion requires different values than the factory pre-sets, Transferring data to PNP synthesizers using I2C protocol
then the PNP device must first be initialized by loading varies significantly from that of SPI or MICROWIRE.
data into each of the affected registers. It is not neces- PNP modules operate as slaves on the I2C Bus and do
sary to re-load any registers that are already set properly not write to the Bus. However, due to the fact that many
for the application. START defines the lowest desired devices might reside on the same Bus, addressing must
frequency of operation. STOP defines the highest de- be used to direct the flow of data traffic. So, within the bit
sired frequency of operation. STEP is used to channelize stream sent to the PNP device, there is a block of data
the band and REFERENCE defines the frequency of the that comprises the ADDRESS byte. Within this address
external reference. Once the PNP device is initialized, a byte there are 7 bits that are used for the address loca-
fixed number channels are available. Loading the CHAN- tion and the eighth is used as a read/write (R/W) bit.
NEL register sets the operating frequency of the PNP Since PNPs are slaves and will never write to the I2C
device. The formula for calculating the operating fre- Bus, this bit will always be set to 0 (logic low).
quency is:
Each data string is sent using a series of five single byte
START(Hz) + (CHANNEL * STEP(Hz)) = Frequency(Hz) blocks. I2C protocol requires that each string of data be-
gin with a master generated START (S). Each byte
MICROWIRE Interface and SPI Bus within the string must end with a slave generated AC-
KNOWLEDGE (A). Finally, after all five bytes are gener-
MICROWIRE-Interface and SPI Bus are extremely similar ated, the transfer is concluded with a master generated
protocols (Figures 6 & 7). DATA bits are clocked into STOP (P). The master generated STOP must be exe-
the PNP device on the rising edge of the CLOCK input. cuted following each data string for the values to be ac-
CS, or chip select not, must be in a low state for the in- cepted by the PNP device. If this condition is not satis-
coming DATA bits to be accepted. After all 32 bits have fied and a new master generated START occurs, the
been clocked in, the CS line must transition high for the PNP device will purge the previous data without updating
DATA string to be latched. After the string is latched, the the desired attribute. REPEATED START (Sr) operation
information in the FUNCTION block (Figure 5) deter- is not allowed when sending data to the PNP device.
mines where the data will be routed internally.
The flow of data bytes to the PNP device is outlined in
Figure 2. Since FUNCTION SELECT and MULTIPLIER
I2C Bus are 4 bits each, these blocks of data are combined into
one byte. Additionally, since the FREQUENCY/
The I2C Bus is a high-speed method of communicating CHANNEL block of data is 24 bits long, it must be frag-
over a two wire interface. PNP modules are configured mented into three individual bytes as shown.
as “slaves” or receive-only devices and can only listen for
commands from the “master” which is typically a micro-
processor. The I2C two wire Bus consists of SDA (serial
data) and SCL (serial clock) lines. In order to use the I2C
Attribute Definitions PNP-1090-P22

FIGURE 2: FREQUENCY/CHANNEL (DB0 - DB23) This is a 24 bit string used to set the synthesizer’s
START Frequency, STOP Frequency, STEP Frequency, REF Frequency or CHANNEL number.

DB23 DBn DB3 DB2 DB1 DB0

FREQUENCY/CHANNEL
FC23 FCn FC3 FC2 FC1 FC0
0 0 0 0 0 0 0
0 0 0 0 0 1 1
0 0 0 0 1 0 2
0 0 0 0 1 1 3
0 0 1 1 1 1 15

FIGURE 3: MULTIPLIER (DB24 - DB27) The data in FREQUENCY/CHANNEL (DB0-DB23) is multiplied

by 10n where the value of n is determined by the contents of MULTIPLIER (DB24-DB27) as shown below.

DB27 DB26 DB25 DB24

MULTIPLIER
M3 M2 M1 M0
0 0 0 0 100 X contents of DB0-DB23
0 0 0 1 101 X contents of DB0-DB23
0 0 1 0 102 X contents of DB0-DB23
0 0 1 1 103 X contents of DB0-DB23
n n n n 10n X contents of DB0-DB23

FIGURE 4: FUNCTION SELECT (DB28 - DB31). After the data in FREQUENCY/CHANNEL (DB0 - DB23)
is multiplied by 10n where the value of n is determined by the contents of MULTIPLIER (Figure 3), it is then
routed internally to the START, STOP, STEP, REF or CHANNEL registers based on the contents of FUNC-
TION SELECT as shown below.

DB31 DB30 DB29 DB28

FS3 FS2 FS1 FS0 FUNCTION SELECT
0 0 0 0 CHANNEL. Routes data from DB0-DB23 to the CHANNEL REGISTER.
0 0 0 1 START. Routes data from DB0-DB23 to the START REGISTER.
0 0 1 0 STOP. Routes data from DB0-DB23 to the STOP REGISTER.
0 0 1 1 STEP. Routes data from DB0-DB23 to the STEP REGISTER.
0 1 0 0 REFERENCE. Routes data from DB0-DB23 to the REFERENCE REGISTER
All FUNCTION SELECT values not shown above are reserved for factory use.
Data Structures PNP-1090-P22

Figure 1: SPI Bus/Microwire-Interface Data Structure

FUNCTION SELECT (4 BITS) MULTIPLIER (4 BITS) FREQUENCY/CHANNEL (24 BITS)
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DBn DB2 DB1 DB0
FS3 FS2 FS1 FS0 M3 M2 M1 M0 FC23 FC22 FCn FC2 FC1 FC0

Figure 2: I2C Bus Data Structure

START Slave ADDRESS FUNCTION SELECT/MULTIPLIER

A6 A5 A4 A3 A2 A1 A0 R/W FS3 FS2 FS1 FS0 M3 M2 M1 M0
S A A
1 1 n n n n n 0 n n n n n n n n

Master START PNP ADDRESS Read/Write FUNCTION SELECT MULTIPLIER

(See Table below)

Acknowledge Acknowledge

FREQUENCY/CHANNEL STOP
FC FC FC FC FC FC FC FC FC FC FC FC FC FC FC FC FC FC FC FC FC FC FC FC A
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
A A P
n n n n n n n n n n n n n n n n n n n n n n n n n

FREQUENCY/CHANNEL BYTE FREQUENCY/CHANNEL BYTE FREQUENCY/CHANNEL BYTE

Acknowledge Acknowledge Acknowledge

Master STOP

MODEL I2C ADDRESS

NUMBER A6 A5 A4 A3 A2 A1 A0
PNP-1090-P22 1 1 0 0 0 0 0
PNP-1090A-P22 1 1 0 0 0 0 1
PNP-1090B-P22 1 1 0 0 0 1 0
PNP-1090C-P22 1 1 0 0 0 1 1
PNP-1090x-P22 1 1 n n n n n
SPI Bus/MICROWIRE-Interface Timing Characteristics

Figure 6: MICROWIRE Interface Timing Diagram

~
DB31 DB30 DB2 DB1 DB0 DATA

~
t1 t2

~
CLOCK
t3 t4

CS
~

t5 t6

Parameter Limit at tmin to tmax Units Test Conditions/Comments

t1 100 ns min DATA to CLOCK setup time

t2 100 ns min DATA to CLOCK hold time

t3 250 ns min CLOCK high time

t4 250 ns min CLOCK low time

t5 100 ns min CLOCK to CS setup time

t6 200 ns min CS pulse width (applies to MICROWIRE Interface only)

t7 200 ns min CS to CLOCK setup time (applies to SPI BUS only)

Figure 7: SPI BUS Timing Diagram

~

DB31 DB30 DB2 DB1 DB0 DATA

~

t1 t2

CLOCK
~

t7
t3 t4

CS
~

t5
Package Drawing all dimensions in inches

TOP SIDE BOTTOM

0.000

0.100

0.180

0.260

0.340

0.420
0.500

0.600

GND

GND

GND

GND

GND

GND
0.600 0.600

UMC
0.460 0.460 GND DA0

0.380 0.380 REF DA1

PNP-1090-P22 V2 DA2
0.300 0.300
1500-2500 MHz
0.220 0.220 V1 LD
4205
0.140 0.140 RF N/C

0.000 0.000

GND

GND

GND
GND

GND

GND
0.000

0.100

0.180

0.260

0.340

0.420
0.500

0.600

0.000

0.220

Recommended Layout all dimensions in inches

b

c Recommended Layout Dimensions

(min) (typ) (max)
a 0.043 0.046 0.049
a
c

b 0.052 0.055 0.058

d

c 0.475 0.480 0.485

d 0.535 0.540 0.545
b
e 0.080
e

Tape and Reel Specifications all dimensions in mm

Tape and Reel Dimensions

Ao 15.5 E 1.75
Bo 15.5 F 10.2
P 16.0 c 0.06
Po 4.0 d 0.30
Cw 24.0 Tw 21.2
D 1.5 Ko 6.6