Digital Design & Computer Architecture (23EC1202) Lab Manual 2023-24 – Even Semester
EXPERIMENT – 12
IMPLEMENTATION OF 3-STAGE PIPELINING
Aim: To implement 3-stage pipelining using Logisim.
Tools Required: Logisim
Components/devices can be used: Memories, decoders
Need and purpose:
Instruction pipelining is a technique for implementing instruction-level parallelism
within a single processor. Pipelining attempts to keep every part of the processor busy with
some instruction by dividing incoming instructions into a series of sequential steps performedby
different processor units with different parts of instructions processed in parallel. It allows
faster CPU throughput than would otherwise be possible at a given clock rate, but may increase
latency due to the added overhead of the pipelining process itself.
Model Diagram / Table:
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Digital Design & Computer Architecture (23EC1202) Lab Manual 2023-24 – Even Semester
Circuit Diagram:
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Digital Design & Computer Architecture (23EC1202) Lab Manual 2023-24 – Even Semester
Procedure:
1. Analyse the given model diagram and select the required modules in Logisim.
2. Implement 3-stages fetch, decode and execute in pipelining.
3. Verify the operation of 3-stage pipelining using Logisim.
Result: The experiment successfully demonstrated the implementation of 3-stage pipelining using
Logisim.
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