STM32F745xx STM32F746xx Pinouts and pin description

Table 9. Legend/abbreviations used in the pinout table

Name Abbreviation Definition

Unless otherwise specified in brackets below the pin name, the pin function during and after
Pin name
reset is the same as the actual pin name
S Supply pin
Pin type I Input only pin
I/O Input / output pin
FT 5 V tolerant I/O
TTa 3.3 V tolerant I/O directly connected to ADC
I/O structure
B Dedicated BOOT pin
RST Bidirectional reset pin with weak pull-up resistor

Notes Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset

Alternate
Functions selected through GPIOx_AFR registers
functions

Additional
Functions directly selected/enabled through peripheral registers
functions

Table 10. STM32F745xx and STM32F746xx pin and ball definition

Pin Number

Pin
I/O structure
Pin type

name
WLCSP143

UFBGA176
TFBGA100

TFBGA216

Notes

Additional
LQFP100

LQFP144

LQFP176

LQFP208

(function Alternate functions

functions
after
reset)(1)

TRACECLK, SPI4_SCK,
SAI1_MCLK_A,
1 A3 D8 1 A2 1 1 A3 PE2 I/O FT - QUADSPI_BK1_IO2, -
ETH_MII_TXD3,
FMC_A23, EVENTOUT

TRACED0, SAI1_SD_B,
2 B3 C10 2 A1 2 2 A2 PE3 I/O FT - -
FMC_A19, EVENTOUT

TRACED1, SPI4_NSS,
SAI1_FS_A, FMC_A20,
3 C3 B11 3 B1 3 3 A1 PE4 I/O FT - -
DCMI_D4, LCD_B0,
EVENTOUT

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Table 10. STM32F745xx and STM32F746xx pin and ball definition (continued)
Pin Number

Pin

I/O structure
Pin type
name
WLCSP143

UFBGA176
TFBGA100

TFBGA216

Notes
Additional
LQFP100

LQFP144

LQFP176

LQFP208
(function Alternate functions
functions
after
reset)(1)

TRACED2, TIM9_CH1,
SPI4_MISO,
4 D3 D9 4 B2 4 4 B1 PE5 I/O FT - SAI1_SCK_A, FMC_A21, -
DCMI_D6, LCD_G0,
EVENTOUT
TRACED3, TIM1_BKIN2,
TIM9_CH2, SPI4_MOSI,
SAI1_SD_A,
5 E3 E8 5 B3 5 5 B2 PE6 I/O FT - -
SAI2_MCK_B, FMC_A22,
DCMI_D7, LCD_G1,
EVENTOUT
- - - - - - - G6 VSS S - - - -
- - - - - - - F5 VDD S - - - -
6 B2 C11 6 C1 6 6 C1 VBAT S - - - -

(2) RTC_TAMP2/
- - - - D2 7 7 C2 PI8 I/O FT (3) EVENTOUT RTC_TS,WK
UP5

RTC_TAMP1/
(2)
RTC_TS/RTC
7 A2 D10 7 D1 8 8 D1 PC13 I/O FT (3) EVENTOUT
_OUT,WKUP
4
PC14- (2)
8 A1 D11 8 E1 9 9 E1 OSC32_I I/O FT (3) EVENTOUT OSC32_IN
N(PC14)
PC15-
(2)
OSC32_
9 B1 E11 9 F1 10 10 F1 I/O FT (3) EVENTOUT OSC32_OUT
OUT(PC
15)
- - - - - - - G5 VDD S - - - -
CAN1_RX, FMC_D30,
- - - - D3 11 11 E4 PI9 I/O FT - LCD_VSYNC, -
EVENTOUT
ETH_MII_RX_ER,
- - - - E3 12 12 D5 PI10 I/O FT - FMC_D31, LCD_HSYNC, -
EVENTOUT

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STM32F745xx STM32F746xx Pinouts and pin description

Table 10. STM32F745xx and STM32F746xx pin and ball definition (continued)
Pin Number

Pin

I/O structure
Pin type
name
WLCSP143

UFBGA176
TFBGA100

TFBGA216

Notes
Additional
LQFP100

LQFP144

LQFP176

LQFP208
(function Alternate functions
functions
after
reset)(1)

OTG_HS_ULPI_DIR,
- - - - E4 13 13 F3 PI11 I/O FT - WKUP6
EVENTOUT
- - E7 - F2 14 14 F2 VSS S - - - -
- - E10 - F3 15 15 F4 VDD S - - - -
I2C2_SDA, FMC_A0,
- - F11 10 E2 16 16 D2 PF0 I/O FT - -
EVENTOUT
I2C2_SCL, FMC_A1,
- - E9 11 H3 17 17 E2 PF1 I/O FT - -
EVENTOUT
I2C2_SMBA, FMC_A2,
- - F10 12 H2 18 18 G2 PF2 I/O FT - -
EVENTOUT
LCD_HSYNC,
- - - - - - 19 E3 PI12 I/O FT - -
EVENTOUT
LCD_VSYNC,
- - - - - - 20 G3 PI13 I/O FT - -
EVENTOUT
- - - - - - 21 H3 PI14 I/O FT - LCD_CLK, EVENTOUT -
- - G11 13 J2 19 22 H2 PF3 I/O FT - FMC_A3, EVENTOUT ADC3_IN9
- - F9 14 J3 20 23 J2 PF4 I/O FT - FMC_A4, EVENTOUT ADC3_IN14
- - F8 15 K3 21 24 K3 PF5 I/O FT - FMC_A5, EVENTOUT ADC3_IN15
10 C2 H7 16 G2 22 25 H6 VSS S - - - -
11 D2 - 17 G3 23 26 H5 VDD S - - - -

TIM10_CH1, SPI5_NSS,
SAI1_SD_B, UART7_Rx,
- - G10 18 K2 24 27 K2 PF6 I/O FT - ADC3_IN4
QUADSPI_BK1_IO3,
EVENTOUT

TIM11_CH1, SPI5_SCK,
SAI1_MCLK_B,
- - F7 19 K1 25 28 K1 PF7 I/O FT - UART7_Tx, ADC3_IN5
QUADSPI_BK1_IO2,
EVENTOUT

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Table 10. STM32F745xx and STM32F746xx pin and ball definition (continued)
Pin Number

Pin

I/O structure
Pin type
name
WLCSP143

UFBGA176
TFBGA100

TFBGA216

Notes
Additional
LQFP100

LQFP144

LQFP176

LQFP208
(function Alternate functions
functions
after
reset)(1)

SPI5_MISO,
SAI1_SCK_B,
UART7_RTS,
- - H11 20 L3 26 29 L3 PF8 I/O FT - ADC3_IN6
TIM13_CH1,
QUADSPI_BK1_IO0,
EVENTOUT

SPI5_MOSI, SAI1_FS_B,
UART7_CTS,
- - G8 21 L2 27 30 L2 PF9 I/O FT - TIM14_CH1, ADC3_IN7
QUADSPI_BK1_IO1,
EVENTOUT

DCMI_D11, LCD_DE,
- - G9 22 L1 28 31 L1 PF10 I/O FT - ADC3_IN8
EVENTOUT
PH0-
12 C1 J11 23 G1 29 32 G1 OSC_IN( I/O FT - EVENTOUT OSC_IN(4)
PH0)
PH1-
13 D1 H10 24 H1 30 33 H1 OSC_OU I/O FT - EVENTOUT OSC_OUT(4)
T(PH1)
RS
14 E1 H9 25 J1 31 34 J1 NRST I/O - - -
T
SAI2_FS_B,
(4) OTG_HS_ULPI_STP, ADC123_IN1
15 F1 H8 26 M2 32 35 M2 PC0 I/O FT
FMC_SDNWE, LCD_R5, 0
EVENTOUT

TRACED0, ADC123_IN1
(4) SPI2_MOSI/I2S2_SD, 1,
16 F2 K11 27 M3 33 36 M3 PC1 I/O FT
SAI1_SD_A, ETH_MDC, RTC_TAMP3,
EVENTOUT WKUP3

SPI2_MISO,
OTG_HS_ULPI_DIR,
ADC123_IN1
17 E2 J10 28 M4 34 37 M4 PC2 I/O FT (4) ETH_MII_TXD2,
2
FMC_SDNE0,
EVENTOUT

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STM32F745xx STM32F746xx Pinouts and pin description

Table 10. STM32F745xx and STM32F746xx pin and ball definition (continued)
Pin Number

Pin

I/O structure
Pin type
name
WLCSP143

UFBGA176
TFBGA100

TFBGA216

Notes
Additional
LQFP100

LQFP144

LQFP176

LQFP208
(function Alternate functions
functions
after
reset)(1)

SPI2_MOSI/I2S2_SD,
OTG_HS_ULPI_NXT,
ADC123_IN1
18 F3 J9 29 M5 35 38 L4 PC3 I/O FT (4) ETH_MII_TX_CLK,
3
FMC_SDCKE0,
EVENTOUT
- - G7 30 G3 36 39 J5 VDD S - - - -
- - - - - - - J6 VSS S - - - -
19 G1 K10 31 M1 37 40 M1 VSSA S - - - -
- - - - N1 - - N1 VREF- S - - - -
20 - L11 32 P1 38 41 P1 VREF+ S - - - -
21 H1 L10 33 R1 39 42 R1 VDDA S - - - -

TIM2_CH1/TIM2_ETR,
TIM5_CH1, TIM8_ETR,
PA0-
USART2_CTS, ADC123_IN0,
22 G2 K9 34 N3 40 43 N3 WKUP(P I/O FT (5)
UART4_TX, SAI2_SD_B, WKUP1(4)
A0)
ETH_MII_CRS,
EVENTOUT

TIM2_CH2, TIM5_CH2,
USART2_RTS,
UART4_RX,
(4) QUADSPI_BK1_IO3,
23 H2 K8 35 N2 41 44 N2 PA1 I/O FT ADC123_IN1
SAI2_MCK_B,
ETH_MII_RX_CLK/ETH_
RMII_REF_CLK,
LCD_R2, EVENTOUT
TIM2_CH3, TIM5_CH3,
TIM9_CH1, USART2_TX,
ADC123_IN2,
24 J2 L9 36 P2 42 45 P2 PA2 I/O FT (4) SAI2_SCK_B,
WKUP2
ETH_MDIO, LCD_R1,
EVENTOUT
LPTIM1_IN2,
QUADSPI_BK2_IO0,
SAI2_SCK_B,
- - - - F4 43 46 K4 PH2 I/O FT -
ETH_MII_CRS,
FMC_SDCKE0, LCD_R0,
EVENTOUT

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Table 10. STM32F745xx and STM32F746xx pin and ball definition (continued)
Pin Number

Pin

I/O structure
Pin type
name
WLCSP143

UFBGA176
TFBGA100

TFBGA216

Notes
Additional
LQFP100

LQFP144

LQFP176

LQFP208
(function Alternate functions
functions
after
reset)(1)

QUADSPI_BK2_IO1,
SAI2_MCK_B,
- - - - G4 44 47 J4 PH3 I/O FT - ETH_MII_COL, -
FMC_SDNE0, LCD_R1,
EVENTOUT
I2C2_SCL,
- - - - H4 45 48 H4 PH4 I/O FT - OTG_HS_ULPI_NXT, -
EVENTOUT
I2C2_SDA, SPI5_NSS,
- - - - J4 46 49 J3 PH5 I/O FT - FMC_SDNWE, -
EVENTOUT
TIM2_CH4, TIM5_CH4,
TIM9_CH2, USART2_RX,
25 K2 M11 37 R2 47 50 R2 PA3 I/O FT (4) OTG_HS_ULPI_D0, ADC123_IN3
ETH_MII_COL, LCD_B5,
EVENTOUT
26 J1 - 38 - - 51 K6 VSS S - - - -
BYPASS
- E6 N11 - L4 48 - L5 I FT - - -
_REG
27 K1 J8 39 K4 49 52 K5 VDD S - - - -
SPI1_NSS/I2S1_WS,
SPI3_NSS/I2S3_WS,
USART2_CK,
TT (4) ADC12_IN4,
28 G3 M10 40 N4 50 53 N4 PA4 I/O OTG_HS_SOF,
a DAC_OUT1
DCMI_HSYNC,
LCD_VSYNC,
EVENTOUT
TIM2_CH1/TIM2_ETR,
TIM8_CH1N,
TT (4) ADC12_IN5,
29 H3 M9 41 P4 51 54 P4 PA5 I/O SPI1_SCK/I2S1_CK,
a DAC_OUT2
OTG_HS_ULPI_CK,
LCD_R4, EVENTOUT
TIM1_BKIN, TIM3_CH1,
TIM8_BKIN, SPI1_MISO,
30 J3 N10 42 P3 52 55 P3 PA6 I/O FT (4) TIM13_CH1, ADC12_IN6
DCMI_PIXCLK, LCD_G2,
EVENTOUT

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STM32F745xx STM32F746xx Pinouts and pin description

Table 10. STM32F745xx and STM32F746xx pin and ball definition (continued)
Pin Number

Pin

I/O structure
Pin type
name
WLCSP143

UFBGA176
TFBGA100

TFBGA216

Notes
Additional
LQFP100

LQFP144

LQFP176

LQFP208
(function Alternate functions
functions
after
reset)(1)

TIM1_CH1N, TIM3_CH2,
TIM8_CH1N,
SPI1_MOSI/I2S1_SD,
TIM14_CH1,
31 K3 L8 43 R3 53 56 R3 PA7 I/O FT (4) ADC12_IN7
ETH_MII_RX_DV/ETH_R
MII_CRS_DV,
FMC_SDNWE,
EVENTOUT
I2S1_MCK,
SPDIFRX_IN2,
32 G4 M8 44 N5 54 57 N5 PC4 I/O FT (4) ETH_MII_RXD0/ETH_RM ADC12_IN14
II_RXD0, FMC_SDNE0,
EVENTOUT
SPDIFRX_IN3,
(4) ETH_MII_RXD1/ETH_RM
33 H4 N9 45 P5 55 58 P5 PC5 I/O FT ADC12_IN15
II_RXD1, FMC_SDCKE0,
EVENTOUT
- - J7 - - - 59 L7 VDD S - - - -
- - - - - - 60 L6 VSS S - - - -
TIM1_CH2N, TIM3_CH3,
TIM8_CH2N,
(4) UART4_CTS, LCD_R3,
34 J4 N8 46 R5 56 61 R5 PB0 I/O FT ADC12_IN8
OTG_HS_ULPI_D1,
ETH_MII_RXD2,
EVENTOUT
TIM1_CH3N, TIM3_CH4,
TIM8_CH3N, LCD_R6,
35 K4 K7 47 R4 57 62 R4 PB1 I/O FT (4) OTG_HS_ULPI_D2, ADC12_IN9
ETH_MII_RXD3,
EVENTOUT
SAI1_SD_A,
SPI3_MOSI/I2S3_SD,
36 G5 L7 48 M6 58 63 M5 PB2 I/O FT - -
QUADSPI_CLK,
EVENTOUT
- - - - - - 64 G4 PI15 I/O FT - LCD_R0, EVENTOUT -
- - - - - - 65 R6 PJ0 I/O FT - LCD_R1, EVENTOUT -
- - - - - - 66 R7 PJ1 I/O FT - LCD_R2, EVENTOUT -

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Table 10. STM32F745xx and STM32F746xx pin and ball definition (continued)
Pin Number

Pin

I/O structure
Pin type
name
WLCSP143

UFBGA176
TFBGA100

TFBGA216

Notes
Additional
LQFP100

LQFP144

LQFP176

LQFP208
(function Alternate functions
functions
after
reset)(1)

- - - - - - 67 P7 PJ2 I/O FT - LCD_R3, EVENTOUT -

- - - - - - 68 N8 PJ3 I/O FT - LCD_R4, EVENTOUT -
- - - - - - 69 M9 PJ4 I/O FT - LCD_R5, EVENTOUT -
SPI5_MOSI, SAI2_SD_B,
- - M7 49 R6 59 70 P8 PF11 I/O FT - FMC_SDNRAS, -
DCMI_D12, EVENTOUT
- - N7 50 P6 60 71 M6 PF12 I/O FT - FMC_A6, EVENTOUT -
- - - 51 M8 61 72 K7 VSS S - - - -
- - - 52 N8 62 73 L8 VDD S - - - -
I2C4_SMBA, FMC_A7,
- - K6 53 N6 63 74 N6 PF13 I/O FT - -
EVENTOUT
I2C4_SCL, FMC_A8,
- - L6 54 R7 64 75 P6 PF14 I/O FT - -
EVENTOUT
I2C4_SDA, FMC_A9,
- - M6 55 P7 65 76 M8 PF15 I/O FT - -
EVENTOUT
- - N6 56 N7 66 77 N7 PG0 I/O FT - FMC_A10, EVENTOUT -
- - K5 57 M7 67 78 M7 PG1 I/O FT - FMC_A11, EVENTOUT -
TIM1_ETR, UART7_Rx,
37 H5 L5 58 R8 68 79 R8 PE7 I/O FT - QUADSPI_BK2_IO0, -
FMC_D4, EVENTOUT
TIM1_CH1N, UART7_Tx,
38 J5 M5 59 P8 69 80 N9 PE8 I/O FT - QUADSPI_BK2_IO1, -
FMC_D5, EVENTOUT
TIM1_CH1, UART7_RTS,
39 K5 N5 60 P9 70 81 P9 PE9 I/O FT - QUADSPI_BK2_IO2, -
FMC_D6, EVENTOUT
- - H3 61 M9 71 82 K8 VSS S - - - -
- - J5 62 N9 72 83 L9 VDD S - - - -
TIM1_CH2N,
UART7_CTS,
40 G6 J4 63 R9 73 84 R9 PE10 I/O FT - -
QUADSPI_BK2_IO3,
FMC_D7, EVENTOUT

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STM32F745xx STM32F746xx Pinouts and pin description

Table 10. STM32F745xx and STM32F746xx pin and ball definition (continued)
Pin Number

Pin

I/O structure
Pin type
name
WLCSP143

UFBGA176
TFBGA100

TFBGA216

Notes
Additional
LQFP100

LQFP144

LQFP176

LQFP208
(function Alternate functions
functions
after
reset)(1)

TIM1_CH2, SPI4_NSS,
41 H6 K4 64 P10 74 85 P10 PE11 I/O FT - SAI2_SD_B, FMC_D8, -
LCD_G3, EVENTOUT
TIM1_CH3N, SPI4_SCK,
42 J6 L4 65 R10 75 86 R10 PE12 I/O FT - SAI2_SCK_B, FMC_D9, -
LCD_B4, EVENTOUT
TIM1_CH3, SPI4_MISO,
43 K6 N4 66 N11 76 87 R12 PE13 I/O FT - SAI2_FS_B, FMC_D10, -
LCD_DE, EVENTOUT
TIM1_CH4, SPI4_MOSI,
44 G7 M4 67 P11 77 88 P11 PE14 I/O FT - SAI2_MCK_B, FMC_D11, -
LCD_CLK, EVENTOUT
TIM1_BKIN, FMC_D12,
45 H7 L3 68 R11 78 89 R11 PE15 I/O FT - -
LCD_R7, EVENTOUT
TIM2_CH3, I2C2_SCL,
SPI2_SCK/I2S2_CK,
USART3_TX,
46 J7 M3 69 R12 79 90 P12 PB10 I/O FT - -
OTG_HS_ULPI_D3,
ETH_MII_RX_ER,
LCD_G4, EVENTOUT
TIM2_CH4, I2C2_SDA,
USART3_RX,
OTG_HS_ULPI_D4,
47 K7 N3 70 R13 80 91 R13 PB11 I/O FT - -
ETH_MII_TX_EN/ETH_R
MII_TX_EN, LCD_G5,
EVENTOUT
48 F8 N2 71 M10 81 92 L11 VCAP_1 S - - - -
49 - H2 - - - 93 K9 VSS S - - - -
50 - J6 72 N10 82 94 L10 VDD S - - - -
- - - - - - 95 M14 PJ5 I/O FT - LCD_R6, EVENTOUT -
I2C2_SMBA, SPI5_SCK,
TIM12_CH1,
- - - - M11 83 96 P13 PH6 I/O FT - ETH_MII_RXD2, -
FMC_SDNE1, DCMI_D8,
EVENTOUT

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Table 10. STM32F745xx and STM32F746xx pin and ball definition (continued)
Pin Number

Pin

I/O structure
Pin type
name
WLCSP143

UFBGA176
TFBGA100

TFBGA216

Notes
Additional
LQFP100

LQFP144

LQFP176

LQFP208
(function Alternate functions
functions
after
reset)(1)

I2C3_SCL, SPI5_MISO,
ETH_MII_RXD3,
- - - - N12 84 97 N13 PH7 I/O FT - -
FMC_SDCKE1,
DCMI_D9, EVENTOUT
I2C3_SDA, FMC_D16,
- - - - M12 85 98 P14 PH8 I/O FT - DCMI_HSYNC, LCD_R2, -
EVENTOUT
I2C3_SMBA,
TIM12_CH2, FMC_D17,
- - - - M13 86 99 N14 PH9 I/O FT - -
DCMI_D0, LCD_R3,
EVENTOUT
TIM5_CH1, I2C4_SMBA,
- - - - L13 87 100 P15 PH10 I/O FT - FMC_D18, DCMI_D1, -
LCD_R4, EVENTOUT
TIM5_CH2, I2C4_SCL,
- - - - L12 88 101 N15 PH11 I/O FT - FMC_D19, DCMI_D2, -
LCD_R5, EVENTOUT
TIM5_CH3, I2C4_SDA,
- - - - K12 89 102 M15 PH12 I/O FT - FMC_D20, DCMI_D3, -
LCD_R6, EVENTOUT
- - - - H12 90 - K10 VSS S - - - -
- - - - J12 91 103 K11 VDD S - - - -
TIM1_BKIN, I2C2_SMBA,
SPI2_NSS/I2S2_WS,
USART3_CK, CAN2_RX,
51 K8 M2 73 P12 92 104 L13 PB12 I/O FT - OTG_HS_ULPI_D5, -
ETH_MII_TXD0/ETH_RM
II_TXD0, OTG_HS_ID,
EVENTOUT
TIM1_CH1N,
SPI2_SCK/I2S2_CK,
USART3_CTS,
OTG_HS_VB
52 J8 N1 74 P13 93 105 K14 PB13 I/O FT - CAN2_TX,
US
OTG_HS_ULPI_D6,
ETH_MII_TXD1/ETH_RM
II_TXD1, EVENTOUT

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STM32F745xx STM32F746xx Pinouts and pin description

Table 10. STM32F745xx and STM32F746xx pin and ball definition (continued)
Pin Number

Pin

I/O structure
Pin type
name
WLCSP143

UFBGA176
TFBGA100

TFBGA216

Notes
Additional
LQFP100

LQFP144

LQFP176

LQFP208
(function Alternate functions
functions
after
reset)(1)

TIM1_CH2N,
TIM8_CH2N,
SPI2_MISO,
53 H10 K3 75 R14 94 106 R14 PB14 I/O FT - USART3_RTS, -
TIM12_CH1,
OTG_HS_DM,
EVENTOUT
RTC_REFIN,
TIM1_CH3N,
TIM8_CH3N,
54 G10 J3 76 R15 95 107 R15 PB15 I/O FT - SPI2_MOSI/I2S2_SD, -
TIM12_CH2,
OTG_HS_DP,
EVENTOUT
USART3_TX,
55 K9 L2 77 P15 96 108 L15 PD8 I/O FT - SPDIFRX_IN11, -
FMC_D13, EVENTOUT
USART3_RX, FMC_D14,
56 J9 M1 78 P14 97 109 L14 PD9 I/O FT - -
EVENTOUT
USART3_CK, FMC_D15,
57 H9 H4 79 N15 98 110 K15 PD10 I/O FT - -
LCD_B3, EVENTOUT
I2C4_SMBA,
USART3_CTS,
QUADSPI_BK1_IO0,
58 G9 K2 80 N14 99 111 N10 PD11 I/O FT - -
SAI2_SD_A,
FMC_A16/FMC_CLE,
EVENTOUT
TIM4_CH1, LPTIM1_IN1,
I2C4_SCL,
USART3_RTS,
59 K10 H6 81 N13 100 112 M10 PD12 I/O FT - QUADSPI_BK1_IO1, -
SAI2_FS_A,
FMC_A17/FMC_ALE,
EVENTOUT
TIM4_CH2,
LPTIM1_OUT, I2C4_SDA,
60 J10 H5 82 M15 101 113 M11 PD13 I/O FT - QUADSPI_BK1_IO3, -
SAI2_SCK_A, FMC_A18,
EVENTOUT

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Table 10. STM32F745xx and STM32F746xx pin and ball definition (continued)
Pin Number

Pin

I/O structure
Pin type
name
WLCSP143

UFBGA176
TFBGA100

TFBGA216

Notes
Additional
LQFP100

LQFP144

LQFP176

LQFP208
(function Alternate functions
functions
after
reset)(1)

- - - 83 - 102 114 J10 VSS S - - - -

- - L1 84 J13 103 115 J11 VDD S - - - -
TIM4_CH3, UART8_CTS,
61 H8 J2 85 M14 104 116 L12 PD14 I/O FT - -
FMC_D0, EVENTOUT
TIM4_CH4, UART8_RTS,
62 G8 K1 86 L14 105 117 K13 PD15 I/O FT - -
FMC_D1, EVENTOUT
- - - - - - 118 K12 PJ6 I/O FT - LCD_R7, EVENTOUT -
- - - - - - 119 J12 PJ7 I/O FT - LCD_G0, EVENTOUT -
- - - - - - 120 H12 PJ8 I/O FT - LCD_G1, EVENTOUT -
- - - - - - 121 J13 PJ9 I/O FT - LCD_G2, EVENTOUT -
- - - - - - 122 H13 PJ10 I/O FT - LCD_G3, EVENTOUT -
- - - - - - 123 G12 PJ11 I/O FT - LCD_G4, EVENTOUT -
- - - - - - 124 H11 VDD S - - - -
- - - - - - 125 H10 VSS S - - - -
- - - - - - 126 G13 PK0 I/O FT - LCD_G5, EVENTOUT -
- - - - - - 127 F12 PK1 I/O FT - LCD_G6, EVENTOUT -
- - - - - - 128 F13 PK2 I/O FT - LCD_G7, EVENTOUT -
- - J1 87 L15 106 129 M13 PG2 I/O FT - FMC_A12, EVENTOUT -
- - G3 88 K15 107 130 M12 PG3 I/O FT - FMC_A13, EVENTOUT -
FMC_A14/FMC_BA0,
- - G5 89 K14 108 131 N12 PG4 I/O FT - -
EVENTOUT
FMC_A15/FMC_BA1,
- - G6 90 K13 109 132 N11 PG5 I/O FT - -
EVENTOUT
DCMI_D12, LCD_R7,
- - G4 91 J15 110 133 J15 PG6 I/O FT - -
EVENTOUT
USART6_CK, FMC_INT,
- - H1 92 J14 111 134 J14 PG7 I/O FT - DCMI_D13, LCD_CLK, -
EVENTOUT

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STM32F745xx STM32F746xx Pinouts and pin description

Table 10. STM32F745xx and STM32F746xx pin and ball definition (continued)
Pin Number

Pin

I/O structure
Pin type
name
WLCSP143

UFBGA176
TFBGA100

TFBGA216

Notes
Additional
LQFP100

LQFP144

LQFP176

LQFP208
(function Alternate functions
functions
after
reset)(1)

SPI6_NSS,
SPDIFRX_IN2,
USART6_RTS,
- - G2 93 H14 112 135 H14 PG8 I/O FT - -
ETH_PPS_OUT,
FMC_SDCLK,
EVENTOUT
- - D2 94 G12 113 136 G10 VSS S - - - -
- F6 G1 95 H13 114 137 G11 VDDUSB S - - - -
TIM3_CH1, TIM8_CH1,
I2S2_MCK, USART6_TX,
63 F10 F2 96 H15 115 138 H15 PC6 I/O FT - SDMMC1_D6, DCMI_D0, -
LCD_HSYNC,
EVENTOUT
TIM3_CH2, TIM8_CH2,
I2S3_MCK, USART6_RX,
64 E10 F3 97 G15 116 139 G15 PC7 I/O FT - -
SDMMC1_D7, DCMI_D1,
LCD_G6, EVENTOUT
TRACED1, TIM3_CH3,
TIM8_CH3, UART5_RTS,
65 F9 E4 98 G14 117 140 G14 PC8 I/O FT - USART6_CK, -
SDMMC1_D0, DCMI_D2,
EVENTOUT
MCO2, TIM3_CH4,
TIM8_CH4, I2C3_SDA,
I2S_CKIN, UART5_CTS,
66 E9 E3 99 F14 118 141 F14 PC9 I/O FT - -
QUADSPI_BK1_IO0,
SDMMC1_D1, DCMI_D3,
EVENTOUT
MCO1, TIM1_CH1,
TIM8_BKIN2, I2C3_SCL,
67 D9 F1 100 F15 119 142 F15 PA8 I/O FT - USART1_CK, -
OTG_FS_SOF, LCD_R6,
EVENTOUT
TIM1_CH2, I2C3_SMBA,
SPI2_SCK/I2S2_CK, OTG_FS_VB
68 C9 E2 101 E15 120 143 E15 PA9 I/O FT -
USART1_TX, DCMI_D0, US
EVENTOUT

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88
Pinouts and pin description STM32F745xx STM32F746xx

Table 10. STM32F745xx and STM32F746xx pin and ball definition (continued)
Pin Number

Pin

I/O structure
Pin type
name
WLCSP143

UFBGA176
TFBGA100

TFBGA216

Notes
Additional
LQFP100

LQFP144

LQFP176

LQFP208
(function Alternate functions
functions
after
reset)(1)

TIM1_CH3, USART1_RX,
69 D10 D5 102 D15 121 144 D15 PA10 I/O FT - OTG_FS_ID, DCMI_D1, -
EVENTOUT
TIM1_CH4,
USART1_CTS,
70 C10 D4 103 C15 122 145 C15 PA11 I/O FT - -
CAN1_RX, OTG_FS_DM,
LCD_R4, EVENTOUT
TIM1_ETR,
USART1_RTS,
71 B10 E1 104 B15 123 146 B15 PA12 I/O FT - SAI2_FS_B, CAN1_TX, -
OTG_FS_DP, LCD_R5,
EVENTOUT
PA13(JT
JTMS-SWDIO,
72 A10 D3 105 A15 124 147 A15 MS- I/O FT - -
EVENTOUT
SWDIO)
73 E7 D1 106 F13 125 148 E11 VCAP_2 S - - - -
74 E5 D2 107 F12 126 149 F10 VSS S - - - -
75 F5 C1 108 G13 127 150 F11 VDD S - - - -
TIM8_CH1N, CAN1_TX,
- - - - E12 128 151 E12 PH13 I/O FT - FMC_D21, LCD_G2, -
EVENTOUT
TIM8_CH2N, FMC_D22,
- - - - E13 129 152 E13 PH14 I/O FT - DCMI_D4, LCD_G3, -
EVENTOUT
TIM8_CH3N, FMC_D23,
- - - - D13 130 153 D13 PH15 I/O FT - DCMI_D11, LCD_G4, -
EVENTOUT
TIM5_CH4,
SPI2_NSS/I2S2_WS,
- - - - E14 131 154 E14 PI0 I/O FT - -
FMC_D24, DCMI_D13,
LCD_G5, EVENTOUT
TIM8_BKIN2,
SPI2_SCK/I2S2_CK,
- - - - D14 132 155 D14 PI1 I/O FT - -
FMC_D25, DCMI_D8,
LCD_G6, EVENTOUT

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STM32F745xx STM32F746xx Pinouts and pin description

Table 10. STM32F745xx and STM32F746xx pin and ball definition (continued)
Pin Number

Pin

I/O structure
Pin type
name
WLCSP143

UFBGA176
TFBGA100

TFBGA216

Notes
Additional
LQFP100

LQFP144

LQFP176

LQFP208
(function Alternate functions
functions
after
reset)(1)

TIM8_CH4, SPI2_MISO,
- - - - C14 133 156 C14 PI2 I/O FT - FMC_D26, DCMI_D9, -
LCD_G7, EVENTOUT
TIM8_ETR,
SPI2_MOSI/I2S2_SD,
- - - - C13 134 157 C13 PI3 I/O FT - -
FMC_D27, DCMI_D10,
EVENTOUT
- - F5 - D9 135 - F9 VSS S - - - -
- - A1 - C9 136 158 E10 VDD S - - - -
PA14(JT
JTCK-SWCLK,
76 A9 B1 109 A14 137 159 A14 CK- I/O FT - -
EVENTOUT
SWCLK)
JTDI,
TIM2_CH1/TIM2_ETR,
HDMI-CEC,
PA15(JT
77 A8 C2 110 A13 138 160 A13 I/O FT - SPI1_NSS/I2S1_WS, -
DI)
SPI3_NSS/I2S3_WS,
UART4_RTS,
EVENTOUT
SPI3_SCK/I2S3_CK,
USART3_TX,
UART4_TX,
78 B9 A2 111 B14 139 161 B14 PC10 I/O FT - -
QUADSPI_BK1_IO1,
SDMMC1_D2, DCMI_D8,
LCD_R2, EVENTOUT
SPI3_MISO,
USART3_RX,
UART4_RX,
79 B8 B2 112 B13 140 162 B13 PC11 I/O FT - -
QUADSPI_BK2_NCS,
SDMMC1_D3, DCMI_D4,
EVENTOUT
TRACED3,
SPI3_MOSI/I2S3_SD,
USART3_CK,
80 C8 C3 113 A12 141 163 A12 PC12 I/O FT - -
UART5_TX,
SDMMC1_CK, DCMI_D9,
EVENTOUT

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88
Pinouts and pin description STM32F745xx STM32F746xx

Table 10. STM32F745xx and STM32F746xx pin and ball definition (continued)
Pin Number

Pin

I/O structure
Pin type
name
WLCSP143

UFBGA176
TFBGA100

TFBGA216

Notes
Additional
LQFP100

LQFP144

LQFP176

LQFP208
(function Alternate functions
functions
after
reset)(1)

CAN1_RX, FMC_D2,
81 D8 B3 114 B12 142 164 B12 PD0 I/O FT - -
EVENTOUT
CAN1_TX, FMC_D3,
82 E8 C4 115 C12 143 165 C12 PD1 I/O FT - -
EVENTOUT
TRACED2, TIM3_ETR,
UART5_RX,
83 B7 A3 116 D12 144 166 D12 PD2 I/O FT - -
SDMMC1_CMD,
DCMI_D11, EVENTOUT
SPI2_SCK/I2S2_CK,
USART2_CTS,
84 C7 B4 117 D11 145 167 C11 PD3 I/O FT - -
FMC_CLK, DCMI_D5,
LCD_G7, EVENTOUT
USART2_RTS,
85 D7 B5 118 D10 146 168 D11 PD4 I/O FT - -
FMC_NOE, EVENTOUT
USART2_TX, FMC_NWE,
86 B6 A4 119 C11 147 169 C10 PD5 I/O FT - -
EVENTOUT
- - - 120 D8 148 170 F8 VSS S - - - -
- - C5 121 C8 149 171 E9 VDD S - - - -
SPI3_MOSI/I2S3_SD,
SAI1_SD_A,
87 C6 F4 122 B11 150 172 B11 PD6 I/O FT - USART2_RX, -
FMC_NWAIT, DCMI_D10,
LCD_B2, EVENTOUT
USART2_CK,
88 D6 A5 123 A11 151 173 A11 PD7 I/O FT - SPDIFRX_IN0, -
FMC_NE1, EVENTOUT
- - - - - - 174 B10 PJ12 I/O FT - LCD_B0, EVENTOUT -
- - - - - - 175 B9 PJ13 I/O FT - LCD_B1, EVENTOUT -
- - - - - - 176 C9 PJ14 I/O FT - LCD_B2, EVENTOUT -
- - - - - - 177 D10 PJ15 I/O FT - LCD_B3, EVENTOUT -

68/227 DocID027590 Rev 4

STM32F745xx STM32F746xx Pinouts and pin description

Table 10. STM32F745xx and STM32F746xx pin and ball definition (continued)
Pin Number

Pin

I/O structure
Pin type
name
WLCSP143

UFBGA176
TFBGA100

TFBGA216

Notes
Additional
LQFP100

LQFP144

LQFP176

LQFP208
(function Alternate functions
functions
after
reset)(1)

SPDIFRX_IN3,
USART6_RX,
QUADSPI_BK2_IO2,
- - E5 124 C10 152 178 D9 PG9 I/O FT - SAI2_FS_B, -
FMC_NE2/FMC_NCE,
DCMI_VSYNC,
EVENTOUT
LCD_G3, SAI2_SD_B,
- - C6 125 B10 153 179 C8 PG10 I/O FT - FMC_NE3, DCMI_D2, -
LCD_B2, EVENTOUT

SPDIFRX_IN0,
ETH_MII_TX_EN/ETH_R
- -- B6 126 B9 154 180 B8 PG11 I/O FT - -
MII_TX_EN, DCMI_D3,
LCD_B3, EVENTOUT

LPTIM1_IN1,
SPI6_MISO,
SPDIFRX_IN1,
- - A6 127 B8 155 181 C7 PG12 I/O FT - -
USART6_RTS, LCD_B4,
FMC_NE4, LCD_B1,
EVENTOUT

TRACED0, LPTIM1_OUT,
SPI6_SCK,
USART6_CTS,
- - D6 128 A8 156 182 B3 PG13 I/O FT - -
ETH_MII_TXD0/ETH_RM
II_TXD0, FMC_A24,
LCD_R0, EVENTOUT
TRACED1, LPTIM1_ETR,
SPI6_MOSI,
USART6_TX,
- - F6 129 A7 157 183 A4 PG14 I/O FT - QUADSPI_BK2_IO3, -
ETH_MII_TXD1/ETH_RM
II_TXD1, FMC_A25,
LCD_B0, EVENTOUT
- - - 130 D7 158 184 F7 VSS S - - - -
- - E6 131 C7 159 185 E8 VDD S - - - -

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88
Pinouts and pin description STM32F745xx STM32F746xx

Table 10. STM32F745xx and STM32F746xx pin and ball definition (continued)
Pin Number

Pin

I/O structure
Pin type
name
WLCSP143

UFBGA176
TFBGA100

TFBGA216

Notes
Additional
LQFP100

LQFP144

LQFP176

LQFP208
(function Alternate functions
functions
after
reset)(1)

- - - - - - 186 D8 PK3 I/O FT - LCD_B4, EVENTOUT -

- - - - - - 187 D7 PK4 I/O FT - LCD_B5, EVENTOUT -
- - - - - - 188 C6 PK5 I/O FT - LCD_B6, EVENTOUT -
- - - - - - 189 C5 PK6 I/O FT - LCD_B7, EVENTOUT -
- - - - - - 190 C4 PK7 I/O FT - LCD_DE, EVENTOUT -
USART6_CTS,
- - A7 132 B7 160 191 B7 PG15 I/O FT - FMC_SDNCAS, -
DCMI_D13, EVENTOUT
JTDO/TRACESWO,
PB3(JTD TIM2_CH2,
89 A7 B7 133 A10 161 192 A10 O/TRAC I/O FT - SPI1_SCK/I2S1_CK, -
ESWO) SPI3_SCK/I2S3_CK,
EVENTOUT

NJTRST, TIM3_CH1,
PB4(NJT SPI1_MISO, SPI3_MISO,
90 A6 C7 134 A9 162 193 A9 I/O FT - -
RST) SPI2_NSS/I2S2_WS,
EVENTOUT

TIM3_CH2, I2C1_SMBA,
SPI1_MOSI/I2S1_SD,
SPI3_MOSI/I2S3_SD,
CAN2_RX,
91 C5 C8 135 A6 163 194 A8 PB5 I/O FT - -
OTG_HS_ULPI_D7,
ETH_PPS_OUT,
FMC_SDCKE1,
DCMI_D10, EVENTOUT
TIM4_CH1, HDMI-CEC,
I2C1_SCL, USART1_TX,
CAN2_TX,
92 B5 A8 136 B6 164 195 B6 PB6 I/O FT - -
QUADSPI_BK1_NCS,
FMC_SDNE1, DCMI_D5,
EVENTOUT

TIM4_CH2, I2C1_SDA,
USART1_RX, FMC_NL,
93 A5 B8 137 B5 165 196 B5 PB7 I/O FT - -
DCMI_VSYNC,
EVENTOUT

94 D5 C9 138 D6 166 197 E6 BOOT I B - - VPP

70/227 DocID027590 Rev 4

STM32F745xx STM32F746xx Pinouts and pin description

Table 10. STM32F745xx and STM32F746xx pin and ball definition (continued)
Pin Number

Pin

I/O structure
Pin type
name
WLCSP143

UFBGA176
TFBGA100

TFBGA216

Notes
Additional
LQFP100

LQFP144

LQFP176

LQFP208
(function Alternate functions
functions
after
reset)(1)

TIM4_CH3, TIM10_CH1,
I2C1_SCL, CAN1_RX,
95 B4 A9 139 A5 167 198 A7 PB8 I/O FT - ETH_MII_TXD3, -
SDMMC1_D4, DCMI_D6,
LCD_B6, EVENTOUT
TIM4_CH4, TIM11_CH1,
I2C1_SDA,
SPI2_NSS/I2S2_WS,
96 A4 B9 140 B4 168 199 B4 PB9 I/O FT - -
CAN1_TX, SDMMC1_D5,
DCMI_D7, LCD_B7,
EVENTOUT
TIM4_ETR,
LPTIM1_ETR,
UART8_Rx,
97 D4 B10 141 A4 169 200 A6 PE0 I/O FT - -
SAI2_MCK_A,
FMC_NBL0, DCMI_D2,
EVENTOUT

LPTIM1_IN2, UART8_Tx,
98 C4 A10 142 A3 170 201 A5 PE1 I/O FT - FMC_NBL1, DCMI_D3, -
EVENTOUT

99 E4 - - D5 - 202 F6 VSS S - - - -
- F7 A11 143 C6 171 203 E5 PDR_ON S - - - -
100 F4 D7 144 C5 172 204 E7 VDD S - - - -
TIM8_BKIN,
SAI2_MCK_A,
- - - - D4 173 205 C3 PI4 I/O FT - -
FMC_NBL2, DCMI_D5,
LCD_B4, EVENTOUT

TIM8_CH1,
SAI2_SCK_A,
- - - - C4 174 206 D3 PI5 I/O FT - FMC_NBL3, -
DCMI_VSYNC, LCD_B5,
EVENTOUT

DocID027590 Rev 4 71/227

88
Pinouts and pin description STM32F745xx STM32F746xx

Table 10. STM32F745xx and STM32F746xx pin and ball definition (continued)
Pin Number

Pin

I/O structure
Pin type
name
WLCSP143

UFBGA176
TFBGA100

TFBGA216

Notes
Additional
LQFP100

LQFP144

LQFP176

LQFP208
(function Alternate functions
functions
after
reset)(1)

TIM8_CH2, SAI2_SD_A,
- - - - C3 175 207 D6 PI6 I/O FT - FMC_D28, DCMI_D6, -
LCD_B6, EVENTOUT

TIM8_CH3, SAI2_FS_A,
- - - - C2 176 208 D4 PI7 I/O FT - FMC_D29, DCMI_D7, -
LCD_B7, EVENTOUT

1. Function availability depends on the chosen device.

2. PC13, PC14, PC15 and PI8 are supplied through the power switch. Since the switch only sinks a limited amount of current
(3 mA), the use of GPIOs PC13 to PC15 and PI8 in output mode is limited:
- The speed should not exceed 2 MHz with a maximum load of 30 pF.
- These I/Os must not be used as a current source (e.g. to drive an LED).
3. Main function after the first backup domain power-up. Later on, it depends on the contents of the RTC registers even after
reset (because these registers are not reset by the main reset). For details on how to manage these I/Os, refer to the RTC
register description sections in the STM32F75xxx and STM32F74xxx reference manual.
4. FT = 5 V tolerant except when in analog mode or oscillator mode (for PC14, PC15, PH0 and PH1).
5. If the device is delivered in an WLCSP143, UFBGA176, LQFP176, TFBGA100 or TFBGA216 package, and the
BYPASS_REG pin is set to VDD (Regulator OFF/internal reset ON mode), then PA0 is used as an internal Reset (active
low).

72/227 DocID027590 Rev 4

 Table 12. STM32F745xx and STM32F746xx alternate function mapping (continued)
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

SAI2/US
Port SPI2/3/U CAN1/2/T SAI2/QU
TIM8/9/10/ ART6/UA FMC/SD
I2C1/2/3/ SPI1/2/3/ SPI3/ SART1/2/ IM12/13/ ADSPI/O ETH/
SYS TIM1/2 TIM3/4/5 11/LPTIM RT4/5/7/8 MMC1/O DCMI LCD SYS
4/CEC 4/5/6 SAI1 3/UART5/ 14/QUAD TG2_HS/ OTG1_FS
1/CEC /SPDIFR TG2_FS
SPDIFRX SPI/LCD OTG1_FS
X

TIM1_ET USART1 SAI2_FS CAN1_T OTG_FS_ EVEN

PA12 - - - - - - - - - LCD_R5
R _RTS _B X DP TOUT

JTMS- EVEN
PA13 - - - - - - - - - - - - - -
SWDIO TOUT
STM32F745xx STM32F746xx

Port A
JTCK- EVEN
PA14 - - - - - - - - - - - - - -
SWCLK TOUT

TIM2_C SPI1_NS SPI3_NS

HDMI- UART4_ EVEN
PA15 JTDI H1/TIM2 - - S/I2S1_ S/I2S3_ - - - - - - -
CEC RTS TOUT
_ETR WS WS

TIM1_C TIM3_C TIM8_CH UART4_ OTG_HS_ ETH_MII_ EVEN

PB0 - - - - - LCD_R3 - - -
H2N H3 2N CTS ULPI_D1 RXD2 TOUT

TIM1_C TIM3_C TIM8_CH OTG_HS_ ETH_MII_ EVEN

PB1 - - - - - - LCD_R6 - - -
H3N H4 3N ULPI_D2 RXD3 TOUT

SPI3_MO
SAI1_SD QUADSP EVEN
PB2 - - - - - - SI/I2S3_ - - - - -
_A I_CLK TOUT
SD

DocID027590 Rev 4
JTDO/T SPI1_SC SPI3_SC
TIM2_C EVEN
PB3 RACES - - - K/I2S1_ K/I2S3_ - - - - - - - -
H2 TOUT
WO CK CK

SPI2_NS
TIM3_C SPI1_MI SPI3_MI EVEN
Port B PB4 NJTRST - - - S/I2S2_ - - - - - - -
H1 SO SO TOUT
WS

SPI1_M SPI3_M
TIM3_C I2C1_SM CAN2_R OTG_HS_ ETH_PPS FMC_SD DCMI_D EVEN
PB5 - - - OSI/I2S1 OSI/I2S3 - - -
H2 BA X ULPI_D7 _OUT CKE1 10 TOUT
_SD _SD

QUADSPI
TIM4_C HDMI- I2C1_SC USART1 CAN2_T FMC_SD DCMI_D EVEN
PB6 - - - - - _BK1_NC - -
H1 CEC L _TX X NE1 5 TOUT
S

TIM4_C I2C1_SD USART1 DCMI_V EVEN

PB7 - - - - - - - - - FMC_NL -
H2 A _RX SYNC TOUT

TIM4_C TIM10_C I2C1_SC CAN1_R ETH_MII_ SDMMC DCMI_D EVEN

PB8 - - - - - - LCD_B6
H3 H1 L X TXD3 1_D4 6 TOUT

77/227
Pinouts and pin description
 Table 12. STM32F745xx and STM32F746xx alternate function mapping (continued)
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

78/227
SAI2/US
Port SPI2/3/U CAN1/2/T SAI2/QU
TIM8/9/10/ ART6/UA FMC/SD
I2C1/2/3/ SPI1/2/3/ SPI3/ SART1/2/ IM12/13/ ADSPI/O ETH/
SYS TIM1/2 TIM3/4/5 11/LPTIM RT4/5/7/8 MMC1/O DCMI LCD SYS
4/CEC 4/5/6 SAI1 3/UART5/ 14/QUAD TG2_HS/ OTG1_FS
1/CEC /SPDIFR TG2_FS
SPDIFRX SPI/LCD OTG1_FS
X

SPI2_NS
TIM4_C TIM11_CH I2C1_SD CAN1_T SDMMC DCMI_D EVEN
PB9 - - S/I2S2_ - - - - - LCD_B7
H4 1 A X 1_D5 7 TOUT
WS

SPI2_SC
TIM2_C I2C2_SC USART3 OTG_HS_ ETH_MII_ EVEN
PB10 - - - K/I2S2_ - - - - - LCD_G4
Pinouts and pin description

H3 L _TX ULPI_D3 RX_ER TOUT

CK

ETH_MII_
TIM2_C I2C2_SD USART3 OTG_HS_ TX_EN/E EVEN
PB11 - - - - - - - - - LCD_G5
H4 A _RX ULPI_D4 TH_RMII_ TOUT
TX_EN

ETH_MII_
SPI2_NS
Port B TIM1_B I2C2_SM USART3 CAN2_R OTG_HS_ TXD0/ET OTG_HS EVEN
PB12 - - - S/I2S2_ - - - -
KIN BA _CK X ULPI_D5 H_RMII_T _ID TOUT
WS
XD0

ETH_MII_
SPI2_SC
TIM1_C USART3 CAN2_T OTG_HS_ TXD1/ET EVEN
PB13 - - - - K/I2S2_ - - - - -
H1N _CTS X ULPI_D6 H_RMII_T TOUT
CK
XD1

DocID027590 Rev 4
TIM1_C TIM8_CH SPI2_MI USART3 TIM12_C OTG_HS EVEN
PB14 - - - - - - - - -
H2N 2N SO _RTS H1 _DM TOUT

SPI2_M
RTC_R TIM1_C TIM8_CH TIM12_C OTG_HS EVEN
PB15 - - OSI/I2S2 - - - - - - -
EFIN H3N 3N H2 _DP TOUT
_SD

OTG_HS_
SAI2_FS FMC_SD EVEN
PC0 - - - - - - - - - ULPI_ST - - LCD_R5
_B NWE TOUT
P

SPI2_M
TRACE SAI1_SD ETH_MD EVEN
PC1 - - - - OSI/I2S2 - - - - - - -
D0 _A C TOUT
_SD
Port C
SPI2_MI OTG_HS_ ETH_MII_ FMC_SD EVEN
PC2 - - - - - - - - - - -
SO ULPI_DIR TXD2 NE0 TOUT

SPI2_M OTG_HS_
ETH_MII_ FMC_SD EVEN
PC3 - - - - - OSI/I2S2 - - - - ULPI_NX - -
TX_CLK CKE0 TOUT
_SD T
STM32F745xx STM32F746xx
 Table 12. STM32F745xx and STM32F746xx alternate function mapping (continued)
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

SAI2/US
Port SPI2/3/U CAN1/2/T SAI2/QU
TIM8/9/10/ ART6/UA FMC/SD
I2C1/2/3/ SPI1/2/3/ SPI3/ SART1/2/ IM12/13/ ADSPI/O ETH/
SYS TIM1/2 TIM3/4/5 11/LPTIM RT4/5/7/8 MMC1/O DCMI LCD SYS
4/CEC 4/5/6 SAI1 3/UART5/ 14/QUAD TG2_HS/ OTG1_FS
1/CEC /SPDIFR TG2_FS
SPDIFRX SPI/LCD OTG1_FS
X

ETH_MII_
I2S1_M SPDIFRX RXD0/ET FMC_SD EVEN
PC4 - - - - - - - - - - -
CK _IN2 H_RMII_ NE0 TOUT
RXD0

ETH_MII_
STM32F745xx STM32F746xx

SPDIFRX RXD1/ET FMC_SD EVEN

PC5 - - - - - - - - - - - -
_IN3 H_RMII_ CKE0 TOUT
RXD1

TIM3_C TIM8_CH I2S2_M USART6 SDMMC DCMI_D LCD_HS EVEN

PC6 - - - - - - - -
H1 1 CK _TX 1_D6 0 YNC TOUT

TIM3_C TIM8_ I2S3_M USART6 SDMMC DCMI_D EVEN

PC7 - - - - - - - - LCD_G6
H2 CH2 CK _RX 1_D7 1 TOUT

TRACE TIM3_C TIM8_ UART5_ USART6 SDMMC DCMI_D EVEN

PC8 - - - - - - - -
D1 H3 CH3 RTS _CK 1_D0 2 TOUT

QUADSP
TIM3_C TIM8_ I2C3_SD I2S_CKI UART5_ SDMMC DCMI_D EVEN
PC9 MCO2 - - - I_BK1_IO - - -
Port C H4 CH4 A N CTS 1_D1 3 TOUT
0

SPI3_SC QUADSP

DocID027590 Rev 4
USART3 UART4_T SDMMC DCMI_D EVEN
PC10 - - - - - - K/I2S3_ I_BK1_IO - - LCD_R2
_TX X 1_D2 8 TOUT
CK 1

QUADSP
SPI3_MI USART3 UART4_ SDMMC DCMI_D EVEN
PC11 - - - - - - I_BK2_N - - -
SO _RX RX 1_D3 4 TOUT
CS

SPI3_M
TRACE USART3 UART5_T SDMMC DCMI_D EVEN
PC12 - - - - - OSI/I2S3 - - - -
D3 _CK X 1_CK 9 TOUT
_SD

EVEN
PC13 - - - - - - - - - - - - - - -
TOUT

EVEN
PC14 - - - - - - - - - - - - - - -
TOUT

EVEN
PC15 - - - - - - - - - - - - - - -
TOUT

79/227
Pinouts and pin description
 Table 12. STM32F745xx and STM32F746xx alternate function mapping (continued)
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

80/227
SAI2/US
Port SPI2/3/U CAN1/2/T SAI2/QU
TIM8/9/10/ ART6/UA FMC/SD
I2C1/2/3/ SPI1/2/3/ SPI3/ SART1/2/ IM12/13/ ADSPI/O ETH/
SYS TIM1/2 TIM3/4/5 11/LPTIM RT4/5/7/8 MMC1/O DCMI LCD SYS
4/CEC 4/5/6 SAI1 3/UART5/ 14/QUAD TG2_HS/ OTG1_FS
1/CEC /SPDIFR TG2_FS
SPDIFRX SPI/LCD OTG1_FS
X

CAN1_R EVEN
PD0 - - - - - - - - - - - FMC_D2 - -
X TOUT

CAN1_T EVEN
PD1 - - - - - - - - - - - FMC_D3 - -
X TOUT
Pinouts and pin description

TRACE TIM3_ET UART5_ SDMMC DCMI_D EVEN

PD2 - - - - - - - - - -
D2 R RX 1_CMD 11 TOUT

SPI2_SC
USART2 FMC_CL DCMI_D EVEN
PD3 - - - - - K/I2S2_ - - - - - LCD_G7
_CTS K 5 TOUT
CK

USART2 FMC_N EVEN

PD4 - - - - - - - - - - - - -
_RTS OE TOUT

USART2 FMC_N EVEN

PD5 - - - - - - - - - - - - -
_TX WE TOUT

SPI3_M
SAI1_SD USART2 FMC_N DCMI_D EVEN
PD6 - - - - - OSI/I2S3 - - - - LCD_B2
_A _RX WAIT 10 TOUT
_SD
Port D
USART2 SPDIFRX FMC_NE EVEN

DocID027590 Rev 4
PD7 - - - - - - - - - - - -
_CK _IN0 1 TOUT

USART3 SPDIFRX FMC_D1 EVEN

PD8 - - - - - - - - - - - -
_TX _IN1 3 TOUT

USART3 FMC_D1 EVEN

PD9 - - - - - - - - - - - - -
_RX 4 TOUT

USART3 FMC_D1 EVEN

PD10 - - - - - - - - - - - - LCD_B3
_CK 5 TOUT

QUADSP FMC_A1
I2C4_SM USART3 SAI2_SD_ EVEN
PD11 - - - - - - - I_BK1_IO - 6/FMC_ - -
BA _CTS A TOUT
0 CLE

QUADSP FMC_A1
TIM4_C LPTIM1_I I2C4_SC USART3 SAI2_FS_ EVEN
PD12 - - - - - I_BK1_IO - 7/FMC_ - -
H1 N1 L _RTS A TOUT
1 ALE

QUADSP
TIM4_C LPTIM1_ I2C4_SD SAI2_SC FMC_A1 EVEN
PD13 - - - - - - I_BK1_IO - - -
H2 OUT A K_A 8 TOUT
3
STM32F745xx STM32F746xx
 Table 12. STM32F745xx and STM32F746xx alternate function mapping (continued)
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

SAI2/US
Port SPI2/3/U CAN1/2/T SAI2/QU
TIM8/9/10/ ART6/UA FMC/SD
I2C1/2/3/ SPI1/2/3/ SPI3/ SART1/2/ IM12/13/ ADSPI/O ETH/
SYS TIM1/2 TIM3/4/5 11/LPTIM RT4/5/7/8 MMC1/O DCMI LCD SYS
4/CEC 4/5/6 SAI1 3/UART5/ 14/QUAD TG2_HS/ OTG1_FS
1/CEC /SPDIFR TG2_FS
SPDIFRX SPI/LCD OTG1_FS
X

TIM4_C UART8_ EVEN

PD14 - - - - - - - - - - FMC_D0 - -
H3 CTS TOUT
Port D
TIM4_C UART8_ EVEN
PD15 - - - - - - - - - - FMC_D1 - -
H4 RTS TOUT
STM32F745xx STM32F746xx

TIM4_ET LPTIM1_E UART8_ SAI2_MC FMC_NB DCMI_D EVEN

PE0 - - - - - - - - -
R TR Rx K_A L0 2 TOUT

LPTIM1_I UART8_T FMC_NB DCMI_D EVEN

PE1 - - - - - - - - - - -
N2 x L1 3 TOUT

QUADSP
TRACE SPI4_SC SAI1_M ETH_MII_ FMC_A2 EVEN
PE2 - - - - - - I_BK1_IO - - -
CLK K CLK_A TXD3 3 TOUT
2

TRACE SAI1_SD FMC_A1 EVEN

PE3 - - - - - - - - - - - -
D0 _B 9 TOUT

TRACE SPI4_NS SAI1_FS FMC_A2 DCMI_D EVEN

PE4 - - - - - - - - - LCD_B0
D1 S _A 0 4 TOUT

TRACE TIM9_CH SPI4_MI SAI1_SC FMC_A2 DCMI_D EVEN

PE5 - - - - - - - - LCD_G0
D2 1 SO K_A 1 6 TOUT

DocID027590 Rev 4
TRACE TIM1_B TIM9_CH SPI4_M SAI1_SD SAI2_MC FMC_A2 DCMI_D EVEN
PE6 - - - - - - LCD_G1
Port E D3 KIN2 2 OSI _A K_B 2 7 TOUT

TIM1_ET UART7_ QUADSPI EVEN

PE7 - - - - - - - - - FMC_D4 - -
R Rx _BK2_IO0 TOUT

TIM1_C UART7_T QUADSPI EVEN

PE8 - - - - - - - - - FMC_D5 - -
H1N x _BK2_IO1 TOUT

TIM1_C UART7_ QUADSPI EVEN

PE9 - - - - - - - - - FMC_D6 - -
H1 RTS _BK2_IO2 TOUT

TIM1_C UART7_ QUADSPI EVEN

PE10 - - - - - - - - - FMC_D7 - -
H2N CTS _BK2_IO3 TOUT

TIM1_C SPI4_NS SAI2_SD_ EVEN

PE11 - - - - - - - - - FMC_D8 - LCD_G3
H2 S B TOUT

TIM1_C SPI4_SC SAI2_SC EVEN

PE12 - - - - - - - - - FMC_D9 - LCD_B4
H3N K K_B TOUT

TIM1_C SPI4_MI SAI2_FS_ FMC_D1 EVEN

PE13 - - - - - - - - - - LCD_DE
H3 SO B 0 TOUT

81/227
Pinouts and pin description
 Table 12. STM32F745xx and STM32F746xx alternate function mapping (continued)
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

82/227
SAI2/US
Port SPI2/3/U CAN1/2/T SAI2/QU
TIM8/9/10/ ART6/UA FMC/SD
I2C1/2/3/ SPI1/2/3/ SPI3/ SART1/2/ IM12/13/ ADSPI/O ETH/
SYS TIM1/2 TIM3/4/5 11/LPTIM RT4/5/7/8 MMC1/O DCMI LCD SYS
4/CEC 4/5/6 SAI1 3/UART5/ 14/QUAD TG2_HS/ OTG1_FS
1/CEC /SPDIFR TG2_FS
SPDIFRX SPI/LCD OTG1_FS
X

TIM1_C SPI4_M SAI2_MC FMC_D1 LCD_CL EVEN

PE14 - - - - - - - - - -
H4 OSI K_B 1 K TOUT
Port E
TIM1_B FMC_D1 EVEN
PE15 - - - - - - - - - - - - LCD_R7
KIN 2 TOUT
Pinouts and pin description

I2C2_SD EVEN
PF0 - - - - - - - - - - - FMC_A0 - -
A TOUT

I2C2_SC EVEN
PF1 - - - - - - - - - - - FMC_A1 - -
L TOUT

I2C2_SM EVEN
PF2 - - - - - - - - - - - FMC_A2 - -
BA TOUT

EVEN
PF3 - - - - - - - - - - - - FMC_A3 - -
TOUT

EVEN
PF4 - - - - - - - - - - - - FMC_A4 - -
TOUT

EVEN
PF5 - - - - - - - - - - - - FMC_A5 - -
TOUT

DocID027590 Rev 4
QUADSP
TIM10_C SPI5_NS SAI1_SD UART7_ EVEN
PF6 - - - - - I_BK1_IO - - - - -
Port F H1 S _B Rx TOUT
3

QUADSP
TIM11_CH SPI5_SC SAI1_M UART7_T EVEN
PF7 - - - - - I_BK1_IO - - - - -
1 K CLK_B x TOUT
2

SPI5_MI SAI1_SC UART7_ TIM13_C QUADSPI EVEN

PF8 - - - - - - - - - -
SO K_B RTS H1 _BK1_IO0 TOUT

SPI5_M SAI1_FS UART7_ TIM14_C QUADSPI EVEN

PF9 - - - - - - - - - -
OSI _B CTS H1 _BK1_IO1 TOUT

DCMI_D EVEN
PF10 - - - - - - - - - - - - - LCD_DE
11 TOUT

SPI5_M SAI2_SD_ FMC_SD DCMI_D EVEN

PF11 - - - - - - - - - - -
OSI B NRAS 12 TOUT

EVEN
PF12 - - - - - - - - - - - - FMC_A6 - -
TOUT
STM32F745xx STM32F746xx
 Table 12. STM32F745xx and STM32F746xx alternate function mapping (continued)
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

SAI2/US
Port SPI2/3/U CAN1/2/T SAI2/QU
TIM8/9/10/ ART6/UA FMC/SD
I2C1/2/3/ SPI1/2/3/ SPI3/ SART1/2/ IM12/13/ ADSPI/O ETH/
SYS TIM1/2 TIM3/4/5 11/LPTIM RT4/5/7/8 MMC1/O DCMI LCD SYS
4/CEC 4/5/6 SAI1 3/UART5/ 14/QUAD TG2_HS/ OTG1_FS
1/CEC /SPDIFR TG2_FS
SPDIFRX SPI/LCD OTG1_FS
X

I2C4_SM EVEN
PF13 - - - - - - - - - - - FMC_A7 - -
BA TOUT

I2C4_SC EVEN
Port F PF14 - - - - - - - - - - - FMC_A8 - -
L TOUT
STM32F745xx STM32F746xx

I2C4_SD EVEN
PF15 - - - - - - - - - - - FMC_A9 - -
A TOUT

FMC_A1 EVEN
PG0 - - - - - - - - - - - - - -
0 TOUT

FMC_A1 EVEN
PG1 - - - - - - - - - - - - - -
1 TOUT

FMC_A1 EVEN
PG2 - - - - - - - - - - - - - -
2 TOUT

FMC_A1 EVEN
PG3 - - - - - - - - - - - - - -
3 TOUT

FMC_A1
EVEN
PG4 - - - - - - - - - - - - 4/FMC_ - -
TOUT
BA0

DocID027590 Rev 4
FMC_A1
EVEN
Port G PG5 - - - - - - - - - - - - 5/FMC_ - -
TOUT
BA1

DCMI_D EVEN
PG6 - - - - - - - - - - - - - LCD_R7
12 TOUT

USART6 FMC_IN DCMI_D LCD_CL EVEN

PG7 - - - - - - - - - - -
_CK T 13 K TOUT

SPI6_NS SPDIFRX USART6 ETH_PPS FMC_SD EVEN

PG8 - - - - - - - - - -
S _IN2 _RTS _OUT CLK TOUT

QUADSP FMC_NE
SPDIFRX USART6 SAI2_FS_ DCMI_V EVEN
PG9 - - - - - - - I_BK2_IO - 2/FMC_ -
_IN3 _RX B SYNC TOUT
2 NCE

SAI2_SD_ FMC_NE DCMI_D EVEN

PG10 - - - - - - - - - LCD_G3 - LCD_B2
B 3 2 TOUT

83/227
Pinouts and pin description
 Table 12. STM32F745xx and STM32F746xx alternate function mapping (continued)
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

84/227
SAI2/US
Port SPI2/3/U CAN1/2/T SAI2/QU
TIM8/9/10/ ART6/UA FMC/SD
I2C1/2/3/ SPI1/2/3/ SPI3/ SART1/2/ IM12/13/ ADSPI/O ETH/
SYS TIM1/2 TIM3/4/5 11/LPTIM RT4/5/7/8 MMC1/O DCMI LCD SYS
4/CEC 4/5/6 SAI1 3/UART5/ 14/QUAD TG2_HS/ OTG1_FS
1/CEC /SPDIFR TG2_FS
SPDIFRX SPI/LCD OTG1_FS
X

ETH_MII_
SPDIFRX TX_EN/E DCMI_D EVEN
PG11 - - - - - - - - - - - LCD_B3
_IN0 TH_RMII_ 3 TOUT
TX_EN

LPTIM1_I SPI6_MI SPDIFRX USART6 FMC_NE EVEN

Pinouts and pin description

PG12 - - - - - LCD_B4 - - - LCD_B1

N1 SO _IN1 _RTS 4 TOUT

ETH_MII_
TRACE LPTIM1_ SPI6_SC USART6 TXD0/ET FMC_A2 EVEN
Port G PG13 - - - - - - - - LCD_R0
D0 OUT K _CTS H_RMII_T 4 TOUT
XD0

ETH_MII_
QUADSP
TRACE LPTIM1_E SPI6_M USART6 TXD1/ET FMC_A2 EVEN
PG14 - - - - - I_BK2_IO - - LCD_B0
D1 TR OSI _TX H_RMII_T 5 TOUT
3
XD1

USART6 FMC_SD DCMI_D EVEN

PG15 - - - - - - - - - - - -
_CTS NCAS 13 TOUT

EVEN
PH0 - - - - - - - - - - - - - - -
TOUT

DocID027590 Rev 4
EVEN
PH1 - - - - - - - - - - - - - - -
TOUT

QUADSP
LPTIM1_I SAI2_SC ETH_MII_ FMC_SD EVEN
PH2 - - - - - - - - I_BK2_IO - LCD_R0
N2 K_B CRS CKE0 TOUT
0

QUADSP
SAI2_MC ETH_MII_ FMC_SD EVEN
PH3 - - - - - - - - - I_BK2_IO - LCD_R1
K_B COL NE0 TOUT
1
Port H
OTG_HS_
I2C2_SC EVEN
PH4 - - - - - - - - - ULPI_NX - - - -
L TOUT
T

I2C2_SD SPI5_NS FMC_SD EVEN

PH5 - - - - - - - - - - - -
A S NWE TOUT

I2C2_SM SPI5_SC TIM12_C ETH_MII_ FMC_SD DCMI_D EVEN

PH6 - - - - - - - - -
BA K H1 RXD2 NE1 8 TOUT

I2C3_SC SPI5_MI ETH_MII_ FMC_SD DCMI_D EVEN

PH7 - - - - - - - - - -
L SO RXD3 CKE1 9 TOUT
STM32F745xx STM32F746xx
 Table 12. STM32F745xx and STM32F746xx alternate function mapping (continued)
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

SAI2/US
Port SPI2/3/U CAN1/2/T SAI2/QU
TIM8/9/10/ ART6/UA FMC/SD
I2C1/2/3/ SPI1/2/3/ SPI3/ SART1/2/ IM12/13/ ADSPI/O ETH/
SYS TIM1/2 TIM3/4/5 11/LPTIM RT4/5/7/8 MMC1/O DCMI LCD SYS
4/CEC 4/5/6 SAI1 3/UART5/ 14/QUAD TG2_HS/ OTG1_FS
1/CEC /SPDIFR TG2_FS
SPDIFRX SPI/LCD OTG1_FS
X

I2C3_SD FMC_D1 DCMI_H EVEN

PH8 - - - - - - - - - - - LCD_R2
A 6 SYNC TOUT

I2C3_SM TIM12_C FMC_D1 DCMI_D EVEN

PH9 - - - - - - - - - - LCD_R3
BA H2 7 0 TOUT
STM32F745xx STM32F746xx

TIM5_C I2C4_SM FMC_D1 DCMI_D EVEN

PH10 - - - - - - - - - - LCD_R4
H1 BA 8 1 TOUT

TIM5_C I2C4_SC FMC_D1 DCMI_D EVEN

PH11 - - - - - - - - - - LCD_R5
H2 L 9 2 TOUT
Port H
TIM5_C I2C4_SD FMC_D2 DCMI_D EVEN
PH12 - - - - - - - - - - LCD_R6
H3 A 0 3 TOUT

TIM8_CH CAN1_T FMC_D2 EVEN

PH13 - - - - - - - - - - - LCD_G2
1N X 1 TOUT

TIM8_CH FMC_D2 DCMI_D EVEN

PH14 - - - - - - - - - - - LCD_G3
2N 2 4 TOUT

TIM8_CH FMC_D2 DCMI_D EVEN

PH15 - - - - - - - - - - - LCD_G4
3N 3 11 TOUT

DocID027590 Rev 4
SPI2_NS
TIM5_C FMC_D2 DCMI_D EVEN
PI0 - - - - S/I2S2_ - - - - - - LCD_G5
H4 4 13 TOUT
WS

SPI2_SC
TIM8_BKI FMC_D2 DCMI_D EVEN
PI1 - - - - K/I2S2_ - - - - - - LCD_G6
N2 5 8 TOUT
CK

TIM8_CH SPI2_MI FMC_D2 DCMI_D EVEN

PI2 - - - - - - - - - - LCD_G7
4 SO 6 9 TOUT

Port I SPI2_M
TIM8_ET FMC_D2 DCMI_D EVEN
PI3 - - - - OSI/I2S2 - - - - - - -
R 7 10 TOUT
_SD

TIM8_BKI SAI2_MC FMC_NB DCMI_D EVEN

PI4 - - - - - - - - - - LCD_B4
N K_A L2 5 TOUT

TIM8_CH SAI2_SC FMC_NB DCMI_V EVEN

PI5 - - - - - - - - - - LCD_B5
1 K_A L3 SYNC TOUT

TIM8_CH SAI2_SD_ FMC_D2 DCMI_D EVEN

PI6 - - - - - - - - - - LCD_B6
2 A 8 6 TOUT

85/227
Pinouts and pin description
 Table 12. STM32F745xx and STM32F746xx alternate function mapping (continued)
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

86/227
SAI2/US
Port SPI2/3/U CAN1/2/T SAI2/QU
TIM8/9/10/ ART6/UA FMC/SD
I2C1/2/3/ SPI1/2/3/ SPI3/ SART1/2/ IM12/13/ ADSPI/O ETH/
SYS TIM1/2 TIM3/4/5 11/LPTIM RT4/5/7/8 MMC1/O DCMI LCD SYS
4/CEC 4/5/6 SAI1 3/UART5/ 14/QUAD TG2_HS/ OTG1_FS
1/CEC /SPDIFR TG2_FS
SPDIFRX SPI/LCD OTG1_FS
X

TIM8_CH SAI2_FS_ FMC_D2 DCMI_D EVEN

PI7 - - - - - - - - - - LCD_B7
3 A 9 7 TOUT

EVEN
PI8 - - - - - - - - - - - - - - -
TOUT
Pinouts and pin description

CAN1_R FMC_D3 LCD_VS EVEN

PI9 - - - - - - - - - - - -
X 0 YNC TOUT

ETH_MII_ FMC_D3 LCD_HS EVEN

PI10 - - - - - - - - - - - -
RX_ER 1 YNC TOUT

OTG_HS_ EVEN
Port I PI11 - - - - - - - - - - - - - -
ULPI_DIR TOUT

LCD_HS EVEN
PI12 - - - - - - - - - - - - - -
YNC TOUT

LCD_VS EVEN
PI13 - - - - - - - - - - - - - -
YNC TOUT

LCD_CL EVEN
PI14 - - - - - - - - - - - - - -
K TOUT

DocID027590 Rev 4
EVEN
PI15 - - - - - - - - - - - - - - LCD_R0
TOUT

EVEN
PJ0 - - - - - - - - - - - - - - LCD_R1
TOUT

EVEN
PJ1 - - - - - - - - - - - - - - LCD_R2
TOUT

EVEN
PJ2 - - - - - - - - - - - - - - LCD_R3
TOUT

EVEN
Port J PJ3 - - - - - - - - - - - - - - LCD_R4
TOUT

EVEN
PJ4 - - - - - - - - - - - - - - LCD_R5
TOUT

EVEN
PJ5 - - - - - - - - - - - - - - LCD_R6
TOUT

EVEN
PJ6 - - - - - - - - - - - - - - LCD_R7
TOUT
STM32F745xx STM32F746xx
 Table 12. STM32F745xx and STM32F746xx alternate function mapping (continued)
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

SAI2/US
Port SPI2/3/U CAN1/2/T SAI2/QU
TIM8/9/10/ ART6/UA FMC/SD
I2C1/2/3/ SPI1/2/3/ SPI3/ SART1/2/ IM12/13/ ADSPI/O ETH/
SYS TIM1/2 TIM3/4/5 11/LPTIM RT4/5/7/8 MMC1/O DCMI LCD SYS
4/CEC 4/5/6 SAI1 3/UART5/ 14/QUAD TG2_HS/ OTG1_FS
1/CEC /SPDIFR TG2_FS
SPDIFRX SPI/LCD OTG1_FS
X

EVEN
PJ7 - - - - - - - - - - - - - - LCD_G0
TOUT

EVEN
PJ8 - - - - - - - - - - - - - - LCD_G1
TOUT
STM32F745xx STM32F746xx

EVEN
PJ9 - - - - - - - - - - - - - - LCD_G2
TOUT

EVEN
PJ10 - - - - - - - - - - - - - - LCD_G3
TOUT

Port J EVEN
PJ11 - - - - - - - - - - - - - - LCD_G4
TOUT

EVEN
PJ12 - - - - - - - - - - - - - - LCD_B0
TOUT

EVEN
PJ13 - - - - - - - - - - - - - - LCD_B1
TOUT

EVEN
PJ14 - - - - - - - - - - - - - - LCD_B2
TOUT

DocID027590 Rev 4
EVEN
PJ15 - - - - - - - - - - - - - - LCD_B3
TOUT

87/227
Pinouts and pin description
 Table 12. STM32F745xx and STM32F746xx alternate function mapping (continued)
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

88/227
SAI2/US
Port SPI2/3/U CAN1/2/T SAI2/QU
TIM8/9/10/ ART6/UA FMC/SD
I2C1/2/3/ SPI1/2/3/ SPI3/ SART1/2/ IM12/13/ ADSPI/O ETH/
SYS TIM1/2 TIM3/4/5 11/LPTIM RT4/5/7/8 MMC1/O DCMI LCD SYS
4/CEC 4/5/6 SAI1 3/UART5/ 14/QUAD TG2_HS/ OTG1_FS
1/CEC /SPDIFR TG2_FS
SPDIFRX SPI/LCD OTG1_FS
X

EVEN
PK0 - - - - - - - - - - - - - - LCD_G5
TOUT

EVEN
PK1 - - - - - - - - - - - - - - LCD_G6
TOUT
Pinouts and pin description

EVEN
PK2 - - - - - - - - - - - - - - LCD_G7
TOUT

EVEN
PK3 - - - - - - - - - - - - - - LCD_B4
TOUT
Port K
EVEN
PK4 - - - - - - - - - - - - - - LCD_B5
TOUT

EVEN
PK5 - - - - - - - - - - - - - - LCD_B6
TOUT

EVEN
PK6 - - - - - - - - - - - - - - LCD_B7
TOUT

EVEN
PK7 - - - - - - - - - - - - - - LCD_DE
TOUT

DocID027590 Rev 4
STM32F745xx STM32F746xx
Direct memory access controller (DMA) RM0385

The 8 requests from the peripherals (such as TIM, ADC, SPI, I2C) are independently
connected to each channel and their connection depends on the product implementation.
Table 24 and Table 25 give examples of DMA request mappings.

Table 24. DMA1 request mapping

Peripheral
Stream 0 Stream 1 Stream 2 Stream 3 Stream 4 Stream 5 Stream 6 Stream 7
requests
Channel 0 SPI3_RX SPDIFRX_DT SPI3_RX SPI2_RX SPI2_TX SPI3_TX SPDIFRX_CS SPI3_TX

Channel 1 I2C1_RX I2C3_RX TIM7_UP - TIM7_UP I2C1_RX I2C1_TX I2C1_TX

Channel 2 TIM4_CH1 - I2C4_RX TIM4_CH2 - I2C4_RX TIM4_UP TIM4_CH3

TIM2_UP TIM2_CH2 TIM2_UP

Channel 3 - I2C3_RX - I2C3_TX TIM2_CH1
TIM2_CH3 TIM2_CH4 TIM2_CH4

Channel 4 UART5_RX USART3_RX UART4_RX USART3_TX UART4_TX USART2_RX USART2_TX UART5_TX

TIM3_CH4 TIM3_CH1
Channel 5 UART8_TX UART7_TX UART7_RX TIM3_CH2 UART8_RX TIM3_CH3
TIM3_UP TIM3_TRIG

TIM5_CH3 TIM5_CH4 TIM5_CH4

Channel 6 TIM5_CH1 TIM5_CH2 - TIM5_UP -
TIM5_UP TIM5_TRIG TIM5_TRIG

Channel 7 TIM6_UP I2C2_RX I2C2_RX USART3_TX DAC1 DAC2 I2C2_TX

Table 25. DMA2 request mapping

Peripheral
Stream 0 Stream 1 Stream 2 Stream 3 Stream 4 Stream 5 Stream 6 Stream 7
requests
TIM8_CH1 TIM1_CH1
Channel 0 ADC1 SAI1_A TIM8_CH2 SAI1_A ADC1 SAI1_B TIM1_CH2 SAI2_B
TIM8_CH3 TIM1_CH3

Channel 1 - DCMI ADC2 ADC2 SAI1_B SPI6_TX SPI6_RX DCMI

Channel 2 ADC3 ADC3 - SPI5_RX SPI5_TX CRYP_OUT CRYP_IN HASH_IN

Channel 3 SPI1_RX - SPI1_RX SPI1_TX SAI2_A SPI1_TX SAI2_B QUADSPI

Channel 4 SPI4_RX SPI4_TX USART1_RX SDMMC1 - USART1_RX SDMMC1 USART1_TX

Channel 5 - USART6_RX USART6_RX SPI4_RX SPI4_TX - USART6_TX USART6_TX

TIM1_CH4
Channel 6 TIM1_TRIG TIM1_CH1 TIM1_CH2 TIM1_CH1 TIM1_TRIG TIM1_UP TIM1_CH3 -
TIM1_COM

TIM8_CH4
Channel 7 - TIM8_UP TIM8_CH1 TIM8_CH2 TIM8_CH3 SPI5_RX SPI5_TX TIM8_TRIG
TIM8_COM

226/1709 RM0385 Rev 7