Microelectronics Journal 45 (2014) 578–588

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Microelectronics Journal
journal homepage: www.elsevier.com/locate/mejo

A fully integrated analog front-end circuit for 13.56 MHz passive RFID
tags in conformance with ISO/IEC 18000-3 protocol
Jian Zhang a, Wei Zhang a, Yanyan Liu b,n
a
School of Electronic Information Engineering, Tianjin University, 92th Weijin Road, Tianjin 300072, China
b
School of Electronic Information and Optical Engineering, Nankai University, 94th Weijin Road, Tianjin 300071, China

art ic l e i nf o a b s t r a c t

Article history: A fully integrated analog front-end circuit for 13.56 MHz passive RFID tags is presented in this paper. The
Received 7 November 2013 design of the RF analog front-end and digital control is based on ISO/IEC 18000-3 MODE 1 protocol. This
Received in revised form paper mainly focuses on RF analog front-end circuits. In order to supply voltage for the whole tag chip,
20 March 2014
a high efficiency power management circuit with a rather wide input range is proposed by utilizing
Accepted 24 March 2014
15.5 V high voltage MOS transistors. Furthermore, a high sensitivity, low power consumption 10% ASK
Available online 4 May 2014
demodulator with a subthreshold-mode hysteresis comparator is introduced for reader-to-tag commu-
Keywords: nication. The tag chip is fabricated in 0.18-μm 2-poly 5-metal mixed signal CMOS technology with
RFID tags EEPROM process. An on-chip 1 kb EEPROM is used to support tag identification, data writing and
Analog front-end
reading. The core size of the analog front-end is only 0.94
0.84 mm2 with a power consumption of
Power management
0.42 mW. Measured results show that the power management circuit is able to maintain a proper
ASK demodulator
working condition with an input antenna voltage range of 5.82–12.3 V; the maximum voltage conversion
ratio of the rectifier reaches 65.92% when the tag antenna voltage is 9.42 V. Moreover, the power
consumption of the 10% ASK demodulator is only 690.25 nW.
& 2014 Elsevier Ltd. All rights reserved.

1. Introduction relatively greater compatibility and can support more tags operat-
ing simultaneously.
Radio frequency identification (RFID) is a technology which is In this paper, an analog front-end circuit of a 13.56 MHz passive
widely used in many applications today, including supply chain RFID tag complying with ISO/IEC 18000-3 protocol is designed and
management, personal identification, theft detection, air and train fabricated. This paper mainly presents detailed design considera-
package and intelligent transportation [1,2]. Compared with other tions of the proposed power management circuit and 10% ASK
frequency band systems, applications of HF-band passive system demodulation circuit. Specifically, this paper is organized as
are most widely used. For tags' designers, low power consumption follows. Section 2 describes the RF link of the HF-band system
and small size design is the developing trend of today's RFID tag and the system architecture of the proposed analog front-end.
chips, since power consumption decides the tag chip sensitivity Section 3 presents the design of the power management circuit in
(higher sensitivity means longer detection distance of the tag chip) detail. Section 4 presents the analysis and design of the proposed
while size determines manufacturing costs. ASK demodulators. Measurement results are shown in Section 5.
At present, the international standard protocols for 13.56 MHz Finally, conclusions are drawn in Section 6.
RFID system are ISO/IEC 14443, ISO/IEC 15693 and ISO/IEC 18000-3.
ISO/IEC 18000-3 protocol is recently proposed for item manage-
ment. Besides, ISO/IEC 18000-3 provides physical layer, collision 2. RF link and system architecture
management system and protocol values for RFID systems for item
identification operating at 13.56 MHz [3]. This new protocol has a Unlike active tags which are energized by battery, the passive HF-
band RFID tags are energized by a time-varying electromagnetic RF
wave which is transmitted from the reader. HF-band system adopts
inductive coupling to collect power, clock and data. Fig. 1 shows the
n
Corresponding author. Tel.: þ 86 22 23498590.
inductive coupling model between the reader and tag. The tag
E-mail addresses: [email protected] (J. Zhang), antenna inductor Ltag and an off-chip capacitor Ctag form the RF tank
[email protected] (W. Zhang), [email protected] (Y. Liu). circuit with the resonant frequency f (13.56 MHz). The mutual

http://dx.doi.org/10.1016/j.mejo.2014.03.013
0026-2692/& 2014 Elsevier Ltd. All rights reserved.
 J. Zhang et al. / Microelectronics Journal 45 (2014) 578–588 579

pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
inductance M between the reader and tag is Rload Ltag =C tag
Vamp ¼ 2π f NQ AμH cos α ¼ 2π f NAμH cos α
Rtag Rload þ R2tag þ Ltag =Ctag
k
M ¼ pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ð1Þ ð7Þ
Lreader Ltag
where N is the turns of the tag antenna, f is 13.56 MHz, Q is the quality
where k is the coupling factor, which can be calculated by factor of the resonant circuit, A is the area of the tag antenna, B is the
magnetic induction, α is the angle between the reader and tag
r 2reader r 2tag
kðDÞ  qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi3 ð2Þ antennas, H is the magnetic field intensity, μ is the permeability, and
pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi Rload is the equivalent load resistance of the tag chip.
r reader r tag D2 þr 2reader
According to test methods (ISO/IEC DTR 18047-3) for ISO/IEC
18000-3 protocol, A is 77
47 mm2, N is 4. H is between 150 mA/m
where rreader and rtag are the radii of the reader and tag antennas,
(rms) and 5 A/m (rms). When the angle α is 0, the voltage
respectively, and D is the distance between the reader and tag
amplitude range of the tag antenna is
antennas [4].
Based on the principle of electromagnetic induction, the voltage 0:33Q rV amp r 10:95Q ð8Þ
amplitude Vamp of the tag antenna is At 13.56 MHz the nominal inductance Ltag is 3.5 μH and the
R  nominal resistance Rtag is 1 Ω [5]. From Eq. (6), the quality factor Q
dψ d BdS
V amp ¼ N ¼N ¼ 2π f NQ AB cos α ð3Þ is mainly decided by Ctag and Rload. However, the voltage amplitude
dt dt
range of the tag antenna obtained from Eq. (8) is based on an ideal
model. In fact, the energy propagation loss in the air, the distance
B ¼ μH ð4Þ between the reader and tag and other factors can further reduce
the voltage amplitude Vamp.
1 Fig. 2 shows the block diagram of the proposed RFID transpon-
f¼ pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ð5Þ
2π Ltag C tag der. The system is mainly composed of three sections, named
antenna and resonant circuit, analog front end and digital signal
pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
Rload Ltag =C tag processing unit. Antenna1 and Antenna2 are two ports connected
Q¼ ð6Þ to the tag antenna coil. The antenna (inductor Ltag) and the
Rtag Rload þ R2tag þ Ltag =Ctag
capacitor Ctag are external components to form the resonant circuit
in order to ensure that the tag chip can obtain sufficient power
supply.
The analog front-end is the key section to determine the
performance of the whole tag chip. The rectifier converts the
incoming RF power gained from the reader to a DC voltage.
A storage capacitor C1 exists to store and supply power for the
whole chip when the tag chip receives 100% ASK RF signal.
A bandgap reference and two regulators form the voltage gen-
erator, thus generating precise and stable VCC for analog front-end
Fig. 1. Inductive coupling model between the reader and tag. power supply and VDD for digital unit power supply respectively.

Fig. 2. Block diagram of the proposed RFID transponder.

580 J. Zhang et al. / Microelectronics Journal 45 (2014) 578–588

ISO/IEC 18000-3 MODE 1 HF RFID standard uses 10% and 100% ASK Since the rectifier is a unique module to supply power for the
modulation for the reader-to-tag communication; therefore the rest of the chip, the voltage conversion ratio (VCR) and the power
10% ASK demodulator and the 100% ASK demodulator are aimed to conversion efficiency (PCE) are two important indices to measure
extract the 10% ASK data and the 100% ASK data respectively from its performance. The voltage conversion ratio is defined as the
the RF carrier, the control logic block decides which one of the two ratio of average output voltage to the magnitude of AC input
demodulators is operating. The clock extractor provides clock data voltage. The power conversion efficiency is defined as the ratio of
for the digital signal processing unit. The reset circuit is capable of the output DC power to the input RF power.
detecting power-on reset signal and power-off signal. Load mod-
V OUT  av
ulation technology is utilized to send data back to the reader. VCR ¼ ð9Þ
jV IN j
R
P OUT uOUT iOUT dt
3. Power management block PCE ¼
100% ¼ R
100% ð10Þ
P IN uIN iIN dt

In this section, a power management circuit composed of a full- For this rectifier, the output voltage VHOLD can be approximately
wave bridge rectifier, a current-mode bandgap reference and two expressed as
voltage regulators is proposed to supply voltage for the whole tag pffiffiffi
V HOLD ¼ 0:9V amp = 2  V TH ð11Þ
chip. For all conventional HF-band RFID tags, an amplitude limit-
ing circuit is generally designed in power management circuit to where Vamp is the voltage amplitude between the antenna, while
limit the antenna voltage in case of the damage to internal circuits VTH is the threshold voltage of M2 or M3. This structure will start
caused by strong electromagnetic field strength. For instance, a RF to work only when the input level exceeds two times the NMOS
limiter which consists of two diode stacks, a resistor and a large threshold voltage which is around 0.71 V for 15.5 V high voltage
periphery shunting transistor is proposed in [6], while a clamping NMOS transistors. The dropout voltage in the rectifier block is
circuit composed of four diode-connected PMOS transistors, two mainly caused by VTH. However, VTH is a variable and can vary
resistors and two large shunting NMOS transistors is introduced significantly with body effect.
in [7]. Although all RF voltage limiters can protect the internal qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi qffiffiffiffiffiffiffiffiffiffiffiffiffi
   
circuits from being damaged under high RF power, they usually V TH ¼ V TH0 þ γ 2ΦF þ V SB   2ΦF  ð12Þ
occupy a large area by utilizing large shunting transistors; how-
ever a small size is significant for the tag to lower its cost to a few
V SB ¼ V HOLD ð13Þ
cents for wide applications [8]. In this paper, the RF amplitude
limiting circuit is replaced by utilizing 15.5 V high voltage then VTH can be described as
MOS transistors in RF interface circuits. Furthermore, by cutting qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi qffiffiffiffiffiffiffiffiffiffiffiffiffi
   
down the RF limiter, the size of the tag chip decreases by V TH ¼ V TH0 þ γ 2ΦF þ V HOLD   2ΦF  ð14Þ
0.16 mm
0.16 mm. Careful design and simulation is required for
using high voltage transistors so that the power management where VTH0 is the native threshold value, γ is the body effect
circuit can gain wide-range operation while ensuring circuit coefficient, and ΦF is the flat-band voltage of NMOS transistors.
protection. Simulation results show that the RF analog front-end Fig. 3(b) shows the simulation model of the rectifier. An off-
can sustain safe-mode operation when the voltage amplitude chip capacitor C1 is employed to store power and suppress high-
between the two ports of the tag antenna is below 15.3 V. frequency ripples on the rectified voltage. According to ISO/IEC
18000-3 protocol, when the tag is receiving 100% ASK modulated
RF signal, there is a period of 9.44 μs in each cycle without
3.1. Rectifier
incoming RF power, during which the capacitor C1 offers power
for the chip.
The rectifier serves as an extractor which can collect power
The value of C1 can be roughly estimated. In this system, the
from the RF signal by an antenna through inductive links [9]. In the
total impedance load of the rectifier is nearly 8.68 kΩ, and the
front-end system proposed in this paper, the rectifier is required to
minimum rectified voltage is set to be 3.3 V. So the rectifier is
convert an input AC signal to an unregulated DC voltage.
required to provide 380 μA current to the rest of the chip. Then the
In consideration of the current driving capability, a full-wave
average magnitude of the AC voltage collected by the tag antenna
bridge rectifier is adopted instead of a half-wave rectifier. Fig. 3
is supposed to be 7 V. After getting through the rectifier the AC
(a) shows the NMOS bridge rectifier structure configuration. AC1
signal becomes a DC signal with a 2.2-V dropout voltage in the
and AC2 are two ports connected to the antenna of the tag chip.
amplitude, then
VHOLD is the output of the rectifier. AGND is connected to the
analog ground. In order to gain large current driving capability, I Δt 380 μA
9:44 μS
C1 ¼ ¼ ¼ 2391:47 pF ð15Þ
large width to length ratio of the NMOS transistors is required. ΔV 7 V 2:2 V  3:3 V

Fig. 3. (a) Schematic of the NMOS full wave rectifier. (b) Simulation model of the rectifier.
 J. Zhang et al. / Microelectronics Journal 45 (2014) 578–588 581

Fig. 4. (a) Simulated VCR results of the rectifier. (b)Simulated PCE results of the rectifier.

Fig. 5. Block diagram of the proposed voltage generator.

Fig. 4 shows the VCR and the PCE simulation results of the input voltage range and a faster startup speed. Thus this current-
rectifier. Simulations show that the VCR and the PCE both go up mode bandgap is more suitable for RFID tags because the input
with input voltage amplitude. Besides, PCE varies with the load voltage range decides the detecting distance while the startup
level and the output DC voltage level. speed decides the response speed.
Fig. 6 shows the schematic of the proposed current-mode
bandgap reference. The circuit which consists of four sections,
3.2. Voltage regulator
including startup circuit, current bias, two-stage operational
amplifier and bandgap core circuit, is mainly aimed to generate a
The output VHOLD of the full-wave rectifier must be connected
1.25-V supply as a reference for the two LDO regulators. The
to a voltage generator in order to obtain stable and precise VCC and
current bias generates a bias current which is independent of
VDD power supply respectively for analog circuits and digital
supply voltage for the amplifier. A two-stage operational amplifier
circuits despite input power variations. In consideration of getting
is designed to enforce nodes X and Y to have approximately equal
maximum PCE, a low drop-out regulator (LDO) structure is
potential. A proper nulling resistor R2 (R2 ¼ 1/GM8, GM8 is the
utilized. Fig. 5 shows the block diagram of the proposed voltage
transconductance of M8) and a large Miller capacitor C2 are
generator in this paper. In order to avoid the interference of the
utilized for frequency compensation to enhance the stability of
digital switching noise to the sensitive analog supply voltage [6],
the circuit. A PTAT loop is formed by R3, Q1 and Q2 [13]. The PTAT
two separate LDO regulators which share the same bandgap
current can be described as
reference are designed to generate a 2.5-V VCC for analog power
supply and a 1.8-V VDD for digital power supply. V T ln n
I¼ ð16Þ
R3
3.2.1. Bandgap reference where n is the emitter-area ratio of bipolar transistors Q1 and Q2,
In order to provide a reference as a comparison voltage for the and VT is the thermal voltage. The temperature-independent
two LDO regulators, a current-mode bandgap reference is pro- current I is then mirrored to a resistor to yield a temperature-
posed to generate a temperature-independent current by sum- compensated reference voltage [14], so the outputs of the bandgap
ming complementary-to-absolute-temperature (CTAT) currents reference can be represented as
with proportional-to-absolute-temperature (PTAT) currents. Com-
pared with the bandgap references reported in [10–12], the R4
V REF ¼ V BE3 þ V T ln n ð17Þ
proposed current-mode bandgap in this paper has a much wider R3
582 J. Zhang et al. / Microelectronics Journal 45 (2014) 578–588

Fig. 6. Schematic of the proposed current-mode bandgap reference.

V T ln n ðW=LÞ20
I ref ¼ U ð18Þ
R3 ðW=LÞ14

V T ln n ðW=LÞ21
V REF1 ¼ U U R5 ð19Þ
R3 ðW=LÞ14
where VBE3 is the base–emitter voltage of bipolar transistor Q3,
and W/L is the device width to length ratio of a corresponding
MOS transistor.
In order to achieve a fast startup speed, a startup circuit is used
to activate the bandgap reference for forcing it to reach the proper
operating point. Fig. 7 shows that the input voltage range is 3.1–
Fig. 7. Simulated input voltage range of this bandgap.
11.2 V. Fig. 8 shows that the startup time is only 5.9 μs. Fig. 9
shows the reference output voltage versus temperature, the
temperature coefficient is 9.85 ppm/1C in  40 1C to 100 1C range
when input voltage is 5 V, which meets the demands of RFID tags.

3.2.2. LDO regulator

In consideration of the variable distance between the reader
and the tag, the power gained from the electromagnetic field also
varies, leading to a large variation of the output voltage of the
rectifier (3.3–11 V in this system). Therefore, the voltage regulator
in the analog front-end shall be capable of tolerating large input
voltage variation.
The schematic of the proposed LDO regulator for analog supply
is shown in Fig. 10. The circuit is a series-type LDO regulator which
delivers the sampled output voltage back to the input of the error
amplifier by sampling the voltage divided by resistors R3 and R4.
Then, in order to control the output current size, the error
amplifier output takes advantage of controlling the operating state Fig. 8. Simulated startup time of the current-mode bandgap.

of the pass transistor M22, thus adjusting amplitude of the output

voltage by the current through transistor M22. The bias circuit
provides a bias current for transistor M19 and a bias voltage for
transistors M15 and M16. The error amplifier compares VREF which
is generated by the bandgap reference with the feedback voltage
divided by resistors R3 and R4. The error amplifier consists of two
sections, including a telescopic cascade operational amplifier and a
source follower. Resistor R2 and capacitor C1 form a connection in
order to couple the rapid changes of the input VHOLD to the output
of the amplifier, thus accelerating the response speed of the
regulator. The pass transistor M22 is a significant component
because of providing large current for the output load all by itself;
therefore large widths and lengths are required. The LDO regulator
output can reach a balance when the voltage of node X
is approximately equal to VREF; at that time, the output VCC is
generated Fig. 9. Simulated bandgap reference output voltage versus temperature.

R3 þ R4
V CC ¼ UV REF ð20Þ
R4 regulator, output capacitor Cout and bypass capacitor C2 are
The digital LDO regulator has the same structure as Fig. 10. designed to be large, while RESR, the electrical series resistor, is
In comparison with general LDO regulators, this proposed LDO designed to be low. Thus, a rather wide input range is formed.
regulator has a rather wide input voltage range. In order to obtain Simulation results show that the output voltage keeps 2.507 V
high power supply rejection ratio (PSRR) performance in the with an input range of 3.32–15.0 V under full load in Fig. 11.
 J. Zhang et al. / Microelectronics Journal 45 (2014) 578–588 583

Fig. 10. Schematic of the LDO regulator for analog circuits.

under subthreshold-mode is proposed to extract 10% ASK modu-

lated data from the carrier. This demodulator has a relatively
simple structure, which provides a possibility to lower its con-
sumption and area, as consumption and area determine the costs
of the tags.

4.1. 10% ASK demodulator

The 10% ASK demodulation circuit is shown in Fig. 12. The

demodulator mainly consists of an envelope detector, a low pass
filter and a hysteresis comparator. Transistor M7 acts as a switch
Fig. 11. Simulated input range of the proposed LDO regulator. so that the digital unit can choose which demodulator to work at
one specific time.
4. ASK demodulators The envelope detector detects the changes in the voltage
amplitude to shape an envelope wave form. The envelope detector
The demodulation circuit which is a bridge connecting the tag consists of two diode-connected NMOS transistors M1 and M2,
chip to the reader for real-time transmission of information plays a two equivalent active resistors M3 and M4, and a capacitor C0. The
vital role in the RF front-end. According to the requirements of equivalent active resistors M3 and M4 should be under appro-
ISO/IEC 18000-3 protocol, the front-end shall demodulate both priate operating state; thus transistors M5 and M6 are aimed to
100% ASK signal and 10% ASK signal from the modulated carrier, supply a stable bias for M3 and M4.
fc ¼13.56 MHz. In order to follow the envelope of the input ASK carrier, the
In this paper, two different demodulators are designed to bandwidth of the low-pass circuit composed of capacitor C0 and
extract 100% and 10% ASK signals respectively in order to reduce the active resistors M3 and M4 is essential to be much larger than
power consumption, as it is a waste of energy to demodulate 100% the data rate of reader and far less than the carrier frequency of
ASK signal using a complicated 10% ASK demodulator. The 10% ASK 13.56 MHz, which means
demodulator should be capable of detecting a small change in the 1
rd ⪡ ⪡f ð21Þ
RF envelope caused by process and temperature variations. 2π RC0 c
Besides, the amplitude of the incident signal has a dynamic range
where rd is the data rate of the reader, while fc is the carrier
depending on the changing distance between the tag and reader.
frequency. According to ISO/IEC 18000-3 protocol, the maximum
So the design of the 10% ASK demodulator is always complicated
transfer data rate of the reader is 26.48 kbit/s. Suppose that the
and full of challenges. For example, a 10% demodulator consisting
value of the capacitor C0 is 2 pF; then the value of the resistor R
of two unity gain buffers, a low pass filter, a high gain amplifier
should be
and a hysteresis comparator is proposed in [6]; this demodulator
has large power consumption because of using a high gain 5:87
103 Ω 5 R 5 3
106 Ω ð22Þ
amplifier; besides any mismatch between the reference and the
output common-mode voltage in the gain stage of the amplifier In order to reduce the layout area, transistors M3 and M4 provide
results in an error in the demodulation output. Another 10% ASK a required resistance R by changing their gate voltage or width to
demodulator in [7] uses an envelope detector, a two-stage small length ratio. When M3 and M4 turn on in saturation, the
signal amplifier and a latch for demodulation; this demodulator is resistance R can be estimated as
not stable because the simple bias should be in the narrow low R  g M3 U r M3 U r M4 ð23Þ
gain region of the amplifier. An asynchronous demodulator is
proposed in [15]; the circuit is too complicated to control its sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
2I M3
performance. In this section, a high sensitive, low power con- g M3 ¼ ð24Þ
sumption demodulator with a hysteresis comparator working ðV GSM3 V TH Þ
584 J. Zhang et al. / Microelectronics Journal 45 (2014) 578–588

Fig. 12. Schematic of the proposed 10% ASK demodulator.

1
r M3 ¼ ð25Þ
λM3 I M3
1
r M4 ¼ ð26Þ
λM4 I M4
Since I M3 ¼ I M4 ¼ I, resistance R can be obtained as
sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
2I M3 I  1:5
R¼ U ð27Þ
ðV GSM3  V TH Þ λM3 λM4

where gM3 is the transconductance of M3, VGSM3 is the gate–source

voltage of M3, rM3 and rM4 are the output resistances of M3 and
M4, λM3 and λM4 represent the channel length modulation effect
coefficients of M3 and M4 respectively. I is the drain-source
current of M3 which can be obtained by a current mirror M5.
The envelope detector output is followed by a low pass filter
made up by resistor R1 and capacitor C1. The main purpose of the
low pass filter is to filter out the ripple of 13.56 MHz in the output
of the detector, so the RC filter is expressed as
1
r 2π U 13:56 ð28Þ
R1C1
C2 and R2 act like high pass filters which aim to deliver the Fig. 13. Simulated results of the key points' outputs of the 10% demodulator.

high frequency data to the input of the hysteresis comparator. The

data rate of the reader is 26.48 kbit/s; then the operation of the demodulator, thus leading to form a reliable
1 data extractor.
r 2π U 26:48 ð29Þ Fig. 13 shows the key points' outputs of the demodulator. The
R2C2
key to successful demodulation is that the bandgap reference VREF1
The input of the comparator is level shifted by 1.2-V VREF1
must be in the hysteresis level, meanwhile the hysteresis com-
provided by the bandgap reference in order to ensure that the
parator input range VRANGE shall include the hysteresis level VLEVEL
output voltage of the low pass filter is clamped in the input range
so that the comparator can distinguish the rising pulses and the
of the comparator.
falling pulses of the input small signal, as shown in Fig. 13.
A hysteresis comparator is used to deal with the voltage ripple
By keeping VLEVEL smaller than the difference of VIN1 and VIN2, a
in this demodulator. The proposed demodulator can be designed
sensitive 10% ASK demodulator is generated. Simulation results
for very low power consumption because the hysteresis compara-
show that the detecting modulation index of the demodulator can
tor is the main circuit that consumes power. So keeping the
reach 5%; the power consumption is only 589.6 nW.
comparator in subthreshold-mode operation is the best method
to lower its consumption. A PTAT current Iref (90 nA) generated by
the bandgap reference provides current bias for the comparator.
Using a similar approach [16], the comparator hysteresis level
4.2. 100% ASK demodulator
VLEVEL under the subthreshold mode can be expressed as
  !
W=L 19 Fig. 14 shows the schematic of the proposed 100% ASK
V LEVEL ¼ nV TH ln   ð30Þ demodulator. Since 100% ASK modulated carrier has a large change
W=L 18
in the voltage amplitude, a demodulator which consists of an
where VTH is the threshold voltage, n is the subthreshold slope. envelope detector and several inverters can achieve this 100% ASK
VLEVEL obtained from the above equation is a function of the demodulation. A switch composed of M7 and M14 is used to open
device-size ratio only; hence supply voltage variation cannot affect or close the circuit.
 J. Zhang et al. / Microelectronics Journal 45 (2014) 578–588 585

5. Measurement results The fabricated tag chip is installed in a designed printed circuit
board (PCB) using a chip on board (COB) bonding method. The
The proposed RFID tag chip was fabricated in 0.18-μm 2-poly tag's antenna and resonated circuit are also placed in the test
5-metal mixed signal CMOS technology with EEPROM process. The board. The tag chip is tested in a wireless radio frequency
core of the chip occupies an area of 1.96 mm2 (1.4 mm
0.4 mm) environment using a universal RFID reader which can read tags
including test drivers, while the size of the analog front-end is with ISO/IEC 18000-3 protocol. The tested waveforms are mea-
only 0.94 mm
0.84 mm. A 2.7 nF storage capacitor is placed sured by detecting the pins located in the PCB board using an
outside the chip to be connected to the rectifier output. Micro- oscilloscope with 20 GS/s sampling rate. Fig. 15(b) shows the
photograph is shown in Fig. 15(a). The chip fully integrates analog testing scene.
front-end, digital processing unit and a 1024-bit EEPROM. In order Fig. 16(a) exhibits the measured results of the rectifier output
to test the fabricated chip, a number of separate pads are added to VHOLD versus input voltage amplitude; the input voltage is col-
the chip. lected by the tag's antenna through inductive links. Fig. 16
(b) shows VCR of the rectifier block; the maximum VCR of the
rectifier reaches 65.92% when the tag antenna voltage is 9.42 V.
Fig. 16(c) demonstrates the bandgap reference output versus input
voltage. Measured results show that the bandgap reference has a
large input voltage range and a high stability; the output remains
to be 1.26 V with an input range of 2.8–9.3 V. Fig. 16(d) presents
the analog LDO regulator output versus input voltage; measured
results show that VCC keeps in 2.60–2.63 V range since VHOLD is
3.2 V. The proper operation of the rectifier is the basis to provide
DC energy for the whole tag chip. By measurement, the tag chip
can operate properly with a lowest VHOLD of 3.2 V; when the tag
keeps a 75-mm distance from the reader, the input antenna
voltage range is 5.82–12.3 V.
In order to test the two ASK demodulators separately, a RF
signal generator is used to generate input ASK signals of different
modulation depths. Fig. 17 shows the measured results for differ-
ent modulation depths. The input signal is 10% or 100% ASK
modulated wave with the carrier of 13.56 MHz; the modulation
frequency of the input signal is 52.97 KHz. Measured results show
Fig. 14. Schematic of the proposed 100% ASK demodulator. that the ASK demodulators can demodulate the data of different

Fig. 15. (a) Microphotograph of the tag chip. (b) The testing scene.
586 J. Zhang et al. / Microelectronics Journal 45 (2014) 578–588

Fig. 16. (a) Measured rectifier output VHOLD versus input voltage amplitude. (b) Measured VCR of the rectifier versus input voltage amplitude. (c) Measured bandgap
reference output versus input VHOLD. (d) Measured LDO output for analog versus input VHOLD.

Fig. 17. (a) Measured results of the 100% ASK demodulator. (b) Measured results of the 10% ASK demodulator.

modulation depths accurately. Moreover, the power consumption the tag accomplishes its response by utilizing load modulation
of the 10% ASK demodulator is only 690.25 nW. technology in order to send its unique identification data. Measure-
Fig. 18(a) shows a complete receive and response process of the ment results confirm that the tag chip uses one sub-carrier
analog front-end. Fig. 18(b) shows the measured results of the (423.75 KHz) encoding method as a response. When the digital unit
analog front-end for receiving a complete read command from the sends one sub-carrier encoded data to the load modulator, the load
reader. The reader sends a read command which is a 100% ASK modulator must transform the input data to the amplitude changes
modulated signal. The results show an accurate demodulator output. on the antenna, as shown in Fig. 18(c).
The output level is 1.8 V which is suitable for the recognition of the Table 1 describes the measured performance summary of
digital processing unit. After receiving the read command correctly, the tag chip analog front-end meeting ISO/IEC 18000-3 MODE
 J. Zhang et al. / Microelectronics Journal 45 (2014) 578–588 587

Fig. 18. (a) Measured results of a complete receive and response process of the front-end. (b) Measured results of the analog front-end for receiving a complete read
command from the reader. (c) Measured results of the tag response by load modulation.

Table 1
Measured performance summary of the front-end.

Features Performance

RF carrier frequency 13.56 MHz7 7 kHz

Protocol ISO/IEC 18000-3 MODE 1
Technology 0.18 μm 2P5M CMOS technology
DC supply voltage Analog: 2.61 V; Digital: 1.82 V
Voltage amplitude on tag antenna 5.82–12.3 V
Modulation type index (reader-to-tag) ASK 100%, ASK 10%
Modulation Load switching
Modulation type (tag-to-reader) ASK
Sub-carrier frequency (tag-to-reader) One sub-carrier: 423.75 kHz

Table 2
Performance comparison between the proposed analog front-end and previous works.

Ref. [17] Ref. [18] Ref. [19] Ref. [20] Ref. [15] This work

Technology 1.5 μm 0.5 μm 0.5 μm 0.35 μm 0.35 μm 0.18 μm

Modulation type FSK ASK BPSK FSK ASK ASK
Demodulator supply voltage 5V 3.3–5 V 3.3 V 1.5 V  3.3 V N/A 2.61 V
Operating frequency 10 MHz 13.56 MHz 13.56 MHz 13.56 MHz 13.56 MHz 13.56 MHz
Data rate 2.5 Mbps 200–800 kbps 20 kbps 10–1000 kbps 26.48 kbps 26.48 kbps
Maximum operating distance 14 mm N/A N/A 50 mm 65 mm 75 mm
Power consumption 0.38 mW 5.24 mW 3 mW 0.96 mW 0.34 mW 0.42 mW
Chip area 2.2 mm
2.2 mm 1 mm
2 mm 1 mm
1 mm 0.74 mm
0.43 mm N/A 0.94 mm
0.84 mm

1 standard. Table 2 shows the performance comparison between Acknowledgments

the proposed analog front-end and previous works.
The authors would like to thank Seed Foundation of Tianjin
University, Program for New Century Excellent Talents in Univer-
sity, National Natural Science Funds for Youth (Grant No.
61204028) and Natural Science Fund and the Youth Science
6. Conclusion Foundation of Tianjin (Grant No. 13JCQNJC01100) for supporting
this work. The authors acknowledge Semiconductor Manufactur-
This paper mainly presents a fully integrated analog front-end ing International Corporation for chip fabrication.
circuit for 13.56 MHz passive RFID tag chips with ISO/IEC 18000-3
MODE 1 protocol. The designed tag chip analog front-end has
a maximum detecting distance of 75 mm. The whole size of the References
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