College Name: R.

R INSTITUTE OF TECHNOLOGY Academic year : 2023-24

Programme : BE Semester or Year : III Sem
Subject Name : Digital Design and Computer
Subject Code : BS302
Organization

Total contact hours : 50 IA Marks: 40

Faculty Name : Lakshmidevi H M Reviewed by : Dr. Manjunath R

Signature : Signature :

Lesson Plan

Significance of the Subject:

The speed, density, and complexity of today’s digital devices are made possible by
advances in physical processing technology and digital design methodology. The design of
leading-edge devices depends critically on hardware description languages (HDLs) and
synthesis tools. Three public-domain languages, Verilog, VHDL, and SystemVerilog, all play
a role in design flows for today’s digital devices. HDLs, together with fundamental
knowledge of digital logic circuits, provide an entry point to the world of digital design for
students majoring in computer science, computer engineering.
Computer Organization describes the function and design of the various units of digital
computers that process information. Computer hardware consists of electronic circuits,
displays, magnetic and optical storage media, electromechanical equipment and
communication facilities. Computer architecture encompasses the specification of an
instruction set and the hardware units that implement the instructions.
Course Objective:
 To demonstrate the functionalities of binary logic system
 To explain the working of combinational and sequential logic system
 To realize the basic structure of computer system
 To illustrate the working of I/O operations and processing unit
Course Outcomes:
CO1: Apply the K–Map techniques to simplify various Boolean expressions.
CO2: Design different types of combinational and sequential circuits along with Verilog
programs.
CO3: Describe the fundamentals of machine instructions, addressing modes and
Processor performance.
CO4: Explain the approaches involved in achieving communication between processor and
I/O devices.
CO5: Analyze internal Organization of Memory and Impact of cache/Pipelining on
Processor Performance.

Program Outcomes(PO)
PO 1: Engineering Knowledge: Apply knowledge of mathematics and science, with
fundamentals of Computer Science & Engineering to be able to solve complex
engineering problems related to CSE.

Page 1 of 7
PO 2: Problem Analysis: Identify, Formulate, review research literature and analyse
complex engineering problems related to CSE and reaching substantiated
conclusions using first principles of mathematics, natural sciences and engineering
sciences.

PO 3: Design/Development of Solutions: Design solutions for complex engineering

problems related to CSE and design system components or processes that meet the
specified needs with appropriate consideration for the public health and safety and
the cultural societal and environmental considerations.

PO 4: Conduct Investigations of Complex Problems: Use research–based knowledge and

research methods including design of experiments, analysis and interpretation of
data, and synthesis of the information to provide valid conclusions.

PO 5: Modern Tool Usage: Create, Select and apply appropriate techniques, resources and
modern engineering and IT tools including prediction and modelling to computer
science related complex engineering activities with an understanding of the
limitations.

PO 6: The Engineer and Society: Apply Reasoning informed by the contextual knowledge
to assess societal, health, safety, legal and cultural issues and the consequent
responsibilities relevant to the CSE professional engineering practice.

PO 7: Environment and Sustainability: Understand the impact of the CSE professional

engineering solutions in societal and environmental contexts and demonstrate the
knowledge of, and need for sustainable development.

PO 8: Ethics: Apply Ethical Principles and commit to professional ethics and responsibilities
and norms of the engineering practice.

PO 9: Individual and Team Work: Function effectively as an individual and as a member or

leader in diverse teams and in multidisciplinary Settings.

PO 10: Communication: Communicate effectively on complex engineering activities with

the engineering community and with society at large such as able to comprehend
and with write effective reports and design documentation, make effective
presentations and give and receive clear instructions.

PO 11: Project Management and Finance: Demonstrate knowledge and understanding of

the engineering management principles and apply these to one’s own work, as a
member and leader in a team, to manage projects and in multi-disciplinary
environments.

PO 12: Life-Long Learning: Recognize the need for and have the preparation and ability to
engage in independent and life-long learning the broadest context of technological

Page 2 of 7
 change.

Program Specific Outcomes

PSO 1: Apply the software practices, principals to design and analyse the complex
computer based system.

PSO 2: Design, implement and validate system software and application software to the
various societal needs.

Cl Module & Topic to be covered Tea Skill Date Blo CO Remark

ass Hours chin Dev om s
No g elop Planne Comple s
aids men d ted leve
t l

1. Module1 Binary Logic, CT QZ/ 11/10/2 CO

Introductio Basic Theorems AA/ 3 1
n to Digital And Properties Of CC
Design: Boolean Algebra
2. Boolean Functions CT QZ/ CO
AA/ 1
CC
3. Digital Logic Gates CT QZ/ CO
AA/ 1
CC
4. Introduction, The CT QZ/ CO
Map Method AA/ 1
CC
5. Four-Variable Map CT QZ/ CO
AA/ 1
CC
6. Don’t-Care CT QZ/ CO
Conditions AA/ 1
CC
7. NAND and NOR CT QZ/ CO
Implementation AA/ 1
CC
8. NAND and NOR CT QZ/ CO
Implementation AA/ 1
CC
9. Other Hardware CT QZ/ CO
Description AA/ 1
Language – Verilog CC
Model of a
simple circuit
10. Other Hardware CT QZ/ CO
Description AA/ 1
Language – Verilog CC
Model of a
simple circuit.
11. Module 02 Introduction, CT QZ/ CO
AA/ 2
Page 3 of 7
 Combinatio Combinational CC
nal Logic Circuits
12. Design Procedure CT QZ/ CO
AA/ 2
CC
13. Binary Adder- CT QZ/ CO
Subtractor AA/ 2
CC
14. Decoders, CT QZ/ CO
Encoders AA/ 2
CC
15. Multiplexers CT QZ/ CO
AA/ 2
CC
16. HDL Models of CT QZ/ CO
Combinational AA/ 2
CC
Circuits – Adder
17. Multiplexer, CT QZ/ CO
Encoder AA/ 2
CC
18. Sequential Logic: CT QZ/ CO
Introduction, AA/ 2
CC
Sequential Circuits
19. Storage Elements: CT QZ/ CO
Latches AA/ 2
CC
20. Flip-Flops CT QZ/ CO
AA/ 2
CC
21. Module 03 Functional Units, CT QZ/ CO
Basic Basic Operational AA/ 3
Structure CC
Concepts,
22. of Bus structure, CT QZ/ CO
Computers: Performance – AA/ 3
Processor Clock CC
23. Basic Performance CT QZ/ CO
Equation, Clock AA/ 3
CC
Rate, Performance
Measurement
24. Machine CT QZ/ CO
Instructions and AA/ 3
Programs: CC
Memory Location
and Addresses
25. Memory Location CT QZ/ CO
and Addresses AA/ 3
CC
26. Memory CT QZ/ CO
Operations AA/ 3
CC
27. Instruction and CT QZ/ CO
Instruction AA/ 3
sequencing CC
28. Instruction and CT QZ/ CO

Page 4 of 7
 Instruction AA/ 3
sequencing CC
29. Addressing Modes CT QZ/ CO
AA/ 3
CC
30. Addressing Modes CT QZ/ CO
AA/ 3
CC
31. Module 04 Accessing I/O PPT CC/ CO
Input/ Devices AA 4
output
32. Interrupts – Interrupt PPT CC/ CO
Organizatio
Hardware AA 4
n:
33. Enabling and PPT CC/ CO
Disabling AA 4
Interrupts
34. Enabling and PPT CC/ CO
Disabling AA 4
Interrupts
35. Handling Multiple PPT CC/ CO
Devices AA 4

36. Direct Memory PPT CC/ CO

Access: Bus AA 4
Arbitration
37. Bus Arbitration PPT CC/ CO
AA 4

38. Speed, size and Cost PPT CC/ CO

of AA 4
memory systems
39. Cache Memories – PPT CC/ CO
Mapping Functions AA 4

40. Cache Memories – PPT CC/ CO

Mapping Functions AA 4

41. Module 05 Some Fundamental PPT CC/ CO

Basic Concepts: Register AA 5
Processing Transfers
42. Unit: Performing ALU PPT CC/ CO
operations AA 5

43. Performing ALU PPT CC/ CO

operations AA 5

44. fetching a word PPT CC/ CO

from Memory AA 5

45. Storing a word in PPT CC/ CO

memory AA 5

46. Execution of a PPT CC/ CO

Complete AA 5
Instruction
47. Execution of a PPT CC/ CO
Complete
Page 5 of 7
 Instruction AA 5

48. Pipelining: PPT CC/ CO

Basic concepts AA 5

49. Role of Cache PPT CC/ CO

memory AA 5

50. Pipeline PPT CC/ CO

Performance AA 5

51. Revision Revision 1 PPT CC/ CO

AA 1

52. Revision 2 PPT CC/ CO

AA 2

53. Revision 3 PPT CC/ CO

AA 3

54. Revision 4 PPT CC/ CO

AA 4

55. Revision 5 PPT CC/ CO

AA 5

Bloom’s Taxonomy Level

L1-Remembering L2-Understanding L3-Applying L4-Analysing L5-Evaluating L6-Creating
Text Books:
1 M. Morris Mano & Michael D. Ciletti, Digital Design With an Introduction to Verilog Design, 5e,
Pearson Education.
2 Carl Hamacher, ZvonkoVranesic, SafwatZaky, Computer Organization, 5th Edition, Tata McGraw
Hill.

Web links and Video Lectures (e-Resources):

https://cse11-iiith.vlabs.ac.in/

Curricula Gap Analysis

Sl. Curricula Gap Action Date-Month- Resource Person % of students Relevance to POs,
No. taken Year with designation present PSOs
1

Signature of Faculty Signature of HOD

Page 6 of 7
Page 7 of 7