EC200A&EC200U Series

PCB Design Guideline

LTE Standard Module Series

Version: 1.0

Date: 2022-09-09

Status: Released
 LTE Standard Module Series

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EC200A&EC200U_Series_PCB_Design_Guideline 1 / 36
 LTE Standard Module Series

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Copyright © Quectel Wireless Solutions Co., Ltd. 2022. All rights reserved.

EC200A&EC200U_Series_PCB_Design_Guideline 2 / 36
 LTE Standard Module Series

Safety Information
The following safety precautions must be observed during all phases of operation, such as usage, service
or repair of any cellular terminal or mobile incorporating the module. Manufacturers of the cellular terminal
should notify users and operating personnel of the following safety information by incorporating these
guidelines into all manuals of the product. Otherwise, Quectel assumes no liability for customers’ failure to
comply with these precautions.

Full attention must be paid to driving at all times in order to reduce the risk of an
accident. Using a mobile while driving (even with a handsfree kit) causes
distraction and can lead to an accident. Please comply with laws and regulations
restricting the use of wireless devices while driving.

Switch off the cellular terminal or mobile before boarding an aircraft. The operation
of wireless appliances in an aircraft is forbidden to prevent interference with
communication systems. If there is an Airplane Mode, it should be enabled prior to
boarding an aircraft. Please consult the airline staff for more restrictions on the use
of wireless devices on an aircraft.

Wireless devices may cause interference on sensitive medical equipment, so

please be aware of the restrictions on the use of wireless devices when in
hospitals, clinics or other healthcare facilities.

Cellular terminals or mobiles operating over radio signal and cellular network
cannot be guaranteed to connect in certain conditions, such as when the mobile bill
is unpaid or the (U)SIM card is invalid. When emergency help is needed in such
conditions, use emergency call if the device supports it. In order to make or receive
a call, the cellular terminal or mobile must be switched on in a service area with
adequate cellular signal strength. In an emergency, the device with emergency call
function cannot be used as the only contact method considering network
connection cannot be guaranteed under all circumstances.

The cellular terminal or mobile contains a transceiver. When it is ON, it receives

and transmits radio frequency signals. RF interference can occur if it is used close
to TV sets, radios, computers or other electric equipment.

In locations with explosive or potentially explosive atmospheres, obey all posted

signs and turn off wireless devices such as mobile phone or other cellular
terminals. Areas with explosive or potentially explosive atmospheres include
fuelling areas, below decks on boats, fuel or chemical transfer or storage facilities,
and areas where the air contains chemicals or particles such as grain, dust or
metal powders.

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 LTE Standard Module Series

About the Document

Revision History

Version Date Author Description

- 2022-07-28 Lim PENG Creation of the document

1.0 2022-09-09 Lim PENG First official release

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 LTE Standard Module Series

Contents
About the Document .................................................................................................................................. 4
Table Index .................................................................................................................................................. 6
Figure Index ................................................................................................................................................ 7

1 Introduction ......................................................................................................................................... 8
1.1. Special Mark .............................................................................................................................. 8

2 PCB Design Overview ........................................................................................................................ 9

2.1. Basic Check Items ..................................................................................................................... 9
2.2. Design Priorities and Considerations for PCB Traces ............................................................. 10
2.2.1. Design Priorities ............................................................................................................ 10
2.2.2. Design Considerations .................................................................................................. 10

3 Interface Design ................................................................................................................................ 12

3.1. Power Supply ........................................................................................................................... 12
3.1.1. DC-DC Converter .......................................................................................................... 12
3.1.2. VBAT ............................................................................................................................. 13
3.2. PWRKEY & RESET_N ............................................................................................................ 15
3.3. USB Interface ........................................................................................................................... 16
3.3.1. USB_DM & USB_DP Signals ....................................................................................... 16
3.3.2. USB_VBUS Signal ........................................................................................................ 17
3.4. Ethernet PHY ........................................................................................................................... 18
3.4.1. RGMII/RMII Interface .................................................................................................... 18
3.4.2. Ethernet Components ................................................................................................... 20
3.5. Audio Interfaces ....................................................................................................................... 22
3.5.1. PCM Interface ............................................................................................................... 22
3.5.2. Codec & Microphone & Speaker .................................................................................. 22
3.6. SD card interface ..................................................................................................................... 24
3.7. LCM Interface........................................................................................................................... 26
3.8. (U)SIM Interface ....................................................................................................................... 27
3.9. ADC Interface........................................................................................................................... 28
3.10. GPIOs....................................................................................................................................... 29
3.11. Antenna Interfaces ................................................................................................................... 30
3.11.1. PCB Structures of Microstrip and Coplanar Waveguide .............................................. 30
3.11.1.1. PCB Structure of Microstrip Waveguide ............................................................ 30
3.11.1.2. PCB Structure of Coplanar Waveguide ............................................................. 30
3.11.2. Reference Design of RF Layout.................................................................................... 32
3.11.3. PCB Layout Considerations of Coplanar Waveguide ................................................... 33

4 Appendix References ....................................................................................................................... 35

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 LTE Standard Module Series

Table Index

Table 1: Special Mark................................................................................................................................... 8

Table 2: Recommended Values of W and S for 50 Ω Coplanar Waveguide under Different PCB Structures
(Unit: mm) ..................................................................................................................................... 31
Table 3: Related Documents...................................................................................................................... 35
Table 4: Terms and Abbreviations ............................................................................................................. 35

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 LTE Standard Module Series

Figure Index

Figure 1: Overview of EC200U TE-A 1st Layer ........................................................................................... 9

Figure 2: High-priority Signals to Be Designed (EC200U TE-A 1st Layer) ............................................... 11
Figure 3: DC-DC Converter (EVB 4th Layer) and Module Interfaces On TE-A (EVB 1st Layer).............. 12
Figure 4: VBAT Traces (EC200U TE-A 1st Layer) .................................................................................... 13
Figure 5: Traces of VBAT with Capacitors (EC200A TE-A 4th Layer) ...................................................... 14
Figure 6: Traces of VBAT with a TVS (EC200A TE-A 4th Layer) ............................................................. 14
Figure 7: VBAT & Sensitive Signal Traces (EC200U TE-A 1st Layer) ...................................................... 15
Figure 8: PWRKEY and RESET_N Traces (EC200A TE-A 3rd Layer) ..................................................... 15
Figure 9: Overview of USB_DM/USB_DP Signal Traces (EVB 1st Layer) ................................................ 16
Figure 10: Overview of USB_DM/USB_DP Signal Traces (EVB 3rd Layer) ............................................. 17
Figure 11: Overview of USB_VBUS Signal Trace (EVB 1st Layer) .......................................................... 17
Figure 12: Overview of USB_VBUS Signal Trace (EVB 3rd Layer) .......................................................... 18
Figure 13: Overview of RGMII/RMII Signal Traces (EC200A TE-A 1st Layer) ......................................... 19
Figure 14: Overview of RGMII/RMII Signal Traces (EC200A TE-A 3rd Layer) ......................................... 19
Figure 15: Layout of Recommended Inductor, GND and Traces of YT8521 (EVB 1st Layer) ................. 20
Figure 16: Recommended Reference Interface (EVB 2nd Layer)............................................................. 21
Figure 17: Recommended PCB Layout of RGMII/RMII Interface (EC200A TE-A 4th Layer) ................... 21
Figure 18: Overview of PCM Signal Traces (EC200U TE-A 3rd Layer) .................................................... 22
Figure 19: Overview of Codec ALC5616 (EVB 1st Layer)......................................................................... 23
Figure 20: Overview of Analog Audio Signal Traces (EVB 1st Layer) ...................................................... 24
Figure 21: Overview of SD Card Signal Traces (EVB 1st Layer) ............................................................. 25
Figure 22: Overview of SD Card Signal Traces (EVB 3rd Layer) ............................................................. 25
Figure 23: Overview of LCD Signal Traces (EC200U TE-A 2nd Layer) ................................................... 26
Figure 24: Overview of ISINK Signal Trace (EC200U TE-A 3rd Layer) .................................................... 26
Figure 25: Overview of (U)SIM Signal Traces (EVB 1st Layer) ................................................................ 27
Figure 26: Overview of (U)SIM Signal Traces (EVB 2nd Layer) .............................................................. 27
Figure 27: Overview of ADC Signal Traces (EVB 3rd Layer) ................................................................... 28
Figure 28: Overview of GPIO Signal Traces (EC200A TE-A Without Copper Pouring) ........................... 29
Figure 29: PCB Structure of Microstrip Waveguide ................................................................................... 30
Figure 30: PCB Structure of Coplanar Waveguide .................................................................................... 31
Figure 31: Microstrip Design on a 2-layer PCB ......................................................................................... 32
Figure 32: Coplanar Waveguide Design on a 2-layer PCB ....................................................................... 32
Figure 33: Coplanar Waveguide Design on a 4-layer PCB (Layer 3 as Reference Ground) .................... 33
Figure 34: Coplanar Waveguide Design on a 4-layer PCB (Layer 4 as Reference Ground) .................... 33
Figure 35: Overview of RF Traces (EVB 1st Layer).................................................................................. 34
Figure 36: Overview of RF Traces (EVB 1st and 2nd Layers) .................................................................. 34

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 LTE Standard Module Series

1 Introduction
This document introduces the PCB reference design for Quectel LTE Standard EC200A series and
EC200U series modules. It takes EC200U TE-A or EC200A TE-A and UMTS&LTE EVB as example to
illustrate interface design in PCB. For detailed information of PCB thermal design, see document [1].

1.1. Special Mark

Table 1: Special Mark

Mark Definition

Brackets ([…]) used after a pin enclosing a range of numbers indicate all pins of the same
[…] type. For example, RGMII/RMIII_TX_[0:1] refers to all two RGMII/RMIII_TX pins,
RGMII/RMIII_TX_0 and RGMII/RMIII_TX_1.

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 LTE Standard Module Series

2 PCB Design Overview

2.1. Basic Check Items

⚫ A 4-layer PCB is strongly recommended.

⚫ First, check whether the module’s footprint is of the latest version provided by Quectel. For specific
footprint of each module, see document [2] and [3].
⚫ It is recommended to pour the rest of the PCB area (except keep-out zone) with ground copper for a
better transmission performance.

Antenna
interfaces

VBAT Audio
interfaces

SD Card
interfaces

USB PCM
interfaces interfaces
Matrix Keypad
interfaces

SDIO LCM
interfaces interfaces (U)SIM
interfaces

Figure 1: Overview of EC200U TE-A 1st Layer

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 LTE Standard Module Series

2.2. Design Priorities and Considerations for PCB Traces

2.2.1. Design Priorities

Design the PCB traces according to the recommended order as follows:

⚫ Antenna traces
⚫ High-speed signal (RGMII/RMII, SD card, USB, etc.) traces
⚫ Sensitive signals (PCM and ADC) traces
⚫ Power supply (VBAT_BB, VBAT_RF, USIM_VDD, SDIO_VDD, VDD_EXT) traces
⚫ Other traces

2.2.2. Design Considerations

⚫ The radiation of PCM interface and its power supply could affect RF performance, so keep them
away from RF signal traces and components.
⚫ Drill as fewer vias as possible for high-speed signal traces (such as RGMII/RMII, SDIO and USB
signal traces) since vias would affect the continuity of the impedance. Route the differential pair
traces on the same layer.
⚫ To minimize the signal return path, the GND vias for signals such as USB, SDIO, RGMII/RMIII,
PWRKEY and RESET_N should be close to the vias where the traces change layers.

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 LTE Standard Module Series

Antenna
interfaces

High-speed
High-speed
signals (USB
signals
interfaces)
(SD Card interfaces)

High-speed
signals (SDIO
interfaces)

Figure 2: High-priority Signals to Be Designed (EC200U TE-A 1st Layer)

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 LTE Standard Module Series

3 Interface Design

3.1. Power Supply

3.1.1. DC-DC Converter

⚫ Place the DC-DC converter away from the sensitive signal traces such as SD card, USB, RGMII/RMII,
audio and RF signals. If possible, shield DC-DC converter with shielding cover and reserve clearance
for shielding frame.
⚫ Place the capacitor and inductor for the DC-DC converter as close as possible to the corresponding
pins of the DC-DC converter to minimize the loop area.
⚫ Place output capacitors near input capacitors to share common ground area on outer layers.
⚫ Provide adequate thermal relief area at the ground area on outer layers along with any additional
inner ground planes.

TE-A interfaces

DC-DC
converter

Figure 3: DC-DC Converter (EVB 4th Layer) and Module Interfaces On TE-A (EVB 1st Layer)

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 LTE Standard Module Series

3.1.2. VBAT

⚫ Place 100 μF, 100 nF, 33 pF and 10 pF capacitors for both VBAT_BB and VBAT_RF respectively.
The smaller the capacitance is, the closer the capacitors are to the two pins.
⚫ Separate the VBAT_RF and VBAT_BB traces. Star configuration for wiring is recommended.
⚫ For EC200U series, the trace widths of VBAT_RF and VBAT_BB are recommended to be not less
than 2.5 mm and 2 mm respectively; For EC200A series, the trace widths of VBAT_RF and
VBAT_BB are recommended to be not less than 2 mm and 1 mm respectively. Moreover, pay
attention to the capability and quantity of vias in the VBAT traces as shown in the diagram below. The
GND vias of the filter capacitors for VBAT should be drilled down to the nearest main ground.

GND

GND
2.5 mm

VBAT_RF

Vias

VBAT_BB

2 mm GND

Figure 4: VBAT Traces (EC200U TE-A 1st Layer)

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 LTE Standard Module Series

Vias Capacitors

GND

GND

GND

Figure 5: Traces of VBAT with Capacitors (EC200A TE-A 4th Layer)

⚫ Place the TVS for VBAT close to module’s VBAT_BB and VBAT_RF.
⚫ VBAT traces should be away from sensitive signal traces, such as SD card, RGMII/RMII, USB, audio
and RF signals, to avoid paralleling or crossing with them.
⚫ A layer with VBAT traces and reference ground plane is recommended. When a power plane is used,
a complete ground plane should be added in adjacent layer as the reference plane.

TVS

GND

Figure 6: Traces of VBAT with a TVS (EC200A TE-A 4th Layer)

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 LTE Standard Module Series

Antenna
interfaces

VABT Audio
interfaces

SD card
interfaces

USB PCM
interface interfaces
Matrix keypad
interfaces

SDIO LCM
interfaces interfaces (U)SIM
interfaces

Figure 7: VBAT & Sensitive Signal Traces (EC200U TE-A 1st Layer)

3.2. PWRKEY & RESET_N

⚫ Surround PWRKEY and RESET_N signal traces with ground.

⚫ If filter capacitors are required, put them near PWRKEY and RESET_N.

PWRKEY

RESET_N

GND

GND

GND

Figure 8: PWRKEY and RESET_N Traces (EC200A TE-A 3rd Layer)

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 LTE Standard Module Series

3.3. USB Interface

3.3.1. USB_DM & USB_DP Signals

⚫ The clearance between USB_DP/USB_DM and other signal traces should be larger than 0.5 mm.
⚫ Maintain the integrity of the reference plane and avoid crossing with signal lines on adjacent layers.
⚫ Route USB_DP and USB_DM traces on the inner layer, with the differential impedance controlled to
90 Ω 10 %.
⚫ Keep the clearance and length between traces comparatively equal, with the length tolerance less
than 2 mm and the total length less than 120 mm.
⚫ When a TVS needs to be added for USB_DP and USB_DM signal traces, place it close to USB
connector and use a TVS with a junction capacitance of less than 2 pF.
⚫ Decrease the number of vias for USB_DM/USB_DP. Keep the reference ground plane for USB_DP
and USB_DM complete. Keep three times the trace width from other signal traces.

TE-A
interface

USB_DM/
DP

GND
Test
points

GND
USB
connector GND

Figure 9: Overview of USB_DM/USB_DP Signal Traces (EVB 1st Layer)

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 LTE Standard Module Series

USB_DM/DP

GND

GND
GND

Figure 10: Overview of USB_DM/USB_DP Signal Traces (EVB 3rd Layer)

3.3.2. USB_VBUS Signal

USB_VBUS is a USB detection signal, with maximum current of 1 mA. In general, a trace width of 0.1 mm
is sufficient.

TE-A
interface

USB_VBUS

GND

Test
points
GND

GND

USB
connector

Figure 11: Overview of USB_VBUS Signal Trace (EVB 1st Layer)

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 LTE Standard Module Series

USB_VBUS

GND

GND
GND

Figure 12: Overview of USB_VBUS Signal Trace (EVB 3rd Layer)

3.4. Ethernet PHY

Ethernet PHY is for EC200A series module only.

3.4.1. RGMII/RMII Interface

⚫ Keep RMII and RGMII data and control signals away from other sensitive circuits/signals such as RF
circuits and analog signals, as well as noisy signals generated by clock, DC-DC, etc.
⚫ The single-ended impedance of RGMII data trace is 50 Ω ±10 %.
⚫ The length difference of RGMII/RMIII_TX_[0:1], RGMII_TX_[2:3], RGMII/RMIII_CTL_TX and
RGMII_CK_TX should be less than 2 mm, and the clearance between the signal traces should be
larger than twice the trace width. Similarly, the length difference of RGMII/RMIII_RX_[0:1],
RGMII_RX_[2:3], RGMII/RMIII_CTL_RX and RGMII/RMIII_CLK should be less than 2 mm, and the
clearance between the signal traces should be larger than twice the trace width.
⚫ It is recommended to route RGMII/RMIII signal trace with total ground shielded. If there is a limit on
space, the four traces of RGMII/RMIII_TX_[0:1] and RGMII_TX_[2:3] can be routed together with
ground. The same rule is applied to RGMII/RMIII_RX_[0:1] and RGMII_RX_[2:3] traces.
⚫ Clearance between Tx bus and Rx bus is larger than 2.5 times the trace width.
⚫ Clearance between Tx bus or Rx bus and other signal trace is larger than 3 times the trace width.

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 LTE Standard Module Series

GND

GND

GND

GND
RGMII/RMII_CTRL_RX

RGMII/RMII_RX_1

RGMII_CK_RX
RGMII/RMII_RX_0

GND
RGMII_RX_2
GND
RGMII_RX_3

Figure 13: Overview of RGMII/RMII Signal Traces (EC200A TE-A 1st Layer)

GND

GND

RGMII_CTRL_TX

RGMII_CK_TX

RGMII/RMII_TX_0 GND

RGMII/RMII_TX_1
GND

RGMII_TX_2 GND

RGMII_TX_3

Figure 14: Overview of RGMII/RMII Signal Traces (EC200A TE-A 3rd Layer)

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 LTE Standard Module Series

3.4.2. Ethernet Components

Use a PCB of at least four layers when using the RGMII/RMII interface to implement the Ethernet function
in the application.

⚫ The first layer is for non-sensitive traces and 1.2 V power supply traces.
⚫ The second layer is recommended for 3.3 V power supply traces and ground plane.
⚫ The third layer should be a reference ground.
⚫ The fourth layer is for main signal traces.

The trace width for the inductor is recommended to be at least 1 mm. Besides, A reference ground plane
for inductance isolation near the inductor is needed. The following figure shows the recommended
inductor placement as well as trace routing and trace width for YT8521 pins.

GND
GND

1.2V Power
MDI signal traces

Inductor

GND

GND
YT8521SC

GND
1V2 Power

Figure 15: Layout of Recommended Inductor, GND and Traces of YT8521 (EVB 1st Layer)

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 LTE Standard Module Series

GND
GND

GND
GND

GND

VDD_3V3

GND

Figure 16: Recommended Reference Interface (EVB 2nd Layer)

Ethernet
connector GND
GND

RGMII/RMII TX
traces

GND

RGMII/RMII RX
traces

Figure 17: Recommended PCB Layout of RGMII/RMII Interface (EC200A TE-A 4th Layer)

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 LTE Standard Module Series

3.5. Audio Interfaces

3.5.1. PCM Interface

⚫ The filter capacitors for PCM_CLK/PCM_SYNC should be placed close to the two pins.
⚫ The PCM bus is recommended to be routed on inner layers, and each trace is recommended to be
surrounded by ground traces separately. If there is a limit on space, at least ensure that PCM_CLK is
separately surrounded by ground traces, and other three signal traces can be surrounded together
by ground traces.
⚫ PCM traces should be kept away from interference sources such as clock signals, RF signals,
crystals, and power supplies.

GND
GND

PCM_CLK

PCM_SYNC

PCM_OUT

PCM_IN

GND

GND

GND

Figure 18: Overview of PCM Signal Traces (EC200U TE-A 3rd Layer)

3.5.2. Codec & Microphone & Speaker

The codec should be kept away from interference sources such as high-power consumption components,
power sources, CPU, DRAM, Flash, PMU, LCD, RF antennas and other high-frequency components, and
should be isolated and placed close to one of the edges or corners of the board. It could be shielded if
there is sufficient space.

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 LTE Standard Module Series

GND

GND

GND

ALC5616

GND

GND

Figure 19: Overview of Codec ALC5616 (EVB 1st Layer)

⚫ Keep the traces for microphone and speaker as short as possible. For MIC signals, it is
recommended to design differential pairs.
⚫ The analog output could only be capable of driving earphone and headset. For larger power loads
such as loudspeakers, an audio power amplifier should be added in the design.
⚫ All MIC and SPK signal traces should be routed with ground on the same layer and with ground
planes above and below, and far away from interference sources.
⚫ The clearance between MIC_P and MIC_N should be more than 0.25 mm. To avoid cross-talk, the
clearance between the differential pair traces should be more than 1.5 mm. To avoid interference
between different MIC traces, MIC1 and MIC2 traces should be routed on different layers as much as
possible.
⚫ For signal traces of speaker, the length should be more than 0.5 mm and has low impedance.
⚫ The reference ground for microphone, speaker and MICBIAS should be analog while for PCM
interface it should be digital. Besides, pay attention to the integrity of the analog signal reference
plane.

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 LTE Standard Module Series

SPK1_P

SPK1_M

Speaker
amplifier
MIC_P MIC_N
MIC1_N

MIC1_P SPK2_M

SPK2_P
Handset
SPK_L application
Earphone
application SPK_R

AGND MIC2_P

Figure 20: Overview of Analog Audio Signal Traces (EVB 1st Layer)

3.6. SD card interface

⚫ It is important to route the SDIO signal traces with ground on the same layer and with ground planes
above and below. The impedance of SDIO data trace is 50 Ω ±10 %.
⚫ Keep SDIO signals far away from other sensitive circuits or signals such as RF circuits and analog
signals, as well as noisy signals such as clock signals and DC-DC signals.
⚫ SD_CLK and SD_CMD should be surrounded with ground on the layer and ground planes above and
below. If there is a limit on space, the SD_DATA[0:3] could be surrounded with ground together.
⚫ The total length of each SDIO signal trace should be less than 50 mm, and the difference between
them should be less than 1 mm.
⚫ Make sure the adjacent trace spacing is twice the the trace width and the load capacitance of SDIO
bus should be less than 15 pF.

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SD card connector

TVS & capacitors & resistors GND

GND

GND

SD card signal traces

GND

GND

Figure 21: Overview of SD Card Signal Traces (EVB 1st Layer)

GND GND
SD_CLK

SD_CMD
VDD_SDIO

SD_INS_DET
GND

GND

SD_DATA
GND

Figure 22: Overview of SD Card Signal Traces (EVB 3rd Layer)

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3.7. LCM Interface

LCM interface is for EC200U series module only.

⚫ LCD_CLK is recommended to be surrounded with ground on the same layer and with ground planes
above and below separately.
⚫ Keep LCD_SI/O singal surrounded with ground.

LCD_SI/O
LCD_CLK

GND

GND

GND

GND

GND

Figure 23: Overview of LCD Signal Traces (EC200U TE-A 2nd Layer)

⚫ ISINK is recommended to be surrounded with ground on the same layer and with ground planes
above and below separately. The recommended trace width for ISINK is 0.3 mm.

GND

GND

ISINK

Figure 24: Overview of ISINK Signal Trace (EC200U TE-A 3rd Layer)

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3.8. (U)SIM Interface

⚫ The total length of each (U)SIM signal trace should be less than 200 mm.
⚫ Isolate USIM_CLK and USIM_DATA with ground plane to avoid the interference between each other.
⚫ Place TVS, capacitors, resistors and other peripheral components near the (U)SIM card connector.

(U)SIM
interface
GND
GND

TVS & capacitors &

resistors

GND
(U)SIM card connector
GND

GND

Figure 25: Overview of (U)SIM Signal Traces (EVB 1st Layer)

USIM_RST GND
USIM_VDD USIM_CLK
USIM_DATA

GND USIM_DET

GND
GND

GND

Figure 26: Overview of (U)SIM Signal Traces (EVB 2nd Layer)

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3.9. ADC Interface

All ADC signal traces should be surrounded with ground.

GND

ADC0 ADC1

GND

GND

GND

Figure 27: Overview of ADC Signal Traces (EVB 3rd Layer)

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3.10. GPIOs

⚫ Keep GPIO traces away from interference signals such as clock, RF and power supplies.
⚫ Filter capacitors need to be added and be placed close to the module when GPIO is used as the
input.

Figure 28: Overview of GPIO Signal Traces (EC200A TE-A Without Copper Pouring)

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3.11. Antenna Interfaces

3.11.1. PCB Structures of Microstrip and Coplanar Waveguide

3.11.1.1. PCB Structure of Microstrip Waveguide

Figure 29: PCB Structure of Microstrip Waveguide

3.11.1.2. PCB Structure of Coplanar Waveguide

Factors affecting impedance include dielectric constant (4.2 to 4.6 usually, 4.4 here), dielectric layer
height (H), RF trace width (W), spacing between RF traces, ground (S) and copper thickness (T). When T
= 0.035 mm, the following table lists the recommended values of W and S for 50 Ω coplanar waveguide
under different PCB structures.

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Figure 30: PCB Structure of Coplanar Waveguide

Table 2: Recommended Values of W and S for 50 Ω Coplanar Waveguide under Different PCB
Structures (Unit: mm)

Dielectric Height (H) RF Trace Width (W) Spacing Between RF Trace and the Ground (S)

0.076 0.1188 0.15

0.1 0.1623 0.2

0.15 0.24 0.2

0.8 0.8 0.18

1.0 0.8 0.17

1.2 0.8 0.16

1.6 0.8 0.15

2 0.8 0.14

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3.11.2. Reference Design of RF Layout

For user’s PCB, the characteristic impedance of all RF traces should be controlled to 50 Ω. The
impedance of the RF traces is usually determined by the trace width (W), the materials’ dielectric constant,
the height from the reference ground to the signal layer (H), and the spacing between RF traces and
grounds (S). Microstrip or coplanar waveguide is typically used in RF layout to control characteristic
impedance.

If there is a 2-layer PCB, the top layer is used for signal trace routing, and the bottom layer should be the
reference ground layer, as shown in Figure 31 and Figure 32. If there is a 4-layer PCB, the reference
ground layer can be the second, the third, or the fourth layer. If the third layer is selected as the ground
layer, the second layer should be kept out, and the width of the keep-out area should be at least 5 times
the width of the trace. If the fourth layer is selected as the ground layer, the operation is similar, as shown
in Figure 33 and Figure 34. The following are reference designs of microstrip and coplanar waveguide
with different PCB structures.

Figure 31: Microstrip Design on a 2-layer PCB

Figure 32: Coplanar Waveguide Design on a 2-layer PCB

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Figure 33: Coplanar Waveguide Design on a 4-layer PCB (Layer 3 as Reference Ground)

Figure 34: Coplanar Waveguide Design on a 4-layer PCB (Layer 4 as Reference Ground)

3.11.3. PCB Layout Considerations of Coplanar Waveguide

6 guidelines of the PCB layout should be taken into consideration. Each guideline is corresponding to the
marks in the following two figures respectively.

1. Control the trace width (W) and the spacing between RF traces and grounds (S) corresponding to the
50 Ω coplanar waveguide. Taking common PCB board with FR4 medium (dielectric constant 4.2) and
copper thickness of 35 μm as an example, the W and the S corresponding to the thickness between
different signal layers and reference grounds are shown in Table 2. It is particularly reminded that
PCB manufacturers need to control the accuracy of the W and the S.

2. The GND pins adjacent to RF pins should not be designed as thermal relief pads, and should be fully
connected to ground.

3. Leave a small keepout area for RF traces on the top layer to reduce parasitic effects. Keep the traces
as short as possible. Avoid right-angle routing for RF traces and 135 degrees is recommended when
traces turn corner.

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4. Keep a certain distance between signal pad and ground when packaging the component. If the signal
pad is SMD type, pour the copper on the corresponding signal pad.

5. Ensure that reference ground planes corresponding to RF traces are complete. Increase the number
of GND vias for current reflow of RF signal, and the spacing between GND vias and RF traces should
be more than twice the trace width. Keep the ground plane area for RF traces within the same layer
as large as possible and the reference ground plane in other layer complete as well. Besides, the
number of through vias for those two ground planes should be sufficient.

6. The pads for π-type matching circuit consisting of a resistor and two capacitors should be near the
module’s antenna pins.

Figure 35: Overview of RF Traces (EVB 1st Layer)

Figure 36: Overview of RF Traces (EVB 1st and 2nd Layers)

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4 Appendix References

Table 3: Related Documents

Document Name

[1] Quectel_Module_Thermal_Design_Guide

[2] Quectel_EC200A_Series_Footprint&Part

[3] Quectel_EC200U_Series_Footprint&Part

Table 4: Terms and Abbreviations

Abbreviation Description

ADC Analog-to-Digital Converter

CPU Central Processing Unit

DRAM Dynamic Random Access Memory

ESD Electrostatic Discharge

GPIO General-Purpose Input/Output

I/O Input/Output

LCD Liquid Crystal Display

LCM LCD Module

LTE Long Term Evolution

PCB Printed Circuit Board

PCM Pulse Code Modulation

PHY Physical Layer

PMU Power Management Unit

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RF Radio Frequency

RGMII/RMII Reduced Gigabit Media Independent Interface

SD Secure Digital

SDIO Secure Digital Input/Output

USB Universal Serial Bus

(U)SIM (Universal) Subscriber Identity Module

VBAT Voltage at Battery

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