UNIT 3

BASIC ORGANIZATION- 1
CONTENTS
General register organization
ALU
Instruction codes
Instruction format
Stack organization
Addressing modes

COMPUTER ORGANISATION AND ARCHITECTURE

BY PROF. SHINDE M.D. 2
INTRODUCTION TO PROCESSOR ORGANIZATION
• Requirements of processor (what processor should do):
1. Fetch instruction
2. Interpret instruction
3. Fetch data
4. Process data
5. Write data

COMPUTER ORGANISATION AND ARCHITECTURE

BY PROF. SHINDE M.D. 3
• To do all above… processor needs to store some data
temporarily.

• It should remember the location of the last instruction.

• It need to store instructions and data temporarily while
an instruction is being executed.

• In short, processor needs a small internal memory.

• Fig. shows the simplified view of the processor.

COMPUTER ORGANISATION AND ARCHITECTURE

BY PROF. SHINDE M.D. 4
Fig. Simplified View Of Processor Data bus

Registers

ALU

Control Unit

Control bus
Address bus
COMPUTER ORGANISATION AND ARCHITECTURE
BY PROF. SHINDE M.D. 5
 REGISTERS
• A control unit operates by fetching instructions from
memory and executing them one at a time.
• Fig shows the memory format of the processor
0 1 39

a. Number Word

0 8 20 28 39

opcode address opcode address

b. Instruction Word
COMPUTER ORGANISATION AND ARCHITECTURE
BY PROF. SHINDE M.D. 6
• Both ALU and CU contain storage locations, called
registers., defined as:
1. MBR : Memory Buffer Register
2. IR : Instruction Register
3. MAR : Memory Address Register
4. IBR : Instruction Buffer Register
5. PC : Program Counter
6. AC & MQ : Accumulator And Multiplier Quotient

COMPUTER ORGANISATION AND ARCHITECTURE

BY PROF. SHINDE M.D. 7
1. MBR :contains a word of data to be written to memory
or the word most recently read.
2. IR: contains the instruction most recently fetched.
3. MAR : contains the address of a location in memory.
4. IBR : contains the right hand instruction from a word in
memory.
5. PC: contain the address of the next instruction.
6. AC & MQ : holds operands and result of ALU
operations.

COMPUTER ORGANISATION AND ARCHITECTURE

BY PROF. SHINDE M.D. 8
 REGISTER ORGANISATION
• The register in the processor perform two roles:

1. User visible registers

2. Control and status registers

• There is not a clean separation of registers into these

two categories.
• For ex. On some machines the program counter is user
visible, but on many it is not.

COMPUTER ORGANISATION AND ARCHITECTURE

BY PROF. SHINDE M.D. 9
USER-VISIBLE REGISTERS
• A user-visible register is one that may be referenced by
means of the machine language that the processor
executes.
• Categories :

1. General purpose
2. Data
3. Address
4. Condition codes

COMPUTER ORGANISATION AND ARCHITECTURE

BY PROF. SHINDE M.D. 10
General Purpose Registers
• These registers can be assigned to the variety of functions by the
programmer.
• Any general purpose register can contain the operand for any
opcode.
• In some cases, these registers can be used for addressing function.

Data Registers
• These registers may be used only to hold data and can not be
employed in the calculation of an operand address.

COMPUTER ORGANISATION AND ARCHITECTURE

BY PROF. SHINDE M.D. 11
Address registers
• These registers may themselves be general purpose registers
• Or, they may be devoted to a particular addressing mode.
• Ex:
 Segment pointers
 Index registers
 Stack pointer

Conditional codes
• Referred as flags.
• These are bits set by the processor hardware as the result of
operations.

COMPUTER ORGANISATION AND ARCHITECTURE

BY PROF. SHINDE M.D. 12
Control And Status Registers
• These registers are used for controlling the execution of
the instruction.
• Four essential to instruction execution :

 PC
 IR
 MAR
 MBR

COMPUTER ORGANISATION AND ARCHITECTURE

BY PROF. SHINDE M.D. 13
• Many processor design include a set of registers to hold
the status, known as PSW-program status word.
• Common fields or flags are
 Sign
 Zero
 Carry
 Equal
 Overflow
 Interrupt enable / disable
 supervisor

COMPUTER ORGANISATION AND ARCHITECTURE

BY PROF. SHINDE M.D. 14
ALU
• This is the part of the computer which actually perform arithmetic and
logical operations in CPU.
• All other elements of the Computer System(control unit, registers,
memory, IO) are mainly to bring data to the ALU.
• ALU processes the data and take the result back out.
• As computer uses only binary digits (0,1), ALU performs the operations of
Boolean Logic Expressions.
Fig. ALU Input & Output

Flags
Control Unit

ALU
Registers Registers

COMPUTER ORGANISATION AND ARCHITECTURE

BY PROF. SHINDE M.D. 15
• Instead of having individual registers performing the
operations directly, computer system employ a number of
storage registers connected to a common operational unit
called ALU.
• To perform a operation, the content of specified registers are
placed in the inputs of the common ALU.
• ALU performs an operation and the result is then transferred
to the destination register.
• ALU is a combinational circuit.
• The arithmetic, logic and shift circuits are combined into one
ALU with common selection variables.

COMPUTER ORGANISATION AND ARCHITECTURE

BY PROF. SHINDE M.D. 16
 ALU OPERATIONS (INTEGER ALU)

Add (A+B)
Add with Carry (A+B+Cin)  Not A
Subtract (A-B)  Not B
Subtract with Borrow (A-B-Cin)  A
[Subract reverse (B-A)]
 B
[Subract reverse with Borrow (B-A-Cin)]
Negative A (-A)  Multiply Step or Multiply
Negative B (-B)  Divide Step or Divide
Increment A (A+1)
 Mask
Increment B (B+1)
Decrement A (A-1)  Conditional AND/OR (uses
Decrement B (B-1) Mask)
Logical AND  Shift
Logical OR  Zero
Logical XOR
COMPUTER ORGANISATION AND ARCHITECTURE
BY PROF. SHINDE M.D. 17
 • The encoding of the ALU operations for the CPU is
specified in table below.
• The OPR has five bits and each operation is designed
with a symbolic name.
OPR Select Operation Symbol
00000 Transfer A TSFA
00001 Increment A INCA
00010 Add A+B ADD
00101 Subtract A-B SUB
00110 Decrement A DECA
01000 AND A and B AND
01010 OR A and B OR
01100 XOR A and B XOR
01110 Complement A COMA
10000 Shift right A SHRA
11000 Shift left A SHLA 18
COMPUTER ORGANISATION AND ARCHITECTURE BY PROF. SHINDE M.D.
• Example Of Operation:

• R1 R2 – R3

COMPUTER ORGANISATION AND ARCHITECTURE

BY PROF. SHINDE M.D. 19
Instruction Codes
• A Computer instruction is binary code that specify the
sequence of micro operation for the computer.

• The Computer reads each instruction from memory and

places it in a control register.

• The control then interprets the binary code of the instruction

and proceeds to execute it by issue a sequence of micro
operation

COMPUTER ORGANISATION AND ARCHITECTURE

BY PROF. SHINDE M.D. 20
Instruction Codes
• An instruction code is a group of bits that instruct the
computer to perform a specific task.

• It is usually divided into two parts each having its own

particular interpretation.

• They are
-Operation code and
-operands.
• The most basic part of an instruction code is its operation
part

COMPUTER ORGANISATION AND ARCHITECTURE

BY PROF. SHINDE M.D. 21
Operation Code
• The Operation code (OpCode) of an instruction is a group of bits
that define each operation such add, subtract, multiply, shift and
complement.

• It must consist of at least n bits for a given 2n district operations.

• Suppose we are having 64 (26) operation then the length of

OpCode will be 6.

• The control unit decode the OpCode and do the required operation.

COMPUTER ORGANISATION AND ARCHITECTURE

BY PROF. SHINDE M.D. 22
Operands
• The operation must be performed on Some data stored in
processor register or in memory.

• Every Computer has its own particular instruction code format.

• The simplest way to organize a computer is to have an instruction

code format with two parts.

• The first part specifies the operation to be performed and the

second specifies an address

COMPUTER ORGANISATION AND ARCHITECTURE

BY PROF. SHINDE M.D. 23
Instruction Codes
• The basic computer has three instruction code format.

• The OpCode part of the instruction contains three bits and

the meaning of the remaining 13 bits depend on the
operation code encountered.

• The three instruction code formats are:

1. Memory-reference instructions
2. Register-reference instruction
3. Input-output instruction

COMPUTER ORGANISATION AND ARCHITECTURE

BY PROF. SHINDE M.D. 24
Memory-reference Instructions

• A Memory-reference instructions uses 12 bits to specify

an address and one bit to specify the addressing mode I.

• I is equal to 0 for direct address and to 1 for indirect

address.

COMPUTER ORGANISATION AND ARCHITECTURE

BY PROF. SHINDE M.D. 25
Register-reference Instruction

• The register-reference instruction are recognized by the

operation code 111 with 0 in the leftmost bit (bit 15) of the
instruction.

• It specifies the operation on or test of the AC register.

• An operand from memory is not needed, so the other 12 bits

are used to specify the operation or test to be executed.

COMPUTER ORGANISATION AND ARCHITECTURE

BY PROF. SHINDE M.D. 26
Input-output Instruction

• An input or output instruction does not need a

reference to memory and recognized by the operation
code 111 with a 1 in the leftmost bit of the instruction.

• The remaining 12 bits are used to specify the type of

input -output operation or test performed.

COMPUTER ORGANISATION AND ARCHITECTURE

BY PROF. SHINDE M.D. 27
 INSTRUCTION FORMATS

• The most common fields in instruction formats are:

1. Mode field: Specifies the way the effective address is determined

2. Operation code: Specifies the operations to be performed.
3. Address field: Designates a memory address or a processor
register

Mode Opcode Address

COMPUTER ORGANISATION AND ARCHITECTURE

BY PROF. SHINDE M.D. 28
Instruction Formats
• Zero address instruction: Stack is used. Arithmetic operation pops
two operands from the stack and pushes the result.

• One address instructions: AC and memory. Since the accumulator

always provides one operand, only one memory address needs to be
specified.

• Two address instructions: Two address registers or two memory

locations are specified, one for the final result.

• Three address instructions: Three address registers or memory

locations are specified, one for the final result.
It is also called general address organization.

COMPUTER ORGANISATION AND ARCHITECTURE

BY PROF. SHINDE M.D. 29
 ZERO ADDRESS INSTRUCTIONS

Push and pop operations need to specify one address

involved in data transfer.

Instruction: POP X

PUSH, and POP instructions need an address

field to specify the operand

COMPUTER ORGANISATION AND ARCHITECTURE

BY PROF. SHINDE M.D. 30
ZERO ADDRESS INSTRUCTIONS

PUSH A
PUSH B
ADD
PUSH C
PUSH D
ADD
MUL
POP X

Advantages: No memory addresses needed during the operation.

Disadvantages: results in longer program codes.

COMPUTER ORGANISATION AND ARCHITECTURE

BY PROF. SHINDE M.D. 31
ONE ADDRESS INSTRUCTIONS
• One address can be a register name or memory address.
• SINGLE ACCUMULATOR ORGANIZATION

• Since the accumulator always provides one operands,

only one memory address needs to be specified.
Instruction: ADD X

• Microoperation: AC ¬ AC + M[X]

COMPUTER ORGANISATION AND ARCHITECTURE

BY PROF. SHINDE M.D. 32
ONE ADDRESS INSTRUCTIONS

LOAD A AC  M [ A]
ADD B AC  AC  M [ B]
STORE T M [T ]  AC

All operations are done between the AC register and memory operand

Advantages: fewer bits are needed to specify the address.

Disadvantages: results in writing long programs.

COMPUTER ORGANISATION AND ARCHITECTURE

BY PROF. SHINDE M.D. 33
TWO ADDRESS INSTRUCTIONS
• Assumes that the destination address is the same as
that of the first operand. Can be a memory address or
a register name.

Instruction: ADD R1, R2

Microoperation: R1  R1 + R2

COMPUTER ORGANISATION AND ARCHITECTURE

BY PROF. SHINDE M.D. 34
 TWO ADDRESS INSTRUCTIONS

MOV R1, A R1  M [ A]
MOV R2, B R 2  M [ B]
ADD R1, R2 R1  R1  R 2
MOV X, R1 M [ x]  R1

most common in commercial computers

Each address fields specify either a processor register or a memory

operand

Advantages: results in writing medium size programs

Disadvantages: more bits are needed to specify two addresses.
COMPUTER ORGANISATION AND ARCHITECTURE
BY PROF. SHINDE M.D. 35
 THREE ADDRESS ORGANIZATION
GENERAL REGISTER ORGANIZATION

• Three address instructions: Memory addresses for the two operands and
one destination need to be specified.

Instruction: ADD R1, R2, R3

Microoperation: R1  R2 + R3

ADD R1, R2, R3 R1  R2  R3

Advantages: results in writing short programs

Disadvantages: more bits are needed to specify three addresses.

COMPUTER ORGANISATION AND ARCHITECTURE

BY PROF. SHINDE M.D. 36
EXAMPLE: Show how can the following operation be
performed using:
a- three address instruction
b- two address instruction
c- one address instruction
d- zero address instruction
X = (A + B) * (C + D)

COMPUTER ORGANISATION AND ARCHITECTURE

BY PROF. SHINDE M.D. 37
A-THREE-ADDRESS INSTRUCTIONS
(GENERAL REGISTER ORGANIZATION)

ADD R1, A, B
R1  M[A] + M[B]
ADD R2, C, D
R2  M[C] + M[D]
MUL X, R1, R2
M[X]  R1 * R2

COMPUTER ORGANISATION AND ARCHITECTURE

BY PROF. SHINDE M.D. 38
 B-TWO-ADDRESS INSTRUCTIONS
(GENERAL REGISTER ORGANIZATION)
MOV R1, A
R1  M[A]
ADD R1, B
R1  R1 + M[B]
MOV R2, C
R2  M[C]
ADD R2, D
R2  R2 + M[D]
MOV X, R2
M[X] R2
MUL X, R1
M[X]  R1 * M[X]
COMPUTER ORGANISATION AND ARCHITECTURE
BY PROF. SHINDE M.D. 39
 C- ONE-ADDRESS INSTRUCTIONS
LOAD A
AC M[A]
ADD B
AC  AC + M[B]
STORE T
M[T ] AC
LOAD C
AC  M[C]
ADD D
AC  AC + M[D]
MUL T
AC  AC * M[T ]
STORE X
M[X]  AC Store
COMPUTER ORGANISATION AND ARCHITECTURE
BY PROF. SHINDE M.D. 40
 D- ZERO-ADDRESS INSTRUCTIONS
(STACK ORGANIZATION)
Push value
Else If operator is encountered: Pop, pop, operation, push
Pop operand pop another operand then perform an operation
and push the result back into the stack.

PUSH A TOS  A Push

PUSH B TOS  B
ADD TOS  (A+B) Pop, pop, operation, push
PUSH C TOS  C
PUSH D TOS  D
ADD TOS  (C+D)
MUL TOS  (C+D)*(A+B)
POP X M[X]  TOS
(*TOS stands for top of stack).
COMPUTER ORGANISATION AND ARCHITECTURE
BY PROF. SHINDE M.D. 41
STACK ORGANIZATION
Stack: A storage device that stores information in
such a manner that the item stored last is the
first item retrieved.

Also called last-in first-out (LIFO) list. Useful for

compound arithmetic operations and nested
subroutine calls.

COMPUTER ORGANISATION AND ARCHITECTURE

BY PROF. SHINDE M.D. 42
STACK ORGANIZATION

• Stack pointer (SP): A register that holds the

address of the top item in the stack.
SP always points at the top item in the
stack
• Push: Operation to insert an item into the stack.
• Pop: Operation to retrieve an item from the
stack.

COMPUTER ORGANISATION AND ARCHITECTURE 43

BY PROF. SHINDE M.D.
 REGISTER STACK

• A stack can be
organized as a
collection of a finite
number of registers.

COMPUTER ORGANISATION AND ARCHITECTURE

BY PROF. SHINDE M.D. 44
 REGISTER STACK
IN A 64-WORD STACK, THE STACK
POINTER CONTAINS 6 BITS.

THE ONE-BIT REGISTER FULL IS SET

TO 1 WHEN THE STACK IS FULL;
EMPTY REGISTER IS 1 WHEN THE
STACK IS EMPTY.

THE DATA REGISTER DR HOLDS THE

DATA TO BE WRITTEN INTO OR READ
FROM THE STACK.

COMPUTER ORGANISATION AND ARCHITECTURE

BY PROF. SHINDE M.D. 45
 The Following Are The Micro-operations
Associated With The Stack

Initialization
SP 0, EMPTY 1, FULL 
0
Push
SP SP + 1
M[SP] DR
If (SP = 0) then (FULL 1)
Note that SP becomes 0 after 63
EMPTY 0

COMPUTER ORGANISATION AND ARCHITECTURE

BY PROF. SHINDE M.D. 46
 The following are the micro-operations
associated with the stack

Pop
DR M[SP]
SP SP - 1
IF (SP = 0) THEN (EMPTY 
1)
FULL 0

COMPUTER ORGANISATION AND ARCHITECTURE

BY PROF. SHINDE M.D. 47
STACK OPERATIONS
REVERSE POLISH NOTATION (Postfix)

REVERSE POLISH NOTATION :IS A POSTFIX NOTATION (PLACES

OPERATORS AFTER OPERANDS)

(EXAMPLE)
INFIX NOTATION A+B
REVERSE POLISH NOTATION AB+ ALSO CALLED POSTFIX.

COMPUTER ORGANISATION AND ARCHITECTURE

BY PROF. SHINDE M.D. 48
STACK OPERATIONS
REVERSE POLISH NOTATION (POSTFIX)
A STACK ORGANIZATION IS VERY EFFECTIVE FOR EVALUATING
ARITHMETIC EXPRESSIONS

A * B + C * D  (AB *)+(CD *)  AB * CD * +

( 3 * 4 ) + ( 5 * 6 )  34 * 56 * +

COMPUTER ORGANISATION AND ARCHITECTURE

BY PROF. SHINDE M.D. 49
STACK OPERATIONS
REVERSE POLISH NOTATION (POSTFIX)
• EVALUATION PROCEDURE:

1. SCAN THE EXPRESSION FROM LEFT TO RIGHT.

2. WHEN AN OPERATOR IS REACHED, PERFORM THE OPERATION WITH THE
TWO OPERANDS FOUND ON THE LEFT SIDE OF THE OPERATOR.
3. REPLACE THE TWO OPERANDS AND THE OPERATOR BY THE RESULT
OBTAINED FROM THE OPERATION.

(EXAMPLE)
INFIX 3 * 4 + 5 * 6 = 42
POSTFIX 3 4 * 5 6 * +

12 5 6 * +
12 30 +
42

COMPUTER ORGANISATION AND ARCHITECTURE

BY PROF. SHINDE M.D. 50
STACK OPERATIONS
REVERSE POLISH NOTATION (POSTFIX)

• REVERSE POLISH NOTATION EVALUATION WITH A STACK.

STACK IS THE MOST EFFICIENT WAY FOR EVALUATING
ARITHMETIC EXPRESSIONS.

stack evaluation:
Get value
If value is data: push data
Else if value is operation: pop, pop
evaluate and push.

COMPUTER ORGANISATION AND ARCHITECTURE

BY PROF. SHINDE M.D. 51
STACK OPERATIONS
REVERSE POLISH NOTATION (POSTFIX)

(Example) using stacks to do this.

3 * 4 + 5 * 6 = 42
=> 3 4 * 5 6 * +

COMPUTER ORGANISATION AND ARCHITECTURE

BY PROF. SHINDE M.D. 52
ADDRESSING MODES

• The way the operands are chosen during

execution of an instruction is determined by
the addressing mode.

Opcode Mode Address

Instruction Format with mode field

COMPUTER ORGANISATION AND ARCHITECTURE

BY PROF. SHINDE M.D. 53
PURPOSE OF ADDRESSING MODES

• To provide programming flexibility to the user

like pointers to memory, counters for loop
control, indexing of data, etc.
• To reduce the no. of bits in the addressing
field of the instruction.

COMPUTER ORGANISATION AND ARCHITECTURE

BY PROF. SHINDE M.D. 54
ADDRESSING MODES

• Mode fields is used to locate operands.

• If instruction contains an address field, it may
be a register or a memory address.
• If more than one address field, each field is
associated with its own mode.

COMPUTER ORGANISATION AND ARCHITECTURE

BY PROF. SHINDE M.D. 55
 TYPES OF ADDRESSING MODES
• Implied Mode
• Immediate Mode
• Register Mode
• Register Indirect Mode
• Auto-increment or Auto-decrement
• Direct Address mode
• Indirect Address Mode
• Relative Addressing Mode
• Indexed Addressing Mode
• Base Register Addressing Mode

COMPUTER ORGANISATION AND ARCHITECTURE

BY PROF. SHINDE M.D. 56
 TYPES OF ADDRESSING MODES

• Implied Mode- operands are specified implicitly in the

instruction itself. Eg. “Increment Accumulator”

• Immediate Mode- the address field contains the

operand itself instead of the address of the operand.

COMPUTER ORGANISATION AND ARCHITECTURE

BY PROF. SHINDE M.D. 57
• Register Mode- the address field contains the
address of a CPU register which contains the
operand.

• Register Indirect Mode- the address field contains the

address of a register which holds the memory
address of the operand. Advantage : fewer bits
required to represent a register than a memory word.

COMPUTER ORGANISATION AND ARCHITECTURE

BY PROF. SHINDE M.D. 58
• Autoincrement or Autodecrement – similar to register
indirect mode except that the value of the register is
incremented or decremented after it has been used
to access memory. Usually used to refer to a table of
data.

• Direct Address mode- the address field contains the

memory address of the operand.

COMPUTER ORGANISATION AND ARCHITECTURE

BY PROF. SHINDE M.D. 59
• Indirect Address Mode- the address field contains
the address of the memory location that contains the
operand.
• Relative Addressing Mode-
 the address of the program counter is added to the
address field to get the address of the operand.
 Usually used in branch type instructions.
 Lesser no. of bits to represent the relative address
than compared to the full memory address.

COMPUTER ORGANISATION AND ARCHITECTURE

BY PROF. SHINDE M.D. 60
• Indexed Addressing Mode-
 The content of an index register is added to the address
part of the instruction in order to obtain the effective
address.
 Useful in case of an array.
• Base Register Addressing Mode-
 The content of a base register is added to the address
part of the instruction in order to obtain the effective
address.
 The difference with Indexed addressing mode is in its
use.
 Used for relocation of programs in memory.

COMPUTER ORGANISATION AND ARCHITECTURE

BY PROF. SHINDE M.D. 61
NUMERICAL EXAMPLE

COMPUTER ORGANISATION AND ARCHITECTURE

BY PROF. SHINDE M.D. 62
THANKS 

COMPUTER ORGANISATION AND ARCHITECTURE

BY PROF. SHINDE M.D. 63