DEPARTMENT OF ARTIFCIAL INTELLIGENCE AND DATA
SCIENCE
DIGITAL DESIGN AND COMPUTER ORGANIZATION
(BCS302)
LABORATORY MANUAL
FOR
3RD SEM
ARTIFICIAL INTELLIGENCE AND DATA
SCIENCE
Prepared by:
Prof. SAFRA MAMTHAZ BHANU
Assistant Professor Lab instructor
Department of AI&DS Department of AI&DS
DEPARTMENT OF AI&DS
DCO Lab BCS302
[Link] Experiments
1 Write Verilog description for all basic and universal gates using dataflow
style.
2 Given a 4- variable logic expression, simplify it using appropriate technique
and simulate the same using basic gates.
3 Design adders and subtractors, simulate the same using gates.
4 Design Verilog module to implement simple circuit using behavioral and
structural model.
5 Design Verilog program for implementing various types of flip-flops such as
SR, JK, D and T.
6 Design Verilog program for implement different types of multiplexer like 2:1,
4:1 and 8:1.
7 Design Verilog program to implement types of De-Multiplexer.
8 Design Verilog program to implement decimal adder.
2023-24 Page 1
DDCO Lab BCS302
DDCO Lab BCS302
PROGRAM-1:
Write Verilog description for all basic and universal gates using dataflow style.
module pgm1(a,b,c,d,e,f,g,h,i);
input a,b; output
c,d,e,f,g,h,i; assign
c=~a; assign
d=a&b; assign
e=a|b; assign
f=~(a&b); assign
g=~(a|b); assign
h=a^b; assign
i=~(a^b);
endmodule
OUTPUT:
DDCO Lab BCS302
PROGRAM-2:
Given a 4- variable logic expression, simplify it using appropriate technique and
simulate the same using basic gates.
module kmap(w,x,y,z,f);
input w, x, y, z; output
f;
assign f=w|(~x &~y)|(~x & z);
endmodule
OUTPUT:
DDCO Lab BCS302
PROGRAM-3:
Design adders and subtractors, simulate the same using gates.
3.a. Half-adder
module pgm3(a,b,sum, carry);
input a,b; output
sum,carry; assign
sum=a|b; assign
carry=a&b;
endmodule
OUTPUT:
DDCO Lab BCS302
3.b Full adder
module pgm3(a,b,c,sum, carry);
input a,b,c; output
sum,carry; assign
sum=a^b^c;
assign carry=(a&b)|(a&c)|(b&c);
endmodule
OUTPUT:
DDCO Lab BCS302
3.c. Half-subtractor
module pgm3(a,b,diff, borrow);
input a,b; output
diff, borrow; assign
sum=a^b; assign
carry=~a&b;
endmodule
OUTPUT:
DDCO Lab BCS302
3.d. Full subtractor
module pgm2d(a,b,c,diff, borrow);
input a,b,c; output diff, borrow;
assign sum=a^b^c; assign
carry=(~a&b)|(~a&c)|(b&c);
endmodule
OUTPUT:
DDCO Lab BCS302
PROGRAM-4
Design Verilog module to implement simple circuit using behavioural and structural
model.
4.a. Behavioural Model
module bcd_e3(B,E);
input [3:0]B;
output[3:0]E;
reg[3:0]E; always@(B)
begin
case(B)
4'b000:E =4'b0011;
4'b001:E =4'b0100;
4'b010:E =4'b0101;
4'b011:E =4'b0110;
4'b100:E =4'b0111;
4'b101:E =4'b1000;
4'b000:E =4'b0011;
4'b0110:E =4'b1001;
4'b0111:E =4'b1010;
4'b1000:E =4'b1011;
4'b1001:E
=4'b1100; default;
endcase
end
endmodule
OUTPUT:
DDCO Lab BCS302
4.b. Structural model
module fullllll(a,b,c,sum,carry);
input a,b,c; output
sum, carry; wire
s1,s2,s3,s4,s5; xor
x1(s1,a,b); xor
x2(sum,s1,c); and
a1(s2,a,b); and
a2(s3,b,c); and
a3(s4,a,c); or
o1(s5,s2,s3); or
o2(carry,s5,s4);
endmodule
OUTPUT:
DDCO Lab BCS302
PROGRAM-5:
Design Verilog program for implementing various types of flip-flops such as SR, JK, D
and T.
5.a. SR flip-flop:
module srff(clk,sr,q,qb);
input clk;
input[1:0]sr; output
q,qb; reg q,qb; initial
q=1'b0;
always@(posedge(clk))
begin
case(sr)
2'b00:q=q;
2'b01:q=1'b0;
2'b10:q=1'b1;
2'b11:q=1'bz;
default;
endcase qb=~q;
end
endmodule
OUTPUT:
5.b. JK flip-flop:
module jkff(clk,jk,q,qb);
input clk;
input[1:0]jk;
DDCO Lab BCS302
output q,qb;
reg q,qb; initial
q=1'b0;
always@(negedge(clk))
begin case(jk)
2'b00:q=q;
2'b01:q=1'b0;
2'b10:q=1'b1;
2'b11:q=~q;
default;
endcase qb=~q;
end
endmodule
OUTPUT:
5. c. D flip-flop:
module dff(clk,d,q,qb);
input clk;
input d; output
q,qb; reg q,qb;
initial q=1'b0;
DDCO Lab BCS302
always@(posedge(clk))
begin case(d)
1'b0:q=0; 1'b1:q=1;
default; endcase
qb=~q; end
endmodule
OUTPUT:
5.d. T flip-flop:
module tff(clk,t,q,qb);
input clk;
input t; output
q,qb; reg q,qb;
initial q=1'b0;
always@(negedge(clk))
begin case(t)
1'b0:q=q; 1'b1:q=~q;
DDCO Lab BCS302
default; endcase
qb=~q; end
endmodule
OUTPUT:
DDCO Lab BCS302
PROGRAM-6:
Design Verilog program for implement different types of multiplexer like 2:1,
4:1 and 8:1.
6. a. 2:1 MUX
module dmxxx(En,S,I,y);
input En, S; input[1:0]I;
output y; reg y;
always@(En,S) begin
if(En ==1'b0)
y<=1'b0; else
case(S)
1'b0:y =I[0];
1'b1:y =I[1];
default;
endcase end
endmodule
OUTPUT:
6.b 4:1 MUX:
module muxxx(En,S,I,y);
input En;
input[1:0]S;
input[3:0]I; output y;
DDCO Lab BCS302
reg y;
always@(En,S)
begin
if(En ==1'b0)
y<=1'b0; else
case(S)
2'b00:y =I[0];
2'b01:y =I[1];
2'b10:y =I[2];
2'b11:y =I[3];
default; endcase
end
endmodule
OUTPUT:
6.c. 8:1 MUX:
module muxx(En,S,I,y);
input En; input[2:0]S;
input[7:0]I; output y; reg
y; always@(En,S) begin
if(En ==1'b0)
y<=1'b0; else
case(S)
3'b000:y =I[0];
3'b001:y =I[1];
3'b010:y =I[2];
3'b011:y =I[3];
DDCO Lab BCS302
3'b100:y =I[4];
3'b101:y =I[5];
3'b110:y =I[6];
3'b111:y =I[7];
default; endcase
end
endmodule
OUTPUT:
DDCO Lab BCS302
PROGRAM-7:
Design Verilog program to implement types of De-Multiplexer.
module dmm(En,S,A,y);
input En,A; input[2:0]S;
output[7:0]y; reg[7:0]y;
always@(En,S)
begin
if(En ==1'b0)
y<=8'b00000000;
else case(S)
3'b000:y[0]=A;
3'b001:y[1]=A;
3'b010:y[2]=A;
3'b011:y[3]=A;
3'b100:y[4]=A;
3'b101:y[5]=A;
3'b110:y[6]=A;
3'b111:y[7]=A; default;
endcase
end
endmodule
OUTPUT:
DDCO Lab BCS302
PROGRAM-8:
Design Verilog program to implement decimal adder
module decimaladder (A,B,cin,sum,cout);
input[3:0]A,B;
input cin;
output[3:0]sum; output
cout;
assign{cout,sum} =A+B+4'b0000;
endmodule
OUTPUT:
