CXA2006Q

Digital CCD Camera Head Amplifier

Description
The CXA2006Q is a bipolar IC developed as a 32 pin QFP (Plastic)
head amplifier for digital CCD cameras. This IC
provides the following functions: correlated double
sampling, AGC for the CCD signal, GCA for the low-
band chroma signal, AMP for high-band chroma and
line signals, A/D sample and hold, blanking, A/D
reference voltage, and an output driver.

Features
• High sensitivity made possible by a high-gain AGC
amplifier
• Blanking function provided for the purpose of
calibrating the CCD output signal black level
• Regulator output pin provided for A/D converter
reference voltage
• Built-in GCA and AMP for amplifying video signals
(chroma and line signals) from external sources
• Built-in sample-and-hold circuits (for camera signals
and for video signals) required by external A/D
converters

Absolute Maximum Ratings

• Supply voltage VCC 14 V
• Operating temperature Topr –20 to +75 °C
• Storage temperature Tstg –65 to +150 °C
• Allowable power dissipation
PD 640 mW

Operating Conditions
Supply voltage VCC1, 2, 3 4.5 to 5 V

Applications
Digital CCD cameras

Structure
Bipolar silicon monolithic IC

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

–1–
E94X41B8X-PS
 CXA2006Q

Block Diagram and Pin Configuration

CCDLEVEL

AGCCONT
CLPDM

GND1

VCC1
SHP
SHD

N.C.
24 23 22 21 20 19 18 17

PIN 25 16 AGCCLP

AGCCLP
DIN 26 SH1 SH2 15 CLPOB
AGC LPF CAMSH BLK
SH3
VCC2 27 14 XRS
COSCLP1

N.C. 28 REF REF 13 PBLK

COSCLP2
BOTTOM TOP

LIN/CH 29 12 OFFSET
LIN/CH SW
C/V SW OFFSET
LIN CLP VI SW SW
GND2 30 AMP 11 VRT
VISH
CENTER BIAS

CH/CL
RFCONT 31 10 VRB
DC

CENTER BIAS GCA DRV

PBRFC 32 9 VCC3
MODE SWITCHING LOUTCLP

1 2 3 4 5 6 7 8
VSHP

DRVOUT
CH/CL

GND3
CAM/VIDEO

PS

LOUTCLP
PB/REC

–2–
 CXA2006Q

Pin Description (VCC1, 2, 3 = 4.75V)

Pin
Symbol Pin voltage Equivalent circuit Description
No.

CAM Camera and video

1
/VIDEO signal selector.
25µA 25µA
68k
Chroma signal and
2 PB/REC composite video
1 127 signal selector.
VTH = 1.35V 2 1.35V
High-band chroma
3
3 CH/CL signal and low-band
4 chroma signal selector.
10k 24k 27k

4 PS Power save mode.

16.25k
Sampling

VTH = 1.32V 127 Sample-and-hold

5 VSHP 5 1.32V pulse input for video.

10k 2mA 6.25k

400µA
Sampling

6 GND3
23 GND23 GND Ground.
30 GND2

100µA 200µA
Capacitor connection
for LOUTCLP which
66k 1.1k clamps the output
minimum level in
7 LOUTCLP Approx. 2V modes which pass
7 the composite video
16k 127 signal.
4µA 1.27V
(Recommended
24k 100k
value: 0.1µF)

–3–
 CXA2006Q

Pin
Symbol Pin voltage Equivalent circuit Description
No.

100µA 4mA

Driver output for A/D

• Camera mode 8
converter capable of
(CAM) DRVOUT
127 DC coupling.
VRB – 200mV
< black level 1.5mA 50
Dynamic range
< VRB + 300mV
= 2Vp-p
• Composite 1.5mA
8 DRVOUT video mode 30k
(LIN) SW1 SW2 Mode
VRB + 100mV 0 0 CH, CL
2.1V
• Chroma mode
(CH, CL) SW1 SW2 0 1 CAM
Center voltage = 1 0 LIN
10p
(VRT – VRB)/2
1 1 —
0: Closed
1: Open
OFFSET

9 VCC3
20 VCC1 VCC Power supply.
27 VCC2

2V regulator output.

Be sure to decouple
13.75k
10 this pin near the IC
pins to prevent the
10 VRB 2.0V
2V oscillation and external
2k noise when this pin is
10k not used.
100µA
(Recommended
capacitor value: 4.7µF)

4V regulator output.
3.75k 1.1k
4V 11 Be sure to decouple
3k this pin near the IC
pins to prevent the
11 VRT 4.0V
oscillation and external
20k noise when this pin is
not used.
(Recommended
100µA 100µA 100µA
capacitor value: 4.7µF)

–4–
 CXA2006Q

Pin
Symbol Pin voltage Equivalent circuit Description
No.

Controls the output

offset during camera
66k 100µA 100µA mode.
127
23k 12 When 0V:
12 OFFSET 0 to 3V
less than
(VRB – 200mV)
24k 1.1k 10k When 3.0V:
greater than
(VRB + 300mV)

Camera signal pre-

25µA 25µA blanking pulse input.

VTH = 1.35V 68k

Active when Low only
during camera mode.
Calibrates the black
13 PBLK
127 level of the AGC
13 1.35V output waveform.
When PBLK is Low,
24k 27k
Active: Low the DRVOUT
10k
potential is forced to
2V.

12.25k 200
VTH = 2.16V

2.16V
Camera signal
127
14 XRS sample-and-hold
14
pulse input.
5p
100µA 2.5mA
10.25k 10k
200
Sampling

VTH = 1.45V 1.1k 66k Clamp pulse used to

clamp the optical
15 1.45V black portion of the
15 CLPOB
127 camera signal after it
passes through the
100µA 29k
10k AGC amplifier.
Active: Low

–5–
 CXA2006Q

Pin
Symbol Pin voltage Equivalent circuit Description
No.

1.1k 2k

16 AGC clamp capacitor.

16 AGCCLP Approx. 3V (Recommended
127
value: 0.1µF)
50µA
2k

20µA
AGC gain control.

4k 20k 38k When 0V: 8dB

18 AGCCONT 0 to 3.0V 127 (Minimum gain)
18 When 3.0V: 38dB
10k
(Maximum gain)

40µA 40µA 20µA 20µA 20µA 20µA

200
DIN input
Enables monitoring
CCD signal
19 CCDLEVEL 19 of the SHD output
black level:
camera signal.
approx. 2.7V
40µA

25k 200 Preset level sample-

21 SHP
2.38V
and-hold pulse input.
VTH = 2.38V 127
21
22
25k 40µA 670µA
10k
200 Data level sample-
22 SHD Sampling and-hold pulse input.

–6–
 CXA2006Q

Pin
Symbol Pin voltage Equivalent circuit Description
No.

1.1k 1.1k 66k

VTH = 1.45V Clamp pulse used to

127
24 1.45V clamp the dummy
24 CLPDM
pixel portion of the
29k input CCD signal.
85µA 85µA
Active: Low

14k 2k
90µA
25 PIN Black level: 127
25 CCD signal input.
26 DIN approx. 2.7V 200
26 36k
0.9µA
2k

1k 10k

127
29

Clamp 2.1V
LIN mode
potential
during LIN Common input for
mode: 200µA 100µA 2µA the composite video
29 LIN/CH approx. 2.4V signal (LIN) and
10k high-band chroma
During CH 100µA
signal (CH).
19k
mode:
approx. 2.7V
2.7V

26k CH mode

–7–
 CXA2006Q

Pin
Symbol Pin voltage Equivalent circuit Description
No.

50µA
50µA 41k Gain control for the
low-band chroma
signal (CL).
31 RFCONT 0 to 3.0V 42k When 0V: 3.5dB
127 (Minimum gain)
31 50µA 50µA 0.86V When 3.0V: 15.5dB
9k (Maximum gain)
10k 1k

127
32
7.3k

10k

100µA 100µA
Low-band chroma
32 PBRFC Approx. 2.94V
signal (CL) input.
10k
46k 18k

41k

–8–
 CXA2006Q

Electrical Characteristics (Ta = 25°C, VCC1, 2 and 3 = 4.5V, VCC4 = OPEN)

Item Symbol Conditions Min. Typ. Max. Unit
AGCCONT = 0V, open between VRT and VRB
Camera
IDC CAM/VIDEO = 3V, PB/REC = 0V, 31 46 60
mode
CH/CL = 0V, PS = 3V
Open between VRT and VRB
LINE mode IDL CAM/VIDEO = 0V, PB/REC = 0V, 19 27 36
CH/CL = 0V, PS = 3V
Current
consump- Open between VRT and VRB mA
tion CH mode IDCH CAM/VIDEO = 0V, PB/REC = 3V, 17 26 35
CH/CL = 3V, PS = 3V
RFCONT = 0V, open between VRT and VRB
CL mode IPCL CAM/VIDEO = 0V, PB/REC = 3V, 16 24 33
CH/CL = 0V, PS = 3V
PS mode IDP PS = 0V 6 10 13
Maximum A CONT DIN = 1µs, 10mVp-p pulse
36 38 40
gain max. AGCCONT = 3V
Minimum A CONT DIN = 1µs, 600mVp-p pulse
— 8 10 dB
gain min. AGCCONT = 0V
Range of
AGC G A CON max. – A CON min. 28 30 32
gain variance
AGC
Dynamic
AGCmax. AGCCONT = 3V
range 1.9 2.1 2.5
D CLPOUT output signal at saturation level
maximum
V
Dynamic
AGCmin. AGCCONT = 0V
range 1.9 2.1 2.5
D CLPOUT output signal at saturation level
minimum
CAOF VCC1, 2, 3 = 4.75V, OFFSET = 3V
Offset high 560 660 —
high camera mode
DRV mV
CAOF VCC1, 2, 3 = 4.75V, OFFSET = 0V
Offset low — –270 –200
low camera mode
VRT
VRTO VCC1, 2, 3 = 4.75V with a 400Ω load 3.97 4 4.03
DC level
REF VRB V
VRBO VCC1, 2, 3 = 4.75V with a 400Ω load 1.9 2 2.1
DC level
VRT – VRB ∆VR VCC1, 2, 3 = 4.75V with a 400Ω load 1.9 2 2.1
BLK Offset BLKOF BLKOF (PBLK = 3V) – BLKOF (PBLK = 0V) –5 8.5 15 mV
LIN mode LIN/CH = 3MHz, 500mVp-p,
LIN G 8.5 9.5 10.5
gain sine wave + offset voltage
AMP
CH mode
CH G LIN/CH = 3MHz, 500mVp-p, sine wave 8.1 9.1 10.1
gain
CL mode dB
RF RFCONT = 3V
maximum 16 20.5 —
CONmax. 15kHz 80mVp-p sine wave
gain
GCA
CL mode
RF RFCONT = 0V
minimum — 0.4 2
CONmin. 15kHz 400mVp-p sine wave
gain
–9–
 CXA2006Q

Electrical Characteristics Measurement Circuit

GND GND GND GND GND GND

PL1 PL2 PL3 VCC1 V12

4.75V 0 to 3V

CCDLEVEL

AGCCONT
CLPDM

GND1

VCC1
SHD

N.C.
SHP
24 23 22 21 20 19 18 17

C4 C7
GND

1µF PIN AGCCLP 0.1µ

GND
25 16
AC C3
V5 AGCCLP PL4
GND

1µF DIN CLPOB

GND
26 SH1 SH2 15
AGC LPF CAMSH BLK
VCC2
SH3 PL5
GND

4.75V VCC2 XRS

GND
27 14
COSCLP1
N.C. PBLK PL6

GND
28 COSCLP2 REF REF 13
OFF SW5 BOTTOM TOP
AC ON V15
V3 LIN/
GND

OFFSET 0 to 3V

GND
CH
29 12
V1 C1 LIN/CH SW C9
0 to 4.75V 0.1µF GND2 LIN CLP VI SW C/V SW OFFSET 4.7 µ
GND

SW VRT

GND
30 AMP 11
VISH R3 OFF
V2 CENTER BIAS 400 ON
0 to 3V SW6
GND

RFCONT VRB

GND
CH/CL
31 DC 10
VCC3 C8
AC CENTER BIAS GCA DRV 4.7µ
V4 4.75V
GND

PBRFC VCC3

GND
32 9
C2 MODE SWITCHING LOUTCLP
0.047µF

1 2 3 4 5 6 7 8
REC

LOUTCLP
GND3

DRVOUT
PS

VSHP
CH/CL
VIDEO

PB/
CAM/

R2
22
SW4
SW1 SW2 SW3
L HL HL HL H C5 R1
V7 V8 V9 V10 PL7 0.1µ 20k C6
3V 3V 3V 3V V13 25p
3V

GND GND GND GND GND GND GND GND GND

SW1 SW2 SW3 SW5 SW4 MODE

L L H
OFF CAM
H L L
H L H
ON LIN
L L L H
H H L
CL
L H L OFF
L H H CH
L POWER SAVE

– 10 –
 CXA2006Q

Measurement Timing Chart

1H
2µs

1.5V
PL4 (CLPOB)

1H GND
2µs

1.5V
PL1 (CLPDM)
GND

1.5V
PL6 (PBLK)
GND
1H

V5 (DIN) Different for each test

Equivalent to CCD
signal black level

V3 (CH)
V4 (PBRFC)
V1 + V3 (LIN)
Different for each test

PL2 (SHD) 2.5V

PL3 (SHP)
PL5 (XRS)
PL7 (VSHP) GND

– 11 –
 CXA2006Q

Application Circuit

GND GND GND GND GND

CLPDM SHD SHP V12

VCC 0 to 3V

CCDLEVEL

AGCCONT
CLPDM

GND1

VCC1
SHD

N.C.
SHP
24 23 22 21 20 19 18 17

1µF C7
PIN AGCCLP 0.1µ

GND
25 16

CLPOB
CCD 1µF
DIN AGCCLP CLPOB

GND
26 SH1 SH2 15
AGC LPF CAMSH BLK

XRS
VCC2 SH3 XRS

GND
VCC 27 14

PBLK
COSCLP1
N.C. PBLK

GND
28 COSCLP2 REF REF 13
BOTTOM TOP
LIN/CH OFFSET 0 to 3V

GND
LIN/CH 29 12
0.1µF LIN/CH SW
LIN CLP VI SW C/V SW OFFSET 4.7µF
GND

GND2 SW VRT

GND
30 AMP 11
VISH
CENTER BIAS
0 to 3V
GND

RFCONT VRB

GND
CH/CL
31 DC 10
DRV 4.7µF
CENTER BIAS GCA
PBRFC VCC3
PBRFC 32 9 VCC
0.047µF MODE SWITCHING LOUTCLP

1 2 3 4 5 6 7 8
VIDEO

VSHP
PS
REC

LOUTCLP
CH/CL

GND3

DRVOUT

VRB VRT
PB/
CAM/

22
A/D
0.1µ A/D IN
VSHP
3V 3V 3V 3V

GND GND GND GND GND GND GND

Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.

– 12 –
 CXA2006Q

Description of Operation

1. Camera signal processing system

Process the video signal processing pins as follows only in camera mode.
<5> VSHP ... Connect to GND.
<7> LOUTCLP ... Connect to GND.
<29> LIN/CH ... Connect to GND.
<31> RFCONT ... Connect to GND.
<32> PBRFC ... Connect to GND via the capacitor (approx. 0.01µF).

Operating conditions
The camera signal processing system operates when PS is high, CAM/VIDEO is low, PB/REC is low and
CH/CL is high, or when PS is high, CAM/VIDEO is high, PB/REC is low and CH/CL is low.

Camera signal processing system timing chart (when VCC = 4.75V)

Sig interval OPB interval Idle transfer Sig interval

interval
Precharge level

CCD output

Signal level
SHP
SHD

SH1 output
2.7V
SH2 output [∗1]
[∗2]
SH3 output
2.7V
CLPDM
(2µ dummy bit
portion during the 2µs
idle transfer interval)
AGC output Basic black level Black level
SH3 output 2.16V
–N times –SH2 output
[∗3]
XRS
CLPOB
(2µ during the
OPB interval) 2µs

CAMSH output
2.16V
PBLK
(10µ during the idle
transfer interval)
10µs

BLK output
CAMVISW output
2.16V [∗4]

DRVOUT output

[∗5]
Approx. 2.65V when OFFSET = 3V

Approx. 1.73V when OFFSET = 0V

– 13 –
 CXA2006Q

CDS:
The CCD signal from the CCD image sensor is input to PIN and DIN where correlated double sampling (CDS)
is performed by SH1, SH2 and SH3. The precharge level of the CCD output signal is sampled, held and output
by the SH2 output, and the signal level is sampled, held and output by the SH3 output.

CDSCLP:
The CDSCLP stabilizes the input signal DC level, clamps (CLPDM) the input signal during the idle transfer
interval for the purpose of eliminating the AGC input offset, and synchronizes the DC level ([∗1], [∗2]) of SH2
and SH3.

AGC:
The gain can be varied from 8 to 38dB by adjusting the AGCCONT voltage control VAGCCONT from 0 to 3V.

LPF:
A primary low-pass filter is installed for the purpose of eliminating unused bands and white noise and
improving S/N.

CAMSH:
The CAMSH is used for camera signal processing system. It is a sample-and-hold circuit which synchronizes
the data read-in timing for the external A/D.

AGCCLP:
The basic black level is set ([∗3]) by clamping the AGC output waveform with the CLPOB clock during the OPB
interval. The AGCCLP capacitance is connected to the AGCCLP pin.

BLK:
The black level is calibrated by blanking the black level signal of the AGC output waveform so that it does not
fall below the basic black level and replacing the DC potential. ([∗4])
The signal is blanked when PBLK is low.

C/VSW:
When the CAM/VIDEO, PB/REC, CH/CL and PS pin voltages are set so that the camera signal processing
system operates, C/VSW conducts the BLK output (camera signal) into the DRV. In addition, when these
voltages are set so that the video signal processing system operates, C/VSW conducts the VISH output (video
signal) into the DRV.

OFFSET SW:
The OFFSET SW selects [OFFSET], [CH/CLDC] or [LOUTCLP] as the offset adjustment input pin of the DRV
block and activates these pins by selecting the CAM/VIDEO, PB/REC, CH/CL and PS pin voltages.
When the camera signal processing system is in camera mode, the OFFSET pin is conducted [OFFSET],
allowing the camera signal offset to be adjusted. ([∗5])
When the video signal processing system is in LIN mode, the LOUTCLP pin is conducted [LOUTCLP],
clamping the video composite signal at its sync level and offsetting the signal. In addition, CH/CL mode
conducts the CH/CL DC [CH/CLDC], which gives center potential to the high-band chroma and low-band
chroma signals of the video signal.

DRV:
DRV drives the external A/D. Camera and video (LIN, CH, CL modes) signals are input by switching C/VSW,
and offset adjusted signals are output from DRVOUT pin.
– 14 –
 CXA2006Q

REFBOTTOM, REFTOP:
REFBOTTOM and REFTOP are reference voltage source for the external A/D. They are connected to VRT and
VRB of the A/D, and 2V and 4V are supplied.

MODE SWITCHING:
MODE SWITCHING is a mode selection block which selects camera signal system or video signal system
operation by selecting high or low potentials for the CAM/VIDEO, PB/REC, CH/CL and PS pins. PS is the
power save pin, and power save functions when this pin is low.

2. Video signal processing system

Operating conditions
The video signal processing system has three modes: LIN signal mode, CH signal mode and CL signal mode.
The video signal processing system operates in LIN signal mode when PS is high, CAM/VIDEO is high,
PB/REC is low and CH/CL is high, or when PS is high, CAM/VIDEO is low, PB/REC is low and CH/CL is low.
The video signal processing system operates in CH signal mode when PS is high, CAM/VIDEO is low,
PB/REC is high and CH/CL is high.
The video signal processing system operates in CL signal mode when PS is high, CAM/VIDEO is low, PB/REC
is high and CH/CL is low, or when PS is high, CAM/VIDEO is low, PB/REC is high and CH/CL is high.

Video signal processing system timing chart

LIN mode

LIN/CH input

2.4V

AMP output
9.5dB

2.1V

VISP

DRVOUT output

2.1V

– 15 –
 CXA2006Q

LIN signal mode

LINCLP:
The video composite signal is input to LIN/CH pin. LINCLP expands the input dynamic range, and sync tip
clamps the input signal at 2.4V to allow full input. The input level and frequency are respectively 571mVp-p
(Max.) and DC is up to 7MHz.

LINAMP:
This is a fixed gain amplifier with a gain of 9.5dB.

LIN/CHSW:
LIN/CHSW switches between the LIN signal and CH (high-band chroma) signal. The signals are switched
according to the mode selection.

VISH:
The VISH is used for video signal processing system.
It is a sample-and-hold circuit which synchronizes the data read-in timing for the external A/D.

VISW:
VISW switches between the LIN, CH and CL low-band chroma signals for the video signal processing system.
The signals are switched according to the mode selection.

LOUTCLP:
LOUTCLP is a clamp circuit which operates when the LIN signal is output to the DRV. The clamp potential is
the sync portion, and is 2.1V.

– 16 –
 CXA2006Q

CH (high-band chroma) signal mode

CENTER BIAS:
The video high-band chroma signal is input to LIN/CH pin. CENTER BIAS expands the input dynamic range
and sets a center DC bias so that the center potential of the SIN signal is 2.7V to allow full input. The input
level and frequency are respectively 470mVp-p (Max.) and from 1 to 7MHz.

CH/CL DC:
CH/CL DC is a DC bias circuit which operates when the CH signal is output to the DRV. The DC bias potential
is 3V.

CH mode

LIN/CH input 2.7V

AMPOUT output 3V
9.1dB

VISH

DRVOUT output 3V

– 17 –
 CXA2006Q

CL (low-band chroma) signal mode

CENTER BIAS:
The video low-band chroma signal is input to PBRFC pin. CENTER BIAS expands the input dynamic range
and sets a center DC bias so that the center potential of the SIN signal is 2.94V to allow full input. The input
level and frequency are respectively 1490mVp-p (Max.) and DC is up to 1.5MHz.

GCA:
The GCA amplifier controls the gain of the CL signal input to PBRFC. The gain can be varied from 0.4 to
20.5dB by adjusting the RFCONT voltage from 0 to 3V.

CH/CL DC:
CH/CL DC is a DC bias circuit which operates when the CL signal is output to the DRV. The DC bias potential
is 3V.

CL mode

PBREC input 2.94V

GCAOUT output 3V
0.4 to 20.5dB

VISH

DRVOUT output 3V

– 18 –
 CXA2006Q

Example of Representative Characteristics

CAM mode AGCCONT control supply voltage characteristics
VAGCCONT vs. Gain
40

VCC = 4.5V
30

Gain [dB]

20 VCC = 5.0V

10

0
0.0 1.0 2.0 3.0
VAGCCONT [V]

CAM mode OFFSET control supply voltage characteristics

VOFFSET vs. OFFSET
VCC = 4.5V
700
VCC = 4.75V
600 VCC = 5.0V

500

400
OFFSET [mV]

300

200

100

–100

–200

–300
0.0 1.0 2.0 3.0
VOFFSET [V]

CL mode RFGCA gain control supply voltage characteristics

VRFCONT vs. Gain
26

20
Gain [dB]

VCC = 4.5V
10

VCC = 5.0V

0
0.0 1.0 2.0 3.0
VRFCONT [V]
– 19 –
 CXA2006Q

CAM mode AGCCONT control temperature characteristics (VCC = 4.75V)

AGCCONT vs. Gain
40 –20°C
27°C
75°C

30

Gain [dB]
20

10
VCC = 4.75V

0
0.0 1.0 2.0 3.0
AGCCONT [V]
CAM mode OFFSET control temperature characteristics
VOFFSET vs. OFFSET
75°C
700
27°C
600 –20°C

500

400
OFFSET [mV]

300

200

100

–100
VCC = 4.75V
–200
–300
0.0 1.0 2.0 3.0
VOFFSET [V]
CL mode RFGCA gain control temperature characteristics
VRFCONT vs. Gain
22 –20°C
20 27°C
75°C
Gain [dB]

10

VCC = 4.75V
0
–1
0.0 1.0 2.0 3.0
VRFCONT [V]

– 20 –
 CXA2006Q

CAM mode maximum signal amplitude CH mode AMP gain temperature characteristics
temperature characteristics
Ta vs. VOUT (camera mode) Ta vs. Gain (CH mode)
11
2.50

2.40
minGain (in = 0.4Vp-p)
2.30

2.20 10
VOUT [Vp-p]

Gain [dB]
2.10

2.00

1.90
9
1.80

1.70
VCC = 4.75V VCC = 4.75V
1.60
1.50 8
–20 0 20 40 60 –20 0 20 40 60
Ta [°C] Ta [°C]

CL mode maximum signal amplitude LIN mode AMP gain temperature characteristics
temperature characteristics
Ta vs. VOUT (CL mode) Ta vs. Gain (CL mode)
11
3.50

3.40
3.30

3.20 10
VOUT [Vp-p]

Gain [dB]

3.10
maxGain
3.00

2.90
9
2.80

2.70
VCC = 4.75V VCC = 4.75V
2.60
2.50 8
–20 0 20 40 60 –20 0 20 40 60
Ta [°C] Ta [°C]

– 21 –
 CXA2006Q

VRT, VRB and output DC (CAM, LIN, CH and CL modes) CH mode 2nd/3rd harmonic distortion
temperature characteristics temperature characteristics
Ta vs. VRT, VRB, DCOUT Ta vs. 2nd /3rd harmonic distortion
–30
4.00 –35
3.80 VRT 2nd: OUT = 1.8Vp-p

2nd/3rd Harmonic Distortion [dB]

–40
3.60
VRT, VRB, DCOUT [V]

–45
3.40 2nd: OUT = 1.4Vp-p
CLOutDC
3.20 –50

3.00 –55
3rd: OUT = 1.8Vp-p
2.80 CHOutDC –60 3rd: OUT = 1.4Vp-p
2.60
VCC = 4.75V –65
2.40
LinOutDC CamOutDC (cont = 1.0V) –70
2.20 f = 5MHz
–75 VCC = 4.5V
2.00
VRB
1.80 –80
–20 0 20 40 60 –20 0 20 40 60
Ta [°C] Ta [°C]

CL mode 2nd/3rd harmonic distortion LIN mode 2nd/3rd harmonic distortion

temperature characteristics temperature characteristics
Ta vs. 2nd/3rd harmonic distortion Ta vs. 2nd/3rd harmonic distortion
–30 –30

–35 –35
3rd: OUT = 1.8Vp-p
2nd/3rd Harmonic Distortion [dB]

2nd/3rd Harmonic Distortion [dB]

2nd: IN = 800mVp-p,
–40 OUT = 1.8Vp-p –40 2nd: OUT = 1.8Vp-p
–45 –45
2nd: IN = 100mVp-p,
–50 OUT = 0.6Vp-p –50

–55 –55
2nd: OUT = 1.4Vp-p
–60 –60 3rd: OUT = 1.4Vp-p
3rd: IN = 800mVp-p,
–65 OUT = 1.8Vp-p –65

–70 –70
f = 700kHz f = 5MHz
3rd: IN = 100mVp-p, VCC = 4.5V VCC = 4.5V
–75 OUT = 0.6Vp-p –75

–80 –80
–20 0 20 40 60 –20 0 20 40 60
Ta [°C] Ta [°C]

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 CXA2006Q

Package Outline Unit: mm

32PIN QFP (PLASTIC)

9.0 ± 0.2
0.1
+ 0.3 + 0.35
7.0 – 0.1 1.5 – 0.15

24 17

25 16

(8.0)
32 9 + 0.2
0.1 – 0.1

1 8

0.50
+ 0.15 + 0.1
0.8 0.3 – 0.1 0.127 – 0.05
0.24 M
0° to 10°

PACKAGE MATERIAL EPOXY RESIN

SONY CODE QFP-32P-L01 LEAD TREATMENT SOLDER PLATING

EIAJ CODE QFP032-P-0707 LEAD MATERIAL 42 ALLOY

JEDEC CODE PACKAGE MASS 0.2g

– 23 –