Combinational Circuits

Lecturer: Mu-Hua Yuan

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 Outline
✓ Section 1 Introduction to design flow
✓ Section 2 Basic Description of Verilog
✓ Section 3 Behavior Models of Combinational circuit
✓ Section 4 Simulations

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SECTION 1
INTRODUCTION TO DESIGN FLOW

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 How Does Hardware Accelerate System

✓ Profiling
– Profiling is a form of dynamic program analysis that measures the
space/time complexity of a program to aid program optimization.
– by doing profiling we can find the most time-consuming part of the
system
– designers can implement this part in hardware instead of software

✓ Application Specific IC (ASIC)

– Specially designed IC are much faster than general purpose CPU.
– we can design dedicated datapath and controller for the time-
consuming part which requires less time

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 Example
✓ An algorithm contains steps:
– (1)  (2)  (3)  (4)

✓ Mathematical Analysis: ✓ Profiling

– (1) : O(C) – Running 1000 times takes 100sec
– (2) : O(n) – (1) : 5s
– (3) : O(n2) – (2) : 10s
– (4) : O(n) – (3) : 70s
– (4) : 15s
Make ASIC for (3), easily accelerated by 100x
✓ Profiling with ASIC : Running 1000 times
– (1) : 5s
– (2) : 10s
– (3) : 0.7s + 0.3s (communication time) takes 31s
– (4) : 15s

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 Introduction to Design Flow
✓ Cell-based RAM ALU ROM Description of circuits in large
Design Flow Architectural blocks and estimates of chip area
Level PLA IO (Behavior; Area estimate)

Partitioning of blocks into smaller

Register Transfer
functional modules
Level (Functions;)

✓ Full-Custom Description of blocs as logic gate

Logic Level and sequential elements
Design Flow (Bits; Timing)

Description of elements as a
transistor and parasitic elements
Circuit Level (Voltages; Currents)

Description of elements as a
transistor and parasitic elements
Physical Level (Voltages; Currents)

Device Level Device modeling and electrical char. of transistors (I/V

Char.)
Technology Level

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 Cell-based ASIC
✓ Cell-based IC (CBIC)
– use pre-designed logic cells (known as standard cells) and micro
cells (e.g. microcontroller)
– designers save time, money, and reduce risk
– each standard cell can be optimized individually
– all mask layers are customized
– custom blocks can be embedded

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 Cell-based Design Flow
Specification Development
System Architecture
System models

RTL code development

Functional Verification RTL

Synthesis
Synthesis
Timing Verificaiton

Physical Synthesis/Place and Route

Physical Design
Physical Verification

Prototype System Integration and

Build and Test Software Test

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 Cell-based Design Tools
✓ System and behavioral ✓ Synthesis and Verification
description (math. or – Synopsys
building module )
– RTL Compiler, Design Compiler
– C/C++
– PrimeTime, SI and StarRC™.
– Matlab
– … – Cadence
– BuildGates Extreme
✓ Hardware based – Verplex (Formal Verification)
description language – …
– System C
– SystemVerilog ✓ Physical Design and post-
– Verilog layout simulation
– … – SoC Encounter
✓ RTL simulation and – IC compiler
debug – Calibre
– NC-Verilog – Nanosim, HSIM, UltraSim: a high-
– nLint, Verdi performance transistor-level FastSPICE
–ICLAB
… NCTU Institute of Electronics circuit simulator …
9
 Full-Custom Design
✓ An engineer designs some or all of the logic cells,
circuits, layout specifically for one ASIC
– required cells/IPs are not available
– existing cell libraries are not fast enough
– logic cells are not small enough or consume too much power
– technology migration (mixed-mode design)
– demand long design cycle

✓ Not our focus

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SECTION 2
BASIC DESCRIPTION OF VERILOG

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 Basic Description of Verilog
✓ Design Scope of Verilog
✓ Lexical convention
✓ Data type & Port
✓ Gate level modeling
✓ Data assignment
✓ Simulation Environment

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 Design Scope of Verilog
✓ We use Verilog HDL to design
– Typical design flow

Design Specification

Algorithmic Model
Behavior
language
RTL Model
Verilog HDL
Gate-Level Model
Structural
language
Switch-Level Model

Physical Layout

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 What is Verilog?
✓ Hardware Description Language

✓Hardware Description Language

✓Hardware Description Language

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 Hardware Description Language
✓ Hardware Description Language
– HDL is a kind of language that can “describe” the hardware module
we plan to design
– Verilog and VHDL are both widely using in the IC company
– The difference between HDL and other programming
language is that we must put the “hardware circuit” in our
brain during designing the modules

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 A Module
✓ Encapsulate structural and functional details

module module_name(port_list); module test ( Q,S,clk );

output reg Q;
input S,clk;
port declaration
always@(S or clk)
data type declaration Q<=(S&clk) ;
endmodule
task & function declaration
module functionality or structure

endmodule

✓ All modules run concurrently

✓ Encapsulation makes the model available for instantiation in other
modules
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 Identifier and Comment
✓ Verilog is a case sensitive language
✓ Terminate lines with semicolon ;
✓ Identifiers
– starts only with a letter or an _(underline), can be any
sequence of letters, digits, $, _ .
– case-sensitive !
• e.g. shiftreg_a
_bus3
n$657
12_reg  illegal !!!!

✓ Comments
– single line : //
– multiple line : /* … */

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 Naming Conventions
✓ Consistent naming convention for the design
✓ Lowercase letters for signal names
✓ Uppercase letters for constants
✓ clk sub-string for clocks
✓ rst sub-string for resets
✓ Suffix
– _n for active-low, _z for tri-state, _a for async , …

✓ [name]_cs for current state, [name]_ns for next state

– or [name]_r and [name]_w

✓ Identical(similar) names for connected signals and ports

✓ Consistency within group, division and corporation

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 Port

✓ Interface is defined by ports

wire
✓ Port declaration wire inout
– input : input port wire or reg wire wire or reg wire
– output : output port input output
– inout : bidirectional port Module
✓ Port connection
– input : only wire can be assigned to represent this port in the module
– output : only wire can be assigned to represent this port out of module
– inout : register assignment is forbidden neither in module nor out of
module [Tri-state]

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 Port : Module Connection
✓ Port ordering
– one port per line with appropriate comments
– inputs first then outputs
– clocks, resets, enables, other controls, address bus, then data bus

✓ Modules connected by port order (implicit)

– Here order shall match correctly. Normally, it not a good idea to
connect ports implicitly. It could cause problem in debugging when
any new port is added or deleted.
– e.g. : FA U01( A, B, CIN, SUM, COUT );

✓ Modules connect by name (explicit) Use this!!!

– Use named mapping instead of positional mapping
– name shall match correctly.
– e.g. : FA U01( .a(A), .b(B), .cin(CIN), .sum(SUM), .cout(COUT) );
foo u_foo1(4’h2, 4’h5, 4’h8); X

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 Port : Examples

module MUX2_1(out,a,b,sel,clk,reset);
input sel,clk,reset; `include “mux.v”
input a,b; module test;
output out; reg out; //incorrect define
wire c; reg a,b;
reg a,b; //incorrect define reg clk,sel,reset;
reg out;
// 1. connect port by ordering
//Continuous assignment MUX2_1 mux(out,a,b,sel,clk,reset);
assign c = (sel==1’b0)?a:b;
// 2. connect port by name
//Procedural assignment, MUX2_1 mux(.clk(clk), .reset(reset),
//only reg data type can be assigned value .sel(sel), .a(a), .b(b), .out(out));
always@(posedge reset or posedge clk)
begin initial begin
if(reset==1’b1) out <= 0; ………
else out <= c; end
end endmodule
endmodule 【 sub module】 【test module】

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 Gate-Level Modeling

✓ Primitive logic gate

– and/or gates
• nand
• and
• nor
• or
• xnor
• xor

-- can use without instance name i.e. and( out, in1, in2 ) ;
-- can use with multiple inputs i.e. xor( out, in1, in2, in3 ) ;

in1
in1
out in2 out
in2 in3

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 Gate-Level Modeling (cont.)

✓ Gate Delays
– Rise, Fall, and Turn-off Delays Why do we need these?
• Rise Delays
• Fall Delays
• Turn-off Delays enable

input
enable
1
output HiZ
in out 0
tpLH tpHL tpZ
notif1 ( out, in, enable ) ;

gate #( each_delay ) a1( out, i1, i2 );

gate #( rise_delay, fall_delay ) a2( out, i1, i2 ) ;
gate #( rise_delay, fall_delay, turnoff_delay ) a3( out, in, enable ) ;
• Only bufif0, bufif1, notif0, notif1 have turn-off delays
i.e. and #(3,4) ( out, i1, i2 ); //rise=3,fall=4
i.e. bufif1 #(3,4,5) ( out, in, enable ); //rise=3,fall=4,turnoff=5

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 Gate-Level Modeling (cont.)
✓ Gate Delays
– Min/Typ/Max delay time Why do we need these?
• Min/Typ/Max : expectation minimum/typical/maximum delay
gate #( mindelay:typdelay:maxdelay ) b( out, i1, i2 );
i.e. nand #(1:2:3) ( out , in1 , in2 );

– Combine min/typ/max and rise/fall/turn-off delays

i.e. notif1 #(3:4:5,6:7:8,1:2:3) ( out, in, enable );
/*minimum rise=3,fall=6,turn-off=1,typical rise=4,fall=7,turn-off=2,
maximum rise=5,fall=8,turn-off=3*/

• Use the +maxdelays(typdelays/mindelays) to select

maximum(typical/minimum) delays for simulation

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 Gate-Level Modeling (cont.)

module MUX2_1(out,a,b,sel) ;
//declare ports
input a, b, sel ;
output out ; w0
//declare inside wire a
wire seln ;
wire w0, w1 ; out
//gate instances sel seln
not #(0.2:0.3:0.5, 0.2:0.3:0.5) n0( seln, sel ) ;

and #(0.4:0.6:0.9, 0.4:0.6:0.9) a0( w0, a, seln ); w1

and #(0.4:0.6:0.9, 0.4:0.6:0.9) a1( w1, b, sel ); b
or #(0.4:0.6:0.9, 0.4:0.6:0.9) o0( out, w0, w1 ) ;

endmodule

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 Number
✓ Number Specification
– <size>’<base><value>
• <size> is the length of desired value in bits.
• <base> can be b(binary), o(octal), d(decimal) or h(hexadecimal).
• <value> is any legal number in the selected base.
[When <size> is smaller than <value>: left-most bits of <value>are truncated
When <size> is larger than <value>, then left-most bits are filled based on
the value of the left-most bit in <value>.]
 Left most '0' or '1' are filled with '0', 'Z' are filled with 'Z' and 'X‘ with 'X'
• Default size is 32-bits decimal number
• e.g. 4’d10  4-bit, 10, decimal
• e.g. 6’hca  6-bit, store as 6’b001010 (truncated, not 11001010!)
• e.g. 6’ha  6-bit, store as 6’b001010 (filled with 2-bit ‘0’ on left!)
• Extension:
• 12’hz  zzzz zzzz zzzz;6’bx xx xxxx;8’b0 0000 0000;8’b1 0000 0001
– Negative : -<size>’<base><value>
• e.g. –8’d3  legal 8’d–3  illegal
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 Operator
✓ Operators
– Arithmetic Description
• A = B + C;
• A = B – C;
• A = B * C;
• A = B / C;
• A = B % C; modulus  some synthesis tools don’t support this operator
– Shift Operator (bit-wise)
• A = B >> 2;  shift right ‘B’ by 2-bit
• A = B << 2;  shift left ‘B’ by 2-bit

– Shift Operator (arithmetic)

• A = B >>> 2; “>>>”, ”<<<“ are used only for ‘signed’ data type in Verilog 2001
• A = B <<< 2;
• e.g. B = 4’b1000; (A = 4’b1110 ,which is 1000 shifted to the right two
A = B >>>2; positions and sign-filled.)

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 Operator
✓ Bit-wise Operator ✓ Conditional Description
– NOT: A = ~ B; – if else
– AND: A = B & C;
– case endcase
– OR: A = B | C;
– ? :  c = sel ? a : b;
– XOR: A = B ^ C; // if (sel==1’b1)
– e.g. 4’b1001 | 4’b1100  4’b1101 // c = a;
// else
✓ Logical Operators: return 1- // c = b;

bit true/false ✓ Relational and

– NOT: A = ! B; equality(conditional)
– AND: A = B && C; – <=, <, >, >=, ==, !=
– OR: A = B || C; – i.e. if( (a<=b) && (c==d) ||
– e.g. 4’b1001 || 4’b1100  true, (e>f))
1’b1

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 If-then-else vs. case
✓ If-then-else often infers a cascaded encoder
– inputs signals with different arrival time

✓ case infers a single-level mux

– case is better if priority encoding is not required
– case is generally simulated faster than if-then-else

✓ conditional assignment (? :)
– infers a mux with slower simulation performance
– better avoided

d 0 a 00

c 1 b 01
0

b 0 c 10
1 out
sel Sel=10
1 d 11
a
Sel=01
2
Sel=00 Sel

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 Concatenation
– Concatenation b[3]
a[7]

…
b[0]

……
• {}  a = {b, c}; c[3]

…
a[0]
c[0]

a[7]

……
C[3]
• {{}}  a = {2{c}};

…
a[0]
C[0]

• a[4:0] = {b[3:0],1’b0};  a = b << 1;

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 Data Type
✓ 4-value logic system in Verilog: 0, 1, x or X, z or Z
✓ Declaration Syntax<data_type>[<MSB> : <LSB>]<list_of_identifier>
– Nets : represent physical connections between devices (default=z)
• represent connections between things (ex: wire)
• Cannot be assigned in an initial or always block
– Register : represent abstract data storage element (default=x)
• represent data storage (ex: reg)
• Hold their value until explicitly assigned in an initial or always block
• Can be used to model latches, flip-flops, etc., but do not correspond exactly
Register type Attribute
reg Unsigned value with Varying bit width
integer 32-bit signed (2’s complement)
time 64-bit unsigned
real Real number
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 Data Type : Vector and Array
– Vectors : the wire and register can be represented as a vector
• wire [7:0] vec;  8-bit bus
• reg [0:7] vec;  vec[0] is the MSB

– Arrays : <array_name>[<subscript>] For this reason, we do not use

array as memory,
It isn’t well for the backend verifications
Memory component will be
• integer mem[0:7] (8x32)-bit mem introduced later
• reg [7:0] mem[0:1023]  Memories!! (1k - 1byte)

– What’s difference between Vector and Array?

• Vector : single-element with multiple-bit
• Array : multiple-element with multiple-bit

Memory Vector
(Array) :
:

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 Data Type : Signed and Unsigned

✓ Signed & Un-signed

– Verilog-1995
• Signed : integer
• Unsigned : reg, time, and all net data type.

– Verilog-2001
• allows reg variables and all net data types to be declared
using the reserved keyword signed

module verilog2001(a, b, c);

a 1010 output signed [3:0] b;

output [3:0] c;
b 1110 input signed [3:0] a;

c 0010 assign b = a >>> 2; //arithmetic shift

assign c = a >> 2; //bit-wise shift

endmodule

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 Example

module Add_half(a, b, sum, c_out);

input a, b;
output sum, c_out;
wire c_out_bar;
xor (sum, a, b);
and (c_out, a, b);
endmodule

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 Example (cont.)

module Add_full(a, b, c_in, sum, c_out);

input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
Add_half M1(.a(a), .b(b), .sum(w1), .c_out(w2));
Add_half M2(.a(w1), .b(c_in), .sum(sum), .c_out(w3));
or (c_out, w2, w3);
endmodule

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 Data Assignment
✓ Continuous Assignment  for wire assignment
– Imply that whenever any change on the RHS of the assignment occurs, it
is evaluated and assigned to the LHS.
• e.g. wire [3:0] a;
assign a = b + c; //continuous assignment

✓ Procedural Assignment  for reg assignment

– assignment to “register” data types may occur within always,
initial, task and function. These expressions are controlled by
triggers which cause the assignment to evaluate.
• e.g. reg a,clk;
always #5 clk = ~clk; //procedural assignment
• e.g. always @ (b) //procedural assignment with triggers
a = ~b;

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 Data Assignment : Example

module MUX2_1(out,a,b,sel,clk,reset);
input sel,clk,reset;
input a,b;
output out;
wire c;
reg a,b; //incorrect define
reg out;

//Continuous assignment
assign c = (sel==1’b0)?a:b;

//Procedural assignment,
//only reg data type can be assigned valve
always@(posedge reset or posedge clk)
begin
if(reset==1’b1) out <= 0;
else out <= c;
end
endmodule

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 Data Assignment (cont.)
In the behavior-level modeling, Verilog code is just
like C language. In the behavior level, it uses two
essential statements.
✓ initial module example;
– An initial block starts at 0, .
and executes once in a simulation. .
initial clk=1’b0;
✓ always always #10 clk=~clk;
– An always block starts at 0,
and executes repeatedly as a loop. initial //multiple statements uses
begin //begin-end to be grouped
$display (“end”);
#1000 $finish ;
Don’t forget the corresponding hardware end
when writing design! endmodule

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SECTION 3
BEHAVIOR MODELS OF COMBINATIONAL CIRCUIT

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 Combinational Circuits
✓ The output of combinational circuit depends on the
present input only.
(This property contrast to the sequential circuit which
will be introduced in next chapter)
✓ Combinational circuit can be used to do mathematical
computation and circuit control.

Combinational circuit

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 Behavioral Modeling – Combinational Blocks
✓ Using always construct
– assignment should be applied in topological order

– always@*begin
– x = a & b;
– y = x | c | d;
– end

✓ Using continuous assignments

✓ assign y = x | c | d ;
– assign x = a & b ;
a
x
b
c
d y

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 Combinational Circuits – Continuous Assignment (cont.)
✓ LHS should be “wire” type

✓ Logic Assignments
– Ex: // b=5’b01110 c=5’b00101

– assign a = !b ; // a=1’b0

– assign a = ~b ; // a=5’b10001

– assign a = b & c ; // a=5’b00100

✓ Arithmatic Assignments
– Ex: // b=5’b01110 c=5’b00101

– assign a = - b ; // a=5’d -14

– assign a = b * c ; // a=10’d 70

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 Useful Boolean Operators
✓ Bitwise operators perform bit-sliced operations on vectors
– ~(4’b0101) = {~0,~1,~0,~1} = 4’b1010
– 4’b0101 & 4’b0011 = 4’b0001

✓ Logical operators return one-bit (true/false) results

– !(4’b0101) = ~1 = 1’b0

✓ Reduction operators act on each bit of a single input vector

– &(4’b0101) = 0 & 1 & 0 & 1 = 1’b0

✓ Comparison operators perform a Boolean test on two arguments

Bitwise Logical Reduction Comparison
~a NOT !a NOT &a AND Relational
a<b
a&b AND a && b AND ~& NAND a>b
a <= b
| OR a >= b
a|b OR a || b OR
[in]equality
a^b XOR ~| NOR a == b returns x when x or z
a != b in bits. Else returns 0
a ~^ b XNOR ^ XOR or 1
case [in]equality
Note distinction between ~a and !a a === b returns 0 or 1 based
a !== b on bit by bit
comparison

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 Combination Circuits – always construct
✓ Procedural assignments update the value of reg
variables under the control of the procedural flow.
✓ Updating reg, integer, time, memory variables.
– Occur within always, initial, task and function.
• i.e. reg a,clk; //Note “reg”, not “wire”
• always#5 clk = ~clk; // procedural assignment
• i.e. always @ (b) // procedural assignment with triggers
a = ~b;

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 Combination Circuits – always construct
✓ Using blocking assignments in always construct
✓ The “always” block runs once
✓ whenever a signal in the sensitivity list changes value

Better !!

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 Coding style
✓ Data has to be described in one always block
✓ Don’t use initial block for synthesis
✓ Data bit order can’t vary
✓ Avoid combinational loop

always@* begin initial begin reg [15:0] a; always@* begin

A=B+C; A=B; reg [3:0] b; A=B;
B=C; B=A;
end
end assign a[b]=0; end
always@* begin
A=B+D;
end

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 Examples

module CORE (A,B,MODE,OUT);

input[3:0] A,B;
input[1:0] MODE;
output reg signed[6:0] OUT;

always@* begin

case(MODE)
2'b00: OUT = A+B;
2'b01: OUT = A-B;
2'b10: OUT = A*B;
2'b11: OUT = A/B;
endcase
end

endmodule

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SECTION 4
SIMULATIONS

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 Simulation Environment

TESTBED.v

DESIGN.v PATTERN.v

Port declaration
input
data type declaration

Applying simulation
output
Display results

Can use behavior-level

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 Simulation Environment (cont.)

TESTBED.v Just like a breadboard

`timescale 1ns/10ps
`include “MUX2_1.v”
`include “PATTERN.v”

module TESTBED;

wire out,a,b,sel,clk,reset;

MUX2_1 mux(.out(out),.a(a),.b(b),.sel(sel)); Putting devices on the board and

PATTERN pat(.sel(sel),.out(out),.a(a),.b(b)); connect them together!

enmodule

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 Simulation Environment (cont.)

#cycle sel=1;
PATTERN.v for(i=0;i<=3;i=i+1)
begin
#cycle {a,b}=i;
module PATTERN(sel,out,a,b); #cycle $display( "sel=%b, a=%b, b=%b,
out=%b" , sel, a, b, out);
input out; end
output a,b,sel;
#cycle sel=0;
reg a,b,sel,clk,reset; for(i=0;i<=3;i=i+1)
integer i; begin
parameter cycle=10; #cycle {a,b}=i;
#cycle $display( "sel=%b, a=%b, b=%b,
always #(cycle/2) clk = ~clk; out=%b" , sel, a, b, out);
end
initial begin
a=0;b=0;sel=0;reset=0;clk=0; #cycle $finish;
#3 reset = 1; end
#10 reset = 0;
endmodule

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 Simulation Environment (cont.)
fsdb is a file format that contains
✓ Dump a FSDB file for debug information of the waveform
– General debussy waveform generator during the simulation
• $fsdbDumpfile(“file_name.fsdb”);  Dump an fsdb file
• $fsdbDumpvars;  Dump all values
– Other debussy waveform generator
• $fsdbSwitchDumpfile(“file_name.fsdb”);
 close the previous fsdb file and create a new one and open it
• $fsdbDumpflush (“file_name.fsdb”);
 not wait the end of simulation and Dump an fsdb file
• $fsdbDumpMem(memory_name, begin_cell, size);
 the memory array is stored in an fsdb file
• $fsdbDumpon; $fsdbDumpoff;
 just Dump and not Dump

✓ Put the above command in an initial block

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 Simulation Environment (cont.)

✓ Clock Generation 50% duty cycle

initial clk = 0;
always #25 clk = ~clk;
25 25
✓ Display simulation result
– Texture format output
• $display(“Output #%d=%d ”, count , value);
 Displays the values of the argument list whenever any of the arguments change
except $time.
• $monitor($time,”clk=%b out=%b\n”,clk,out);
 Prints out the current values of the signals in the argument list
format (display): %d (decimal), %b (binary), %h (hexadecimal),
%o (octal), %c(ASCII),%s (strings), %v (strength),
%m(hierarchical name), %t (time)
$time : current time
\n: new line, \t: tab, \\: backslash, \”: double quote

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 Simulation Environment (cont.)
✓ Random number generation ✓ Control command
• $random • $finish;
• $random(seed) //finish the simulation
e.g. in1=$random; • $stop;
in2=$random(37); //stop the simulation

✓ Simulation command
input waveforms
– Verilog compile
Your
• ncverilog test_file_name.v Verilog Verilog
• ncverilog test_file_name.v design Test pattern
output test data
+access+wr (dump the waveform)
– Debussy waveform generation
• nWave &
– Stop the simulation and continue the simulation
• Ctrl+z Suspend the simulation at anytime you want.(not terminate yet!)
• . Continue if you stop your simulation by $stop command
• jobs Here you can see the jobs which are processing with a index on
the left [JOB_INDEX]
• kill Use the command “kill %JOB_INDEX to terminate the job
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 Overview

✓ Verdi
– An HDL Debug & Analysis tool developed by NOVAS Software, Inc. It mainly
contains the following three parts.

– nTrace : A source code viewer and analyzer that can display the design hierarchy and source code
(Verilog, VHDL, SysmVerilog, SystemC, PSL, OVA, mixed) for selected design blocks.
– nWave : A state-of-the-art graphical waveform viewer and analyzer that is fully integrated with Verdi’s
source code, schematic, and flow views.
– nSchema : A schematic viewer and analyzer that generates interactive debug-specific logic diagrams
showing the structure of selected portions of a design.

✓ Invoke nWave
– By command : nWave &

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 nWave

✓ Overview Cursor Marker

Tool Bar
Position Position Delta Zoom Scale Ruler

Pull Down
Menu

Signal
Window

Value Window Full Scale Ruler Scroll Bar

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 nWave (cont.)

✓ Open fsdb file

– Use File Open… command

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 nWave (cont.)

✓ Get signal
– Use Signal  Get Signals... command

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 nWave (cont.)

✓ Choose value format

– On the value window click Left Button

Default : Hexadecimal

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 nWave (cont.)

✓ Reload nWave
– Update fsdb file in Debussy database
• File  Reload
• Hot key  L (shift + l)

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 Authors
2004 Chia-Hao Lee ([email protected])
2006revised Yi-Min Lin ([email protected])
2008revised Chien-Ying Yu ([email protected])
2008revised Chi-Heng Yang ([email protected])
2009revised Yung-Chih Chen ([email protected])
2010revised Liang-Chi Chiu ([email protected])
2012revised Shyh-Jye Jou
2014revised Sung-Shine Lee ([email protected])

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