03-02-2024

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Micro Processor
Unit 5

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Multitasking
• Multitasking is the ability of a computer to run more than
one program or task at the same time.
• On a single processor actually multi-system multitasking
system or multiprocessors they do not run actually at the
same time.
• Instead the processor will switch among the processes that
are currently active at that time.
• It appears to the user as though the processor is executing
all of the task at once.
• Apart from the simple task switching the 80386 will support
two other task-management features:
• Interrupts and Exceptions
• Task Isolation

Multitasking
• The 80386 microprocessor has special registers and data
structures to support efficient and protected multitasking
system.
• Task State Segment
• Task State Segment Descriptor
• Task Registers
• Task Gate Descriptors
• With these registers and data structures the 80386 will
switches execution from one task to another, saving the
environment of the current task so that the task can be
restarted later.

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Interrupts and Task Isolation

• Interrupts and exceptions cause task switches. The 80386
not only switches automatically to the task that handles the
interrupt or exception but it will also automatically switch
back to the interrupted task when the interrupt or exception
has been serviced.
• Interrupt task may interrupt lower priority interrupt task to
any depth.
• With each task switching, 80386 can also switch to another
LDT and page directory.
• So Now, Each task can have separate LDT and page
directory i.e. it can have a different mapping system like
logical to physical mapping.

Task State
Segment

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Task State Segment

• The Task State Segment (TSS) is a data structure used by
the 80386 to store information about a particular task.
• 80386 microprocessor it uses the TSS like a scratch pad.(Or
a painter’s color palette).
• It stores everything it needs to know about a task in TSS.
• TSS is not accessible to the any user program even at the
privilege level zero.
• The fields of a TSS are divided into two sets: one is
dynamic and the second is static

Task State Segment

• Dynamic: • Instruction pointer (EIP)
• flag register (EFLAGS)
• General registers
(EAX, ECX, EDX, EBX, ESP, EBP, ESI, EDI)
• Segment registers (ES, CS, SS, DS, FS and GS)
• backlink
• Saving EIP guarantees that the task can be restarted from the
point where it was stopped.
• Saving the flags guarantees the execution of conditional
instructions properly.
• Back link is used by the 80386 microprocessor to keep the track
of the previous task.
• Executing the return instruction at the end of new task
automatically loads the backlink selector for the previous TSS
into the task register.

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Task State Segment

• Static: The processor only reads from them during a task and
don’t change their values
• Selector of the Task’s LDT
• CR3 register (that contains the base address of page directory)
• Pointer to the stacks for privilege levels 0-2.
• The T bit (debug trap bit)
• The I/O map Offset
• The T bit in the 386 TSS indicates that the processor should
generate a debug exception when switching to a task.
• If T = 1 then upon entry to a new task a debug exception 1 will
be generated.

• Any control transfer that changes CPL within a task

causes a change of stacks as a result of the privilege
level change.
• Due to this the initial values of SS:ESP for PL0, 1
and 2 are retained in the task state segment. Upon
task switching new stack pointer is loaded into the
SS and ESP registers and the previous ESP value is
pushed onto the new stack..
• When the control is returned to previous task, the
previous stack is restored.
• The I/O map base holds the 16-bit offset of the
beginning of the I/O permission bit map. It is
different for different tasks and affects the I/O
privilege checking.

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TSS Descriptor
• The Descriptors for the TSS of each Task are present in the
GDT. The TSS Descriptor is of 8 bytes
• The ‘b’ bit in the type field indicate whether the the task is
busy. A code of 9 indicate a non-busy task. A code of 11(0Bh)
indicate a busy task.
• Base, Limit, G-bit and P-bit are same as general segment
descriptor.
• However, the limit of a 386 TSS must be greater than
103(0064h) otherwise exception will be occurred. (max 64GB)

Task Register
• Task Register is a 16 bit
register.
• It contains a selector,
which points to the TSS
Descriptor in the GDT.
• Every task in 80386 µP has
a TSS (Task State
Segment).
• As soon as we load a
selector in Task Switch
register, the corresponding
TSS Descriptor is copied This descriptor cache is
from the GDT into an on invisible to the program
chip TSS Descriptor cache.

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Task Gate Descriptor

• Task gates are used to switch tasks indirectly in a
protected environment.
• Task Gate Descriptor contains a TSS selector
• RPL bits in this selector are not used by the processor.
• A procedure may not select a task gate descriptor unless
the EPL is numerically less than or equal to the DPL of
the descriptor.

Task Switching without task gate

• There are five steps of task switching:
1. Privilege check : The status of the current task is
checked in order to see whether it is permitted to switch
to the desired task or not. If EPL < TSS descriptor
DPL then only the current task is allowed to switch
to the desired task.
2. Limit and present bit checking: For the limits and
presence the TSS descriptor of desired task is checked.
3. Save the state of current task : The 80386DX processor
takes the base address of current TSS from the task
register cache and stores the context into the current
TSS. For the current task the selector is stored as a back
link selector in the new task.

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4. Task register loading : The selector of desired tasks TSS

descriptor is loaded in the visible part of the Task Register.
The ‘B' bit in the new task's descriptor is indicated as busy
and ‘TS' bit in the CR0 register is set to indicate that a task is
active.
5. Resuming Execution : While doing this the selector of the
old TSS is saved as the back-link selector in the new task
state segment. Switching is complete and execution resumes
with the instruction identified by the new contents of the
CS:EIP.

Task Switching with Task Gate

1. Privilege check: The gate selectors EPL is compared with the
DPL of the Task gate descriptor. IF task gate DPL > EPL then
only current task is allowed to switch to the new task.
All other steps are same ☺ ☺ ☺

Task Linking Back Link Field (TSS)

NT bit (Flag reg.)
• CALL instruction,
• an interrupt instruction,
• an external interrupt,
• an exception causes a switch to a new task.
• the 80386 automatically fills the back-link of the new TSS
with the selector of the outgoing task's TSS and, at the
same time, sets the NT bit in the new task's flag register.
• The NT flag indicates whether the back-link field is valid.
• When completing the current task, the 80386 examines the
NT flag. If NT is set, the 80386 switches back to the task
selected by the back-link field.

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Busy bit
• A chain of back-links may grow to any length as interrupt tasks
interrupt other interrupt tasks or as called tasks call other tasks.
• The busy bit ensures that the CPU can detect any attempt to
create a loop.
• A loop would indicate an attempt to re-enter a task that is already
busy.
• The TSS is not a re-entrable resource.
1. When switching to a task, the processor automatically sets the busy bit
of the new task.
2. When switching from a task, the processor automatically clears the
busy bit of the old task if that task is not to be placed on the back-link
chain (i.e., the instruction causing the task switch is JMP or IRET). If
the task is placed on the back-link chain, its busy bit remains set.
3. When switching to a task, the processor signals an exception if the busy
bit of the new task is already set.
• By these actions, the processor prevents a task from switching to
itself or to any task that is on a back-link chain, thereby
preventing invalid re-entry into a task.

Modifying Task Linkages

• Trusted software that removes a task from the back-
link chain must follow the following policies:

1. First change the back-link field in the TSS of the

interrupting task, then clear the busy-bit in the TSS
descriptor of the task removed from the list.
2. Ensure that no interrupts occur between updating the
back-link chain and the busy bit.

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Task Address Space

• The ability for tasks to have distinct address spaces is
an important aspect of 80386 protection.
• A module in one task cannot interfere with a module in
another task if the modules do not have access to the
same address spaces.
• The flexible memory management features of the 80386
allow systems designers to assign areas of shared
address space to those modules of different tasks that
are designed to cooperate with each other.

1. Task Linear To Physical Space Mapping

1. One linear-to-physical mapping shared among all tasks:
• When paging is not enabled, this is the only possibility. Without page
tables, all linear addresses map to the same physical addresses.
• When paging is enabled, this style of linear-to-physical mapping results
from using one page directory for all tasks
2. Several partially overlapping linear-to-physical mappings.
• This style is implemented by using a different page directory for each
task. Because the PDBR (page directory base register) is loaded from
the TSS with each task switch, each task may have a different page
directory.
• In theory, if Entries of different page directories point to different page
tables and the page tables point to different page of physical memory,
then the tasks do not share any physical addresses.
• In practice, some portion of the linear address spaces of all tasks must
map to the same physical addresses. The task state segments must lie in
a common space so that the mapping of TSS addresses does not change
while the processor is reading and updating the TSSs during a task
switch.
• The linear space mapped by the GDT should also be mapped to a
common physical space; otherwise, the purpose of the GDT is defeated.

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2. Task Logical Address Space

• A common linear-to-physical space mapping alone
does not enable sharing of data among tasks.
• To share data, tasks must also have a common logical-
to-linear space mapping: i.e., they must also have
access to descriptors that point into a shared linear
address space.
• There are three ways to create common logical-to-
physical address-space mappings :
1. Via the GDT.
2. By sharing LDTS
3. By descriptor aliases in LDTs

2. Task Logical Address Space

• There are three ways to create common logical-to-
physical address-space mappings :
1. Via the GDT. All tasks have access to the descriptors in
the GDT. If those descriptors point into a linear-address
space that is mapped to a common physical-address space
for all tasks, then the tasks can share data and instructions.
2. By sharing LDTS. Two or more tasks can use the same
LDT if the LDT selectors in their TSSs select the same
LDT segment. Those LDT-resident descriptors that point
into a linear space that is mapped to a common physical
space permit the tasks to share physical memory.
3. By descriptor aliases in LDTs. It is possible for certain
descriptors of different LDT's to point to the same linear
address space. If that linear address space is mapped to the
same physical space by the page mapping of the tasks
involved. These descriptors permit the tasks to share the
common space. Such descriptors are commonly called
aliases"

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Virtual 86 Mode – Features May 18, 19

Dec 19

• The purpose of a V86 task is to form a "virtual machine"

with which to execute an 8086 program considering the
mechanism of 80386 protection.
• It is a hardware virtualization technique that allowed
multiple 8086 processors to be emulated by the 386 chip.
• V86 mode uses a segmentation scheme identical to that of
real mode (which creates 20-bit linear addresses in the
same manner as 20-bit physical addresses)
• When the VM bit of flag register is set, the 80386 will enter
the virtual mode.
• The 80386 processor checks for two conditions when the
VM bit is set:
• Whether to execute 8086 programs while loading the segment
registers.
• To find the instructions sensitive to IOPL.

Advantages of Virtual 86 Mode

• On an 80386 supporting multitasking we can execute
multiple 8086 applications in virtual mode.
• In a multitasking system, it is essential to switch between
the 8086 and the protected mode.
• The 80386 processor can switch back and forth rapidly
between the virtual-86 (V86) and the protected mode.
• The programs in V86 mode are executed at PL3
• Multiple 8086 real-mode software applications can execute
at one time.(using ‘time-slicing’).
• The VM-86 mode could be used to share one 80386
processor with many users by partitioning the memory, so
that each user has its own DOS partition

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Memory Management in Virtual Mode May 17,

(Hardware & software cooperation) Dec 18

• A complete virtual machine consists not only of 80386 hardware

but also of systems software. Thus, the emulation of an 8086 is
the result of cooperation between hardware and software:
• The hardware provides a virtual set of registers (via the TSS), a
virtual memory space (the first megabyte of the linear address
space of the task), and directly executes all instructions that deal
with these registers and with this address space.
• The software controls the external interfaces of the virtual machine
(I/O, interrupts, and exceptions) in a manner consistent with the
larger environment in which it executes. In the case of I/O, software
can choose either to emulate I/O instructions or to let the hardware
execute them directly without software intervention.
• The register set available in V86 mode includes all the registers
defined for the 8086 plus the new registers introduced by the
80386: FS, GS, debug registers, control registers, and test
registers.

Entering and leaving Virtual mode May 18, 19,

Dec 17

• The processor can enter V86 by either of two means:

• A Task Switch to an 80386 task loads the image of EFLAGS from
the new TSS. A value of one in the VM bit of the new EFLAGS
indicates that the new task is executing 8086 instructions;
therefore, while loading the segment registers from the TSS, the
processor enters in V86 mode.
• An IRET instruction from a procedure of an 80386 task loads the
image of EFLAGS from the stack. A value of one in VM in this
case indicates that the procedure to which control is being returned
is an 8086 procedure. The CPL at the time the IRET is executed
must be zero, else the processor does not change VM.
• The processor leaves V86 mode when an interrupt or exception
occurs. There are two cases:
• The interrupt or exception causes a task switch. A task switch
from a V86 task to any other task loads EFLAGS from the TSS of
the new task. If the new TSS is an 80386 TSS and the VM bit in
the EFLAGS image is zero, then the processor clears the VM bit of
EFLAGS, and enters in protected-mode.

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• The interrupt or exception vectors to a privilege-level zero

procedure. The processor stores the current setting of EFLAGS on
the stack, then clears the VM bit. The interrupt or exception
handler, therefore, executes as "native" 80386 protected-mode
code.
• Systems software does not manipulate the VM flag directly, but rather
manipulates the image of the EFLAGS register that is stored on the
stack or in the TSS. The V86 monitor sets the VM flag in the
EFLAGS image on the stack or in the TSS when first creating a V86
task.
• Exception and interrupt handlers can examine the VM flag on the
stack. If the interrupted procedure was executing in V86 mode, the
handler may need to invoke the V86 monitor.

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Pyq
• Multi tasking short note
• Register and data structures used in MT
• TSS
• Task register and its instruction
• Task gate descriptor
• Interrupt gate and trap gate descriptor, difference
• TSs and task gate descriptor difference
• Task linking
• V86 mode
• Linear add in v86 mode’entering and leaving v86mode
• Mem mapped i/o and i/o mapped i/o
• V86 and real mode diff

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