5 4 3 2 1

Table of Contents
Page Title Page Title Page Title

01 TABLE OF CONTENTS 31 Power/Volume Button Debug 61 X

D 02 Build Options 32 Sensors 62 +1.8VSB & Load SW D

03 BLOCK DIAGRAM 33 Debug Conn 63 CHARGER

04 CLOCK DISTRIBUTION 34 SAM_1_PWR_ADC_Debug 64 +5V Load SW
05 SIGNAL & RESET MAP 35 SAM_2 65 +3P3V Load SW
06 POWER FLOW 1 of 3 36 X 66 VCCIN Coontroller
07 POWER FLOW 2 of 3 37 Level Shifters 67 VCCIN DRMOS
08 POWER FLOW 3 of 3 38 TPM 68 VCCINAUX Controller
09 I2C MAP 39 Temp Sensor 69 VCCINAUX DRMOS
10 CPU(1)_Disp,Type-C,MISC 40 REALTEK ALC3269C-GRT CODEC 70 SL1 PWR/ BATT CONN.
11 CPU(2)_LPDDR 41 Headphone/Speaker Connector 71 SL1 SIGNALS
C C

12 CPU(3)_ICL POWER1_DDR_VCCSTG 42 Audio Smart Amp 72 +3P3V_HPD/LCD backlight

13 CPU(4)_ICL_POWER2_VCCIN 43 X 73 X
14 CPU(5)_GND 44 M.2 SSD Connector 74 KBTP Connector
15 CPU(6)_CFG_RESERVED 45 USB A 3.0 Port 75 X
16 LPDDR3(1)_MEMORY DOWN 46 DP Dongle Control 76 X
17 LPDDR3(2)_MEMORY DOWN 47 X 77 USB Type-C Port
18 SFF 48 uSD Card B2B 78 X
19 Mechanical Parts 49 X 79 USB Type-C PD
20 PCH(1)_SD,HDA,RTC, CLK 50 Wi-Fi_BT 80 X
B 21 PCH(2)_CLK,SMB,LPC, SPI 51 X 81 X B

22 PCH(3)_SYS PWR CONTR 52 X 82 X

23 PCH(4)_CSI,eMMC,CNVi 53 X
24 PCH(5)_PCIE,USB 54 Camera Front/IR Connector
25 PCH(6)_CPU,GPIO,MISC 55 VA and VCCRTC
26 PCH(7)_POWER 56 +VCCSTG
27 PCH(8)_VCCIN_AUX_Decoupling 57 eDP connector
28 Power Monitor 58 Silego Controller
29 Type-C Debug 59 +5VSB & +3P3VSB
30 Touch Con & Key 60 +1P2V_DUAL&++0P6V_DDR_VDDQ
A A
DBG_S - Replace with board short for MP
CAD Note: DBG_R - Replace with lower cost component for MP <Variant Name>
Property: BUILD-OPT DBG_N - Install for Non-Debug Builds
DNP = Do Not Place DBG_D - Remove from BOM (Depopulate) for MP Title: Table of Contents
DBG_T - Used for Telemetry in MP as needed Engineer:
<OrgAddr1>
DBG_TS - Used for Telemetry in MP as needed. This part needs to be Size Project Name Rev

replaced with a short if telemetry is not needed. A3 EDAN_A_EV1 <RevCode>

Date: Tuesday, May 21, 2019 Sheet 1 of 82
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Title: Build Options

CAD Note:
Defaults: Footprint SMD 0201, Cap tmp Coeff X5R, 1% resistors Size Project Name
Engineer:
<OrgAddr1>
Rev
A3 EDAN_A_EV1 1.00
Date: Tuesday, May 21, 2019 Sheet 2 of 82
5 4 3 2 1
 5 4 3 2 1

LAST UPDATE - Oct 25 2018

D D

EDAN-A
Dragonfly Debug connector Multiple MB IR
IR Camera
OV7251
Front RGB Camera Block Diagram 1.6
interfaces LED OV9734
TPM
MIPI MIPI 16MB
Nuvoton
SPI ROM
Power Monitors
ALS NationZ
TCS3430
MIPI MIPI
I2C
RTS5849D-GR ISP
USB-C Multiple MB Chimera USB2 SPI
Firefly conn
Type C Debug interfaces Chimera FPC ALC 3300 R ALC1304M
Right
USB2 Codec L AMP
Chimera FPC
SSD M.2 Left
USB2 I2C I2C Digital
128GB, 256GB Mic
Digital
Mic
Analog audio combo jack
512GB, 1TB I2C I2C
SPI
C

PCIe HDA HD Audio C

4x PCIe
LPDDR4X x32 PDM PDM
LPDDR3
LPDDR3 x32
x32
LPDDR3GB
8,16,32 x32 128-bit (32b x 4) – 2 Chl -64 bit each DDR USB3 USB3.1
USB2 USB2
USB A Port

I2C I2C USB3

LCD eDP
USB2
USB3.1
CONN
13.5" eDP eDP USB2
SL40
Thermal 15" DP
DP

Sensors NTRIG G5 SPI SPI Ice Lake PWR_SL

U 4+2
Hall Wifi
Sensor
BU52072
IO IOx Backlight PWM_EN CNVi CNVi
Chimera AND Harrison Peak
Controller PWM
BT

Greenpak IOx
USBC USBC Retimer USBC USB C Port
B
I2C eSPI eSPI 8Mb SPI B

SPI
UART UART Flash
GPIO
KBTP CONN USB2 USB2
UART SML1
SAM
16Mb SPI I2C
SPI PWM FAN
Flash
Battery I2C CC1/CC2
Connector I2C PD Controller TCP_VBUS

BQ25713
EXT_DC_IN +5VSB SPI
Battery
I2C
VBAT Charger LEGEND
8Mb SPI
Charging Flash Edan-A specific
VBAT
I2C VBAT FET’s Common to Foxburg
A
Fuel 2S3P batt VCCIN ROP Debug feature A

Gauge 49.4 WHr IMVP9

PWR_SL AUX Power

Title: BLOCK DIAGRAM

<OrgName> Engineer: <OrgAddr1>
Size Project Name Rev
A1 EDAN_A_EV1 1.00
Date: Tuesday, May 21, 2019 Sheet 3 of 82
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

<Variant Name>

Title: CLCOK DISTRIBUTION

<OrgName> Engineer: <OrgAddr1>
Size Project Name Rev
A3 EDAN_A_EV1 2.89.6
Date: Tuesday, May 21, 2019 Sheet 4 of 82
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 5 4 3 2 1

SIGNAL & RESET MAP

Last Update - Feb 13 2018
D +VDD_BATA_PACK D

Battery

SL1_PWR_GOOD
PWR_SL1_F SW Switch 1-1 +V_ALWAYS_ON
SL1 (Diode)
TCP0_VBUS_PWR_GOOD
+VBUS_P0_CONN SW 2
USB-C +3P3VAS +VCC_RTC
Step Down
TCP1_VBUS_PWR_GOOD +1P8VAS
+VBUS_P1_CONN SW LDO
USB-C
Silego 3P3VA_EN 16 SLP_S4#
1 of 2 LDO
SAM_SL1_PWR_EN LS 3 4
18 SLP_S3#
+1P8V_SAM
TCP0_LS_EN_N Charging
LS
circuit 15 SAM_PCH_PWRBTN#
EXT_DC_IN PWRBTN# SLP_S3#
TCP1_LS_EN_N & Switch
LS
5 SAM 14
RSMRST#
SLP_S4#
RSMRST#
C Power PWRBTN#_1V8 LPC C

Button
8 PCH_DPWROK Intel
CHG_BATDRV_A DSW_PWROK
FET 6 VSUS_ON PCH
+3P3VSB SAM
9 SLP_SUS#
+5VSB SUS_PWRGD 7
SLP_SUS# TPM
+5VSB2 SSD/M.2
+1P8VSB
1-2

PLTRST_BUF#
+VSYS

10 1P8VSB_PG
+VCCIN_AUX
11 VCCIN_AUX_READY 23
PM_PCH_PWROK
+VNN_BYP PCH_PWROK
25
AND Gate
12 +V1P05_BYP_EN PLTRST#
24
PLTRST# Buffer
+1P8V_DDR_VDD1 +V1P05_BYP 13 VCCIN_AUX_PG
SYS_PWROK
+1P1V_DDR_VDD2 SYS_PWROK
17 SLP_S4_DRV#
B
21 B

19 SLP_S3_DRV# VCCST_PWRGD
+1P1V_DDR_PG

VCCST_PWRGD

Silego page 75

2 of 2 OD
3P3V/5V
3P3V_SSD_M2
ML_3P3V_PWR_FUSE (MDP)

+3P3V_SSD
Power On Sequence
20 ALL_SYS_PWRGD
1 25
EN
VCCIN
A 22 VRM_PWRGD A

VRDY

<Core Design>

Title: SIGNAL&RESET MAP

<OrgName> Engineer:
<OrgAddr1>
Size Project Name Rev
A2 EDAN_A_EV1 1.00
Date: Tuesday, May 21, 2019 Sheet 5 of 82
5 4 3 2 1
 5 4 3 2 1

LAST UPDATE - Sept 13 2018

EDAN/HOOK Power Flow EV1

D D

C C

B B

A A

Vinafix.com
<Core Design>

Title: POWER FLOW (1 OF 3)

<OrgName> Engineer:
<OrgAddr1>
Size Project Name Rev
A1 EDAN_A_EV1 1.00
Date: Tuesday, May 21, 2019 Sheet 6 of 82
5 4 3 2 1
 5 4 3 2 1

LAST UPDATE - SEPT. 13 2018

D D

C C

B B

A A

<Core Design>

Title: POWER FLOW (2 OF 3)

<OrgName> Engineer:
<OrgAddr1>
Size Project Name Rev
A1 EDAN_A_EV1 1.00
Date: Tuesday, May 21, 2019 Sheet 7 of 82
5 4 3 2 1
 5 4 3 2 1

LAST UPDATE - SEPT. 13 2018

D D

C C

B B

A A

<Core Design>

Title: POWER FLOW (3 OF 3)

<OrgName> Engineer:
<OrgAddr1>
Size Project Name Rev
A3 EDAN_A_EV1 1.00
Date: Tuesday, May 21, 2019 Sheet 8 of 82
5 4 3 2 1
 5 4 3 2 1

LAST UPDATE - APR.2018 (OUTDATED)

D D

C C

B B

A A

Title: 09. I2C MAP

Engineer:
<OrgAddr1>
Size Project Name Rev
A1 EDAN_A_EV1 1.00
Date: Tuesday, May 21, 2019 Sheet 9 of 82
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 5 4 3 2 1

+VCCST_CPU

+1P8VSB
C1001
0.1u 6.3V
R1012
U1003 10K
5
VCC
2 4
I O PCH_CATERR#_1V8 [33,34]
PCB1001
1
NC1 3
D TOP D
GND
Bottom
74AUP1G07GX

M1098028-005

+VCCSTG_TERM +3P3VSB

100K
R1021
5.1 DBG_D
DBG_D

R1013
D
Q1002 G
SAM_SOC_JTAG_TRST# [35]
DBG_D
+VCCST_CPU +VCCSTG_TERM

100
R1020
TP_CATERR#_R [76]
R1001 1K
330 +VCCST_CPU 0201S_P28-W 35
Added termination when PECI trans is DNP
+VCCSTG_TERM
ALL
Intel recommended 200-400 Ohm PD
R1018 0PM_THRMTRIP#
[58] H_THERMTRIP#

R1038
R1016 0201S_P28-W 35 +VCCSTG_TERM
U1001D
R1008 49.9
1K 0201S_P28-W 35 4 OF 19
0201S_P28-W 35 TP_CATERR#_R J4 P3
CATERR PROC_TCK XDP_TCK [18,76]

1K
100
PECI CD5 K5

49.9

49.9
H_PROCHOT# H_PROCHOT#_R PECI PROC_TDI XDP_TDI [18,76]
R1002 499 C3 K3
[26,63,66,76] H_PROCHOT# PM_THRMTRIP# E3 PROCHOT PROC_TDO XDP_TDO [18,76]
0201S_P28-W 35 P4
THRMTRIP PROC_TMS XDP_TMS [18,76]
DNP C1008 47p N1

R1027

R1028

R1026

R1030
PROC_TRST XDP_TRST# [18,76]

DNP
R1037 0201S_P33 PROC_POPIRCOMP CJ41
100 PCH_OPIRCOMP DU3 PROC_POPIRCOMP N5
0402S_P4 A14 PCH_OPIRCOMP PCH_TRST R5 PCH_TRST# [18,76]
RSVD_A14 PCH_TCK PCH_JTAG_TCK [18,76]
C B14 K1 C
RSVD_B14 PCH_TDI PCH_JTAG_TDI [18,76]
K2
49.9

49.9
0201S_P28-W35

0201S_P28-W35

DBG_PMODE PCH_TDO PCH_JTAG_TDO [18,76]

DL15 N3
D

INT. PU
DBG_PMODE PCH_TMS PCH_JTAG_TMS [18,76]
N2
PCH_JTAGX PCH_JTAGX [18,76]
G DV11
[35] SAM_PROCHOT [18] GPP_E3 GPP_E3/CPU_GP0
DT11 P6
R1022

R1023

[18] GPP_E7 GPP_E7/CPU_GP1 PROC_PRDY PROC_PRDY# [18]

Q1001 0 R1043 PCH_PW RBTN# CR38 M6 DNP
[22,37] SAM_PCH_PW RBTN# GPP_B3/CPU_GP2 PROC_PREQ PROC_PREQ# [18]
SOT-VMT3_1P2XP8XP55_P4MM-1 CR39 R1029
S

[77,79] BB_FORCE_PW R GPP_B4/CPU_GP3 49.9

R1010 +3P3VSB DT12 0201S_P28-W 35
[18] GPP_E6 GPP_H2 INT. PD DJ38 GPP_E6
DNP R1007 1K

[18,29] DBG_PMODE
1K DNP DL38 GPP_H2/CNV_BT_I2S_SDO
GPP_H19/TIME_SYNC0 TBL1001
+VCCST_CPU +1P8VSB

49.9

49.9
[44] PCIE_SSD_PERST# M1042225-001

DNP
U1002 Table is not avaliable now.
R1039 R1040

R1004

R1005
5 10K 49.9K
VCC 0201S_P28-W 35
H_PROCHOT# 2 4
I O H_PROCHOT_1P8V# [33,34]
1 C1009
NC1 U1001A
3 0.1u 10V
GND
1 OF 19
Y5 BB5
74AUP1G07GX [57] EDP_TX0_DN DDIA_TXN_0 TCP0_TX_N0 TCP0_TX_N0 [77]
Y3 BB6
[57] EDP_TX0_DP DDIA_TXP_0 TCP0_TX_P0 TCP0_TX_P0 [77]
Y1 AV6
[57] EDP_TX1_DN DDIA_TXN_1 TCP0_TX_N1 TCP0_TX_N1 [77]
Y2 AV5
[57] EDP_TX1_DP DDIA_TXP_1 TCP0_TX_P1 TCP0_TX_P1 [77]
V2 BH2 TCP0_TXRX_N0 [77]
+3P3VSB +1P8VSB eDP [57] EDP_TX2_DN DDIA_TXN_2 TCP0_TXRX_N0
V1 BH1 TCP0_TXRX_P0 [77] USB-C
[57] EDP_TX2_DP DDIA_TXP_2 TCP0_TXRX_P0
V3 BF1 TCP0_TXRX_N1 [77]
[57] EDP_TX3_DN DDIA_TXN_3 TCP0_TXRX_N1
V5 BF2 TCP0_TXRX_P1 [77]
[57] EDP_TX3_DP DDIA_TXP_3 TCP0_TXRX_P1
R1011 R1042 W4 AY5 TCP0_AUX_DN [77]
[57] EDP_AUX_DN DDIA_AUX TCP0_AUX
100K 75K W3 AY6 TCP0_AUX_DP [77]
[57] EDP_AUX_DP DDIA_AUX_P TCP0_AUX_P
ALL DNP
AE3
AE5 DDIB_TXN_0 AR5
GPP_E6 AE2 DDIB_TXP_0 TCP1_TX_N0 AR6
AE1 DDIB_TXN_1 TCP1_TX_P0 AL5
B HIGH: JTAG ODT ENABLED AC5 DDIB_TXP_1 TCP1_TX_N1 AL3 B
mDP DDIB_TXN_2 TCP1_TX_P1
AC3 BD2 USB-C
AC1 DDIB_TXP_2 TCP1_TXRX_N0 BD1
AC2 DDIB_TXN_3 TCP1_TXRX_P0 BB1
DDIB_TXP_3 TCP1_TXRX_N1 BB2
AD3 TCP1_TXRX_P1
AD4 DDIB_AUX AN3
DDIB_AUX_P TCP1_AUX AN5
R1015 15 GPP_E22_SERIRQ DP15 TCP1_AUX_P
[38] PCH_SERIRQ R1034 0 GPP_E23_3P3_PNL DJ17 GPP_E22/DDPA_CTRLCLK/PCIE_LNK_DOWN
[65] +3P3V_PANEL_EN_R GPP_E23/DDPA_CTRLDATA/BK4/SBK4 BF6
TCP2_TX_N0 SL_DATA0_DN [71]
DL40 BF5
GPP_H16/DDPB_CTRLCLK TCP2_TX_P0 SL_DATA0_DP [71]
DP42 BJ5
GPP_H17/DDPB_CTRLDATA TCP2_TX_N1 SL_DATA2_DN [71]
BJ6
TCP2_TX_P1 SL_DATA2_DP [71]
DL17 BL1
[77] TBT_LSX0_TXD GPP_E18/DDP1_CTRLCLK/TBT_LSX0_TXD TCP2_TXRX_N0 SL_DATA1_DN [71]
[77] TBT_LSX0_RXD DK17 BL2
GPP_E19/DDP1_CTRLDATA/TBT_LSX0_RXD TCP2_TXRX_P0 SL_DATA1_DP [71] SL40
BM2
TCP2_TXRX_N1 SL_DATA3_DN [71]
DN17 BM1
GPP_E20/DDP2_CTRLCLK/TBT_LSX1_TXD TCP2_TXRX_P1 SL_DATA3_DP [71]
R1091 DP17
20K GPP_E21/DDP2_CTRLDATA/TBT_LSX1_RXD BG6
TCP2_AUX SLDP_AUX_DN [46]
R1014 0 DK34 BG5
[46] SLDP_CTRL_CLK GPP_D9/ISH_SPI_CS_N/DDP3_CTRLCLK/GSPI2_CS0_N/TBT_LSX2_TXD TCP2_AUX_P SLDP_AUX_DP [46]
R1006 0 DL34
[46] SLDP_CTRL_DATA GPP_D10/ISH_SPI_CLK/DDP3_CTRLDATA/GSPI2_CLK/TBT_LSX2_RXD
DN33 BP6
DL33 GPP_D11/ISH_SPI_MISO/DDP4_CTRLCLK/GSPI2_MISO/TBT_LSX3_TXD TCP3_TX_N0 BP5
Pull up or down straps required GPP_D12/ISH_SPI_MOSI/DDP4_CTRLDATA/GSPI2_MOSI/TBT_LSX3_RXD TCP3_TX_P0
LOW: 1.8V FOR BSSB SINGAL THROUGH LS BV5
DW11 TCP3_TX_N1 BV6
DDP1 I2C/TBT LSX #0/BSSB-LS#0 VCC [57] EDP_HPD GPP_E14/DPPE_HPDA/DISP_MISCA TCP3_TX_P1
CV42 BR1
CV39 GPP_A18/DDSP_HPDB/DISP_MISCB TCP3_TXRX_N0 BR2
CY43 GPP_A19/DDSP_HPD1/DISP_MISC1 TCP3_TXRX_P0 BT2
GPP_E19/DDP1_CTRLDATA GPP_A20/DDSP_HPD2/DISP_MISC2 TCP3_TXRX_N1
CR41 BT1
[71] SL1_DP_HPD GPP_A14/USB_OC1_N/DDSP_HPD3/DISP_MISC3 TCP3_TXRX_P1
1M
100K

CT41
DV14 GPP_A15/USB_OC2_N/DDSP_HPD4/DISP_MISC4 BT6
0 1.8V GPP_E17 TCP3_AUX
GPP_E17 reserved for GPU_EVENT# for SB BT5
DN21 TCP3_AUX_P
[30,65] PCH_VDD_PANEL_EN DL19 EDP_VDDEN AY1TCRCOMP_DN R1009
R1017

R1033

1 3.3V EDP_BKLTEN TC_RCOMP

[34,72] PCH_LCD_BKLT_EN DU19 AY2TCRCOMP_DP 150
eSPI Flash Sharing Mode [72] PCH_BKLT_CTRL_PW M EDP_BKLTCTL TC_RCOMP_P
DDP2 I2C/TBT LSX #1/BSSB-LS#1 VCC J3
RSVD_1 USBA_EN [45]
CT38
EDP_DISP_UTIL GPP_A17/DISP_MISCC TP1001
GPP_H2 D2 CV43
DP_RCOMP R2 DISP_UTILS GPP_A21 CV41
A
GPP_E21/DDP2_CTRLDATA DISP_RCOMP GPP_A22 EDP_I2C_INT [57,76] A
DNP
0 DEFAULT Master Attached R1019 R1003
0 1.8V 0 150
M1042225-001
1 Slave Attached
1 3.3V

W x H 437 x 328 mm
<OrgName> Title: CPU(1)_Disp,Type-C,MISC
Engineer: <OrgAddr1>
Size Project Name Rev
A2 EDAN_A_EV1 0.23
Date: Tuesday, May 21, 2019 Sheet 10 of 82
5 4 3 2 1
 5 4 3 2 1

D
U1001B U1001C D

[16] M_A_0_DQ_[7:0] 2 OF 19 [17] M_C_0_DQ_[7:0] 3 OF 19

M_A_0_DQ_0 CA48 BL48 M_C_0_DQ_0 AK48 Y48
M_A_0_DQ_1 DDRA_DQ0_0/DDR0_DQ0_0/DDR0_DQ0_0 DDRA_CLK_N/DDR0_CLK_N_0 M_A_LP4_CLK_N [16] M_C_0_DQ_1 DDRC_DQ0_0/DDR1_DQ0_0/DDR0_DQ4_0 DDRC_CLK_N/DDR1_CLK_N_0 M_C_LP4_CLK_N [17]
CA47 BL47 AK45 Y47
M_A_0_DQ_2 DDRA_DQ0_1/DDR0_DQ0_1/DDR0_DQ0_1 DDRA_CLK_P/DDR0_CLK_P_0 M_A_LP4_CLK_P [16] M_C_0_DQ_2 DDRC_DQ0_1/DDR1_DQ0_1/DDR0_DQ4_1 DDRC_CLK_P/DDR1_CLK_P_0 M_C_LP4_CLK_P [17]
CA49 BF42 AK49 M43
M_A_0_DQ_3 DDRA_DQ0_2/DDR0_DQ0_2/DDR0_DQ0_2 DDRB_CLK_N/DDR0_CLK_N_1 M_B_LP4_CLK_N [16] M_C_0_DQ_3 DDRC_DQ0_2/DDR1_DQ0_2/DDR0_DQ4_2 DDRD_CLK_N/DDR1_CLK_N_1 M_D_LP4_CLK_N [17]
BV49 BF43 AG47 M42
M_A_0_DQ_4 DDRA_DQ0_3/DDR0_DQ0_3/DDR0_DQ0_3 DDRB_CLK_P/DDR0_CLK_P_1 M_B_LP4_CLK_P [16] M_C_0_DQ_4 DDRC_DQ0_3/DDR1_DQ0_3/DDR0_DQ4_3 DDRD_CLK_P/DDR1_CLK_P_1 M_D_LP4_CLK_P [17]
CA45 AK47
M_A_0_DQ_5 BV47 DDRA_DQ0_4/DDR0_DQ0_4/DDR0_DQ0_4 BG49 M_C_0_DQ_5 AG45 DDRC_DQ0_4/DDR1_DQ0_4/DDR0_DQ4_4 U45
M_A_0_DQ_6 DDRA_DQ0_5/DDR0_DQ0_5/DDR0_DQ0_5 DDRA_CKE0/DDR0_CKE0 M_A_LP4_CKE0 [16] M_C_0_DQ_6 DDRC_DQ0_5/DDR1_DQ0_5/DDR0_DQ4_5 DDRC_CKE0/DDR1_CKE0 M_C_LP4_CKE0 [17]
BV45 BJ47 AG48 V46
M_A_0_DQ_7 DDRA_DQ0_6/DDR0_DQ0_6/DDR0_DQ0_6 DDRA_CKE1/NC M_A_LP4_CKE1 [16] M_C_0_DQ_7 DDRC_DQ0_6/DDR1_DQ0_6/DDR0_DQ4_6 DDRC_CKE1/NC M_C_LP4_CKE1 [17]
BV48 BF38 AG49 M41
[16] M_A_1_DQ_[7:0] M_A_1_DQ_0 DDRA_DQ0_7/DDR0_DQ0_7/DDR0_DQ0_7 DDRB_CKE0/NC M_B_LP4_CKE0 [16] [17] M_C_1_DQ_[7:0] M_C_1_DQ_0 DDRC_DQ0_7/DDR1_DQ0_7/DDR0_DQ4_7 DDRD_CKE0/NC M_D_LP4_CKE0 [17]
CC42 BF41 AJ38 P43
M_A_1_DQ_1 DDRA_DQ1_0/DDR0_DQ1_0/DDR1_DQ0_0 DDRB_CKE1/DDR0_CKE1 M_B_LP4_CKE1 [16] M_C_1_DQ_1 DDRC_DQ1_0/DDR1_DQ1_0/DDR1_DQ4_0 DDRD_CKE1/DDR1_CKE1 M_D_LP4_CKE1 [17]
CC39 AL39
M_A_1_DQ_2 CC43 DDRA_DQ1_1/DDR0_DQ1_1/DDR1_DQ0_1 BM38 M_C_1_DQ_2 AJ39 DDRC_DQ1_1/DDR1_DQ1_1/DDR1_DQ4_1 V42
M_A_1_DQ_3 DDRA_DQ1_2/DDR0_DQ1_2/DDR1_DQ0_2 DDRA_CS_0/DDR0_CS_N_0 M_A_LP4_CS#0 [16] M_C_1_DQ_3 DDRC_DQ1_2/DDR1_DQ1_2/DDR1_DQ4_2 DDRC_CS_0/DDR1_CS_N_0 M_C_LP4_CS#0 [17]
CE38 BM42 AL43 V39
M_A_1_DQ_4 DDRA_DQ1_3/DDR0_DQ1_3/DDR1_DQ0_3 DDRA_CS_1/NC M_A_LP4_CS#1 [16] M_C_1_DQ_4 DDRC_DQ1_3/DDR1_DQ1_3/DDR1_DQ4_3 DDRC_CS_1/NC M_C_LP4_CS#1 [17]
CC38 BP42 AL38 Y39
M_A_1_DQ_5 DDRA_DQ1_4/DDR0_DQ1_4/DDR1_DQ0_4 DDRB_CS_0/NC M_B_LP4_CS#0 [16] M_C_1_DQ_5 DDRC_DQ1_4/DDR1_DQ1_4/DDR1_DQ4_4 DDRD_CS_0/NC M_D_LP4_CS#0 [17]
CE39 BG42 AJ42 T39
M_A_1_DQ_6 DDRA_DQ1_5/DDR0_DQ1_5/DDR1_DQ0_5 DDRB_CS_1/DDR0_CS_N_1 M_B_LP4_CS#1 [16] M_C_1_DQ_6 DDRC_DQ1_5/DDR1_DQ1_5/DDR1_DQ4_5 DDRD_CS_1/DDR1_CS_N_1 M_D_LP4_CS#1 [17]
CE42 AL42
M_A_1_DQ_7 CE43 DDRA_DQ1_6/DDR0_DQ1_6/DDR1_DQ0_6 BM43 M_B_CA4 M_C_1_DQ_7 AJ43 DDRC_DQ1_6/DDR1_DQ1_6/DDR1_DQ4_6 T38 M_D_CA4
[16] M_A_2_DQ_[7:0] M_A_2_DQ_0 DDRA_DQ1_7/DDR0_DQ1_7/DDR1_DQ0_7 DDRB_CA4/DDR0_BA0 [17] M_C_2_DQ_[7:0] M_C_2_DQ_0 DDRC_DQ1_7/DDR1_DQ1_7/DDR1_DQ4_7 DDRD_CA4/DDR1_BA0
BT48 BG39 AB49 T42
M_A_2_DQ_1 BT47 DDRA_DQ2_0/DDR0_DQ2_0/DDR0_DQ1_0 NC/DDR0_BA1 M_C_2_DQ_1 AB48 DDRC_DQ2_0/DDR1_DQ2_0/DDR0_DQ5_0 NC/DDR1_BA1
M_A_2_DQ_2 BT49 DDRA_DQ2_1/DDR0_DQ2_1/DDR0_DQ1_1 BB49 M_A_CA5 M_C_2_DQ_2 AE49 DDRC_DQ2_1/DDR1_DQ2_1/DDR0_DQ5_1 R45 M_C_CA5
M_A_2_DQ_3 BN49 DDRA_DQ2_2/DDR0_DQ2_2/DDR0_DQ1_2 DDRA_CA5/DDR0_BG0 BD47 M_C_2_DQ_3 AE47 DDRC_DQ2_2/DDR1_DQ2_2/DDR0_DQ5_2 DDRC_CA5/DDR1_BG0 N47
M_A_2_DQ_4 BT45 DDRA_DQ2_3/DDR0_DQ2_3/DDR0_DQ1_3 NC/DDR0_BG1 M_C_2_DQ_4 AE48 DDRC_DQ2_3/DDR1_DQ2_3/DDR0_DQ5_3 NC/DDR1_BG1
M_A_2_DQ_5 BN47 DDRA_DQ2_4/DDR0_DQ2_4/DDR0_DQ1_4 BB48 M_C_2_DQ_5 AB47 DDRC_DQ2_4/DDR1_DQ2_4/DDR0_DQ5_4 P42
M_A_2_DQ_6 BN45 DDRA_DQ2_5/DDR0_DQ2_5/DDR0_DQ1_5 NC/DDR0_MA0 BL49 M_C_2_DQ_6 AB45 DDRC_DQ2_5/DDR1_DQ2_5/DDR0_DQ5_5 NC/DDR1_MA0 Y49
M_A_2_DQ_7 BN48 DDRA_DQ2_6/DDR0_DQ2_6/DDR0_DQ1_6 NC/DDR0_MA1 BG38 M_B_CA5 M_C_2_DQ_7 AE45 DDRC_DQ2_6/DDR1_DQ2_6/DDR0_DQ5_6 NC/DDR1_MA1 U48 M_D_CA5
[16] M_A_3_DQ_[7:0] M_A_3_DQ_0 DDRA_DQ2_7/DDR0_DQ2_7/DDR0_DQ1_7 DDRB_CA5/DDR0_MA2 [17] M_C_3_DQ_[7:0] M_C_3_DQ_0 DDRC_DQ2_7/DDR1_DQ2_7/DDR0_DQ5_7 DDRD_CA5/DDR1_MA2
BV42 BL45 AD38 Y45
M_A_3_DQ_1 BV39 DDRA_DQ3_0/DDR0_DQ3_0/DDR1_DQ1_0 NC/DDR0_MA3 BJ46 M_C_3_DQ_1 AD39 DDRC_DQ3_0/DDR1_DQ3_0/DDR1_DQ5_0 NC/DDR1_MA3 U47
DDRA_DQ3_1/DDR0_DQ3_1/DDR1_DQ1_1 NC/DDR0_MA4 M_A_CA[5:0] [16] DDRC_DQ3_1/DDR1_DQ3_1/DDR1_DQ5_1 NC/DDR1_MA4 M_C_CA[5:0] [17]
M_A_3_DQ_2 BV43 BG48 M_A_CA0 M_C_3_DQ_2 AE39 R49 M_C_CA0
M_A_3_DQ_3 BW38 DDRA_DQ3_2/DDR0_DQ3_2/DDR1_DQ1_2 DDRA_CA0/DDR0_MA5 BE45 M_A_CA2 M_C_3_DQ_3 AE43 DDRC_DQ3_2/DDR1_DQ3_2/DDR1_DQ5_2 DDRC_CA0/DDR1_MA5 U49 M_C_CA2
M_A_3_DQ_4 BV38 DDRA_DQ3_3/DDR0_DQ3_3/DDR1_DQ1_3 DDRA_CA2/DDR0_MA6 BG45 M_A_CA4 M_C_3_DQ_4 AE38 DDRC_DQ3_3/DDR1_DQ3_3/DDR1_DQ5_3 DDRC_CA2/DDR1_MA6 M47 M_C_CA4
M_A_3_DQ_5 BW39 DDRA_DQ3_4/DDR0_DQ3_4/DDR1_DQ1_4 DDRA_CA4/DDR0_MA7 BG47 M_A_CA3 M_C_3_DQ_5 AD43 DDRC_DQ3_4/DDR1_DQ3_4/DDR1_DQ5_4 DDRC_CA4/DDR1_MA7 M45 M_C_CA3
C M_A_3_DQ_6 BW42 DDRA_DQ3_5/DDR0_DQ3_5/DDR1_DQ1_5 DDRA_CA3/DDR0_MA8 BE47 M_A_CA1 M_C_3_DQ_6 AD42 DDRC_DQ3_5/DDR1_DQ3_5/DDR1_DQ5_5 DDRC_CA3/DDR1_MA8 R47 M_C_CA1 C
M_A_3_DQ_7 BW43 DDRA_DQ3_6/DDR0_DQ3_6/DDR1_DQ1_6 DDRA_CA1/DDR0_MA9 BJ38 M_A_CA5 M_C_3_DQ_7 AE42 DDRC_DQ3_6/DDR1_DQ3_6/DDR1_DQ5_6 DDRC_CA1/DDR1_MA9 P39 M_C_CA5
[16] M_B_0_DQ_[7:0] M_B_0_DQ_0 DDRA_DQ3_7/DDR0_DQ3_7/DDR1_DQ1_7 NC/DDR0_MA10 [17] M_D_0_DQ_[7:0] M_D_0_DQ_0 DDRC_DQ3_7/DDR1_DQ3_7/DDR1_DQ5_7 NC/DDR1_MA10
AY48 BB47 J48 N46
M_B_0_DQ_1 AY47 DDRB_DQ0_0/DDR0_DQ4_0/DDR0_DQ2_0 NC/DDR0_MA11 BE48 M_D_0_DQ_1 J45 DDRD_DQ0_0/DDR1_DQ4_0/DDR0_DQ6_0 NC/DDR1_MA11 R48
DDRB_DQ0_1/DDR0_DQ4_1/DDR0_DQ2_1 NC/DDR0_MA12 M_B_CA[5:0] [16] DDRD_DQ0_1/DDR1_DQ4_1/DDR0_DQ6_1 NC/DDR1_MA12 M_D_CA[5:0] [17]
M_B_0_DQ_2 AY49 BM39 M_B_CA0 M_D_0_DQ_2 J49 Y41 M_D_CA0
M_B_0_DQ_3 AU45 DDRB_DQ0_2/DDR0_DQ4_2/DDR0_DQ2_2 DDRB_CA0/DDR0_MA13 BG43 M_B_CA2 M_D_0_DQ_3 G47 DDRD_DQ0_2/DDR1_DQ4_2/DDR0_DQ6_2 DDRD_CA0/DDR1_MA13 V41 M_D_CA2
M_B_0_DQ_4 AY45 DDRB_DQ0_3/DDR0_DQ4_3/DDR0_DQ2_3 DDRB_CA2/DDR0_MA14WE BJ42 M_B_CA1 M_D_0_DQ_4 J47 DDRD_DQ0_3/DDR1_DQ4_3/DDR0_DQ6_3 DDRD_CA2/DDR1_MA14WE Y42 M_D_CA1
M_B_0_DQ_5 AU47 DDRB_DQ0_4/DDR0_DQ4_4/DDR0_DQ2_4 DDRB_CA1/DDR0_MA15CAS BM41 M_B_CA3 M_D_0_DQ_5 G45 DDRD_DQ0_4/DDR1_DQ4_4/DDR0_DQ6_4 DDRD_CA1/DDR1_MA15CAS V47 M_D_CA3
M_B_0_DQ_6 AU48 DDRB_DQ0_5/DDR0_DQ4_5/DDR0_DQ2_5 DDRB_CA3/DDR0_MA16RAS M_B_CA4 M_D_0_DQ_6 G48 DDRD_DQ0_5/DDR1_DQ4_5/DDR0_DQ6_5 DDRD_CA3/DDR1_MA16RAS M_D_CA4
M_B_0_DQ_7 AU49 DDRB_DQ0_6/DDR0_DQ4_6/DDR0_DQ2_6 BJ39 M_B_CA5 M_D_0_DQ_7 E48 DDRD_DQ0_6/DDR1_DQ4_6/DDR0_DQ6_6 V43 M_D_CA5
[16] M_B_1_DQ_[7:0] M_B_1_DQ_0 DDRB_DQ0_7/DDR0_DQ4_7/DDR0_DQ2_7 NC/DDR0_ODT_0 [17] M_D_1_DQ_[7:0] M_D_1_DQ_0 DDRD_DQ0_7/DDR1_DQ4_7/DDR0_DQ6_7 NC/DDR1_ODT_0
AY42 BB45 J38 V38
M_B_1_DQ_1 AY38 DDRB_DQ1_0/DDR0_DQ5_0/DDR1_DQ2_0 NC/DDR0_ODT_1 M_D_1_DQ_1 G39 DDRD_DQ1_0/DDR1_DQ5_0/DDR1_DQ6_0 NC/DDR1_ODT_1
M_B_1_DQ_2 AY43 DDRB_DQ1_1/DDR0_DQ5_1/DDR1_DQ2_1 BY47 M_D_1_DQ_2 G38 DDRD_DQ1_1/DDR1_DQ5_1/DDR1_DQ6_1 AH46
M_B_1_DQ_3 DDRB_DQ1_2/DDR0_DQ5_2/DDR1_DQ2_2 DDRA_DQSN_0/DDR0_DQSN_0/DDR0_DQSN_0 M_A_DQS_0_DN [16] M_D_1_DQ_3 DDRD_DQ1_2/DDR1_DQ5_2/DDR1_DQ6_2 DDRC_DQSN_0/DDR1_DQSN_0/DDR0_DQSN_4 M_C_DQS_0_DN [17]
BB39 BY46 G42 AH47
M_B_1_DQ_4 DDRB_DQ1_3/DDR0_DQ5_3/DDR1_DQ2_3 DDRA_DQSP_0/DDR0_DQSP_0/DDR0_DQSP_0 M_A_DQS_0_DP [16] M_D_1_DQ_4 DDRD_DQ1_3/DDR1_DQ5_3/DDR1_DQ6_3 DDRC_DQSP_0/DDR1_DQSP_0/DDR0_DQSP_4 M_C_DQS_0_DP [17]
AY39 CC41 J39 AJ41
M_B_1_DQ_5 DDRB_DQ1_4/DDR0_DQ5_4/DDR1_DQ2_4 DDRA_DQSN_1/DDR0_DQSN_1/DDR1_DQSN_0 M_A_DQS_1_DN [16] M_D_1_DQ_5 DDRD_DQ1_4/DDR1_DQ5_4/DDR1_DQ6_4 DDRC_DQSN_1/DDR1_DQSN_1/DDR1_DQSN_4 M_C_DQS_1_DN [17]
BB38 CE41 J42 AL41
M_B_1_DQ_6 DDRB_DQ1_5/DDR0_DQ5_5/DDR1_DQ2_5 DDRA_DQSP_1/DDR0_DQSP_1/DDR1_DQSP_0 M_A_DQS_1_DP [16] M_D_1_DQ_6 DDRD_DQ1_5/DDR1_DQ5_5/DDR1_DQ6_5 DDRC_DQSP_1/DDR1_DQSP_1/DDR1_DQSP_4 M_C_DQS_1_DP [17]
BB42 BR47 G43 AC47
M_B_1_DQ_7 DDRB_DQ1_6/DDR0_DQ5_6/DDR1_DQ2_6 DDRA_DQSN_2/DDR0_DQSN_2/DDR0_DQSN_1 M_A_DQS_2_DN [16] M_D_1_DQ_7 DDRD_DQ1_6/DDR1_DQ5_6/DDR1_DQ6_6 DDRC_DQSN_2/DDR1_DQSN_2/DDR0_DQSN_5 M_C_DQS_2_DN [17]
BB43 BR46 J43 AC46
[16] M_B_2_DQ_[7:0] M_B_2_DQ_0 DDRB_DQ1_7/DDR0_DQ5_7/DDR1_DQ2_7 DDRA_DQSP_2/DDR0_DQSP_2/DDR0_DQSP_1 M_A_DQS_2_DP [16] [17] M_D_2_DQ_[7:0] M_D_2_DQ_0 DDRD_DQ1_7/DDR1_DQ5_7/DDR1_DQ6_7 DDRC_DQSP_2/DDR1_DQSP_2/DDR0_DQSP_5 M_C_DQS_2_DP [17]
AR48 BV41 B43 AE41
M_B_2_DQ_1 DDRB_DQ2_0/DDR0_DQ6_0/DDR0_DQ3_0 DDRA_DQSN_3/DDR0_DQSN_3/DDR1_DQSN_1 M_A_DQS_3_DN [16] M_D_2_DQ_1 DDRD_DQ2_0/DDR1_DQ6_0/DDR0_DQ7_0 DDRC_DQSN_3/DDR1_DQSN_3/DDR1_DQSN_5 M_C_DQS_3_DN [17]
AR47 BW41 D43 AD41
M_B_2_DQ_2 DDRB_DQ2_1/DDR0_DQ6_1/DDR0_DQ3_1 DDRA_DQSP_3/DDR0_DQSP_3/DDR1_DQSP_1 M_A_DQS_3_DP [16] M_D_2_DQ_2 DDRD_DQ2_1/DDR1_DQ6_1/DDR0_DQ7_1 DDRC_DQSP_3/DDR1_DQSP_3/DDR1_DQSP_5 M_C_DQS_3_DP [17]
AR49 AV46 A43 H47
M_B_2_DQ_3 DDRB_DQ2_2/DDR0_DQ6_2/DDR0_DQ3_2 DDRB_DQSN_0/DDR0_DQSN_4/DDR0_DQSN_2 M_B_DQS_0_DN [16] M_D_2_DQ_3 DDRD_DQ2_2/DDR1_DQ6_2/DDR0_DQ7_2 DDRD_DQSN_0/DDR1_DQSN_4/DDR0_DQSN_6 M_D_DQS_0_DN [17]
AM45 AV47 C40 H46
M_B_2_DQ_4 DDRB_DQ2_3/DDR0_DQ6_3/DDR0_DQ3_3 DDRB_DQSP_0/DDR0_DQSP_4/DDR0_DQSP_2 M_B_DQS_0_DP [16] M_D_2_DQ_4 DDRD_DQ2_3/DDR1_DQ6_3/DDR0_DQ7_3 DDRD_DQSP_0/DDR1_DQSP_4/DDR0_DQSP_6 M_D_DQS_0_DP [17]
AR45 AY41 C43 G41
M_B_2_DQ_5 DDRB_DQ2_4/DDR0_DQ6_4/DDR0_DQ3_4 DDRB_DQSN_1/DDR0_DQSN_5/DDR1_DQSN_2 M_B_DQS_1_DN [16] M_D_2_DQ_5 DDRD_DQ2_4/DDR1_DQ6_4/DDR0_DQ7_4 DDRD_DQSN_1/DDR1_DQSN_5/DDR1_DQSN_6 M_D_DQS_1_DN [17]
AM47 BB41 D40 J41
M_B_2_DQ_6 DDRB_DQ2_5/DDR0_DQ6_5/DDR0_DQ3_5 DDRB_DQSP_1/DDR0_DQSP_5/DDR1_DQSP_2 M_B_DQS_1_DP [16] M_D_2_DQ_6 DDRD_DQ2_5/DDR1_DQ6_5/DDR0_DQ7_5 DDRD_DQSP_1/DDR1_DQSP_5/DDR1_DQSP_6 M_D_DQS_1_DP [17]
AM48 AN46 B40 C42
M_B_2_DQ_7 DDRB_DQ2_6/DDR0_DQ6_6/DDR0_DQ3_6 DDRB_DQSN_2/DDR0_DQSN_6/DDR0_DQSN_3 M_B_DQS_2_DN [16] M_D_2_DQ_7 DDRD_DQ2_6/DDR1_DQ6_6/DDR0_DQ7_6 DDRD_DQSN_2/DDR1_DQSN_6/DDR0_DQSN_7 M_D_DQS_2_DN [17]
AM49 AN47 A40 D42
[16] M_B_3_DQ_[7:0] M_B_3_DQ_0 DDRB_DQ2_7/DDR0_DQ6_7/DDR0_DQ3_7 DDRB_DQSP_2/DDR0_DQSP_6/DDR0_DQSP_3 M_B_DQS_2_DP [16] [17] M_D_3_DQ_[7:0] M_D_3_DQ_0 DDRD_DQ2_7/DDR1_DQ6_7/DDR0_DQ7_7 DDRD_DQSP_2/DDR1_DQSP_6/DDR0_DQSP_7 M_D_DQS_2_DP [17]
AT42 AR41 B35 D36
M_B_3_DQ_1 DDRB_DQ3_0/DDR0_DQ7_0/DDR1_DQ3_0 DDRB_DQSN_3/DDR0_DQSN_7/DDR1_DQSN_3 M_B_DQS_3_DN [16] M_D_3_DQ_1 DDRD_DQ3_0/DDR1_DQ7_0/DDR1_DQ7_0 DDRD_DQSN_3/DDR1_DQSN_7/DDR1_DQSN_7 M_D_DQS_3_DN [17]
AT39 AT41 D35 C36
M_B_3_DQ_2 DDRB_DQ3_1/DDR0_DQ7_1/DDR1_DQ3_1 DDRB_DQSP_3/DDR0_DQSP_7/DDR1_DQSP_3 M_B_DQS_3_DP [16] M_D_3_DQ_2 DDRD_DQ3_1/DDR1_DQ7_1/DDR1_DQ7_1 DDRD_DQSP_3/DDR1_DQSP_7/DDR1_DQSP_7 M_D_DQS_3_DP [17]
AR43 A35
M_B_3_DQ_3 AT38 DDRB_DQ3_2/DDR0_DQ7_2/DDR1_DQ3_2 BF39 M_D_3_DQ_3 D38 DDRD_DQ3_2/DDR1_DQ7_2/DDR1_DQ7_2 P38
M_B_3_DQ_4 AR38 DDRB_DQ3_3/DDR0_DQ7_3/DDR1_DQ3_3 NC/DDR0_PAR BE49 M_D_3_DQ_4 C35 DDRD_DQ3_3/DDR1_DQ7_3/DDR1_DQ7_3 NC/DDR1_PAR M48
M_B_3_DQ_5 AR39 DDRB_DQ3_4/DDR0_DQ7_4/DDR1_DQ3_4 NC/DDR0_ACT BD46 DDR0_ALERT# R1135 0 M_D_3_DQ_5 C38 DDRD_DQ3_4/DDR1_DQ7_4/DDR1_DQ7_4 NC/DDR1_ACT M49 DDR1_ALERT# R1136 0
B M_B_3_DQ_6 AR42 DDRB_DQ3_5/DDR0_DQ7_5/DDR1_DQ3_5 NC/DDR0_ALERT 0201S_P28-W35 M_D_3_DQ_6 B38 DDRD_DQ3_5/DDR1_DQ7_5/DDR1_DQ7_5 NC/DDR1_ALERT 0201S_P28-W35 B
M_B_3_DQ_7 AT43 DDRB_DQ3_6/DDR0_DQ7_6/DDR1_DQ3_6 M38 M_D_3_DQ_7 A38 DDRD_DQ3_6/DDR1_DQ7_6/DDR1_DQ7_6
DDRB_DQ3_7/DDR0_DQ7_7/DDR1_DQ3_7 RSVD_M38 C44 DDRD_DQ3_7/DDR1_DQ7_7/DDR1_DQ7_7
D47 DDR0_VREF_CA B45
E46 DDR_RCOMP_0 DDR1_VREF_CA M39 DDR_VTT_CTRL
C47 DDR_RCOMP_1 DDR_VTT_CTL DK47 M1042225-001
DDR_RCOMP_2 DRAM_RESET
DNP
R1117
M1042225-001 10K
0201S_P28-W35

+1P1V_DDR_VDD2

R1103 R1105 R1102

100 100 100 R1104
470

DRAM_RESET_N_R R1101
Use Seperated Via To GND 0
DRAM_RESET# [16,17]

A A

W x H 512 x 331 mm
<OrgName> Title: CPU(2)_LPDDR4
Engineer: <OrgAddr1>
Size Project Name Rev
Custom EDAN_A_EV1 1.00
Date: Tuesday, May 21, 2019 Sheet 11 of 82
5 4 3 2 1
 5 4 3 2 1

+VCCSTG_OUT +1P1V_DDR_VDD2
U1001M +1P1V_DDR_VDD2
13 OF 19
AA37 BP39
AG36 VDDQ_1 VDDQ_31 BR37
AJ36 VDDQ_2 VDDQ_32 BT38
AL36 VDDQ_3 VDDQ_33 AC35
D
C1204 AL49 VDDQ_4 VDDQ_34 BU37
D

1u 6.3V AN36 VDDQ_5 VDDQ_35 BU49

0201S_P35-W35 AP37 VDDQ_6 VDDQ_36 CA39
AR36 VDDQ_7 VDDQ_37 CB49
AR37 VDDQ_8 VDDQ_38 L38
AT36 VDDQ_9 VDDQ_39 L49
AT49 VDDQ_10 VDDQ_40 N36
AA49 VDDQ_11 VDDQ_41 T49
AV36 VDDQ_12 VDDQ_42 AC37
AW37 VDDQ_13 VDDQ_43 AD35
AY36 VDDQ_14 VDDQ_44 AD36
BA37 VDDQ_15 VDDQ_45 AE36
BA49 VDDQ_16 VDDQ_46 AF49
BB36 VDDQ_17 VDDQ_47
BD36 VDDQ_18
BE37 VDDQ_19
BF36 VDDQ_20 A33 VCCIN_AUX0_R TP1201 SP_TP_SMDP58
BF37 VDDQ_21 RSVD_2 B33 VCCIN_AUX1_R TP1202 SP_TP_SMDP58
AB36 VDDQ_22 RSVD_3 +VCC1P8A
BF49 VDDQ_23 BG9
BG36 VDDQ_24 VCC1P8A_1 BJ9
BJ36 VDDQ_25 VCC1P8A_2 BM9
BL37 VDDQ_26 VCC1P8A_3 BW1
BM49 VDDQ_27 VCC1P8A_4 BW2
BN37 VDDQ_28 VCC1P8A_5 +VCCSTG_OUT
+VCCSTG +VCCST_CPU BP38 VDDQ_29 R35
VDDQ_30 VCCSTG_OUT_R35 V34
C CB1 VCCSTG_OUT_V34 T34 C
VCCST VCCSTG_OUT_T34 U35
BY1 VCCSTG_OUT_U35 AB34 +VCC1.05_OUT_SFR
VCCSTG VCCSTG_OUT_AB34 W35
+VCCSTG_OUT RSVD_W35 AA35
RSVD_AA35 Y34
F33 RSVD_Y34
G33 VCCSTG_OUT_F33
VCCSTG_OUT_G33 CD2 +VCCPLL_OC
E5 VCCPLL
VCCSTG_OUT_LGC CG38
VCCPLL_OC_1 CG41
VCCPLL_OC_2 CG42
VCCPLL_OC_3 CG49
VCCPLL_OC_4
+VCCSTG_TERM AD7
VCCIO_OUT VCCIO_OUT [18]
+VCCSTG_OUT_LGC

R1201 M1042225-001
0 5%
1/10W
0603S_P6-W95

B B

+1P1V_DDR_VDD2
TOP SIDE +1P1V_DDR_VDD2
BOTTOM SIDE +1P1V_DDR_VDD2
TOP SIDE SOCKET
C1222 C1206 C1233 C1221
+1P1V_DDR_VDD2 1u 1u 1u 1u C1214 C1224 C1213 C1225 C1215
6.3V 6.3V 6.3V 6.3V 10u 10u 10u 10u 10u
C1211 C1220 C1228
22u 22u 22u 20% 20% 20% 20% 20% 20% 20% 20% 20%
0603 0603 0603 0201 0201 0201 0201 6.3V 6.3V 6.3V 6.3V 6.3V
0402 0402 0402 0402 0402
20% 20% 20%
DNP DNP DNP
C1218 C1238 C1207 C1208
10V 10V 10V
1u 1u 1u 1u
DNP
6.3V 6.3V 6.3V 6.3V
20% 20% 20% 20%
0201 0201 0201 0201

+VCCSTG
+VCCST_CPU +VCCSTG_OUT +VCCPLL_OC +VCC1.05_OUT_FET +VCC1P8A

A A

C1203 C1247 C1205 C1202

1u 1u 1u 1u 6.3V C1253 C1254 C1252 C1251
0201S_P35-W35 0201S_P35-W35 0201S_P35-W35 0201S_P35-W35 C1250 C1249 1u 1u 1u 1u C1248 C1201

W x H 437 x 328 mm
6.3V 6.3V 6.3V 1u 1u 0201S_P35-W35 0201S_P35-W35 0201S_P35-W35 0201S_P35-W35 10u 6.3V 22u
DNP DNP 0201S_P35-W35 0201S_P35-W35 6.3V 6.3V 6.3V 6.3V 0402S_P7-W70 0603S_1-W100
6.3V 6.3V DNP DNP 20% <OrgName> Title: CPU(3)_ICL_POWER1
DNP 10V DNP
Place close to U1001M Place close to U1001M
Engineer: <OrgAddr1>
Place close to U1001M Place close to U1001M Place close to U1001M Place close to U1001M
Size Project Name Rev
Custom EDAN_A_EV1 1.00
Date: Tuesday, May 21, 2019 Sheet 12 of 82
5 4 3 2 1
 5 4 3 2 1

+VCCIN BACKSIDE CAP

U1001L +VCCIN
12 OF 19 +VCCIN
A19 CJ35
AC12 VCCIN_1 VCCIN_52 CK10
V13 VCCIN_2 VCCIN_53 J32 C1322 C1301 C1325 C1310
W12 VCCIN_3 VCCIN_54 CL34 1u 1u 1u 1u
Y13 VCCIN_4 VCCIN_55 CL35
Place close as possible to A29
VCCIN_5 VCCIN_56 6.3V 6.3V 6.3V 6.3V
K29 CN34
K31 VCCIN_6 VCCIN_57 CN35 20% 20% 20% 20%
B19 VCCIN_7 VCCIN_58 CP33
VCCIN_8 VCCIN_59 0201 0201 0201 0201
B23 CR34
D B27 VCCIN_9 VCCIN_60 A29 D
B29 VCCIN_10 VCCIN_61 CR35
BN10 VCCIN_11 VCCIN_62 CT33
BP11 VCCIN_12 VCCIN_63 CT34
BP9 VCCIN_13 VCCIN_64 CT35
BR10 VCCIN_14 VCCIN_65 CU33
BT11 VCCIN_15 VCCIN_66 D19
A21 VCCIN_16 VCCIN_67 D21
BT9 VCCIN_17 VCCIN_68 D23
BU10 VCCIN_18 VCCIN_69 D24
BV36 VCCIN_19 VCCIN_70 D27
BV9 VCCIN_20 VCCIN_71 AA12
BW10 VCCIN_21 VCCIN_72 D29
BW36 VCCIN_22 VCCIN_73 F19
BW9 VCCIN_23 VCCIN_74 F21
BY10 VCCIN_24 VCCIN_75 F23
C19 VCCIN_25 VCCIN_76 F24
PRIMARY SIDE
C23 VCCIN_26 VCCIN_77 F27
A23 VCCIN_27 VCCIN_78 F29 +VCCIN
C27 VCCIN_28 VCCIN_79 G1
C29 VCCIN_29 VCCIN_80 G19
CA36 VCCIN_30 VCCIN_81 G23
CA9 VCCIN_31 VCCIN_82 AB1
CB10 VCCIN_32 VCCIN_83 G27
CC11 VCCIN_33 VCCIN_84 G29
CC36 VCCIN_34 VCCIN_85 H19
CC9 VCCIN_35 VCCIN_86 H23
CD10 VCCIN_36 VCCIN_87 H27
CE11 VCCIN_37 VCCIN_88 H29
A24 VCCIN_38 VCCIN_89 J18 C1320 C1311 C1321 C1318
TODO: Update rail CE34 VCCIN_39 VCCIN_90 J20 22u 22u 22u 22u
CE35 VCCIN_40 VCCIN_91 J22
VCCIN_41 VCCIN_92 0603 0603 0603 0603
CF10 J23
+VCCST_CPU CF33 VCCIN_42 VCCIN_93 AB13 20% 20% 20% 20%
C CG11 VCCIN_43 VCCIN_94 J26 C
VCCIN_44 VCCIN_95 10V 10V 10V 10V
CG34 J28
CG35 VCCIN_45 VCCIN_96 K17
CH10 VCCIN_46 VCCIN_97 K19
0201S_P28-W35

0201S_P28-W35

VCCIN_47 VCCIN_98
56
100

J30 K21 C1313 C1323 C1326 C1303 C1314 C1307

CJ11 VCCIN_48 VCCIN_99 K23 22u 22u 22u 22u 22u 22u
A27 VCCIN_49 VCCIN_100 K24
VCCIN_50 VCCIN_101 0603 0603 0603 0603 0603 0603
CJ34 K27
VCCIN_51 VCCIN_102 M1 20% 20% 20% 20% 20% 20%
R1304

R1303

VCCIN_103 U1
H_CPU_SVIDALERT# H1 VCCIN_104 10V 10V 10V 10V 10V 10V
0201S_P28-W35 0 R1302
[66] SVID_ALERT# H_CPU_SVIDCLK VIDALERT
0201S_P28-W35 0 R1305 H2 F17
[66] VIDSCLK H_CPU_SVIDDAT VIDSCK VCCIN_SENSE VCCIN_VIN_SENSE [66]
0201S_P28-W35 0 R1301 H3 G17
[66] VIDSOUT VIDSOUT VSSIN_SENSE VCCIN_VSS_SENSE [66]

C1316 C1309 C1324

M1042225-001 22u 22u 22u
SP_TP_SMDP58 TP1303
0603 0603 0603
20% 20% 20%
10V 10V 10V

C1327 C1306
22u 22u
0603 0603
20% 20%
10V 10V
B B

C1364 C1360
22u 22u
0603 0603
20% 20%
10V 10V
DNP DNP

A A

W x H 512 x 331 mm
<OrgName> Title: CPU(4)_ICL_POWER2
Engineer: <OrgAddr1>
Size Project Name Rev
Custom EDAN_A_EV1 1.00
Date: Tuesday, May 21, 2019 Sheet 13 of 82
5 4 3 2 1
 5 4 3 2 1

U1001P U1001Q
U1001O
16 OF 19 17 OF 19
15 OF 19 BT3 CR37 DJ33 F11
A11 AF45 BT39 VSS_149 VSS_223 CR45 DJ36 VSS_297 VSS_362 F31
A46 VSS_1 VSS_75 AF47 BT41 VSS_150 VSS_224 CR49 DJ42 VSS_298 VSS_363 F45
BA45 VSS_2 VSS_76 AG1 BT42 VSS_151 VSS_225 CT37 DK3 VSS_299 VSS_364 F47
BA47 VSS_3 VSS_77 AG11 BT43 VSS_152 VSS_226 CT39 DK4 VSS_300 VSS_365 F8
BB11 VSS_4 VSS_78 AG3 BT7 VSS_153 VSS_227 CT42 DK49 VSS_301 VSS_366 G21
BB3 VSS_5 VSS_79 AG38 BU45 VSS_154 VSS_228 CT9 DK6 VSS_302 VSS_367 G24
D BB7 VSS_6 VSS_80 AG39 BU47 VSS_155 VSS_229 CU45 DK8 VSS_303 VSS_368 G3 D
BC37 VSS_7 VSS_81 AG41 BV1 VSS_156 VSS_230 CU47 DL10 VSS_304 VSS_369 G31
BD3 VSS_8 VSS_82 A31 BV11 VSS_157 VSS_231 CU49 DL13 VSS_305 VSS_370 G36
BD38 VSS_9 VSS_83 AG42 BV2 VSS_158 VSS_232 CV3 DL44 VSS_306 VSS_371 G49
BD39 VSS_10 VSS_84 AG43 BV3 VSS_159 VSS_233 CV34 DL47 VSS_307 VSS_372 G5
BD41 VSS_11 VSS_85 AG5 BV7 VSS_160 VSS_234 CV35 DM47 VSS_308 VSS_373 H17
A48 VSS_12 VSS_86 AG9 BW3 VSS_161 VSS_235 CV5 DN15 VSS_309 VSS_374 H21
BD42 VSS_13 VSS_87 AH2 BW37 VSS_162 VSS_236 CV9 DN19 VSS_310 VSS_375 H24
BD43 VSS_14 VSS_88 AH37 BW5 VSS_163 VSS_237 CY41 DN24 VSS_311 VSS_376 H31
BD45 VSS_15 VSS_89 AH45 BW6 VSS_164 VSS_238 CY45 DN31 VSS_312 VSS_377 H33
BD49 VSS_16 VSS_90 AH49 BW7 VSS_165 VSS_239 CY49 DN36 VSS_313 VSS_378 H36
BD5 VSS_17 VSS_91 AJ2 BY37 VSS_166 VSS_240 CY9 DN42 VSS_314 VSS_379 H45
BD6 VSS_18 VSS_92 AJ3 BY45 VSS_167 VSS_241 D13 DP45 VSS_315 VSS_380 H49
BD7 VSS_19 VSS_93 A34 BY49 VSS_168 VSS_242 D17 DR49 VSS_316 VSS_381 J10
BE1 VSS_20 VSS_94 AK37 C11 VSS_169 VSS_243 D31 DT1 VSS_317 VSS_382 J13
BE2 VSS_21 VSS_95 AL2 C13 VSS_170 VSS_244 D44 DT10 VSS_318 VSS_383 J16
BF3 VSS_22 VSS_96 AL45 C14 VSS_171 VSS_245 D49 DT15 VSS_319 VSS_384 J36
A49 VSS_23 VSS_97 AL47 C17 VSS_172 VSS_246 DA10 DT20 VSS_320 VSS_385 J6
BF45 VSS_24 VSS_98 AL6 C21 VSS_173 VSS_247 DA33 DT27 VSS_321 VSS_386 K11
BF47 VSS_25 VSS_99 AM2 C24 VSS_174 VSS_248 DA9 DT3 VSS_322 VSS_387 K33
BF7 VSS_26 VSS_100 AM37 C31 VSS_175 VSS_249 DB32 DT32 VSS_323 VSS_388 K8
BG3 VSS_27 VSS_101 AN2 C34 VSS_176 VSS_250 DB35 DT37 VSS_324 VSS_389 L36
C VSS_28 VSS_102 VSS_177 VSS_251 VSS_325 VSS_390 C
BG41 AN38 C39 DB38 DT42 L39
BG7 VSS_29 VSS_103 AN39 C48 VSS_178 VSS_252 DB45 DT49 VSS_326 VSS_391 L41
BH37 VSS_30 VSS_104 A36 C49 VSS_179 VSS_253 DB47 DT6 VSS_327 VSS_392 L42
BJ1 VSS_31 VSS_105 AN41 C6 VSS_180 VSS_254 DB49 DT7 VSS_328 VSS_393 L43
BJ2 VSS_32 VSS_106 AN42 CA3 VSS_181 VSS_255 DC3 DT8 VSS_329 VSS_394 L45
BJ3 VSS_33 VSS_107 AN43 CA38 VSS_182 VSS_256 DC49 DU1 VSS_330 VSS_395 L47
AA45 VSS_34 VSS_108 AN45 CA41 VSS_183 VSS_257 DC5 DU10 VSS_331 VSS_396 M10
BJ41 VSS_35 VSS_109 AN49 CA42 VSS_184 VSS_258 DC6 DU15 VSS_332 VSS_397 M3
BJ43 VSS_36 VSS_110 AN6 CA43 VSS_185 VSS_259 DD37 DU2 VSS_333 VSS_398 M36
BJ45 VSS_37 VSS_111 AR1 CA7 VSS_186 VSS_260 DD42 DU20 VSS_334 VSS_399 M5
BJ49 VSS_38 VSS_112 AR11 CB37 VSS_187 VSS_261 DE10 DU27 VSS_335 VSS_400 N45
BJ7 VSS_39 VSS_113 AR2 CB45 VSS_188 VSS_262 DE13 DU32 VSS_336 VSS_401 N49
BM11 VSS_40 VSS_114 AR3 CB47 VSS_189 VSS_263 DE17 DU37 VSS_337 VSS_402 P11
BM3 VSS_41 VSS_115 A39 CC3 VSS_190 VSS_264 DE18 DU48 VSS_338 VSS_403 P41
BM45 VSS_42 VSS_116 AR7 CC7 VSS_191 VSS_265 DE20 DU49 VSS_339 VSS_404 P8
BM47 VSS_43 VSS_117 AR9 CE37 VSS_192 VSS_266 DE22 DU7 VSS_340 VSS_405 R3
BM5 VSS_44 VSS_118 AT3 CE45 VSS_193 VSS_267 DE23 DV2 VSS_341 VSS_406 R37
AA47 VSS_45 VSS_119 AT45 CE49 VSS_194 VSS_268 DE26 DV44 VSS_342 VSS_407 T11
BM6 VSS_46 VSS_120 AT47 CE9 VSS_195 VSS_269 DE28 DV48 VSS_343 VSS_408 T36
BM7 VSS_47 VSS_121 AT5 CG37 VSS_196 VSS_270 DE29 DV8 VSS_344 VSS_409 T41
BP1 VSS_48 VSS_122 AT6 CG39 VSS_197 VSS_271 DE33 DW1 VSS_345 VSS_410 T43
B BP2 VSS_49 VSS_123 AT7 CG43 VSS_198 VSS_272 DE45 DW10 VSS_346 VSS_411 T45 B
BP3 VSS_50 VSS_124 AU37 CG45 VSS_199 VSS_273 DE6 DW2 VSS_347 VSS_412 T47
BP43 VSS_51 VSS_125 AV11 CG47 VSS_200 VSS_274 DF13 DW20 VSS_348 VSS_413 U3
BP7 VSS_52 VSS_126 A42 CG9 VSS_201 VSS_275 DF22 DW27 VSS_349 VSS_414 U37
BR45 VSS_53 VSS_127 AV3 CH3 VSS_202 VSS_276 DF28 DW44 VSS_350 VSS_415 U5
BR49 VSS_54 VSS_128 AV38 CH5 VSS_203 VSS_277 DF33 DW46 VSS_351 VSS_416 V11
AB11 VSS_55 VSS_129 AV39 CJ37 VSS_204 VSS_278 DF35 DW48 VSS_352 VSS_417 V36
AB3 VSS_56 VSS_130 AV41 CJ42 VSS_205 VSS_279 DF39 DW49 VSS_353 VSS_418 V45
AB38 VSS_57 VSS_131 AV42 CJ9 VSS_206 VSS_280 DG10 DW7 VSS_354 VSS_419 V49
AB39 VSS_58 VSS_132 AV43 CK45 VSS_207 VSS_281 DG12 E11 VSS_355 VSS_420 V9
AB41 VSS_59 VSS_133 AV45 CK49 VSS_208 VSS_282 DG13 E34 VSS_356 VSS_421 W37
A17 VSS_60 VSS_134 AV49 CK9 VSS_209 VSS_283 DG15 E36 VSS_357 VSS_422 Y36
AB42 VSS_61 VSS_135 AV7 CL37 VSS_210 VSS_284 DG22 E39 VSS_358 VSS_423 Y38
AB43 VSS_62 VSS_136 AY3 CL42 VSS_211 VSS_285 DG23 E42 VSS_359 VSS_424 Y43
AB5 VSS_63 VSS_137 A44 CL49 VSS_212 VSS_286 DG47 E6 VSS_360 VSS_425 Y9
AB6 VSS_64 VSS_138 AY7 CM45 VSS_213 VSS_287 DG6 VSS_361 VSS_426 DE15
AC45 VSS_65 VSS_139 B17 CM47 VSS_214 VSS_288 DH1 VSS_427
AC49 VSS_66 VSS_140 B2 CM9 VSS_215 VSS_289 DH3
AD10 VSS_67 VSS_141 B21 CN3 VSS_216 VSS_290 DH45
AD11 VSS_68 VSS_142 B24 CN37 VSS_217 VSS_291 DH5 M1042225-001
AD34 VSS_69 VSS_143 B3 CN39 VSS_218 VSS_292 DJ19
AD37 VSS_70 VSS_144 B31 CN5 VSS_219 VSS_293 DJ21
A
A3 VSS_71 VSS_145 B48 CP9 VSS_220 VSS_294 DJ27
A

AE6 VSS_72 VSS_146 BA1 CR32 VSS_221 VSS_295 DJ31

W x H 347 x 225 mm
AF37 VSS_73 VSS_147 BA2 VSS_222 VSS_296
VSS_74 VSS_148 <OrgName> Title: CPU(5)_GND
M1042225-001
M1042225-001 Engineer: <OrgAddr1>
Size Project Name Rev
Custom EDAN_A_EV1 1.00
Date: Tuesday, May 21, 2019 Sheet 14 of 82
5 4 3 2 1
 5 4 3 2 1

CFG4 TP1516
0 Default enable eDP U1001S

1 Disable eDP 19 OF 19
AG6 A47
[18] CFG0 CFG_0 RSVD_TP_1
AE7 B47
[18] CFG1 CFG_1 RSVD_TP_2
AG7
[18] CFG2 CFG_2
AD9 C1
[18] CFG3 CFG_3 RSVD_60
AE9 E1
[18] CFG4 CFG_4 RSVD_61
D AB9 D
[18] CFG5 CFG_5
AJ6 CT32
[18] CFG6 CFG_6 RSVD_TP_CT32 U1001R
AB7 CV32
[18] CFG7 CFG_7 RSVD_TP_CV32
TP1519 CFG8 V10 18 OF 19
TP1520 CFG9 AJ5 CFG_8 G15 N34 DA11
TP1521 CFG10 Y10 CFG_9 RSVD_G15 F15 AK10 RSVD_TP_N34 RSVD_TP_DA11 CL32
AJ7 CFG_10 RSVD_F15 BT36 RSVD_TP_AK10 RSVD_TP_CL32 CN32
AB10 CFG_11 BW11 AH10 RSVD_7 RSVD_TP_CN32 CY35
AL7 CFG_12 RSVD_TP_BW11 CA11 BC10 RSVD_TP_AH10 RSVD_32 DB37
AL9 CFG_13 RSVD_TP_CA11 CH33 RSVD_TP_BC10 RSVD_33 DF37
AJ9 CFG_14 C16 RSVD_TP_CH33 RSVD_34
CFG_15 VSS_428 A16 CJ32 BF11
CFG16 V6 VSS_429 AM10 RSVD_12 IST_TP_0 BD11
V7 CFG_16 C2 TP1501 FIVR_VLOAD_TCSS BH10 RSVD_TP_AM10 IST_TP_1 BE10
[18] CFG17 CFG_17 RSVD_58 RSVD_TP_BH10 IST_TRIG_0
A4 J34 BF10
CFG18 Y6 RSVD_59 RSVD_TP_J34 IST_TRIG_1
Y7 CFG_18 DP5 Y11 CW33
CFG_19 RSVD_71 DR5 L34 RSVD_9 PCH_IST_TP0 CY32
R1507 49.9 CFG_RCOMP AD6 RSVD_72 RSVD_10 PCH_IST_TP1
0201S_P28-W35 CFG_RCOMP D14 AJ11 CY37
TP1528 BPM_N_0 T9 RSVD_65 E16 CG32 RSVD_17 RSVD_27 CV37
TP1529 BPM_N_1 T7 BPM_N_0 RSVD_66 RSVD_21 RSVD_28
T10 BPM_N_1 DV6
T6 BPM_N_2 RSVD_TP_DV6 DW6 CK33 C33
C C
BPM_N_3 RSVD_TP_DW6 BP41 RSVD_22 VCCIN_AUX_OUT G34
BPM_N_2 BJ11 DP2 AL11 RSVD_20 RSVD_35 H34
SP_TP_SMDP58 TP1518 BPM_N_3 BL10 RSVD_68 RSVD_TP_DP2 DP1 BG11 RSVD_23 RSVD_46 DJ34
SP_TP_SMDP58 TP1514 RSVD_69 RSVD_TP_DP1 AN11 RSVD_24 RSVD_48 DK31
AV1 DW4 M13 RSVD_16 RSVD_49 DK15
Place outside of thermal module RSVD_TP_AV1 RSVD_TP_DW4 DV4 M34 RSVD_18 RSVD_50 CP3
AT2 RSVD_TP_DV4 RSVD_19 RSVD_51 CP5
AT1 RSVD_TP_AT2 CM33 RSVD_52 AN9
AU1 RSVD_TP_AT1 TP_3 DB10 RSVD_53 AN7
AU2 RSVD_TP_AU1 TP_4 RSVD_54 AF10
RSVD_TP_AU2 R1 DU42 RSVD_36 AE11
AV2 RSVD_TP_R1 DW42 RSVD_42 RSVD_37 H5
RSVD_TP_AV2 DW3 D33 RSVD_43 RSVD_38 D1
DP3 RSVD_TP_DW3 DV3 L13 RSVD_44 RSVD_39 DJ40
DT2 RSVD_83 RSVD_TP_DV3 K13 RSVD_45 RSVD_40 DK40
RSVD_84 DH49 RSVD_47 RSVD_41
AR10 RSVD_TP_DH49
AP10 RSVD_85 DL8 M1042225-001
BP36 RSVD_87 RSVD_TP_DL8
BM36 RSVD_86 DW47
RSVD_88 TP_1 DV47
J15 TP_2 DU47 CFG16
B K15 VSS_430 VSS_432 CFG18 B
VSS_431 P10 CFG4
RSVD_TP_P10

49.9

49.9
C5
D4 SKTOCC
A5 RSVD_D4
RSVD_70

R1503

R1504
R1501
R1502 1K
0 0201S_P28-W35
M1042225-001

A A

W x H 367 x 237 mm
<OrgName> Title: CPU(6)_CFG,RESERVED
Engineer: <OrgAddr1>
Size Project Name Rev
Custom EDAN_A_EV1 1.00
Date: Tuesday, May 21, 2019 Sheet 15 of 82
5 4 3 2 1
 5 4 3 2 1

[11] M_A_2_DQ_[7:0] U1601

M_A_2_DQ_4 M_A_0_DQ_1 M_A_0_DQ_[7:0] [11]
B2 AA2 U1602
M_A_2_DQ_1 DQ0_A DQ0_B M_A_0_DQ_0 [11] M_B_2_DQ_[7:0] M_B_2_DQ_4 M_B_1_DQ_5 M_B_1_DQ_[7:0] [11]
C2 Y2 B2 AA2
M_A_2_DQ_7 E2 DQ1_A DQ1_B V2 M_A_0_DQ_2 M_B_2_DQ_1 C2 DQ0_A DQ0_B Y2 M_B_1_DQ_6
M_A_2_DQ_6 F2 DQ2_A DQ2_B U2 M_A_0_DQ_7 M_B_2_DQ_6 E2 DQ1_A DQ1_B V2 M_B_1_DQ_0
M_A_2_DQ_3 F4 DQ3_A DQ3_B U4 M_A_0_DQ_3 M_B_2_DQ_5 F2 DQ2_A DQ2_B U2 M_B_1_DQ_2
M_A_2_DQ_5 E4 DQ4_A DQ4_B V4 M_A_0_DQ_5 M_B_2_DQ_7 F4 DQ3_A DQ3_B U4 M_B_1_DQ_1
M_A_2_DQ_2 C4 DQ5_A DQ5_B Y4 M_A_0_DQ_4 M_B_2_DQ_3 E4 DQ4_A DQ4_B V4 M_B_1_DQ_4
M_A_2_DQ_0 B4 DQ6_A DQ6_B AA4 M_A_0_DQ_6 M_B_2_DQ_2 C4 DQ5_A DQ5_B Y4 M_B_1_DQ_7
[11] M_A_3_DQ_[7:0] M_A_3_DQ_2 DQ7_A DQ7_B M_A_1_DQ_7 M_A_1_DQ_[7:0] [11] M_B_2_DQ_0 DQ6_A DQ6_B M_B_1_DQ_3
B11 AA11 B4 AA4
M_A_3_DQ_0 C11 DQ8_A DQ8_B Y11 M_A_1_DQ_3 [11] M_B_3_DQ_[7:0] M_B_3_DQ_2 B11 DQ7_A DQ7_B AA11 M_B_0_DQ_4 M_B_0_DQ_[7:0] [11]
D M_A_3_DQ_1 E11 DQ9_A DQ9_B V11 M_A_1_DQ_2 M_B_3_DQ_6 C11 DQ8_A DQ8_B Y11 M_B_0_DQ_1 D
M_A_3_DQ_4 F11 DQ10_A DQ10_B U11 M_A_1_DQ_0 M_B_3_DQ_5 E11 DQ9_A DQ9_B V11 M_B_0_DQ_6
M_A_3_DQ_3 F9 DQ11_A DQ11_B U9 M_A_1_DQ_4 M_B_3_DQ_4 F11 DQ10_A DQ10_B U11 M_B_0_DQ_5
M_A_3_DQ_5 E9 DQ12_A DQ12_B V9 M_A_1_DQ_1 M_B_3_DQ_3 F9 DQ11_A DQ11_B U9 M_B_0_DQ_7
M_A_3_DQ_6 C9 DQ13_A DQ13_B Y9 M_A_1_DQ_6 M_B_3_DQ_1 E9 DQ12_A DQ12_B V9 M_B_0_DQ_3
+0P6V_DDR_VDDQ M_A_3_DQ_7 B9 DQ14_A DQ14_B AA9 M_A_1_DQ_5 M_B_3_DQ_0 C9 DQ13_A DQ13_B Y9 M_B_0_DQ_2
DQ15_A DQ15_B +0P6V_DDR_VDDQ M_B_3_DQ_7 B9 DQ14_A DQ14_B AA9 M_B_0_DQ_0
DQ15_A DQ15_B
1%

D3 W3
1%

[11] M_A_DQS_2_DP DQS0_A_t DQS0_B_t M_A_DQS_0_DP [11]

240

240

E3 V3

1%
D3 W3

1%
[11] M_A_DQS_2_DN DQS0_A_c DQS0_B_c M_A_DQS_0_DN [11] [11] M_B_DQS_2_DP DQS0_A_t DQS0_B_t M_B_DQS_1_DP [11]

240

240
E3 V3
[11] M_B_DQS_2_DN DQS0_A_c DQS0_B_c M_B_DQS_1_DN [11]
D10 W10
[11] M_A_DQS_3_DP DQS1_A_t DQS1_B_t M_A_DQS_1_DP [11]
R1602

R1601

E10 V10 D10 W10

[11] M_A_DQS_3_DN DQS1_A_c DQS1_B_c M_A_DQS_1_DN [11] [11] M_B_DQS_3_DP DQS1_A_t DQS1_B_t M_B_DQS_0_DP [11]

R1603

R1604
E10 V10
C3
DMI0_A DMI0_B
Y3
[11] M_B_DQS_3_DN DQS1_A_c DQS1_B_c M_B_DQS_0_DN [11] VDD2 Decoupling
GND C10 Y10 GND C3 Y3 Performance Scheme, except 0402 10uF, 0201 1uF
DMI1_A DMI1_B C10 DMI0_A DMI0_B Y10
GND DMI1_A DMI1_B GND
ZQ0_1601 A5 DRAM_RESET#
ZQ1_1601 ZQ0 DRAM_RESET# [11,17] ZQ0_1602 DRAM_RESET# +1P1V_DDR_VDD2
A8 T11 A5
NC/ZQ1 RESET_n C1615 0.1u ZQ1_1602 A8 ZQ0 T11 Evenly distributed
GND NC/ZQ1 RESET_n
DNP 10V C1608 0.1u GND
across all 4 DRAMs
J4 P4 M_A_LP4_CKE0 DNP 10V

0402S_P7-W70

0402S_P7-W70

0402S_P7-W70

0402S_P7-W70

0402S_P7-W70
[11] M_A_LP4_CKE0 CKE0_A CKE0_B
J5 P5 M_A_LP4_CKE1 J4 P4 M_B_LP4_CKE0 C1613 C1631 C1618 C1605 C1630
[11] M_A_LP4_CKE1 NC/CKE1_A CKE1_B/NC [11] M_B_LP4_CKE0 CKE0_A CKE0_B
J5 P5 M_B_LP4_CKE1 10u 10u 10u 10u 10u
[11] M_B_LP4_CKE1 NC/CKE1_A CKE1_B/NC
H4 R4 M_A_LP4_CS#0 6.3V 6.3V 6.3V 6.3V 6.3V
[11] M_A_LP4_CS#0 CS0_A CS0_B
H3 R3 M_A_LP4_CS#1 H4 R4 M_B_LP4_CS#0
[11] M_A_LP4_CS#1 NC/CS1_A CS1_B/NC [11] M_B_LP4_CS#0 CS0_A CS0_B
H3 R3 M_B_LP4_CS#1
[11] M_B_LP4_CS#1 NC/CS1_A CS1_B/NC
J8 P8 M_A_LP4_CLK_P
[11] M_A_LP4_CLK_P CK_A_t CK_B_t
J9 P9 M_A_LP4_CLK_N J8 P8 M_B_LP4_CLK_P GND
[11] M_A_LP4_CLK_N CK_A_c CK_B_c [11] M_B_LP4_CLK_P CK_A_t CK_B_t
J9 P9 M_B_LP4_CLK_N
[11] M_B_LP4_CLK_N CK_A_c CK_B_c +1P1V_DDR_VDD2 +1P1V_DDR_VDD2
[11] M_A_CA[5:0] 6 caps per DRAM, 2 per long 6 caps per DRAM, 2 per long
M_A_CA0 H2 R2 M_A_CA0 edge, 1 per short edge edge, 1 per short edge
CA0_A CA0_B [11] M_B_CA[5:0]
M_A_CA1 J2 P2 M_A_CA1 M_B_CA0 H2 R2 M_B_CA0
M_A_CA2 H9 CA1_A CA1_B R9 M_A_CA2 M_B_CA1 J2 CA0_A CA0_B P2 M_B_CA1
M_A_CA3 H10 CA2_A CA2_B R10 M_A_CA3 M_B_CA2 H9 CA1_A CA1_B R9 M_B_CA2 C1614 C1612 C1640 C1623 C1643 C1619 C1645 C1636 C1611 C1610 C1626 C1602
M_A_CA4 H11 CA3_A CA3_B R11 M_A_CA4 +1P1V_DDR_VDD2 M_B_CA3 H10 CA2_A CA2_B R10 M_B_CA3 1u 1u 1u 1u 1u 1u 1u 1u 1u 1u 1u 1u
+1P1V_DDR_VDD2 M_A_CA5 J11 CA4_A CA4_B P11 M_A_CA5 M_B_CA4 H11 CA3_A CA3_B R11 M_B_CA4 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 10V
C CA5_A CA5_B +1P1V_DDR_VDD2 M_B_CA5 J11 CA4_A CA4_B P11 M_B_CA5 +1P1V_DDR_VDD2 C
R1606 0 G2 T2 R1605 0 CA5_A CA5_B
ODT_CA_A ODT_CA_B R1607 0 G2 T2 R1608 0
ODT_CA_A ODT_CA_B
GND GND
A1
A2 DNU_A1 N5 A1
A11 DNU_A2 NC_N5 N8 A2 DNU_A1 N5
LPDDR4X ODT_CA is not used. A12 DNU_A11
DNU_A12
NC_N8
DNU_AA1
AA1 A11 DNU_A2
DNU_A11
NC_N5
NC_N8
N8 VDDQ Decoupling
B1 AA12 A12 AA1 Performance Scheme, except 0402 10uF, 0201 1uF
B12 DNU_B1 DNU_AA12 AB1 B1 DNU_A12 DNU_AA1 AA12 +0P6V_DDR_VDDQ
G11 DNU_B12 DNU_AB1 AB2 B12 DNU_B1 DNU_AA12 AB1 Evenly distributed
K5 NC_G11 DNU_AB2 AB11 G11 DNU_B12 DNU_AB1 AB2 across all 4 DRAMs
K8 NC_K5 DNU_AB11 AB12 K5 NC_G11 DNU_AB2 AB11

0402S_P7-W70

0402S_P7-W70

0402S_P7-W70

0402S_P7-W70

0402S_P7-W70
NC_K8 DNU_AB12 K8 NC_K5 DNU_AB11 AB12 C1620 C1634 C1627 C1616 C1638
NC_K8 DNU_AB12 10u 10u 10u 10u 10u
+1P8V_DDR_VDD1 F1 T4 +1P8V_DDR_VDD1
6.3V 6.3V 6.3V 6.3V 6.3V
F12 VDD1_F1 VDD1_T4 T9 F1 T4
VDD1_F12 VDD1_T9 +1P8V_DDR_VDD1 VDD1_F1 VDD1_T4 +1P8V_DDR_VDD1
G4 U1 F12 T9
G9 VDD1_G4 VDD1_U1 U12 G4 VDD1_F12 VDD1_T9 U1
VDD1_G9 VDD1_U12 G9 VDD1_G4 VDD1_U1 U12
VDD1_G9 VDD1_U12
GND
A4 N1
+1P1V_DDR_VDD2 VDD2_A4 VDD2_N1 +1P1V_DDR_VDD2
A9 N3 +1P1V_DDR_VDD2 A4 N1 +1P1V_DDR_VDD2
F5 VDD2_A9 VDD2_N3 N10 A9 VDD2_A4 VDD2_N1 N3
F8 VDD2_F5 VDD2_N10 N12 F5 VDD2_A9 VDD2_N3 N10 +0P6V_DDR_VDDQ +0P6V_DDR_VDDQ
H1 VDD2_F8 VDD2_N12 R1 F8 VDD2_F5 VDD2_N10 N12 4 caps per DRAM, 2 per long 4 caps per DRAM, 2 per long
H5 VDD2_H1 VDD2_R1 R5 H1 VDD2_F8 VDD2_N12 R1 edge, 1 per short edge edge, 1 per short edge
H8 VDD2_H5 VDD2_R5 R8 H5 VDD2_H1 VDD2_R1 R5
H12 VDD2_H8 VDD2_R8 R12 H8 VDD2_H5 VDD2_R5 R8 C1606 C1639 C1633 C1607 C1628 C1642 C1624 C1629
K1 VDD2_H12 VDD2_R12 U5 H12 VDD2_H8 VDD2_R8 R12 1u 1u 1u 1u 1u 1u 1u 1u
K3 VDD2_K1 VDD2_U5 U8 K1 VDD2_H12 VDD2_R12 U5 10V 10V 10V 10V 10V 10V 10V 10V
K10 VDD2_K3 VDD2_U8 AB4 K3 VDD2_K1 VDD2_U5 U8
K12 VDD2_K10 VDD2_AB4 AB9 K10 VDD2_K3 VDD2_U8 AB4
VDD2_K12 VDD2_AB9 K12 VDD2_K10 VDD2_AB4 AB9
VDD2_K12 VDD2_AB9
GND GND
+0P6V_DDR_VDDQ B3 U3 +0P6V_DDR_VDDQ
B5 VDDQ_B3 VDDQ_U3 U10 B3 U3
VDDQ_B5 VDDQ_U10 +0P6V_DDR_VDDQ VDDQ_B3 VDDQ_U3 +0P6V_DDR_VDDQ
B
B8
B10 VDDQ_B8 VDDQ_W1
W1
W5
B5
B8 VDDQ_B5 VDDQ_U10
U10
W1
VDD1 Decoupling B

D1 VDDQ_B10 VDDQ_W5 W8 B10 VDDQ_B8 VDDQ_W1 W5 Performance Scheme, except 0402 10uF, 0201 1uF
D5 VDDQ_D1 VDDQ_W8 W12 D1 VDDQ_B10 VDDQ_W5 W8 +1P8V_DDR_VDD1
D8 VDDQ_D5 VDDQ_W12 AA3 D5 VDDQ_D1 VDDQ_W8 W12 Evenly distributed
D12 VDDQ_D8 VDDQ_AA3 AA5 D8 VDDQ_D5 VDDQ_W12 AA3 across all 4 DRAMs
F3 VDDQ_D12 VDDQ_AA5 AA8 D12 VDDQ_D8 VDDQ_AA3 AA5

0402S_P7-W70

0402S_P7-W70

0402S_P7-W70

0402S_P7-W70

0402S_P7-W70
F10 VDDQ_F3 VDDQ_AA8 AA10 F3 VDDQ_D12 VDDQ_AA5 AA8 C1632 C1609 C1617 C1635 C1644
VDDQ_F10 VDDQ_AA10 F10 VDDQ_F3 VDDQ_AA8 AA10 10u 10u 10u 10u 10u
VDDQ_F10 VDDQ_AA10 6.3V 6.3V 6.3V 6.3V 6.3V
N2
VSS_N2 N4 N2
A10 VSS_N4 N9 VSS_N2 N4
A3 VSS_A10 VSS_N9 N11 A10 VSS_N4 N9
C1 VSS_A3 VSS_N11 P1 A3 VSS_A10 VSS_N9 N11
VSS_C1 VSS_P1 VSS_A3 VSS_N11 GND
C12 P3 C1 P1
C5 VSS_C12 VSS_P3 P10 C12 VSS_C1 VSS_P1 P3
C8 VSS_C5 VSS_P10 P12 C5 VSS_C12 VSS_P3 P10
D11 VSS_C8 VSS_P12 T1 C8 VSS_C5 VSS_P10 P12 +1P8V_DDR_VDD1 +1P8V_DDR_VDD1
D2 VSS_D11 VSS_T1 T3 D11 VSS_C8 VSS_P12 T1
4 caps per DRAM, 2 per long 4 caps per DRAM, 2 per long
D4 VSS_D2 VSS_T3 T5 D2 VSS_D11 VSS_T1 T3 edge, 1 per short edge edge, 1 per short edge
D9 VSS_D4 VSS_T5 T8 D4 VSS_D2 VSS_T3 T5
E1 VSS_D9 VSS_T8 T10 D9 VSS_D4 VSS_T5 T8 C1603 C1637 C1625 C1604 C1621 C1641 C1622 C1601
E12 VSS_E1 VSS_T10 T12 E1 VSS_D9 VSS_T8 T10 1u 1u 1u 1u 1u 1u 1u 1u
E5 VSS_E12 VSS_T12 V1 E12 VSS_E1 VSS_T10 T12 10V 10V 10V 10V 10V 10V 10V 10V
E8 VSS_E5 VSS_V1 V5 E5 VSS_E12 VSS_T12 V1
G12 VSS_E8 VSS_V5 V8 E8 VSS_E5 VSS_V1 V5
G1 VSS_G12 VSS_V8 V12 G12 VSS_E8 VSS_V5 V8
G10 VSS_G1 VSS_V12 W2 G1 VSS_G12 VSS_V8 V12
VSS_G10 VSS_W2 VSS_G1 VSS_V12 GND GND
G3 W4 G10 W2
G5 VSS_G3 VSS_W4 W9 G3 VSS_G10 VSS_W2 W4
G8 VSS_G5 VSS_W9 W11 G5 VSS_G3 VSS_W4 W9
J1 VSS_G8 VSS_W11 Y1 G8 VSS_G5 VSS_W9 W11
J10 VSS_J1 VSS_Y1 Y5 J1 VSS_G8 VSS_W11 Y1
J12 VSS_J10 VSS_Y5 Y8 J10 VSS_J1 VSS_Y1 Y5
J3 VSS_J12 VSS_Y8 Y12 J12 VSS_J10 VSS_Y5 Y8
K11 VSS_J3 VSS_Y12 AB10 J3 VSS_J12 VSS_Y8 Y12
K2 VSS_K11 VSS_AB10 AB3 K11 VSS_J3 VSS_Y12 AB10
K4 VSS_K2 VSS_AB3 AB5 K2 VSS_K11 VSS_AB10 AB3
A VSS_K4 VSS_AB5 VSS_K2 VSS_AB3 A
K9 AB8 K4 AB5
VSS_K9 VSS_AB8 K9 VSS_K4 VSS_AB5 AB8
32GB VSS_K9 VSS_AB8
GND BGA200_15P1X10P1X1_P65XP8-2 GND 32GB
TBL1601 GND BGA200_15P1X10P1X1_P65XP8-2 GND
TBL1601

W x H 602 x 390 mm
Title: LPDDR4X(1)_MEMORY DOWN
<OrgName> Engineer:
<OrgAddr1>
Size Project Name Rev
Custom EDAN_A_EV1 1.00
Date: Tuesday, May 21, 2019 Sheet 16 of 82
5 4 3 2 1
 5 4 3 2 1

U1701 U1702
[11] M_C_1_DQ_[7:0] M_C_1_DQ_4 M_C_3_DQ_7 M_C_3_DQ_[7:0] [11]
[11] M_D_1_DQ_[7:0] M_D_1_DQ_3 M_D_3_DQ_1 M_D_3_DQ_[7:0] [11]
B2 AA2 B2 AA2
M_C_1_DQ_1 C2 DQ0_A DQ0_B Y2 M_C_3_DQ_3 M_D_1_DQ_6 C2 DQ0_A DQ0_B Y2 M_D_3_DQ_2
M_C_1_DQ_7 E2 DQ1_A DQ1_B V2 M_C_3_DQ_5 M_D_1_DQ_7 E2 DQ1_A DQ1_B V2 M_D_3_DQ_0
M_C_1_DQ_0 F2 DQ2_A DQ2_B U2 M_C_3_DQ_6 M_D_1_DQ_4 F2 DQ2_A DQ2_B U2 M_D_3_DQ_4 VDD2 Decoupling
M_C_1_DQ_2 F4 DQ3_A DQ3_B U4 M_C_3_DQ_0 M_D_1_DQ_0 F4 DQ3_A DQ3_B U4 M_D_3_DQ_3 Performance Scheme, except 0201 1uF
M_C_1_DQ_5 E4 DQ4_A DQ4_B V4 M_C_3_DQ_1 M_D_1_DQ_5 E4 DQ4_A DQ4_B V4 M_D_3_DQ_5
M_C_1_DQ_3 C4 DQ5_A DQ5_B Y4 M_C_3_DQ_2 M_D_1_DQ_1 C4 DQ5_A DQ5_B Y4 M_D_3_DQ_6 +1P1V_DDR_VDD2 +1P1V_DDR_VDD2
DQ6_A DQ6_B DQ6_A DQ6_B
6 caps per DRAM, 2 per long 6 caps per DRAM, 2 per long
M_C_1_DQ_6 B4 AA4 M_C_3_DQ_4 M_D_1_DQ_2 B4 AA4 M_D_3_DQ_7 edge, 1 per short edge edge, 1 per short edge
[11] M_C_0_DQ_[7:0] M_C_0_DQ_0 DQ7_A DQ7_B M_C_2_DQ_7 M_C_2_DQ_[7:0] [11]
[11] M_D_0_DQ_[7:0] M_D_0_DQ_2 DQ7_A DQ7_B M_D_2_DQ_1 M_D_2_DQ_[7:0] [11]
B11 AA11 B11 AA11
M_C_0_DQ_2 C11 DQ8_A DQ8_B Y11 M_C_2_DQ_3 M_D_0_DQ_0 C11 DQ8_A DQ8_B Y11 M_D_2_DQ_4
D M_C_0_DQ_5 E11 DQ9_A DQ9_B V11 M_C_2_DQ_0 M_D_0_DQ_5 E11 DQ9_A DQ9_B V11 M_D_2_DQ_7 C1710 C1725 C1717 C1727 C1703 C1705 C1713 C1726 C1708 C1720 C1709 C1715 D
M_C_0_DQ_7 F11 DQ10_A DQ10_B U11 M_C_2_DQ_5 M_D_0_DQ_3 F11 DQ10_A DQ10_B U11 M_D_2_DQ_5 1u 1u 1u 1u 1u 1u 1u 1u 1u 1u 1u 1u
M_C_0_DQ_3 F9 DQ11_A DQ11_B U9 M_C_2_DQ_1 M_D_0_DQ_7 F9 DQ11_A DQ11_B U9 M_D_2_DQ_3 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V
M_C_0_DQ_6 E9 DQ12_A DQ12_B V9 M_C_2_DQ_6 M_D_0_DQ_6 E9 DQ12_A DQ12_B V9 M_D_2_DQ_6
M_C_0_DQ_4 C9 DQ13_A DQ13_B Y9 M_C_2_DQ_4 M_D_0_DQ_4 C9 DQ13_A DQ13_B Y9 M_D_2_DQ_0
+0P6V_DDR_VDDQ M_C_0_DQ_1 B9 DQ14_A DQ14_B AA9 M_C_2_DQ_2 +0P6V_DDR_VDDQ M_D_0_DQ_1 B9 DQ14_A DQ14_B AA9 M_D_2_DQ_2
DQ15_A DQ15_B DQ15_A DQ15_B
GND GND
1%

1%
D3 W3 D3 W3
1%

1%
[11] M_C_DQS_1_DP DQS0_A_t DQS0_B_t M_C_DQS_3_DP [11] [11] M_D_DQS_1_DP DQS0_A_t DQS0_B_t M_D_DQS_3_DP [11]
240

240

240

240
E3 V3 E3 V3
[11] M_C_DQS_1_DN DQS0_A_c DQS0_B_c M_C_DQS_3_DN [11] [11] M_D_DQS_1_DN DQS0_A_c DQS0_B_c M_D_DQS_3_DN [11] VDDQ Decoupling
D10 W10 D10 W10 Performance Scheme, except 0201 1uF
[11] M_C_DQS_0_DP DQS1_A_t DQS1_B_t M_C_DQS_2_DP [11] [11] M_D_DQS_0_DP DQS1_A_t DQS1_B_t M_D_DQS_2_DP [11]
R1701

R1702

R1703

R1704
E10 V10 E10 V10
[11] M_C_DQS_0_DN DQS1_A_c DQS1_B_c M_C_DQS_2_DN [11] [11] M_D_DQS_0_DN DQS1_A_c DQS1_B_c M_D_DQS_2_DN [11] +0P6V_DDR_VDDQ +0P6V_DDR_VDDQ
C3 Y3 C3 Y3
4 caps per DRAM, 2 per long 4 caps per DRAM, 2 per long
C10 DMI0_A DMI0_B Y10 C10 DMI0_A DMI0_B Y10 edge, 1 per short edge edge, 1 per short edge
GND DMI1_A DMI1_B GND GND DMI1_A DMI1_B GND
ZQ0_1701 A5 DRAM_RESET# ZQ0_1702 A5 DRAM_RESET# C1724 C1706 C1714 C1711 C1721 C1701 C1712 C1707
ZQ1_1701 ZQ0 DRAM_RESET# [11,16] ZQ1_1702 ZQ0
A8 T11 A8 T11 1u 1u 1u 1u 1u 1u 1u 1u
NC/ZQ1 RESET_n C1729 0.1u NC/ZQ1 RESET_n C1723 0.1u 10V 10V 10V 10V 10V 10V 10V 10V
GND GND
DNP 10V DNP 10V
J4 P4 M_C_LP4_CKE0 J4 P4 M_D_LP4_CKE0
[11] M_C_LP4_CKE0 CKE0_A CKE0_B [11] M_D_LP4_CKE0 CKE0_A CKE0_B
J5 P5 M_C_LP4_CKE1 J5 P5 M_D_LP4_CKE1
[11] M_C_LP4_CKE1 NC/CKE1_A CKE1_B/NC [11] M_D_LP4_CKE1 NC/CKE1_A CKE1_B/NC
GND GND
H4 R4 M_C_LP4_CS#0 H4 R4 M_D_LP4_CS#0
[11] M_C_LP4_CS#0 CS0_A CS0_B [11] M_D_LP4_CS#0 CS0_A CS0_B
H3 R3 M_C_LP4_CS#1 H3 R3 M_D_LP4_CS#1
[11] M_C_LP4_CS#1 NC/CS1_A CS1_B/NC [11] M_D_LP4_CS#1 NC/CS1_A CS1_B/NC

[11] M_C_LP4_CLK_P J8 P8 M_C_LP4_CLK_P

[11] M_D_LP4_CLK_P J8 P8 M_D_LP4_CLK_P VDD1 Decoupling
J9 CK_A_t CK_B_t P9 M_C_LP4_CLK_N J9 CK_A_t CK_B_t P9 M_D_LP4_CLK_N
[11] M_C_LP4_CLK_N CK_A_c CK_B_c [11] M_D_LP4_CLK_N CK_A_c CK_B_c
Performance Scheme, except 0201 1uF
+1P8V_DDR_VDD1 +1P8V_DDR_VDD1
[11] M_C_CA[5:0] [11] M_D_CA[5:0] 4 caps per DRAM, 2 per long 4 caps per DRAM, 2 per long
M_C_CA0 H2 R2 M_C_CA0 M_D_CA0 H2 R2 M_D_CA0
M_C_CA1 J2 CA0_A CA0_B P2 M_C_CA1 M_D_CA1 J2 CA0_A CA0_B P2 M_D_CA1 edge, 1 per short edge edge, 1 per short edge
M_C_CA2 H9 CA1_A CA1_B R9 M_C_CA2 M_D_CA2 H9 CA1_A CA1_B R9 M_D_CA2
M_C_CA3 H10 CA2_A CA2_B R10 M_C_CA3 M_D_CA3 H10 CA2_A CA2_B R10 M_D_CA3 C1730 C1718 C1704 C1722 C1728 C1716 C1702 C1719
C M_C_CA4 H11 CA3_A CA3_B R11 M_C_CA4 +1P1V_DDR_VDD2 M_D_CA4 H11 CA3_A CA3_B R11 M_D_CA4 +1P1V_DDR_VDD2 1u 1u 1u 1u 1u 1u 1u 1u C
+1P1V_DDR_VDD2 M_C_CA5 J11 CA4_A CA4_B P11 M_C_CA5 +1P1V_DDR_VDD2 M_D_CA5 J11 CA4_A CA4_B P11 M_D_CA5 10V 10V 10V 10V 10V 10V 10V 10V
CA5_A CA5_B CA5_A CA5_B
R1707 0 G2 T2 R1705 0 R1708 0 G2 T2 R1706 0
ODT_CA_A ODT_CA_B ODT_CA_A ODT_CA_B
GND GND
A1 A1
A2 DNU_A1 N5 A2 DNU_A1 N5
A11 DNU_A2 NC_N5 N8 A11 DNU_A2 NC_N5 N8
A12 DNU_A11 NC_N8 AA1 A12 DNU_A11 NC_N8 AA1
B1 DNU_A12 DNU_AA1 AA12 B1 DNU_A12 DNU_AA1 AA12
B12 DNU_B1 DNU_AA12 AB1 B12 DNU_B1 DNU_AA12 AB1
G11 DNU_B12 DNU_AB1 AB2 G11 DNU_B12 DNU_AB1 AB2
K5 NC_G11 DNU_AB2 AB11 K5 NC_G11 DNU_AB2 AB11
K8 NC_K5 DNU_AB11 AB12 K8 NC_K5 DNU_AB11 AB12
NC_K8 DNU_AB12 NC_K8 DNU_AB12

+1P8V_DDR_VDD1 F1 T4 +1P8V_DDR_VDD1 +1P8V_DDR_VDD1 F1 T4 +1P8V_DDR_VDD1

F12 VDD1_F1 VDD1_T4 T9 F12 VDD1_F1 VDD1_T4 T9
G4 VDD1_F12 VDD1_T9 U1 G4 VDD1_F12 VDD1_T9 U1
G9 VDD1_G4 VDD1_U1 U12 G9 VDD1_G4 VDD1_U1 U12
VDD1_G9 VDD1_U12 VDD1_G9 VDD1_U12

+1P1V_DDR_VDD2 A4 N1 +1P1V_DDR_VDD2 +1P1V_DDR_VDD2 A4 N1 +1P1V_DDR_VDD2

A9 VDD2_A4 VDD2_N1 N3 A9 VDD2_A4 VDD2_N1 N3
F5 VDD2_A9 VDD2_N3 N10 F5 VDD2_A9 VDD2_N3 N10
F8 VDD2_F5 VDD2_N10 N12 F8 VDD2_F5 VDD2_N10 N12
H1 VDD2_F8 VDD2_N12 R1 H1 VDD2_F8 VDD2_N12 R1
H5 VDD2_H1 VDD2_R1 R5 H5 VDD2_H1 VDD2_R1 R5
H8 VDD2_H5 VDD2_R5 R8 H8 VDD2_H5 VDD2_R5 R8
H12 VDD2_H8 VDD2_R8 R12 H12 VDD2_H8 VDD2_R8 R12
K1 VDD2_H12 VDD2_R12 U5 K1 VDD2_H12 VDD2_R12 U5
K3 VDD2_K1 VDD2_U5 U8 K3 VDD2_K1 VDD2_U5 U8
K10 VDD2_K3 VDD2_U8 AB4 K10 VDD2_K3 VDD2_U8 AB4
K12 VDD2_K10 VDD2_AB4 AB9 K12 VDD2_K10 VDD2_AB4 AB9
VDD2_K12 VDD2_AB9 VDD2_K12 VDD2_AB9
B B

+0P6V_DDR_VDDQ B3 U3 +0P6V_DDR_VDDQ +0P6V_DDR_VDDQ B3 U3 +0P6V_DDR_VDDQ

B5 VDDQ_B3 VDDQ_U3 U10 B5 VDDQ_B3 VDDQ_U3 U10
B8 VDDQ_B5 VDDQ_U10 W1 B8 VDDQ_B5 VDDQ_U10 W1
B10 VDDQ_B8 VDDQ_W1 W5 B10 VDDQ_B8 VDDQ_W1 W5
D1 VDDQ_B10 VDDQ_W5 W8 D1 VDDQ_B10 VDDQ_W5 W8
D5 VDDQ_D1 VDDQ_W8 W12 D5 VDDQ_D1 VDDQ_W8 W12
D8 VDDQ_D5 VDDQ_W12 AA3 D8 VDDQ_D5 VDDQ_W12 AA3
D12 VDDQ_D8 VDDQ_AA3 AA5 D12 VDDQ_D8 VDDQ_AA3 AA5
F3 VDDQ_D12 VDDQ_AA5 AA8 F3 VDDQ_D12 VDDQ_AA5 AA8
F10 VDDQ_F3 VDDQ_AA8 AA10 F10 VDDQ_F3 VDDQ_AA8 AA10
VDDQ_F10 VDDQ_AA10 VDDQ_F10 VDDQ_AA10

N2 N2
VSS_N2 N4 VSS_N2 N4
A10 VSS_N4 N9 A10 VSS_N4 N9
A3 VSS_A10 VSS_N9 N11 A3 VSS_A10 VSS_N9 N11
C1 VSS_A3 VSS_N11 P1 C1 VSS_A3 VSS_N11 P1
C12 VSS_C1 VSS_P1 P3 C12 VSS_C1 VSS_P1 P3
C5 VSS_C12 VSS_P3 P10 C5 VSS_C12 VSS_P3 P10
C8 VSS_C5 VSS_P10 P12 C8 VSS_C5 VSS_P10 P12
D11 VSS_C8 VSS_P12 T1 D11 VSS_C8 VSS_P12 T1
D2 VSS_D11 VSS_T1 T3 D2 VSS_D11 VSS_T1 T3
D4 VSS_D2 VSS_T3 T5 D4 VSS_D2 VSS_T3 T5
D9 VSS_D4 VSS_T5 T8 D9 VSS_D4 VSS_T5 T8
E1 VSS_D9 VSS_T8 T10 E1 VSS_D9 VSS_T8 T10
E12 VSS_E1 VSS_T10 T12 E12 VSS_E1 VSS_T10 T12
E5 VSS_E12 VSS_T12 V1 E5 VSS_E12 VSS_T12 V1
E8 VSS_E5 VSS_V1 V5 E8 VSS_E5 VSS_V1 V5
G12 VSS_E8 VSS_V5 V8 G12 VSS_E8 VSS_V5 V8
G1 VSS_G12 VSS_V8 V12 G1 VSS_G12 VSS_V8 V12
G10 VSS_G1 VSS_V12 W2 G10 VSS_G1 VSS_V12 W2
G3 VSS_G10 VSS_W2 W4 G3 VSS_G10 VSS_W2 W4
G5 VSS_G3 VSS_W4 W9 G5 VSS_G3 VSS_W4 W9
G8 VSS_G5 VSS_W9 W11 G8 VSS_G5 VSS_W9 W11
J1 VSS_G8 VSS_W11 Y1 J1 VSS_G8 VSS_W11 Y1
A VSS_J1 VSS_Y1 VSS_J1 VSS_Y1 A
J10 Y5 J10 Y5
J12 VSS_J10 VSS_Y5 Y8 J12 VSS_J10 VSS_Y5 Y8
J3 VSS_J12 VSS_Y8 Y12 J3 VSS_J12 VSS_Y8 Y12
K11 VSS_J3 VSS_Y12 AB10 K11 VSS_J3 VSS_Y12 AB10
K2 VSS_K11 VSS_AB10 AB3 K2 VSS_K11 VSS_AB10 AB3
K4 VSS_K2 VSS_AB3 AB5 K4 VSS_K2 VSS_AB3 AB5
K9 VSS_K4 VSS_AB5 AB8 K9 VSS_K4 VSS_AB5 AB8
VSS_K9 VSS_AB8 VSS_K9 VSS_AB8

W x H 572 x 370 mm
32GB 32GB
GND BGA200_15P1X10P1X1_P65XP8-2
TBL1601
GND GND BGA200_15P1X10P1X1_P65XP8-2
TBL1601
GND
Title: LPDDR4X(2)_MEMORY DOWN
<OrgName> Engineer: <OrgAddr1>
Size Project Name Rev
Custom EDAN_A_EV1 1.00
Date: Tuesday, May 21, 2019 Sheet 17 of 82
5 4 3 2 1
 5 4 3 2 1

D D

+1P8VSB +3P3VSB
+5VSB

0 R1807
J1801
0 R1832
RECEPTACLE DNP
1 2
3 1 2 4
5 3 4 6
7 5 6 8 USB BSSB is moved from SFF to USBC debug.
9 7 8 10
11 9 10 12
[29,33,35,79] SAM_PD_SCL 13 11 12 14
[29,33,35,79] SAM_PD_SDA 13 14
15 16
17 15 16 18
[24] GPP_E5 17 18 GPP_E0 [24]
19 20 GPP_E1 [21]
[10] GPP_E6 19 20
21 22 GPP_E2 [21] Better R1822/1826/1809/1818 put at PCH side.
[10] GPP_E7 21 22
23 24 GPP_E3 [10]
[21] GPP_E8 23 24
25 26 GPP_E4 [24]
C +VCC1.05_OUT_FET 27 25 26 28 C
0 R1803 RSMRST# [22,37]
V1P05A_DEBUG 29 27 28 30
R1805 0 1K R1830 +VCC1.05_OUT_FET
31 29 30 32 MIPI60_TCLK
[15] CFG17 0 R1820 XDP_TCK [10,76]
33 31 32 34 MIPI60_TDI 0 R1808 XDP_TDI [10,76]
35 33 34 36
[10] PROC_PRDY# 35 36 MIPI60_TRST_N DBG_PMODE [10,29]
37 38 0 R1816 XDP_TRST# [10,76]
[21,34] XDP_SPI0_IO2 MIPI60_PRESENT2 37 38 MIPI60_TMS
R1824 0 39 40 0 R1829 XDP_TMS [10,76]
[34,56] XDP_PRESENT# 39 40 MIPI60_TDO
41 42 0 R1806
[15,18] CFG0 41 42 MIPI60_DRRESET_N XDP_TDO [10,76]
43 44 0 R1815 PCH_SYS_RST# [22,33]
[15] CFG1 43 44
45 46
[15] CFG2 45 46
47 48
[15] CFG3 47 48 V1P05A_CPU PROC_PREQ# [10]
49 50 0 R1819
[15] CFG4 49 50 VCCIO_OUT [12]
51 52
[15] CFG5 51 52 SPI0_MOSI_XDP_R
53 54 0 R1828 SPI0_MOSI_XDP [21]
[15] CFG6 53 54 MIPI60_HOOK2
55 56 1K R1817
[15] CFG7 MIPI60_TCLK1 55 56 MIPI60_SMC CFG0 [15,18]
[10,76] PCH_JTAG_TCK R1814 0 57 58 0 R1811
57 58 XDP_PCH_PWRBTN# [22]
[29] PCH_JTAG_TCK_MUX R1836 DBG_D 0 59 60 0 R1802DNP
59 60 PWRBTN#_1V8 [31,33,34]

GND DBG_D GND 0 R1831 PCH_JTAGX [10,76]

0 R1813 PCH_JTAG_TDI [10,76]
0 R1821 PCH_TRST# [10,76]
B 0 R1810 PCH_JTAG_TMS [10,76] B
0 R1823 PCH_JTAG_TDO [10,76]

C1802 C1803 C1801 0 DBG_D R1834 PCH_JTAG_TDI_MUX [29]

0.1u 0.1u 0.1u 0 DBG_D R1835 PCH_JTAG_TMS_MUX [29]
0 DBG_D R1833 PCH_JTAG_TDO_MUX [29]
Pin Pin 0 DBG_D R1837 XDP_TCK_MUX [29]
Signal # Interface # Signal
GND 1 2 GND
USB2_DP 3 4 USB3_TX_DP
GND GND GND
USB2_DN 5 6 USB3_TX_DN
VBUS 7 8 GND
VBUS 9 10 USB3_RX_DP
I2C_SCL 11 12 USB3_RX_DN
I2C_SDA 13 PCH-VISA, 14 GND
GND 15 USB,I2C 16 +V3P3A_PCH_VREF_TRACE
MIPI60_FN13 17 18 MIPI60_FN8
MIPI60_FN14 19 20 MIPI60_FN9
MIPI60_FN15 21 22 MIPI60_FN10
MIPI60_FN_CLK2 23 24 MIPI60_FN11
GND 25 26 MIPI60_FN12
I2C_2_SCL 27 28 PM_RSMRST_N*
+V1.05A_VREF_DEBUG 29 30 GND
MIPI60_NOA_STB0_DP 31 32 MIPI60_TCLK
GND 33 34 MIPI60_TDI
MIPI60_PRDY_N 35 36 DBG_PMODE_MIPI60_RST_R_N
MIPI60_PRESENT1_N 37 38 MIPI60_TRST_N
A MIPI60_OVERRIDE 39 40 MIPI60_TMS A
MIPI60_NOA0_N 41 42 MIPI60_TDO
MIPI60_NOA1_N 43 44 MIPI60_DBRESET_N
MIPI60_NOA2_N 45 CPU-VISA 46 I2C_2_SDA

W x H 392 x 254 mm
MIPI60_NOA3_N 47 48 MIPI60_PREQ_N
MIPI60_NOA4_N 49 50 +V1.05A_CPU_VREF_TRACE
MIPI60_NOA5_N 51 52 GND
Title: SFF
MIPI60_NOA6_N 53 54 SPI0_MOSI_SYS_PWROK_MIPI60

MIPI60_NOA7_N
MIPI60_TCLK1
55
57
MIPI60_HOOK2_CPU_BOOT_STAL
56 L
58 SMC_ONOFF_MIPI60_N
<OrgName> Engineer: <OrgAddr1>
GND 59 60 GND Size Project Name Rev
Custom EDAN_A_EV1 1.00
Date: Tuesday, May 21, 2019 Sheet 18 of 82
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

W x H 372 x 241 mm
Title:
<OrgName> Engineer: <OrgAddr1>
Size Project Name Rev
Custom EDAN_A_EV1 1.00
Date: Tuesday, May 21, 2019 Sheet 19 of 82
5 4 3 2 1
 5 4 3 2 1

R2001 10M

U1001J
R2007 R2004
10 OF 19 0 0
CJ3 CF5
CJ5 CLKOUT_PCIE_N0 CLKOUT_PCIE_N5 CF3
DK33 CLKOUT_PCIE_P0 CLKOUT_PCIE_P5 DP40 R2005 0 CTAL_1 1 2
GPP_D5/SRCCLKREQ0 GPP_H11/SRCCLKREQ5
CL2 C2001 X2001 C2002
CL1 CLKOUT_PCIE_N1 DL48 RTC_X1 15p 25V 32.768KHZ 15p 25V
D DN34 CLKOUT_PCIE_P1 RTCX1 DL49 RTC_X2 XTAL2_3P3X1P6XP9_2P5 D
GPP_D6/SRCCLKREQ1 RTCX2 TP2004
5% 5%
CL3 DT47 RTC_RST#
[44] M2_PCIECLK_N CLKOUT_PCIE_N2 RTCRST SRTC_SRST#
M.2 SSD CL5 DK46
[44] M2_PCIECLK_P CLKOUT_PCIE_P2 SRTCRST +VCC_RTC
DP34
[44] M2_PCIECLK_REQ# GPP_D7/SRCCLKREQ2 TP2001
DF49 R2014 0 SUSCLK [50]
CK3 GPD8/SUSCLK
CK4 CLKOUT_PCIE_N3 R2021 R2002
DP36 CLKOUT_PCIE_P3 DW8 XTAL_38P4M_IN 71.5K
GPP_D8/SRCCLKREQ3 XTAL_IN 71.5K
DU8 XTAL_38P4M_OUT R2035 200K
CJ2 XTAL_OUT
CJ1 CLKOUT_PCIE_N4
DN40 CLKOUT_PCIE_P4 DU6 XCLK_BIASREF
GPP_H10/SRCCLKREQ4 XCLK_BIASREF R2012

D
R2013 0 C2003 C2004
0 10V 2.2u 2.2u
M1042225-001 R2022 G RTCRST_CTRL_FET 0
RTCRST_CTRL [35]
60.4 10V
R2084
Y2001 38.4MHz
Q2002 100K
R2083 0 3 1

S
R2081
4 2
GND
C2007 C2006
10p 50V 10p 50V

C C
NEEDS 38.4MHZ CRYSTAL

+1P8VSB
DNP
R2009 1K

HDA_SDO_R pin has internal pull-up U1001G

7 OF 19 CE46
R2053 0 HDA_BCLK_R CY46 GPP_G6/SD_CLK CC48
[40] MHDA_BCLK HDA_SYNC_R GPP_R0/HDA_BCLK/I2S0_SCLK GPP_G1/SD_DATA0
R2020 0 CV49 CC49
[40] MHDA_SYNC HDA_SDO_R INT. PD CY47 GPP_R1/HDA_SYNC/I2S0_SFRM GPP_G2/SD_DATA1
R2054 0 CC47
[40] MHDA_SDOUT GPP_R2/HDA_SDO/I2S0_TXD GPP_G3/SD_DATA2
CV45 CF45
[40] MHDA_SDIN HDA_RST# GPP_R3/HDA_SDI0/I2S0_RXD GPP_G4/SD_DATA3
DA47 CC45
GPP_R4/HDA_RST GPP_G0/SD_CMD CF49
SD3.0 GPP_G7/SD_WP
R2010 0 TS_IRQ#_R DP33 CE47
[30] TS_IRQ_1V8# GPP_D19/I2S_MCLK GPP_G5/SD_CD
2p

2p

2p

DC45 DK38
[54] ISP_FW_LOCK# GPP_A23/I2S1_SCLK GPP_H0/CNV_BT_I2S_SDO
R2011 DA49 DG38
GPP_R5/HDA_SDI1/I2S1_SFRM GPP_H1/SD_PWR_EN_N/CNV_BT_I2S_SDO TP2003
DA45
C2009

C2010

C2008

75K
DNP DA48 GPP_R6/I2S1_TXD CJ43 SD_RCOMP
CT49 GPP_R7/I2S1_RXD SD3_RCOMP
B CT48 GPP_A7/I2S2_SCLK R2080 B
[33,50] CNV_RF_RESET# GPP_A8/I2S2_SFRM/CNV_RF_RESET
CV47 DG36 200
R2008 33 CT47 GPP_A10/I2S2_RXD GPP_S6/SNDW4_CLK/DMIC_CLK0 DG34 0201S_P26
[33,50] MODEM_CLKREQ GPP_A9/I2S2_TXD/MODEM_CLKREQ GPP_S7/SNDW4_DATA/DMIC_DATA0
10K

CY39 CV38 SNDW_RCOMP

CY38 GPP_S0/SNDW1_CLK SNDW_RCOMP
R2006

GPP_S1/SNDW1_DATA R2003
AUDIO
DB39 200
DD38 GPP_S2/SNDW2_CLK 0201S_P26
GPP_S3/SNDW2_DATA
DF38
DD39 GPP_S4/SNDW3_CLK/DMIC_CLK1
GPP_S5/SNDW3_DATA/DMIC_DATA1

M1042225-001

GPP_R2/HDA_SDO

A 0 Default Enable Flash Security A

1 Disable Flash Security

W x H 417 x 270mm
Title: PCH(1)_SD,HDA,RTC,CLK
Engineer: <OrgAddr1>
Size Project Name Rev
Custom EDAN_A_EV1 1.00
Date: Tuesday, May 21, 2019 Sheet 20 of 82
5 4 3 2 1
 5 4 3 2 1

+1P8VSB
+3P3VSB
[18,34] XDP_SPI0_IO2 DEPROM_PROG [57]
[18] SPI0_MOSI_XDP
7bit i2c
R2133 R2134 R2113 R2132 R2123 Address R2114

0201S_P28-W35

0201S_P28-W35

0201S_P28-W35

0201S_P28-W35

0201S_P28-W35

0201S_P28-W35
1K 1K 75K 75K 75K 0x4D 0 R2102 R2103 R2107 R2110 R2104 R2106
R2117 R2115
R2151 75K 1K 1K 1K 1K 1K 1K
U1001E 1K 1K
DNP DNP DNP DNP
5 OF 19
R2141 5.1 SPI_CLK_PCH DB42 1
[38] SPI_CLK SPI_MOSI_PCH SPI0_CLK
R2154 5.1 DD43 SPI 0 DK27 Customer or Enterprise mode detection
[38] SPI_MOSI SPI_MISO_PCH SPI0_MOSI GPP_C0/SMBCLK
R2155 5.1 DF43 SMBUS DP24
[38] SPI_MISO SPI_W P_IO2 SPI0_MISO GPP_C1/SMBDATA ME_CRYPTO_EN R2111
DF42 DL24 INT. PD 1K
SPI_HOLD#_IO3 DD41 SPI0_IO2 GPP_C2/SMBALERT
SPI_CS#0_R DB43 SPI0_IO3
DF41 SPI0_CS0 DK24 SML0CLK
R2158 0 SPI_CS#2_R DB41 SPI0_CS1 SML 0 GPP_C3/SML0CLK DJ24 SML0DAT
[38] SPI_TPM_CS# SPI0_CS2 GPP_C4/SML0DATA EN_ESPI
D DP22INT. PD D
GPP_C5/SML0ALERT
R2109 33 TS_SPI_CLK_R DV16
[30] TS_SPI_CLK TS_SPI_MOSI_R DT16 GPP_E11/SPI1_CLK/BK1/SBK1
R2101 33 SPI 1 DN22 PD_I2C2_SCL [77,79]
[30] TS_SPI_MOSI TS_SPI_MISO_R DU18 GPP_E13/SPI1_MOSI/BK3/SBK3 GPP_C6/SML1CLK/SUSWARN_N/SUSPWRDNACK
R2105 33 DL22 PD_I2C2_SDA [77,79]
[30] TS_SPI_MISO GPP_E12/SPI1_MISO/BK2/SBK2 SML1 GPP_C7/SML1DATA/SUSACK
DT18
[18] GPP_E1 GPP_E1/SPI1_IO2
DW18
[18] GPP_E2 TS_SPI_CS#_R GPP_E2/SPI1_IO3
R2112 0 DW16 CR47 R2142 49.9
[30] TS_SPI_CS# GPP_E10/SPI1_CS_N/BK0/SBK0 GPP_A5/ESPI_CLK ESPI_CLK [35]
DU16 eSPI CN45 R2143 10
[18] GPP_E8 GPP_E8/SATALED_N/SPI1_CS1 GPP_A0/ESPI_IO0 ESPI_IO_0 [35]
CN48 R2119 10
GPP_A1/ESPI_IO1 ESPI_IO_1 [35]
CN49 R2118 10
GPP_A2/ESPI_IO2 ESPI_IO_2 [35] ESPI_RST# [35]
DV19 CN47 R2129 10
CL_CLK GPP_A3/ESPI_IO3 ESPI_IO_3 [35]
DW19 MLINK CT45 R2140 0
CL_DATA GPP_A4/ESPI_CS ESPI_CS# [35]
DT19 CR46
CL_RST GPP_A6/ESPI_RESET TP2128
SP_TP_SMDP58

R2150
M1042225-001 75K

C C

+1P8VSB UEFI SPI ROM

+1P8VSB

C2111
R2121 R2120
0.1u
1K 1K
DNP 0201 R2122
ALL U2102
1K
8 5 DNP
6 VCC IO0 2
1 CLK IO1 3
4 CS IO2 7
9 GND IO3
MPAD
W 25R128JW PIQ

+1P8VSB
+1P8VSB
DBG_D +1P8VSB
U2103
TS3A27518EZQSR
SPI_CLK = 20/33/50Mhz BGA24_5X5_3P1X3P1X1_P5 R2125
UEFI_SPI1_CLK A1 C2 100K
UEFI_SPI_IO0 COM1 V+ R2148 R2124
B1 0201 IN1/IN2 = L => COM to NC
UEFI_SPI_IO1 COM2 1K 1K DNP IN1/IN2 = H => NC to COM
C1 C4
UEFI_SPI_IO2 D1 COM3 EN# C2110 DBG_D DBG_D
UEFI_SPI_IO3 E1 COM4 B4 0.1u R2126
UEFI_SPI_CS# COM5 IN1 10V SAM_UEFIROM_EN [35,76]
B D2 D3 2K B
COM6 IN2 DBG_D DBG_D
C3 Needs to strap SPI0_IO2, SPI0_IO3 high
A3 GND
B3 N.C. E2
[76] SPI_CLK_R1
A2 NC1 NO1 E3
SAM_UEFIROM_SPI_CLK [34] GPP_C2/SMBALERT#
[76] SPI_MOSI_R1 NC2 NO2 SAM_UEFIROM_SPI_MOSI [34]
A4 E4
[76] SPI_MISO_R1 NC3 NO3 SAM_UEFIROM_SPI_MISO [34]
B5 D5 SPI1_WP#_DBG 0 Default Disable ME crypto TLS
[76] SPI_W P_IO2_R1 NC4 NO4
C5 D4 SPI1_HOLD#_DBG
[76] SPI_HOLD#_IO3_R1 NC5 NO5
A5 E5
[76] SPI_CS#0_R NC6 NO6 SAM_UEFIROM_SPI_CS# [35]
1 Enable ME crypto TLS
R2127 0 DBG_N SPI_CLK_R1 R2138 15 SPI_CLK
R2128 0 DBG_N SPI_MOSI_R1 R2137 15 SPI_MOSI
R2146 0 DBG_N SPI_MISO_R1 R2145 15 SPI_MISO GPP_C5/SMLALERT#
R2130 0 DBG_N SPI_W P_IO2_R1R2144 33 SPI_W P_IO2
R2147 0 DBG_N SPI_HOLD#_IO3_R1R2108 33 SPI_HOLD#_IO3 0 Default Enable eSPI
R2149 0 DBG_N SPI_CS#0_R

1 Disable eSPI
Populate for production only

A A

W x H 417 x 270mm
Title: PCH(2)_CLK,SMB,LPC,SPI
Engineer: <OrgAddr1>
Size Project Name Rev
A2 EDAN_A_EV1 1.00
Date: Tuesday, May 21, 2019 Sheet 21 of 82
5 4 3 2 1
 5 4 3 2 1

+1P8VSUS_ORG

Level shifter needed for connection to SAM

Level Shift Should be Able to Remove
Only 3.3V connected to TPM TP2208
If switch to 1.8V SPI IO, Then change
C2202 TP2218
10V 0.1u
U2202
U1001K
74AUP1G08GX
5 11 OF 19
VCC SLP_SUS#_R DM49 XDP_PCH_PWRBTN# [18]
4 2 R2258 33 CY42 R2232 0
[33,34,38,44] PLT_RST_BUF# Y A [34,62] SLP_SUS# SLP_S5#_R DF45 SLP_SUS GPD3/PWRBTN SAM_PCH_PWRBTN# [10,37]
1 TP2217 DE46
B SLP_S4#_R DC48 GPD10/SLP_S5 GPD1/ACPRESENT SAM_PCH_ACPRESENT [37]
3 [33,34,60] SLP_S4# R2267 33 DH48 BATLOW#_R 10K R2226 +3P3VSB
R2224 GND R2264 33 SLP_S3#_R DF47 GPD5/SLP_S4 GPD0/BATLOW
D C2204 [22,33,34,58] SLP_S3# GPD4/SLP_S3 D
SLP_A#_R

R2268
49.9K 100p [33,34] SLP_A# R2265 33 DH47 CL39 R2211 0
GPD6/SLP_A GPP_B11/PMCALERT PD_BB_I2C2_INT# [77,79]

10K
Note: [33,34] SLP_S0# R2263 33 SLP_S0#_R CL45 DU40 CPU_C10_GATE# [33,56,60,62]
Place C2204 GPP_B12/SLP_S0 GPP_H18/CPU_C10_GATE DG40
next to U2202.2 TP2202 SLP_WLAN# DE49 GPP_H3/SX_EXIT_HOLDOFF_N/CNV_BT_I2S_SDO
TP2203 GPD9/SPL_WLAN
R2223 DNP 0 TP2221 SLP_LAN# DN48 DL45 10K R2212 +3P3VSB +3P3VSB
TP2219 SLP_LAN WAKE
TP2220
DG49 DE47 20K R2259
DK19 RSMRST GPD_2/LAN_WAKE DF48 LANPHYPC
SYS_RESET GPD11/LANPHYPC/DSWLDO_MON TP2216
PLTRST# CM49
[58] PLTRST# GPP_B13/PLTRST VCCST_OVERRIDE
CE4
VCCST_OVERRIDE CF2 VCCST_PWRGD_R 60.4 R2257
+3P3VSB R2208 PCH_DPWROK_R DR48 VCCST_PWRGD CE3 VCCST_PWRGD_TCSS VCCST_PWRGD [58] R2262 0
75K DN47 DSW_PWROK VCCSTPWRGOOD_TCSS CF1 PROCPWRGD TP2211
ALL SYS_PWROK_R DP19 PCH_PWROK PROCPWRGD
R2225 +VCC_RTC SYS_PWROK DC47 INT. PD TP2201
10K INPUT3VSEL_STRAP DN49 GPD7
0201S_P28-W35 1M R2256 INTRUDER# DR47 INPUT3VSEL
INTRUDER BB_PERST# [77]
Fastboot <140mS need
[18,33] PCH_SYS_RST# diode connected

R2202
to both VCCRTC
M1042225-001

10K
R2239 0 PM_RSMRST_R and 3P3VDSW. C2201 R2206
[18,37] RSMRST#
0201S_P28-W35 0.1u 100K
DNP

R2251 C2203
49.9K 470p
0201S_P28-W35
C 0201S_P33 C
25V

+3P3VSB +1P8VSB

R2228 100
[37] SYS_PWROK
0201S_P28-W35
R2252 100K
0201S_P28-W35 VCCST_OVERRIDE R2218 R2219
100K 75K
SLP_S0# DNP

CPU_C10_GATE#
SLP_A#
SLP_S3# SLP_S0#
SLP_S4#
PDG Table 6-113 states 100k PU for
+3P3VSB SLP_SUS# 3.3V and 75k PU for 1.8V. Adding DNP
options for 1.8V and DNP options for
75k PD
R2204 R2209 R2203 R2207 R2201 R2216 R2217
0201 75K 75K 75K 75K 75K 75K 75K
C2205 DNP
0.1u 10V
U2203
5
R2260 01 VCC
[22,33,34,58] SLP_S3# A PM_PCH_PWROK_R
R2261 02 4
[35] PM_PCH_PWROK B O
PCH Signal Glitch Free Implementation Requirements
3
B GND B
SN74LV1T08DCKR

R2255
100K VCCDSW 3V SELECT STRAP
INPUT3VSEL

0 3.3V

1 3.0V

R2235 0 PCH_DPWROK_R
[37] PCH_DPWROK
0201S_P28-W35
R2253 100K
0201S_P28-W35

A A

Title: PCH(3)_SYS PWR CONTR

Engineer: <OrgAddr1>
Size Project Name Rev
A3 EDAN_A_EV1 1.00
Date: Tuesday, May 21, 2019 Sheet 22 of 82
5 4 3 2 1
 5 4 3 2 1

Please place testpoints at back of SoC and as close as possible.

D D

R2339 49.9K SAM_PCH_RTC_WAKE

0201S_P28-W35

R2305 49.9K PCH_SAM_INT2

U1001I Camino
9 OF 19 GPP_F8 is PCH_SAM_INT
GPP_F9 is PCH_SAM_DGPU_STS R2337 49.9K SAM_PCH_INT
D12 DP27 R2319 0 0201S_P28-W35
CSI_E_CLK GPP_F8/EMMC_DATA0 R2306 SAM_PCH_RTC_WAKE [35]
C12 CSI2 eMMC DU30 GPP_F9_PCH_SAM_INT2 0
CSI_E_CLK_P GPP_F9/EMMC_DATA1 PCH_SAM_INT2 [34]
B12 DT30 R2317 0 R2336 49.9K SAM_PCH_BASE
CSI_E_DN_0 GPP_F10/EMMC_DATA2 R2312 SAM_PCH_INT [35]
A12 DT29 0 0201S_P28-W35
G13 CSI_E_DP_0 GPP_F11/EMMC_DATA3 DV30 R2310 SAM_PCH_BASE [35] SAM_PCH_RSK
0 R2335 49.9K
CSI_E_DN_1 GPP_F12/EMMC_DATA4 R2316 SAM_PCH_RSK [35]
F13 DU29 0 0201S_P28-W35
CSI_E_DP_1 GPP_F13/EMMC_DATA5 SAM_PCH_LID_STATE [35]
DW30
K10 GPP_F14/EMMC_DATA6 DW29 R2334 49.9K SAM_PCH_LID_STATE
L10 CSI_F_CLK GPP_F15/EMMC_DATA7 DV28 R2307 DNP 0 0201S_P28-W35
L8 CSI_F_CLK_P GPP_F7/EMMC_CMD DW28 PCH_SAM_INST_ON [34,72]
R2308 0
CSI_F_DN_0 GPP_F16/EMMC_RCLK PCH_SAM_INT [34]
M8 DN27
M11 CSI_F_DP_0 GPP_F17/EMMC_CLK DT28
L11 CSI_F_DN_1 GPP_F18/EMMC_RESET DU28 EMMC_RCOMP_R
CSI_F_DP_1 EMMC_RCOMP R2311 200
D9
C9 CSI_D_CLK DV45
CSI_D_CLK_P CNV_WT_D0N CNV_WT_D0_DN_D100 [50]
A7 CNVi DU45
CSI_D_DN_0 CNV_WT_D0P CNV_WT_D0_DP_D100 [50]
C
B7 DU44 C
CSI_D_DP_0 CNV_WT_D1N CNV_WT_D1_DN_D100 [50]
B9 DT44
A9 CSI_D_DN_1 CNV_WT_D1P DL42 CNV_WT_D1_DP_D100 [50]
CSI_D_DP_1 CNV_WT_CLKN CNV_WT_CLK_DN_D100 [50]
D7 DK42
CSI_D_DN_2/CSI_C_DN_0 CNV_WT_CLKP CNV_WT_CLK_DP_D100 [50]
C7
D8 CSI_D_DP_2/CSI_C_DP_0 DP44
CSI_D_DN_3/CSI_C_CLK CNV_WR_D0N CNV_WR_D0_DN_D100 [50]
C8 DN44
CSI_D_DP_3/CSI_C_CLK_P CNV_WR_D0P DG42 CNV_WR_D0_DP_D100 [50]
CNV_WR_D1N CNV_WR_D1_DN_D100 [50]
G11 DG44
CSI_H_CLK CNV_WR_D1P CNV_WR_D1_DP_D100 [50]
J11 DK44
CSI_H_CLK_P CNV_WR_CLKN CNV_WR_CLK_DN_D100 [50]
F6 DJ44
CSI_H_DN_0 CNV_WR_CLKP CNV_WR_CLK_DP_D100 [50]
G6
G10 CSI_H_DP_0 DT45 R2323 150
F10 CSI_H_DN_1 CNV_WT_RCOMP
G8 CSI_H_DP_1 DL29 CNV_BRI_RSP_R R2327 22
CSI_H_DN_2/CSI_G_DN_0 GPP_F1/CNV_BRI_RSP/UART0_RXD CNV_BRI_RSP [50] +1P8VSB
J8 DP31 CNVI_EN_STRAP R2303 22
CSI_H_DP_2/CSI_G_DP_0 GPP_F2/CNV_RGI_DT/UART0_TXD CNV_RGI_DT [50]
K6 DL31 INT. PD 38.4MHZ_STRAPE
R2304 22
L6 CSI_H_DN_3/CSI_G_CLK GPP_F0/CNV_BRI_DT/UART0_RTS DN29 CNV_RGI_RSP_R CNV_BRI_DT [50]
R2328 22
CSI_H_DP_3/CSI_G_CLK_P GPP_F3/CNV_RGI_RSP/UART0_CTS CNV_RGI_RSP [50]
1% ALL
100 0201 R2322 CSI2_COMP B4 DJ29 R2333
CSI_RCOMP GPP_F4/CNV_RF_RESET DP29
GPP_F6/CNV_PA_BLANKING 20K
DT34 DL27
DP38 GPP_D4/IMGCLKOUT0 GPP_F19/A4WP_PRESENT DK29 BIOS_REC R2331 0 0201S_P28-W35

DK36 GPP_H20/IMGCLKOUT1 GPP_F5/MODEM_CLKREQ

DL36 GPP_H21/IMGCLKOUT2
GPP_H22/IMGCLKOUT3 TP2301SP_TP_SMDP58
DN38 R2332
TP2303 GPP_H23/IMGCLKOUT4 R2309 49.9K
B 0201S_P28-W35 B
75K DNP
[33] PCH_DEBUG_GPP_H23
DNP
M1042225-001

+1P8VSB +1P8VSB +1P8VSB +1P8VSB

DNP
0201S_P28-W35

R2301 R2302 DNP DNP

R2341 R2342
XTAL FREQUENCY SELECTION
100K
10K 20K 20K GPP_F0
CNVI_EN_STRAP 38.4MHZ_STRAPE 0201S_P28-W35 0201S_P28-W35

CNV_BRI_RSP_R CNV_RGI_RSP_R 0 Default 38.4MHZ

DNP
0201S_P28-W35

R2340 1 24MHZ
10K
CNVI ENABLE
GPP_F2

0 Default Integrated CNVi Enabled

A A
1 Integrated CNVi Disabled

W x H 422 x 273 mm
Title: PCH(4)_CSI,eMMC,CNVi,IDs
Engineer: <OrgAddr1>
Size Project Name Rev
Custom EDAN_A_EV1 1.00
Date: Tuesday, May 21, 2019 Sheet 23 of 82
5 4 3 2 1
 5 4 3 2 1

U1001H
8 OF 19
CV7 DJ8
D PCIE7_RXN PCIE1_RXN/USB31_1_RXN USB3_SL1_RXN4 [71] D
CV6 DJ6
PCIE7_RXP PCIE1_RXP/USB31_1_RXP USB3_SL1_RXP4 [71]
DD3 DJ2 USB3 SL40
DD5 PCIE7_TXN PCIE1_TXN/USB31_1_TXN DJ1 USB3_SL1_TXN4 [71]
PCIE7_TXP PCIE1_TXP/USB31_1_TXP USB3_SL1_TXP4 [71]
CT6 DG9
PCIE8_RXN PCIE2_RXN/USB31_2_RXN USB3_USBA_RX_DN [45]
CT7 DG7
PCIE8_RXP PCIE2_RXP/USB31_2_RXP USB3_USBA_RX_DP [45]
DA3 DJ3
DA5 PCIE8_TXN PCIE2_TXN/USB31_2_TXN DJ5 USB3_USBA_TX_DN [45] USB3 TYPE A AND BSSB
PCIE8_TXP PCIE2_TXP/USB31_2_TXP USB3_USBA_TX_DP [45]
CP7 DE7
[44] PCIE_SSD_RX0_DN PCIE9_RXN PCIE3_RXN/USB31_3_RXN
CP6 DE9
[44] PCIE_SSD_RX0_DP PCIE9_RXP PCIE3_RXP/USB31_3_RXP
DA2 DF3
[44] PCIE_SSD_TX0_DN DA1 PCIE9_TXN PCIE3_TXN/USB31_3_TXN DF5
[44] PCIE_SSD_TX0_DP PCIE9_TXP PCIE3_TXP/USB31_3_TXP
CM7 DC7
[44] PCIE_SSD_RX1_DN PCIE10_RXN PCIE4_RXN/USB31_4_RXN
CM6 DC9
[44] PCIE_SSD_RX1_DP PCIE10_RXP PCIE4_RXP/USB31_4_RXP
CY3 DF2
[44] PCIE_SSD_TX1_DN PCIE10_TXN PCIE4_TXN/USB31_4_TXN
CY4 DF1
[44] PCIE_SSD_TX1_DP PCIE10_TXP PCIE4_TXP/USB31_4_TXP
PCIE M.2 SSD CK7 DA6
[44] PCIE_SSD_RX2_DN PCIE11_RXN/SATA0_RXN PCIE5_RXN/USB31_5_RXN
CK6 DA7
[44] PCIE_SSD_RX2_DP PCIE11_RXP/SATA0_RXP PCIE5_RXP/USB31_5_RXP
CW2 DE4
[44] PCIE_SSD_TX2_DN CW1 PCIE11_TXN/SATA0_TXN PCIE5_TXN/USB31_5_TXN DE3
[44] PCIE_SSD_TX2_DP PCIE11_TXP/SATA0_TXP PCIE5_TXP/USB31_5_TXP
CJ6 CY7
[44] PCIE_SSD_RX3_DN PCIE12_RXN/SATA1A_RXN PCIE6_RXN/USB31_6_RXN
CJ7 CY6
C [44] PCIE_SSD_RX3_DP PCIE12_RXP/SATA1A_RXP PCIE6_RXP/USB31_6_RXP C
CW5 DD1
[44] PCIE_SSD_TX3_DN CW3 PCIE12_TXN/SATA1A_TXN PCIE6_TXN/USB31_6_TXN DD2
[44] PCIE_SSD_TX3_DP PCIE12_TXP/SATA1A_TXP PCIE6_TXP/USB31_6_TXP
CG7 DN8 USB2_SL1_DN [71]
CG6 PCIE13_RXN USB2N_1 DP8
PCIE13_RXP USB2P_1 USB2_SL1_DP [71] USB2 SL40
CT3
CT5 PCIE13_TXN DK11
PCIE13_TXP USB2N_2 USB2_USBA_DN [45]
DJ11 USB2 USB-A PORT
CE6 USB2P_2 USB2_USBA_DP [45]
CE7 PCIE14_RXN DP13
CT2 PCIE14_RXP USB2N_3 DN13
CT1 PCIE14_TXN USB2P_3
PCIE14_TXP DK10
USB2N_4 USB2_TCP0_DN [77]
CC5 DJ10 USB2 USB-C PORT1
PCIE15_RXN/SATA1B_RXN USB2P_4 USB2_TCP0_DP [77]
CC6
CR3 PCIE15_RXP/SATA1B_RXP DL5
CR4 PCIE15_TXN/SATA1B_TXN USB2N_5 DL3
PCIE15_TXP/SATA1B_TXP USB2P_5
CA6 DP11
PCIE16_RXN/SATA2_RXN USB2N_6 CAM_USB_DM_SOC [54]
CA5 DN11 USB2 Camera
PCIE16_RXP/SATA2_RXP USB2P_6 CAM_USB_DP_SOC [54]
CP1
CP2 PCIE16_TXN/SATA2_TXN DK13
PCIE16_TXP/SATA2_TXP USB2N_7 DJ13
DW12 USB2P_7
[18] GPP_E0 GPP_E0/SATAXPCIE0/SATAGP0
CR42 DN6
CR43 GPP_A12/SATAXPCIE1/SATAGP1 USB2N_8 DP6
B GPP_A13/SATAXPCIE2/SATAGP2 USB2P_8 B

DW14 DL2
[45] USBA_OVCUR# CT43 GPP_E9/USB_OC0 USB2N_9 DL1
TP2402 GPP_A16/USB_OC3 USB2P_9
[79] TCP0_OC# DU12 DP10
[18] GPP_E4 GPP_E4/DEVSLP0 USB2N_10
DU11 DN10
[18] GPP_E5 GPP_E5/DEVSLP1 USB2P_10
CV48
[57,76] TCON_VENDOR_ID GPP_A11/SATA_DEVSLP2 DL6 10K R2405
DT38 USB_ID
DW38 GPP_H12/M2_SKT2_CFG0 DL11 10K R2408
DV38 GPP_H13/M2_SKT2_CFG1 USB_VBUSSENSE
[33,50] BT_DISABLE# GPP_H14/M2_SKT2_CFG2
DU38 DN5 USB2_COMP R2402 113
[33,50] WLAN_DISABLE# GPP_H15/M2_SKT2_CFG3 USB2_COMP
PCIE_RCOMPN DN1 CD3
PCIE_RCOMPN UFS_RESET TP2401
R2401 100 PCIE_RCOMPP DN3
0201S_P28-W35 PCIE_RCOMPP

M1042225-001

A A
+1P8VSB

0201S_P28-W35 R2410 49.9K TCON_VENDOR_ID

W x H 412 x 267 mm
Title: PCH(5)_PCIE,USB
Engineer: <OrgAddr1>
Size Project Name Rev
Custom EDAN_A_EV1 1.00
Date: Tuesday, May 21, 2019 Sheet 24 of 82
5 4 3 2 1
 5 4 3 2 1

+1P8VSB
SAM NEED DECIDE TO SET UEFI_TOP_SWAP HIGH OR LOW BEFORE ASSERT PCH_PWROK
TP2523

TP2518

R2533

R2536

R2524

R2509
100K
100K

100K

100K
[35] SAM_PCH_TOP_SWAP U1001F
6 OF 19
R2518 CH48 DV33 TPANEL_RST#_R R2511 0
INT. PD CF48 GPP_B16/GSPI0_CLK GPP_D13/ISH_UART0_RXD TPANEL_RST# [30,33,35]
100K DW33
GPP_B18/GSPI0_MOSI GPP_D14/ISH_UART0_TXD RTD3_TPANEL_PWR [62,64]
DNP CF47 DT33 RTD3_CAM_PWREN_R R2517 1K
GPP_B17/GSPI0_MISO GPP_D15/ISH_UART0_RTS_N/GSPI2_CS1_N/IMGCLKOUT5 RTD3_CAM_PWREN [54,76]
D CH49 DU33 FLASH_PROTECT#_R R2515 0 D
INT. PD CH47 GPP_B15/GSPI0_CS0 GPP_D16/ISH_UART0_CTS_N/CNV_WCEN FLASH_PROTECT# [30]
GPP_B14/SPKR/TIME_SYNC1/GSPI0_CS1 DK22 R2513 0 Debug UART +3P3VSB
+1P8V_PANEL GPP_C12/UART1_RXD/ISH_UART1_RXD PCH_DBG_RX [29,33,76]
CL47 DW24 R2505 0
GPP_B20/GSPI1_CLK GPP_C13/UART1_TXD/ISH_UART1_TXD PCH_DBG_TX [29,33,76]
No reboot strap CK47 DV24
Low: Disable (Default) CK46 GPP_B22/GSPI1_MOSI GPP_C14/UART1_RTS_N/ISH_UART1_RTS DU24 MEM_CONFIG
High:Enable CH45 GPP_B21/GSPI1_MISO GPP_C15/UART1_CTS_N/ISH_UART1_CTS R2590 100K
GPP_B19/GSPI1_CS0
2.2K

2.2K
INT. PD CL48 CN43 R2589 100K
GPP_B23/SML1ALERT_N/PCHHOT_N/GSPI1_CS1 GPP_B5/ISH_I2C0_SDA CN42
DP21 GPP_B6/ISH_I2C0_SCL
[29,33,34] SAMTX_PCHRX GPP_C8/UART0_RXD
DK21 CN41
R2583

R2584

[29,33,34] PCHTX_SAMRX GPP_C9/UART0_TXD GPP_B7/ISH_I2C1_SDA

DL21 CL43
[29,33,34,76] PCHRTS_SAMCTS GPP_C10/UART0_RTS GPP_B8/ISH_I2C1_SCL
DJ22
[33,57] PANEL_I2C_SDA [29,33,34,76] SAMRTS_PCHCTS GPP_C11/UART0_CTS CL41
[33,57] PANEL_I2C_SCL DT22 GPP_B9/I2C5_SDA/ISH_I2C2_SDA CJ39
[62] RTD3_AUD_PWR_1P8 GPP_C20/UART2_RXD GPP_B10/I2C5_SCL/ISH_I2C2_SCL
[64] RTD3_AUD_PWR_5P0 DW22 DU36
DV22 GPP_C21/UART2_TXD Should really be a space here in the symbol > GPP_D0/ISH_GP0 DV36
[31,33] VOL_UP# GPP_C22/UART2_RTS GPP_D1/ISH_GP1 ACS_INT# [54]
DU22 DW36
[31,33] VOL_DOWN# GPP_C23/UART2_CTS GPP_D2/ISH_GP2 TP2532
ALL DT36 GPP_D3
R2598 0 PANEL_I2C_SDA_R DT24 GPP_D3/ISH_GP3 DU34
R2597 0 PANEL_I2C_SCL_R DT23 GPP_C16/I2C0_SDA GPP_D17/ISH_GP4 DW34
ALL GPP_C17/I2C0_SCL GPP_D18/ISH_GP5 DT14
GPP_E15/ISH_GP6 TP2501
DW23 DU14
[28,33,76] PMI_I2C_SDA GPP_C18/I2C1_SDA GPP_E16/ISH_GP7 ISH_SAM_INT [34] +3P3VSB
DU23
[28,33,76] PMI_I2C_SCL GPP_C19/I2C1_SCL
DU41 DBG_D
C DV41 GPP_H4/I2C2_SDA R2525 C
GPP_H5/I2C2_SCL 1K
[77] PD_SML0_SCL 0 R2501 DW41 -4mA sync
0 DT41 GPP_H6/I2C3_SDA capability on
[77] PD_SML0_SDA R2502
GPP_H7/I2C3_SCL 3.3V GPIO

A
DT40
[54,76] PCH_SENSOR_I2C_SDA GPP_H8/I2C4_SDA/CNV_MFUART2_RXD
Removed connections from pins DK24 and DJ24 (page21) DW40 DBG_D
Connecting them to page 25 PMI_I2C I2C1 [54,76] PCH_SENSOR_I2C_SCL GPP_H9/I2C4_SCL/CNV_MFUART2_TXD

RED
0ohm straps refdes changed to match with page number LED2501
Red

K
M1042225-001
R2599 DBG_D0 ISH_DBG

+1P8VSB

10K
R2537
DNP

MEM_CONFIG LOW: A,B,C,D CHANNEL ENABLE

HIGH: A,C CHANNEL ENABLE

10K
R2526
B B

R2508 49.9K ISH_SAM_INT

0201S_P28-W35

R2572 49.9K RTD3_AUD_PWR_1P8

0201S_P28-W35

R2595 49.9K RTD3_AUD_PWR_5P0

0201S_P28-W35

R2559 49.9K RTD3_TPANEL_PWR

0201S_P28-W35

R2596 10K TPANEL_RST#

0201S_P28-W35
DNP
R2592 49.9K RTD3_CAM_PWREN
0201S_P28-W35
ALL
A A

CPUNSSC Clock Frequency

GPP_B23/SML1ALERT#/

W x H 417 x 270mm
PCHHOT#/GSPI1_CS1#
Title: PCH(6)_CPU,GPIO,MISC
0 Default 38.4MHz (crystal)
Engineer: <OrgAddr1>
Size Project Name Rev
1 19.2MHz (internal divider) Custom EDAN_A_EV1 1.00
Date: Tuesday, May 21, 2019 Sheet 25 of 82
5 4 3 2 1
 5 4 3 2 1

+3VSUS_ORG
Power rail can breakout with a 3.8mm width plane.

DNP DNP
Place near C2620 C2634
DG26&DF23 1u 6.3V 1u 6.3V
+VCCIN_AUX 0201S_P35-W35 0201S_P35-W35
1P8VSB need to come up after 3P3VSB

U1001N
D D
14 OF 19 +1P8VSUS_ORG
AH1 DF23
AW10 VCCIN_AUX_AH1 VCCPRIM_3P3_2 DG26 Place near
AY11 VCCIN_AUX_AW10 VCCPRIM_3P3_3 DG28 DG20
AY9 VCCIN_AUX_AY11 VCCPRIM_3P3_4
BA10 VCCIN_AUX_AY9 DNP
BB9 VCCIN_AUX_BA10 C2635
CH1 VCCIN_AUX_BB9 DF15 1u 6.3V
CK11 VCCIN_AUX_CH1 VCCPRIM_1P8_2 DF17 0201S_P35-W35 L2601 DNP 0.68uH
CL10 VCCIN_AUX_CK11 VCCPRIM_1P8_3 DF18
VCCIN_AUX_CL10 VCCPRIM_1P8_4 4.3A +1P8VSUS_ORG
CM11 DF20
CN1 VCCIN_AUX_CM11 VCCPRIM_1P8_5 DG17
AJ1 VCCIN_AUX_CN1 VCCPRIM_1P8_6 DG18 R2650 0.01
CN10 VCCIN_AUX_AJ1 VCCPRIM_1P8_7 DG20 trace w 0.8mm C2621 0603S_P6-W100
CP11 VCCIN_AUX_CN10 VCCPRIM_1P8_8 DF34 shield trace 1u 6.3V
VCCIN_AUX_CP11 VCCPRIM_1P8_9 R2601 DBG_S
CR10 PLACE NEAR DW37 WITHIN 3MM 0201S_P35-W35
CT11 VCCIN_AUX_CR10 FROM PACKAGE DNP 0402
CU10 VCCIN_AUX_CT11 C2654 2.2u 6.3V 0
CV1 VCCIN_AUX_CU10 0201
VCCIN_AUX_CV1 5%
CV11
CW10 VCCIN_AUX_CV11 DW37 C2653
CY11 VCCIN_AUX_CW10 VCCLDOSTD_0P85 47u
DC1 VCCIN_AUX_CY11 DW15 Place cap within 3mm from package edge. 0603
AL1 VCCIN_AUX_DC1 VCCA_CLKLDO_1P8 6.3V
P13 VCCIN_AUX_AL1 DW32 C2603 4.7u 0402
R12 VCCIN_AUX_P13 VCCDPHY_1P24
C VCCIN_AUX_R12 C
T13 DD34 close as possible to pin DD34. 6.3V +VCC1.05_OUT_FET
U12 VCCIN_AUX_T13 VCCDSW_1P05 C2604 1u 0201
DC11 VCCIN_AUX_U12 BY2 0.5A
DE12 VCCIN_AUX_DC11 VCC1P05_1 CB2
DF12 VCCIN_AUX_DE12 VCC1P05_2 CC1 +VCC1.05_OUT_SFR
AM1 VCCIN_AUX_DF12 VCC1P05_3
AN1 VCCIN_AUX_AM1 CD1 R2602 0 connected to page 12 only
AT11 VCCIN_AUX_AN1 VCC1P05_OUT_PLL 0402S_P4
AT9 VCCIN_AUX_AT11 DG31
VCCIN_AUX_AT9 VCCPRIM_1P05_1 +VCCPRIM_1P05
AU10 C2629 DNP
AV9 VCCIN_AUX_AU10 DG29 C2606 1u6.3V C2623
VCCIN_AUX_AV9 VCCPRIM_1P05_2 1u 0201S_P35-W35 1u 6.3V
+1P8VSUS_ORG +1P8VSUS_ORG +3VSUS_ORG BF9 DF29 6.3V 0201S_P35-W35
[69] VCCIN_AUX_VIN_SENSE VCCIN_AUX_VCCSENSE VCCPRIM_1P05_3
BD9 0201S_P35-W35
[69] VCCIN_AUX_VSS_SENSE VCCIN_AUX_VSSSENSE DF31
VCCPRIM_1P05_4 +VCC_RTC +3VSUS_ORG +1P8VSUS_ORG
DG33
DJ15 VCCRTC
TP2602 VCC_V1P05EXT_1P05 DE31
CY34 VCCDSW_3P3
TP2601 VCC_VNNEXT_1P05 DF26
DC33 VCCPGPPR
VCCPRIM_3P3_1 CL38
DD35 GPP_B0/CORE_VID0 CJ38 CORE_VID0 [69]
VCCPRIM_1P8_1 GPP_B1/CORE_VID1 CORE_VID1 [69]
CN38
DB34 GPP_B2/VRALERT
B VCCSPI B
+3VSUS_ORG

M1042225-001

+3VSUS_ORG
+VCC_RTC
R2603 100k per reference schematic C2605
100K 10k per Calgary 0.1u C2602 C2601
10V 0.1u 1u
DNP 10V 0201S_P35-W35
6.3V

Place near DE31

+1P8VSB +1P8VSUS_ORG +3P3VSB +3VSUS_ORG D2601 Place near DG33
DBG_TS DBG_TS K A
H_PROCHOT# [10,63,66,76]
R2624 0.01 R2612 0.01
0402S_P5-W65 0402S_P5-W65
RB520CS3002L

PMTP2607 Verify if PROCHOt# to be

PMTP2605 PMTP2606 PMTP2608 used at PCH.
SP-TP-C0P381
SP-TP-C0P381 SP-TP-C0P381 SP-TP-C0P381
A A
BC_PROCHOT# [79]

W x H 422 x 273 mm
Title: PCH(7)_POWER
Engineer: <OrgAddr1>
Size Project Name Rev
Custom EDAN_A_EV1 1.00
Date: Tuesday, May 21, 2019 Sheet 26 of 82
5 4 3 2 1
 5 4 3 2 1

+VCCIN_AUX
Primary Side Cap

C2733 C2722 C2735 C2755 C2707 C2715

22u 22u 22u 22u 22u 22u
D 0603 0603 0603 0603 0603 0603 D
20% 20% 20% 20% 20% 20%
10V 10V 10V 10V 10V 10V
DNP DNP DNP DNP DNP

C2724 C2737 C2753 C2706

22u 22u 22u 22u
0603 0603 0603 0603
20% 20% 20% 20%
10V 10V 10V 10V
DNP DNP

C2720 C2742
22u 22u
0603 0603
20% 20%
C C
10V 10V

C2725 C2741 C2702

22u 22u 22u
0603 0603 0603
20% 20% 20%
10V 10V 10V
DNP DNP

B B

A A

W x H 377 x 244 mm
Title: PCH(8)_decoupling
Engineer: <OrgAddr1>
Size Project Name Rev
Custom EDAN_A_EV1 1.00
Date: Tuesday, May 21, 2019 Sheet 27 of 82
5 4 3 2 1
 5 4 3 2 1

D D

+3P3VSB +3P3V_PMI

R2801 DBG_TS 0.1

+3P3V_PMI
Imax=0.0042A

+3P3V_PMI
2K

2K

C C
Ir*2 = 730uA
R2862

R2863

PMI1_I2C_SCL_R [76]
PMI1_I2C_SDA_R [76]
ALL ALL
ALL DBG_T
R2854 0 R2874 0
[25,33,76] PMI_I2C_SCL PM_DBG_I2C_SCL [29]
0201S_P28-W35
ALL DBG_T to debug connector
R2855 0 R2875 0
[25,33,76] PMI_I2C_SDA +3P3V_PMI PM_DBG_I2C_SDA [29]
0201S_P28-W35
Changed Build-opt to ALL for pull-ups and 0ohm +3P3V_PMI +3P3V_PMI
as Burnside Bridge is connected to the same I2C
Avila +5VSB while Carmel monitors PM_BLADE_IN+ U2802 DBG_T
U2813 DBG_T A3 A4 C2801 U2803 DBG_T
MAX34417 VDD Average Supply Current
[59] PM_5VSB_IN+ IN1+ VDD
[69] PM_VCCIN_AUX_IN+
A3
IN1+ VDD
A4 C2825
[59] PM_5VSB_IN-
A2
IN1-
0.1u 10V
[67] PM_VCCIN_IN+
A3
IN1+ VDD
A4 C2802 700uA PDNB=VIO and SLOW=GND
A2 0.1u 10V B2 0201S_P33-W39 A2 0.1u 10V
[69] PM_VCCIN_AUX_IN- IN1- B2 0201S_P33-W39 A1 VIO
GND
[67] PM_VCCIN_IN- IN1- B2 0201S_P33-W39 10uA PDNB=VIO and SLOW=VIO
VIO [59] PM_3P3VSB_IN+ IN2+ VIO
Avila
+VSYS [34] PM_+1P8V_SAM+
A1
B1 IN2+ GND [59] PM_3P3VSB_IN-
B1
IN2- C4
[60] PM_1P1V_DDR_VDD2_IN+
A1
B1 IN2+ GND 2uA PDNB=GND
while [34] PM_+1P8V_SAM- IN2- C4 D1 SCL D4
[60] PM_1P1V_DDR_VDD2_IN- IN2- C4
Carmel SCL [65] PM_3P3V_SSD+ IN3+ SDA SCL
D1 D4 C1 DBG_T D1 D4
monitors [63] PM_VSYS+
C1 IN3+ SDA DBG_T
[65] PM_3P3V_SSD- IN3- B3 PMI1_PDN_N R2865 10K
[65] PM_3P3V_PANEL_IN+
C1 IN3+ SDA DBG_T
6x700uA=4.2mA
+3P3VAS [63] PM_VSYS- IN3- PDN +3P3V_PMI [65] PM_3P3V_PANEL_IN- IN3-
PDN
B3 PMI0_PDN_N R2856 10K +3P3V_PMI [65] PM_3P3V_WWAN+
D3
IN4+
0201S_P28-W35
PDN
B3 PMI2_PDN_N R2867 10K +3P3V_PMI 3.3Vx4.2mA=13.86mW
D3 0201S_P28-W35 D2 C3 D3 0201S_P28-W35
[62] PM_1P8VSB_IN+ IN4+ [65] PM_3P3V_WWAN- IN4- SLOW [72] PM_BKLT_IN+ IN4+
D2 C3 D2 C3
[62] PM_1P8VSB_IN- IN4- SLOW PMI1_ADDR [72] PM_BKLT_IN- IN4- SLOW
C2
C2 PMI0_ADDR ADDR C2 PMI2_ADDR

A
ADDR
B4 DBG_T
B GND
B4 DBG_T
R2864 C
ADDR
B4 DBG_T
GND R2866 MAX34417 499 GND R2850
MAX34417 0 DBG_T 0201S_P28-W35 MAX34417 931
DBG_T 0201S_P28-W35 DBG_T 0201S_P28-W35
Address(7b) = 0x10 +3P3V_PMI Address(7b) = 0x12 GND

B
GND
GND
GND GNDGND Address(7b) = 0x14 GND GND
GND
B

Ir=12uA

Part B Part C
5VSB 3P3 Panel
3P3 VSB Display Backlight
1P8 VSB 3P3V SSD
3P3V WWAN

A A

W x H 577 x 373 mm
Title: Power Monitor
Engineer: <OrgAddr1>
Size Project Name Rev
Custom EDAN_A_EV1 1.00
Date: Tuesday, May 21, 2019 Sheet 28 of 82
5 4 3 2 1
 5 4 3 2 1
+3P3V_DEBUG
+3P3VA +3P3V_DEBUG +3P3V_DEBUG +3P3V_DEBUG

C2902 R2913 0 DBG_D C2901

U2906
U2901 0.1u 0603S_P6-W95 0.1u C2906
20 10V DBG_D 5 0.1u
VDD keep USB2 traces as short as possible between muxes R2904 DBG_D0 2 VCC 4 10V
DBG_D GND [37,79] PD_SAM_DBG_ACC_MODE A Y
7 8 GND U2902 [29,58] SAM_DBG_MODE R2911 DBG_D0 1
[33,74] SAM_KIP_UART_TX_DBG IA0 YA B DBG_D
6 20 3 GND
[30,33] TS_TCK_1V8 5 IA1 VDD GND
[74,76] KIP_SWD_CLK IA2 +3P3V_DEBUG
[25,33,34] SAMTX_PCHRX 4 7 8 74LVC1G32GX
IA3 [33,34,76] SAM_SWD_CLK IA0 YA
[18] PCH_JTAG_TCK_MUX R2926 DBG_D 0 JTAG_TCK_R 6 R2907 DBG_D
D
13 12 R2918 DBG_D 0 PCH_DBG_TX_R 5 IA1 D
[33,74] SAM_KIP_UART_RX_DBG IB0 YB [25,33,76] PCH_DBG_TX IA2 100K
14 4 0201 C2909 GND
[30,33] TS_TDI_1V8 15 IB1 1 IA3 DBG_D 0.1u
[74] KIP_SWD_DIO IB2 NC_1
16 9 13 12 DBG_D U2908
[25,33,34] PCHTX_SAMRX IB3 NC_2 [33,34,76] SAM_SWD_DIO IB0 YB
11 [18] PCH_JTAG_TDI_MUX R2919 DBG_D0 JTAG_TDI_R 14 5
MUX0_EN# 2 NC_3 18 R2927 DBG_D0 PCH_DBG_RX_R 15 IB1 1 4 VCC 1 DBG_USB_EN
EN NC_4 [25,33,76] PCH_DBG_RX IB2 NC_1 [77] MUX0_EN# Y A
19 16 9 2
USBC_MUX0 17 NC_5 IB3 NC_2 B SAM_MUX0_EN [35]
11 3
S0 10 MUX0_EN# 2 NC_3 18 GND R2924 100K
USBC_MUX1 3 GND 21 EN NC_4 19 SN74LV1T02DCKR
S1 MPAD USBC_MUX2_SEL 17 NC_5
TCP0_DBG0_A_DP [77] GND DBG_D DBG_D GND
PI3USB14-AZHE S0 10
GND GND TCP0_DBG1_A_DN [77]
DBG_D USBC_MUX3_SEL 3 21
+3P3V_DEBUG S1 MPAD TCP0_DBG2_B_DP [77]
TCP0_DBG3_B_DN [77]
PI3USB14-AZHE
U2903 C2904 GND +3P3V_DEBUG
DBG_D
20 0.1u
VDD 10V +3P3V_DEBUG
7 8 GND C2905 U2909 C2910
[18,33,35,79] SAM_PD_SCL IA0 YA DBG_D
6 U2905 R2901 74AUP1G08GX 0.1u
[30,33] TS_TDO_1V8 IA1
[74] KIP_TRACE_SWO 5 20 0.1u 100K DFN5_P85XP85XP4_P48 DBG_D
4 IA2 VDD 10V DBG_D 5
[25,33,34,76] PCHRTS_SAMCTS IA3 USBC_MUX3_SEL_INV 2 VCC 4 USBC_MUX4_SEL
7 8 GND
[33,34,76] SAM_SWD_SWO JTAG_TDO_R IA0 YA USBC_MUX2_SEL 1 A Y
C [18,33,35,79] SAM_PD_SDA 13 12 R2920 DBG_D0 6 DBG_D C
IB0 YB [18] PCH_JTAG_TDO_MUX IA1 B

D
14 R2928 DBG_D0 PM_DBG_I2C_SCL_R5 3
[30,33] TS_TMS_1V8 IB1 [28] PM_DBG_I2C_SCL IA2 GND
[35,74] SAM_KIP_RST# 15 1 4
16 IB2 NC_1 9 IA3 USBC_MUX3_SEL G +3P3V_DEBUG
[25,33,34,76] SAMRTS_PCHCTS IB3 NC_2 GND
11 13 12
NC_3 [33,34,58,76] SAM_RESET# JTAG_TMS_R IB0 YB
2 18 [18] PCH_JTAG_TMS_MUX R2921 DBG_D0 14 Q2902
EN NC_4 19 R2929 DBG_D0 PM_DBG_I2C_SDA_R
15 IB1 1 DBG_D C2903

S
NC_5 [28] PM_DBG_I2C_SDA IB2 NC_1
[35] USBC_MUX0 17 16 9 0.1u
S0 10 IB3 NC_2 11 U2912 10V
GND NC_3 GND
[35] USBC_MUX1 3 21 2 18 20
S1 MPAD EN NC_4 VDD DBG_D
19 GND
PI3USB14-AZHE USBC_MUX2_SEL 17 NC_5 7 8
S0 [29,77] TCP0_BB_SBU1 IA0 YA TCP0_SBU1 [29,77]
DBG_D GND 10 6
USBC_MUX3_SEL 3 GND 21 5 IA1
S1 MPAD [33,34,71,76] SAM_DBG_RX 4 IA2
+3P3V_DEBUG [18] XDP_TCK_MUX IA3
PI3USB14-AZHE GND
DBG_D [29,77] TCP0_BB_SBU2 13 12 TCP0_SBU2 [29,77]
14 IB0 YB
15 IB1 1
[33,34,71,76] SAM_DBG_TX IB2 NC_1
R2923 C2908 [10,18] DBG_PMODE R2902 0 16 9
100K 0.1u IB3 NC_2 11
1% U2910 10V 2 NC_3 18
0201 5 0201S_P28-W35 EN NC_4 19
VCC DBG_D NC_5
1 GND 17
B DBG_D A S0 B
[35] USBC_MUX3 2 4 USBC_MUX3_SEL 10
B O DBG_USB_EN 3 GND 21
S1 MPAD

D
3
GND PI3USB14-AZHE
G SN74LV1T08DCKR +3P3V_DEBUG
[29,58] SAM_DBG_MODE DBG_D
DBG_D R2905
Q2905 1K
R2909 GND C2907 GND
S
DBG_D
100K 0.1u
DBG_D
1% 10V
0201 U2911
DBG_D
5 GND
DBG_D VCC
GND R2903 0 1 [29,77] TCP0_BB_SBU1 R2908 DBG_N 0 TCP0_SBU1 [29,77]
R2910 0 2 A 4 USBC_MUX2_SEL R2906 DBG_N 0
[35] USBC_MUX2 B O [29,77] TCP0_BB_SBU2 TCP0_SBU2 [29,77]
0201S_P28-W35
3
DBG_D
0201S_P28-W35 GND
DBG_D SN74LV1T08DCKR
DBG_D GND
USBC_MUX3

USBC_MUX2

A USBC_MUX1 A

USBC_MUX0

W x H 377 x 244 mm
R2917 R2916 R2915 R2914 Title: Type-C Debug
100K 100K 100K 100K
Engineer: <OrgAddr1>
1% 1% 1% 1%
Size Project Name Rev
0201 0201 0201 0201
DBG_D
GND DBG_D
GNDDBG_D
GND DBG_D
GND
Custom EDAN_A_EV1 1.00
Date: Tuesday, May 21, 2019 Sheet 29 of 82
5 4 3 2 1
 5 4 3 2 1

TS_BOOST_HV_IN D3001 TS_HV_IN

MTP3039 TS_BOOST_HV_IN TS_HV_IN
+5V_TS A K
TPANEL_RST_N
[25,33,35] TPANEL_RST#
PMEG4015EPK315
MTP3024 TS_HV_IN U3002
TS_HV_IN E3 C1 H0
C3022 HV_IN ANT_HV0 C2 H1
25V 10u C3012 C3069 ANT_HV1 D1 H2
TS_V1P0_TCH_DIG +1P8V_TS 0603 2.2u 25V 0.1uF ANT_HV2 D2 H3
0402 DNP ANT_HV3 C3 H4
ANT_HV4 D3 H5
C3075 2.2u C3052 2.2u TSGND_BOOST TS_HV_IN A2 ANT_HV5 E2 H6
6.3V 6.3V BOOST_HV_OUT ANT_HV6 E1 H7
2.2uH TS_BOOST_HV_IN ANT_HV7 F2 H8
C3051 DNP 0.1uF C3037 DNP 0.1uF 1.4A TS_BOOST_HV_IN A1 ANT_HV8 F1 H9
L3003 BOOST_HV_IN ANT_HV9 G2 H10
C3044 C3019 2.0X1.6X1.0MM ANT_HV10 G1 H11
ANT_HV11 NOTE: Place shorts close to Master ATrig.
C3073 10u 0.1uF 6.3V 10u B1 H2 H12
TS_V1P0_TCH_SSI DNP 0603 BOOST_VSS ANT_HV12 H1 H13
+1P8V_TS ANT_HV13 J2 H14
D C3004 10u ANT_HV14 J1 H15 W3002 W3001 D

JMP

JMP
C3007 2.2u C3074 2.2u 0603 B8 ANT_HV15 K2 FC_AY0_HV16
6.3V 6.3V TSGND_BOOST A7 BUCK_1V8_IN ANT_HV16 K1 FC_AY0_HV17
C3035 DNP 0.1uF TS_V1P0_TCH_DIG BUCK_VSS ANT_HV17 L2 C3081 JUMPER_0201_SHORTED_PADS
ANT_HV18 L1 C3030
ANT_HV19 220p
C3046 DNP 0.1uF TSGND_BUCK A8 M2 220p
L3002 4.7uH TS_AYALON1_LVDCDC_LX B7 BUCK_OUT_FB ANT_HV20 M1 GND TSGND_BUCK TSGND_BOOST
0805 BUCK_LX ANT_HV21 M3
ANT_HV22

F11
TS_V1P0_TCH_SSI D4 L3

G3
+1P8VSB C3057 GND

B8

F5
TS_SPI_CLK TS_SPI_CLK U3006 10u 6.3V VDD_SSI ANT_HV23 GND
[21,30] TS_SPI_CLK D6 TS_V1P0_TCH_SSI 0603 C3068 4.7u 0402 B5

VDE_F
VDD_SSI

VDE_H
VDD_CORE
TS_SPI_MOSI TS_SPI_MOSI RESERVED_GND[0] B4 C3054 2.2u 0402 1P8V_TS LDO_1V0_OUT M8 V23
[21] TS_SPI_MOSI RESERVED_GND[1] D5 J3 ANT_LV0 M7 V22
R3011 RESERVED_GND[2] C5 TSGND_BUCK C3011 DNP 0.1uF VDD_1V8_IN ANT_LV1 L8 V21
100K GPIO signals may toggle during boot RESERVED_GND[3] B5 TS_V1P8A ANT_LV2 L7 V20
(see errata document). Please make RESERVED_GND[4] C6 TS_V1P8A C8 ANT_LV3 L6 V19
MTP3029
sure to implement the workaround F2 RESERVED_GND[5] B6 R3001 C3033 C3032 2.2u 0402 AVDD_IN ANT_LV4 K8 V18
described in the errata F4 SPI_CLK/I2C_SCL RESERVED_GND[6] C3 0.1uF F3 ANT_LV5 K7 V17
Q3003 SPI_DI / I2C_SDA RESERVED_GND[7] 4.99K AVDD_1V8_3 ANT_LV6
R3017 22.1 F3
TS_TOUCH_SPI_DO_R C4 DNP C3059 DNP 0.1uF H3 K6 V16
D

[20,30] TS_IRQ_1V8# [21,30] TS_SPI_MISO

NX3008NBKMB G1 GPIO7 / SPI_DO RESERVED_GND[8] B3 G3 AVDD_1V8_2 ANT_LV7 J8
0402 V15
[21,30] TS_SPI_CS# GPIO6 / SPI_CS RESERVED_GND[9] AVDD_1V8_1 ANT_LV8 J7
D V14
GTP3001 TS_GPIO0 D4 D8 ANT_LV9 J6 V13
G G TS_IRQ_1V8 D3 GPIO0 RESERVED_NC[0] J10 TPANEL_RST_N ANT_LV10 H6 V12
D2 GPIO1 / INT RESERVED_NC[1] H10 C3062 0.033u 1P8V_TS L5 ANT_LV11 H7 V11
S R3015 1K C1
TS_FLASH_PROTECTn_GPIO_R GPIO2 / IF_SEL RESERVED_NC[2] J9 0201 VDE_H ANT_LV12 H8 V10
[25,30] FLASH_PROTECT# C2 GPIO3 RESERVED_NC[3] H9 B2 ANT_LV13 G6
TP3002 C3053 C3031 0.033u V9
S

R3016 TP3004 B1 GPIO4 RESERVED_NC[4] J8 0.1u 0201 VDE_F ANT_LV14 G7 V8

10K GPIO5 RESERVED_NC[5] H8 0201 ANT_LV15 G8 V7
R3003 1K H2 RESERVED_NC[6] TPANEL_RST_N M6 ANT_LV16 F6 V6
[57] PANEL_VSYNCH H1 GPIO9 TS_AY_RSTN_D K5 RSTN_H ANT_LV17 F7
TP3003 V5
G2 GPIO10 J1 TS_AY_RSTN_D TS_VDD_OK_F A3 RSTN_D ANT_LV18 F8 V4
GPIO11 RSTN_D J5 TS_VDD_OK_F TS_VDD_OK_H M5 VDD_OK_F ANT_LV19 E7 V3
TS_TCK_1V8 H5 VDD_OK_F B2 TS_VDD_OK_H MTP3038 VDD_OK_H ANT_LV20 E8 V2
TS_TDI_1V8 H6 TCK RSTN ANT_LV21 D7 V1
TS_TDO_1V8 R3013 22.1 TS_JTAG_TS_TDO_R G6 TDI G10 TS_SCKL0 R3012 22.1 TS_SCKL TS_SCKL A6 ANT_LV22 D8 V0
TS_TMS_1V8 0201 F6 TDO SCKL SCLK ANT_LV23
[29,33] TS_TCK_1V8 TMS TS_SD0 TS_SD0
B10 A5 D5
[29,33] TS_TDI_1V8 TS_HOST_CLK SD0 TS_SD1 TS_SD1 A5_SSI_D0 RESERVED_GND1
(If Availible) J3 B11 B4 D6
[29,33] TS_TDO_1V8 CLK_IN SD1 TS_SD2 TS_SD2 A5_SSI_D1 RESERVED_GND2
C9 B3 C6
[29,33] TS_TMS_1V8 TS_DLITE_XI H11 SD2 TS_SD3 TS_SD3 A5_SSI_D2 RESERVED_GND3
R3019 C10 A4
200K TS_DLITE_XO_R J11 XI SD3 C11 TS_SD4 A5_SSI_D3 K3
XO SD4 C8 TS_SD5 RESERVED_NC1 C5
F10 SD5 D9 TS_SD6 MTP3036 TS_SCKL RESERVED_NC2 C4
CLK_SLCT SD6 D10 TS_SD7 MTP3012 TS_SD0 RESERVED_NC3
R3018 G5 SD7 F8 TS_SD8 MTP3020 TS_SD4 B6 C7 TS_AYALON0_ATB TP3006
0 H3 FSCK SD8 G8 TS_SD9 MTP3002 TS_SD8 GND ATB
FSDI SD9 TS_SD10

GND1

GND2
ALL G4 F9
H4 FSDIO SD10 G9 TS_SD11
0201
FSCS SD11
DS-A5048_82BGA Add underfill
TS_FLASH_CSn
4

Y3001 TS_HV_IN U3003

B9

1 3TS_DLITE_XO DS-D5000-B064 J2 TS_HV_IN TS_HV_IN E3 C1 H32

HV_IN ANT_HV0 C2 H33
48MHz Special keepout made to isolate ANT_HV1
XTAL,SM,48 MHZ,10 PPM,7 PF,2X1.6X0.45MM buck and boost ground from system ground C3066 C3040 D1 H34
2

2.2u 25V 0.1uF ANT_HV2 D2 H35

TS_FLASH_MISO
TS_FLASH_MOSI

ANT_HV3
TS_FLASH_SCK

0402 DNP C3 H36

+1P8V_TS ANT_HV4 D3 H37
C3079 C3063 A2 ANT_HV5 E2 H38
2% 25V 12p 2% 25V 12p BOOST_HV_OUT ANT_HV6 E1 H39
C ANT_HV7 F2 H40 C
U3005 C3067 A1 ANT_HV8 F1 H41
SON9_4P1X4P1XP6_P8 2.2u 6.3V BOOST_HV_IN ANT_HV9 G2 H42
1 8 ANT_HV10 G1 H43
6 CS VCC B1 ANT_HV11 H2 H44
The crystal and capacitors should be placed 5 CK BOOST_VSS ANT_HV12 H1 H45
+1P8V_TS as close as possible to the D5, with short and 2 SI/0 +1P8V_TS ANT_HV13 J2 H46
symmetrical traces to the XI and XO pins 3 Q/1 9 ANT_HV14 J1 H47
7 WP/2 MTG 4 B8 ANT_HV15 K2 H48
MTP3027 HLRS/3 VSS A7 BUCK_1V8_IN ANT_HV16 K1 H49
R3014 BUCK_VSS ANT_HV17 L2 H50
200K MTP3023 MX25U1635FZUI TS_V1P0_TCH_SSI ANT_HV18 L1 H51
A8 ANT_HV19 M2 FC_AY1_HV20
DNP MTP3022 B7 BUCK_OUT_FB ANT_HV20 M1 FC_AY1_HV21
MTP3011 C3050 2.2u 0402 BUCK_LX ANT_HV21 M3
MTP3034 D4 ANT_HV22 L3 C3017 C3080
MTP3037 C3064 DNP 0.1uF VDD_SSI ANT_HV23
220p 220p
MTP3042 B5
FLASH_PROTECT# LDO_1V0_OUT M8 V47
FLASH_PROTECT# [25,30] R3002 J3 ANT_LV0 M7
+1P8V_TS TS_V1P8A MTP3035 C3061 2.2u 0402 V46
VDD_1V8_IN ANT_LV1 L8 V45 GND GND
TS_V1P8A C3043 DNP 0.1uF ANT_LV2 L7 V44
ANT_LV3
C3041

C3047

C3025

V1P8 C8 L6 V43
+1P8V_TS 0 C3010 2.2u 0402 AVDD_IN ANT_LV4 K8 V42
Analog ANT_LV5
F3 K7 V41
MTP3001 C3045 DNP 0.1uF H3 AVDD_1V8_3 ANT_LV6 K6 V40
AVDD_1V8_2 ANT_LV7 +5V_TS
10u

10u

10u

0603 0603 0603 G3 J8 V39

AVDD_1V8_1 ANT_LV8 J7 V38 +1P8V_TS
MTP3041 TPANEL_RST# DNP DNP DNP ANT_LV9 J6 V37
MTP3003 FLASH_PROTECT# ANT_LV10 H6 V36
C3056 0.033u 0201 L5 ANT_LV11 H7 V35 C3002 C3029
MTP3021 TS_TCK_1V8 VDE_H ANT_LV12 H8 V34 C3027 C3001 2.2u 6.3V 0.1u 10V
MTP3032 TS_TMS_1V8 C3078 0.033u 0201 B2 ANT_LV13 G6 V33 0.1u 10V 10u 6.3V 0201S_P39-W39 0201S_P33-W39
MTP3026 TS_TDO_1V8 Not to be used for DEBUG build VDE_F ANT_LV14 G7 V32 0201S_P33-W39 0402S_P7-W70
MTP3040 TS_TDI_1V8 ANT_LV15 G8 V31
Use MTP points on pg 31 instead TS_VDD_OK_H M6 ANT_LV16 F6 V30 GND GND
TS_AY_RSTN_D K5 RSTN_H ANT_LV17 F7 V29 GND
RSTN_D ANT_LV18 GND
MTP3031 TS_SPI_CLK A3 F8 V28
MTP3033 TS_SPI_MISO M5 VDD_OK_F ANT_LV19 E7 V27
MTP3030 TS_SPI_MOSI VDD_OK_H ANT_LV20 E8 V26
ANT_LV21 D7 V25
TS_SCKL A6 ANT_LV22 D8 V24
MTP3025 TS_SPI_CS# SCLK ANT_LV23
TS_SD4 A5 D5
TS_SD5 B4 A5_SSI_D0 RESERVED_GND1 D6
MTP3028 TS_SD6 B3 A5_SSI_D1 RESERVED_GND2 C6
TS_SD7 A4 A5_SSI_D2 RESERVED_GND3
A5_SSI_D3 K3
RESERVED_NC1 C5
RESERVED_NC2 C4
RESERVED_NC3
B6 C7 TS_AYALON1_ATB TP3007

80 pin Sense Connector GND ATB

60 pin Drive Connector J3003

TS_HV_IN
DS-A5048_82BGA

U3004
Add underfill

V77 2 1 TS_HV_IN TS_HV_IN E3 C1 H16

B J3002 V75 4 2 1 3 V76 HV_IN ANT_HV0 C2 H17 B
V73 6 4 3 5 V74 C3071 C3021 ANT_HV1 D1 H18
2 1 V71 8 6 5 7 V72 2.2u 25V 0.1uF ANT_HV2 D2 H19
H0 4 2 1 3 V69 10 8 7 9 V70 0402 DNP ANT_HV3 C3 H20
H2 6 4 3 5 H1 V67 12 10 9 11 V68 ANT_HV4 D3 H21
H4 8 6 5 7 H3 V65 14 12 11 13 V66 A2 ANT_HV5 E2 H22
H6 10 8 7 9 H5 V63 16 14 13 15 V64 BOOST_HV_OUT ANT_HV6 E1 H23
H8 12 10 9 11 H7 V61 18 16 15 17 V62 ANT_HV7 F2 H24
H10 14 12 11 13 H9 V59 20 18 17 19 V60 A1 ANT_HV8 F1 H25
H12 16 14 13 15 H11 V57 22 20 19 21 V58 BOOST_HV_IN ANT_HV9 G2 H26
H14 18 16 15 17 H13 V55 24 22 21 23 V56 ANT_HV10 G1 H27
H16 20 18 17 19 H15 V53 26 24 23 25 V54 B1 ANT_HV11 H2 H28
H18 22 20 19 21 H17 V51 28 26 25 27 V52 BOOST_VSS ANT_HV12 H1 H29
H20 24 22 21 23 H19 V49 30 28 27 29 V50 +1P8V_TS ANT_HV13 J2 H30
H22 26 24 23 25 H21 V47 32 30 29 31 V48 TS_V1P0_TCH_SSI ANT_HV14 J1 H31
H24 28 26 25 27 H23 V45 34 32 31 33 V46 B8 ANT_HV15 K2 FC_AY2_HV16
H26 30 28 27 29 H25 V43 36 34 33 35 V44 A7 BUCK_1V8_IN ANT_HV16 K1 FC_AY2_HV17
H28 32 30 29 31 H27 V41 38 36 35 37 V42 BUCK_VSS ANT_HV17 L2 V77
H30 34 32 31 33 H29 V39 40 38 37 39 V40 ANT_HV18 L1 V76 C3024 C3016
H32 36 34 33 35 H31 V37 42 40 39 41 V38 A8 ANT_HV19 M2 V75
36 35 42 41 BUCK_OUT_FB ANT_HV20 220p 220p
H34 38 37 H33 V35 44 43 V36 B7 M1 V74
H36 40 38 37 39 H35 V33 46 44 43 45 V34 C3042 2.2u 0402 BUCK_LX ANT_HV21 M3 V73
H38 42 40 39 41 H37 V31 48 46 45 47 V32 D4 ANT_HV22 L3 V72
H40 44 42 41 43 H39 V29 50 48 47 49 V30 C3018 DNP 0.1uF VDD_SSI ANT_HV23 GND GND
H42 46 44 43 45 H41 V27 52 50 49 51 V28 B5
H44 48 46 45 47 H43 V25 54 52 51 53 V26 LDO_1V0_OUT M8 V71
H46 50 48 47 49 H45 V23 56 54 53 55 V24 C3006 2.2u 0402 J3 ANT_LV0 M7 V70
H48 52 50 49 51 H47 V21 58 56 55 57 V22 VDD_1V8_IN ANT_LV1 L8 V69
H50 54 52 51 53 H49 V19 60 58 57 59 V20 TS_V1P8A C3014 DNP 0.1uF ANT_LV2 L7 V68
56 54 53 55 H51 V17 62 60 59 61 V18 C8 ANT_LV3 L6 V67
58 56 55 57 V15 64 62 61 63 V16 C3008 2.2u 0402 AVDD_IN ANT_LV4 K8 V66
60 58 57 59 V13 66 64 63 65 V14 F3 ANT_LV5 K7 V65
60 59 V11 68 66 65 67 V12 C3013 DNP 0.1uF H3 AVDD_1V8_3 ANT_LV6 K6 V64
62 61 V9 70 68 67 69 V10 G3 AVDD_1V8_2 ANT_LV7 J8 V63
64 MT2 MT1 63 V7 72 70 69 71 V8 AVDD_1V8_1 ANT_LV8 J7 V62
MT4 MT3 V5 74 72 71 73 V6 C3038 10u 0603 ANT_LV9 J6 V61
V3 76 74 73 75 V4 ANT_LV10 H6 V60
V1 78 76 75 77 V2 C3058 0.033u 0201 L5 ANT_LV11 H7 V59
H0 to H47 are the horizontal sensor traces 80 78 77 79 V0 VDE_H ANT_LV12 H8 V58
V0 to V71 are the vertical sensor lines 80 79 C3055 0.033u 0201 B2 ANT_LV13 G6 V57
82 81 VDE_F ANT_LV14 G7 V56
84 MP2
MP4
MP1
MP3
83
TS_VDD_OK_H
ANT_LV15
ANT_LV16
G8 V55 +1P8V_PANEL SPI Buffer
M6 F6 V54
TS_AY_RSTN_D K5 RSTN_H ANT_LV17 F7 V53 +1P8V_PANEL
RSTN_D ANT_LV18

D 0201S_P28-W35
51338-0874 A3 F8 V52
M5 VDD_OK_F ANT_LV19 E7 V51 R3005
VDD_OK_H ANT_LV20 E8 V50 100K
ANT_LV21 D7 V49 C3003
TS_SCKL A6 ANT_LV22 D8 V48 0.1u 10V
SCLK ANT_LV23 0201S_P33-W39
TS_SD8 A5 D5 U3001
TS_SD9 B4 A5_SSI_D0 RESERVED_GND1 D6
TS_SD10 B3 A5_SSI_D1 RESERVED_GND2 C6 14
A5_SSI_D2 RESERVED_GND3 VCC GND
TS_SD11 A4 G Q3002
A5_SSI_D3 [10,65] PCH_VDD_PANEL_EN EDP_SPI_CS_R#
K3 2 3 R3009 33

50 pin Flex Breakout RESERVED_NC1 [21,30] TS_SPI_CS# 1A 1Y EDP_SPI_CS# [57]

C5
RESERVED_NC2 C4 1

S
RESERVED_NC3 1OE
A
80 pin Flex Breakout B6
GND ATB
C7 TS_AYALON2_ATB TP3005
GND
[21,30] TS_SPI_MISO
5

4
2A 2Y
6 EDP_SPI_MISO_R R3008 33 EDP_SPI_MISO [57]
A

2OE
DS-A5048_82BGA Add underfill
9 8 EDP_SPI_INT_R# R3010 33
[20,30] TS_IRQ_1V8# 3A 3Y EDP_SPI_INT# [57]
10
3OE
12 11 EDP_SPI_CLK_R R3007 33
[21,30] TS_SPI_CLK 4A 4Y EDP_SPI_CLK [57]
13
4OE
7
15 GND
EPAD
74LVC125ABQ

GND

Title: Touch Con & Key

Engineer: <OrgAddr1>
Size Project Name Rev
A1 1.00
EDAN_A_EV1
Date: Tuesday, May 21, 2019 Sheet 30 of 82
5 4 3 2 1
 5 4 3 2 1

+1P8VA

+3P3VAS_SIL to silego
PWRBTN#_3V3 [58,74]
R3104
100K +1P8VA
R3109 0201S_P28-W35
100K DNP Power Button Filter DNP
0201S_P28-W35 0 R3105 R3108
100K ALL
Q3101 0201S_P28-W35
R3107
D D S D
PWRBTN#_1V8 [18,33,34]

100 SOTFL-3_1P3XP9XP55_P4
X865865-001 Prevent SAM IO leakage when sysoff

G
A1
Uses Lynx Debug ATM
SW3103 D3102 C3108 C3104
DBG_D 0.1u 1000p +1P8VA
V5.5MLA0402NR

A2
2 1
CDS2C05GTA
4 N-O 3
GND
5
6

GND
GND GND

GND PWRBTN#_1V8_FILT [76]

TP3101

TP3107

C +1P8VSB C

R3103
4.7K

Volume Up Button Filter VOL_UP# [25,33]

R3101

Uses Lynx Debug ATM 100

A1

SW3101 D3104
DBG_D
V5.5MLA0402NR C3107 C3103
A2

2 1 0.1u 1000p
CDS2C05GTA
4 N-O 3
GND
5
6

GND GND GND

B B

VOL_UP#_FILT [76]
GND

+1P8VSB

R3102
4.7K

Volume Down Button Filter

VOL_DOWN# [25,33]
R3106

100
A1

Uses Lynx Debug ATM

A SW3104 D3103 C3105 A
DBG_D 0.1u
V5.5MLA0402NR C3109 Report errors to Steven
A2

2 1 CDS2C05GTA 1000p
4 N-O 3

WxH 422 x 273 mm

GND
Title:Button & Diagnostic Conn
5
6

GND GND GND Engineer: <OrgAddr1>

Size Project Name Rev
VOL_DOWN#_FILT [76] Custom 1.00
GND
Date: Tuesday, May 21, 2019 Sheet 31 of 82
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

W x H 332 x 215 mm
Cethera Title:
Sensor Connection
Engineer: <OrgAddr1>
Size Project Name Rev
A2 EDAN_A_EV1 1.00
Date: Tuesday, May 21, 2019 Sheet 32 of 82
5 4 3 2 1
 5 4 3 2 1

J3302
2 1
[29,34,76] SAM_SWD_CLK 2 1
4 3
[29,34,58,76] SAM_RESET# LTE_JTAG_TCK 6 4 3 SAM_SWD_DIO [29,34,76]
TP3307 5
LTE_JTAG_TDO 8 6 5 LTE_JTAG_TDI SAM_SWD_SWO [29,34,76]
TP3306 7 TP3302
10 8 7 9 LTE_JTAG_TMS TP3305
[29,34,71,76] SAM_DBG_TX 10 9
12 11
[25,29,76] PCH_DBG_RX 12 11 SAM_DBG_RX [29,34,71,76]
D 14 13 D
[25,29,34] PCHTX_SAMRX 14 13 PCH_DBG_TX [25,29,76]
16 15
[29,30] TS_TCK_1V8 16 15 SAMTX_PCHRX [25,29,34]
18 17
[29,30] TS_TDO_1V8 18 17 TS_TDI_1V8 [29,30]
20 19
[35,66] IMVP_SCL_P 20 19 TS_TMS_1V8 [29,30]
22 21
[25,28,76] PMI_I2C_SCL 22 21 IMVP_SDA_P [35,66]
24 23
24 23 PMI_I2C_SDA [25,28,76]

DEBUG CONN
26 25
[35,70] POWER_SMB_SDA 26 25 POWER_SMB_SCL [35,70]
28 27
[29,74] SAM_KIP_UART_RX_DBG 28 27 SAM_KIP_UART_TX_DBG [29,74]
30 29
[25,31] VOL_UP# 30 29 BAT_SHUTDOWN# [58,70,76]
+3P3VSB 32 31
32 31 VOL_DOWN# [25,31]
34 33
[22,34,60] SLP_S4# 34 33 SLP_S3# [22,34,58]
36 35
[10,34] PCH_CATERR#_1V8 36 35 SLP_A# [22,34]
38 37
[18,22] PCH_SYS_RST# 38 37 PWRBTN#_1V8 [18,31,34]
40 39
[22,56,60,62] CPU_C10_GATE# 40 39 SLP_S0# [22,34]
[18,29,35,79] SAM_PD_SDA 42 41
44 42 41 43 SAM_PD_SCL [18,29,35,79]
[20,50] CNV_RF_RESET# 46 44 43 45
[25,57] PANEL_I2C_SCL 48 46 45 47 MODEM_CLKREQ [20,50]
[24,50] BT_DISABLE# 50 48 47 49 PANEL_I2C_SDA [25,57]
52 50 49 51 WLAN_DISABLE# [24,50]
54 52 51 53 1.27mm
[35,76] PIO5_20 54 53 PIO5_21 [35,76]
C 56 55 C
[35,39] SAM_SEN_SDA 56 55 SAM_SEN_SCL [35,39]
RFU (LTE_UART_RX in Carmel DF) 58 57 RFU (LTE_UART_TX in Carmel DF)
[25,29,34,76] SAMRTS_PCHCTS 58 57 PCHRTS_SAMCTS [25,29,34,76]
60 59
[22,34,38,44] PLT_RST_BUF# 62 60 59 61 H_PROCHOT_1P8V# [10,34] +3P3VSB +3P3VA +5VSB +1P8VA
[33,35] SAM_LED1# 64 62 61 63 SAM_LED0# [33,35]
+5VSB 64 63 PCH_DEBUG_GPP_H23 [23]
+1P8VA 66 65 +3P3VA
68 66 65 67
[58,76] FPC_DET_LOGIC_OVERRIDE# 68 67 LTE_JTAG_SRST# TPANEL_RST# [25,30,35]
70 69 TP3303 C3302 C3301 C3304 C3305
70 69 10V 0.1u 10V 0.1u 10V 0.1u 10V 0.1u
72 71 0201 0201 0201 0201
MTG2 MTG1 DBG_D DBG_D DBG_D DBG_D

DBG_D
GND
GND

B
+3P3VA +3P3VA B

R3301 R3302
1K 1K
0201S_P28-W35 0201S_P28-W35
DBG_D DBG_D

LED_R_A LED_O_A
A

A
D3302
Green FW Debug LED Orange
Heartbeat LED DBG_D
D3301
LED_1P1XP6XP6
K

K
DBG_D

[33,35] SAM_LED1#
A [33,35] SAM_LED0# <Core Design> A

W x H 337 x 218 mm
LOW = LED ON LOW = LED ON Title: Debug Conn
<OrgName> Engineer: <OrgAddr1>
Size Project Name Rev
Custom EDAN_A_EV1 1.00
Date: Tuesday, May 21, 2019 Sheet 33 of 82
5 4 3 2 1
 5 4 3 2 1

System Configuration ID TBD

Aggregator
Module +1P8V_SAM +1P8V_SAM +1P8V_SAM +1P8V_SAM

R3402 R3403 R3404 R3405

2K 2K 2K 2K

CFG_ID_THOS
[35] CFG_ID_THOS CFG_ID_HUNS
[35] CFG_ID_HUNS CFG_ID_TENS
CFG_ID_ONES

D D
ADC_RD_EN
PM_+1P8V_SAM+ [28]
R3406 R3407 R3408 R3409
301 402 121 0
TBL3400 TBL3400 TBL3400 TBL3400
10u C3411

CFG_ID_HUNS_EN
PM_+1P8V_SAM- [28]

CFG_ID_THOS_EN

CFG_ID_ONES_EN
CFG_ID_TENS_EN
TP3434
DBG_T TP3435
+1P8V_SAM TP3436
R3413 TP3437
0
47 TP3438

D CFG_ID_EN
DBG_T R3412
DBG_T C3405 C3413 C3406 C3414 C3407 C3415 C3408 C3416 C3417 C3418 C3420 C3421 C3427 C3428
+1P8VA 0.01u 0.1u 0.01u 0.1u 0.01u 0.1u 0.01u 0.1u 0.01u 0.1u 0.01u 0.1u 0.01u 0.1u
10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V
DBG_TS 0201S_P33 0201S_P33 0201S_P33 0201S_P33 0201S_P33 0201S_P33 0201S_P33
0201S_P33-W 39 0201S_P33-W 39 0201S_P33-W 39 0201S_P33-W 39 0201S_P33-W 39 0201S_P33-W 39 0201S_P33-W 39
PMTP3400 R3411 0.2
SP-TP-C0P381
0603S_P6-W 100
PMTP3401 Q3401
SP-TP-C0P381 SOTFL-3_1P3XP9XP55_P4
G
[35,70] ADC_RD_EN
D3402 K A
U3400D C3402
N4 RB520CS3002L R3410 10u

S
VPP TP3401 6.3V
10 0402S_P7-W70
E6 0201S_P28-W 35
C3409 32KHZ_XIN L12 VDD_1 E8
D3401 RTCXIN VDD_2
+1P8V_SAM 18p F5 GND
VDD_3
1

K A 32KHZ_XOUT K11 G5 R3401

[29,33,58,76] SAM_RESET#
X3400
32.768KHZ
RTCXOUT VDD_4
VDD_5
J12
L6 C3426 C3425
10
0201S_P28-W 35
TBL 3400
RB520CS3002L VDD_6 L11 2.2u 0.01u
2

R3400 VDD_7 6.3V 10V

0201S_P39-W39 0201S_P33
10K N13 N6 1V8_SAMA +1P8VAS
R3429 RESETN VDDA
0 N11
VBAT
C3419 P6 VREFP
0.1u 18p VREFP
10V C3410 C3412 C3403
0201S_P33-W 39
B3 0.1u 2.2u
VSS_1 D7 10V 6.3V
0201S_P39-W39
VSS_2 0201S_P33-W 39
SAM_RESET#r D8
VSS_3 E11
C C3401 C3404 C
VSS_4 H5 1u 0.1u
VSS_5 J5 6.3V 10V
VSS_6 0201S_P35-W35 0201S_P33-W 39
K4 K7
XTALIN VSS_7
J4 L5
XTALOUT VSSA
LPC54S001JEV180 Rev 1B

+1P8VA

+1P8VA
C3422
1u 6.3V +1P8VA
0201S_P35-W 35 U3402
+1P8VA NX3P1108UK R3414
DNP
BGA4_2X2_P98XP98XP59_P5 0
GND A2 A1 ALL
VIN VOUT

R3421
10K
R3426 100K B2 B1
R3424 R3425 R3436 R3433 R3434 R3435 EN GND
C3430
DNP DNP 0.1u SPIFI_CS#
47K 47K 47K 47K 47K 47K [35] SAM_FLASH_EN
GND 10V
TP3432
SPIFI_Clk
U3401 TP3431
TP3429
8 1
SAM_PIO0_3 VCC CS 6 SPIFI_io0
SCLK 5
SI/SIO0 TP3428
SAM_SW D_CLK 2 SPIFI_io1
4 SO/SIO1 3
GND WP/SIO2 TP3427
B SAM_SW D_DIO 9 7 SPIFI_io2 B
MPADNC/SIO3
TP3430
SAM_PIO0_2 SPIFI_io3
SAM_PIO0_4_ISP0 MX25U1635EZUI-10G
SAM_PIO0_5_ISP1
SAM_PIO0_6_ISP2

R3415
47K

SAM_UEFIROM_SPI_MOSI [21]
SAM_UEFIROM_SPI_MISO [21]
SAM_UEFIROM_SPI_CLK [21]

[59] SUS_PW RGD_5VSB

U3400A
D6 N3 PIO1_0
TP3422 PIO0_0 PIO1_0/ADC0_6 TP3423
A1 K12FC10 TP3408
[39] FAN_TACH1 SAM_PIO0_2 PIO0_1 PIO1_1
E9 L14 TP3407
SAM_PIO0_3 A10 PIO0_2/TRST PIO1_2 J13
[76] SAM_PIO0_3 PIO0_3/TCK PIO1_3 TP3404
C8 D4
[76] SAM_PIO0_4_ISP0 PIO0_4/TMS PIO1_4 PCH_UART_RXr PD_SAM_INT# [79]
PIO0_4/5/6 used E7 E4 FC0 10 R3416
for ISP Strap [76] SAM_PIO0_5_ISP1 PIO0_5/TDI PIO1_5 PCH_UART_TXr PCHTX_SAMRX [25,29,33]
A5 G4 10 R3417
[76] SAM_PIO0_6_ISP2 PIO0_6/TDO PIO1_6 PCH_UART_RTSr SAMTX_PCHRX [25,29,33]
H12 N1 10 R3418
[22,62] SLP_SUS# PIO0_7 PIO1_7 PCH_UART_CTSr SAMRTS_PCHCTS [25,29,33,76]
H10 P8 10 R3419
[22,33] SLP_A# PIO0_8 PIO1_8 PCH_CATERR#_1V8_SAM PCHRTS_SAMCTS [25,29,33,76]
G12 K6 0 R3427
[58,66] VRM_PW RGD PIO0_9 PIO1_9 DEBUG_RXr PCH_CATERR#_1V8 [10,33]
P2 N9 FC1 R3428 10
[29,33,76] SAM_SW D_SW O PIO0_10/ADC0_0 PIO1_10 DEBUG_TXr SAM_DBG_RX [29,33,71,76]
L3 B4 R3422 10 TP3405
[29,33,76] SAM_SW D_CLK PIO0_11/ADC0_1 PIO1_11 SAM_DBG_TX [29,33,71,76]
M3 K9 TP3402
[29,33,76] SAM_SW D_DIO OD PINF11 PIO0_12/ADC0_2 PIO1_12 SEN_HALL_INT#_S [54,76] ISH_SAM_INT [25]
G10
[18,56] XDP_PRESENT# PIO0_13 PIO1_13 SL1_PSU_DET [70,76] TP3403 BLADE_UART_DBG_EN [74]
0 R3420 OD PINE13 C12
[18,21] XDP_SPI0_IO2 CFG_ID_ONES PIO0_14 PIO1_14 SEN_HALL_INT#_N [54,76]
L4 A11 PIO1_15_A11 10 R3423 TP3406
CFG_ID_TENS PIO0_15/ADC0_3 PIO1_15 PD_SAM_DBG_ACC_MODE_1V8 [37]
R3432 0 M4 B7 TP3409
[10,72] PCH_LCD_BKLT_EN PIO0_16/ADC0_4 PIO1_16 PIO1_17
E14 N12 TP3410
[58,69] VCCIN_AUX_PG PIO0_17 PIO1_17
C14 D1 PIO1_18 TP3411
[23,72] PCH_SAM_INST_ON PIO0_18 PIO1_18
R3430 0 BATEN_PULSE_SAM C6 L1 TP3412
[58,70] BATEN_PULSE PIO0_19 PIO1_19
[39] THERMAL_MODULE_DET D13 M1 KIP_UART_TX 10 R3431
PIO0_20 PIO1_20 SAM_KIP_UART_TX [74,76]
C13 N8 FC4 KIP_UART_RX 0 R3437
[10,33] H_PROCHOT_1P8V# PIO0_21 PIO1_21 SAM_KIP_UART_RX [74]
B12 P11 TP3413
A THERMAL_MODULE_DET SPIFI_CS# N7 PIO0_22 PIO1_22 M10 A
LOW: AVC PIO0_23/ADC0_11 PIO1_23 TP3414
SPIFI_io0 M7 N14
HIGH: DELTA SPIFI_io1 PIO0_24 PIO1_24 PW RBTN#_1V8 [18,31,33]
K8 M12
SPIFI_Clk PIO0_25 PIO1_25 SUS_PW RGD [59]
M13 J10
SPIFI_io3 PIO0_26 PIO1_26 PCH_SAM_INT [23]
L9 F10
SPIFI_io2 PIO0_27 PIO1_27 PCH_SAM_INT2 [23]
M9 E12
B13 PIO0_28 PIO1_28 C11
[70] BAT_DET# PIO0_29 PIO1_29 TP3418 PLT_RST_BUF# [22,33,38,44]
A2 A8 TP3419
[63] CHRG_OK PIO0_31_ADC_05 M5 PIO0_30 PIO1_30
TP3415 C5 TP3420
PIO0_31/ADC0_5 PIO1_31
SLP_S0# [22,33]
LPC54S001JEV180 Rev 1B

W x H 492 x 318 mm
SLP_S3# [22,33,58]
SLP_S4# [22,33,60] SAM Power,
Title: ADC, & Debug
<OrgName> Engineer: <OrgAddr1>
Size Project Name Rev
A2 EDAN_A_EV1 1.00
Date: Tuesday, May 21, 2019 Sheet 34 of 82
5 4 3 2 1
 5 4 3 2 1

TP3530
U3400B
P3 D12
[34] CFG_ID_HUNS PIO2_0/ADC0_7 PIO3_0 SAM_PCH_TOP_SWAP [25]
TP3503 P4 D11 R3507 0 TP3526
[34] CFG_ID_THOS PIO2_1/ADC0_8 PIO3_1
TP3501 C3 C10
[72] SAM_BKLT_CTRL_PWM PIO2_2 PIO3_2 SAM_PCH_RTC_WAKE [23] SAM_KIP_RST# [29,74]
B1 A13
[22] PM_PCH_PWROK PIO2_3 PIO3_3 ESPI_RST# [21]
D3 B11
[37] RSMRST_1v8# PIO2_4 PIO3_4 ESPI_CS# [21]
C1 B10
[20] RTCRST_CTRL PIO2_5 PIO3_5 ESPI_IO_0 [21]
D F3 C9 D
[37] SAM_PWRBTN_1v8# PIO2_6 PIO3_6 ESPI_IO_1 [21]
J2 B8
[58,65] SLP_S3_DRV# PIO2_7 PIO3_7 ESPI_CLK [21]
F4 A7
[58,60,62] SLP_S4_DRV# PIO2_8 PIO3_8 ESPI_IO_2 [21]
K2 C7
[37] SYS_PWROK_1v8 PIO2_9 PIO3_9 ESPI_IO_3 [21]
+1P8VA P1 A3
[55] VCCRTC_RST PIO2_10 PIO3_10 SAM_PCH_RSK [23]
R3523 K3 B2
[59,62,69] VSUS_ON PIO2_11 PIO3_11 SAM_PCH_LID_STATE [23]
100K R3533 499 SL_UART_RXr M2 L2
[37] SL_UART_RX_1V8 PIO2_12 PIO3_12 EXT_VOLT_ADC_EN [63]

2K

2K
0201S_P28-W35
R3532 499 SL_UART_TXr P7 FC5 H4 ADC_RD_EN [34,70]
[37] SL_UART_TX_1V8 PIO2_13 PIO3_13
L7 E3
[57] PANEL_LOGO PIO2_14 PIO3_14 FAN1_PWM_1v8 [37] SAM_SOC_JTAG_TRST# [10]
M8 D2 TP3527
[72] SAM_LCD_BKLT_EN PIO2_15 PIO3_15

R3501

R3500
L8 E1 PD_SDAr R3511 0
[65] SAM_VDD_PANEL_EN PIO2_16 PIO3_16 SAM_PD_SDA [18,29,33,79]
P10 K1 FC8 PD_SCLr R3512 0201S_P28-W350
[37] PCH_DPWROK_1v8 PIO2_17 PIO3_17 0201S_P28-W35 SAM_PD_SCL [18,29,33,79]
0 R3502 BAT_SDAr FC3 N10 M6 TP3511
[33,70] POWER_SMB_SDA PIO2_18 PIO3_18
0 0201S_P28-W35 R3503 BAT_SCLr P12 J3 SAM_3P3V_PD_EN_R R3505 0 SAM_3P3V_PD_EN [79]
[33,70] POWER_SMB_SCL PIO2_19 PIO3_19 SAM_LS_DIR1 [37]
0201S_P28-W35
P13 N2 SAM_PD_HRESET_R R3506 DNP 0
SAM_PD_HRESET [79]
[10] SAM_PROCHOT PIO2_20 PIO3_20
L10 P5
[25,30,33] TPANEL_RST# PIO2_21 PIO3_21/ADC0_9 PSU_VOLT [63]
K10 N5 +1P8VA
[29] SAM_MUX0_EN PIO2_22 PIO3_22/ADC0_10 PIO3_23 SL1_ADC [70]
M14 C2 OD PIN TP3528
[21] SAM_UEFIROM_SPI_CS# SAM_PIO2_24 PIO2_23 PIO3_23 PIO3_24
TP3505 K14 E2 OD PIN FC2 TP3529 C3501 C3502
SAM_PIO2_25 J11 PIO2_24 PIO3_24 P9 ACPRESENT_SAM 0.01u 0.01u
TP3509 PIO2_25 PIO3_25 10V 10V
H11 K5 R3513 R3514 0201S_P33 0201S_P33
[21,76] SAM_UEFIROM_EN PIO2_26 PIO3_26 SAM_PIO3_27
TP3508 H14 P14 TP3525 2K 2K
G13 PIO2_27 PIO3_27 M11 SAM_PIO3_28
[64] SAM_KBTP_PWR_EN [29] USBC_MUX0 PIO2_28 PIO3_28 TP3514
G11 L13 R3526 0
[29] USBC_MUX1 PIO2_29 PIO3_29 SAM_FLASH_EN [34]
F12 K13 R3515 0
[29] USBC_MUX2 PIO2_30 PIO3_30 SAM_SEN_SDA [33,39]
C D14 J14 FC9 R3516 0 C
[29] USBC_MUX3 PIO2_31 PIO3_31 SAM_SEN_SCL [33,39]
LPC54S001JEV180 Rev 1B R3522 0
SAM_PANEL_SDA [72]
R3524 0
SAM_PANEL_SCL [72]

IMVP_PROGRAM_ENABLE [66]
ACPRESENT_SAM [37]
TP3521

+1P8VA
+1P8VA

R3508 U3400C
10K H13 F2 TP3510 R3518 R3504
[33] SAM_LED0# PIO4_0 PIO5_16 PIO5_17
G14 F1 TP3523 2K 2K
[33] SAM_LED1# PIO4_1 PIO5_17
R3534 0 F14 G1 DNP DNP
[63] CHARGER_SDA PIO4_2 PIO5_18 SAM_PCH_INT [23]
B [63] CHARGER_SCL
R3535 0 FC6F13 PIO4_3 PIO5_19
G2
SAM_PCH_BASE [23] B
D9 G3 EXP_SDAr R3519 DNP 0
PIO4_4 PIO5_20 PIO5_20 [33,76]
E10 H1 FC7 EXP_SCLr R3520 DNP 0
PIO4_5 PIO5_21 PIO5_21 [33,76]
TP3516 D10 H2
PIO4_6 PIO5_22 SL1_UART_LS_EN# [37]
TP3517 A14 H3 TP3506
MTP3518 SAM_PIO4_8 B14 PIO4_7 PIO5_23 J1 SAM_PIO5_24
PIO4_8 PIO5_24 TP3507
TP3519 R3517 0 IMVP_SDA_P_R A12 E5
TP3502
PIO4_9 PIO5_25 KIP_LS_EN [74]
TP3520 R3525 0 IMVP_SCL_P_R B9 D5 SAM_PIO5_26 TP3504 +1P8VA
A9 PIO4_10 PIO5_26
[59] +5VSB_EN PIO4_11
A6
[33,66] IMVP_SDA_P [37] SAM_LS_DIR2 PIO4_12
B6 R3510
[33,66] IMVP_SCL_P [70] SL1_RX_SEL# PIO4_13
B5 499K
[63,79] SAM_SL1_PWR_EN PIO4_14
A4
[72,76] SL1_HPD2_EN# +5V_FAN_EN_SAM PIO4_15
R3521 0 C4
[64] +5V_FAN_EN PIO4_16
TDM_DET [54]
LPC54S001JEV180 Rev 1B

R3509
0
DNP

A A

W x H 397 x 257 mm
Title: SAM Buses
<OrgName> Engineer: <OrgAddr1>
Size Project Name Rev
Custom EDAN_A_EV1 1.00
Date: Tuesday, May 21, 2019 Sheet 35 of 82
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Title: Blank
<OrgName> Engineer: <OrgAddr1>
Size Project Name Rev
A1 EDAN_A_EV1 1.00
Date: Tuesday, May 21, 2019 Sheet 36 of 82
5 4 3 2 1
 5 4 3 2 1

+1P8VA

C3701
200K 0.1u SN74AVC2T245RSWR
R3706 10V R3700
DNP 499K U3700 +3P3VA

7 6
D VCCA VCCB D
8 5 R3719 0
[35] SL_UART_TX_1V8 A1 B1 SAM_SL1_TX [70]
9 4 R3720 0
[35] SL_UART_RX_1V8 A2 B2 SAM_SL1_RX [70]
R3740 0 10 2
[35] SAM_LS_DIR1 DIR1 OE
R3741 0 1
[35] SAM_LS_DIR2 DIR2 3
GND
C3700
200K 200K 1u
6.3V
R3701 R3702 200K 200K

R3704 R3705

DNP DNP OE "HIGH" for hi-impedance both sides

R3721 0
[35] SL1_UART_LS_EN#

R3703
C 499K C

DNP

+1P8VA
10K
R3718

+3P3VSB
10K
R3717
G

S D R3716 0
[35] FAN1_PWM_1v8 FAN1_PWM [39]

Q3703

SOTFL-3_1P3XP9XP55_P4

B B

[29,79] PD_SAM_DBG_ACC_MODE R3709 0

PD_SAM_DBG_ACC_MODE_1V8 [34]
+3P3VSB

C3713
0.1u
Series Rs to protec inputs in event SAM 6.3V
drives signals HIGH and Silego IC is not powered U3713
1
VDD GND
R3731 ALL 1K PCH_DPWROK_1v8_R 3 11
[35] PCH_DPWROK_1v8 SAM_PWRBTN_1v8#_R A0 Y0 PCH_DPWROK [22]
R3724 ALL 1K 4 10
[35] SAM_PWRBTN_1v8# SYS_PWROK_1v8# A1 Y1 SAM_PCH_PWRBTN# [10,22]
R3728 ALL 1K 5 9
[35] SYS_PWROK_1v8 ACPRESENT_SAM_R A2 Y2 SYS_PWROK [22]
R3726 ALL 1K 6 8
[35] ACPRESENT_SAM RSMRST_1V8#_R A3 Y3 RSMRST#_R SAM_PCH_ACPRESENT [22]
R3729 ALL 1K 2 12 R3727 1K
[35] RSMRST_1v8# B0 A0B0 RSMRST# [18,22]
7
GND
SLG4R42324

GND

A A

20170908sjs1428
title is: SAM Level shifters Report errors to Steven

WxH 472 x 305mm

Title: SAM Level Shifters
<OrgName> Engineer: <OrgAddr1>
Size Project Name Rev
Custom EDAN_A_EV1 1.00
Date: Tuesday, May 21, 2019 Sheet 37 of 82
5 4 3 2 1
 5 4 3 2 1

Trusted Platform Module +1P8VSB +1P8V_TPM

DBG_S
D TBL3801 R3817 0.1 D
0603S_P65-W95

PMTP3801 PMTP3802
SP-TP-C0P381 SP-TP-C0P381

+1P8V_TPM

+1P8V_TPM

TBL3801
C3807
0.1u 10V ALL
0201S_P33-W39 C3801
0.1u 10V
C 0201S_P33-W39 Neet INT Conn, May need add'l cfg for NatZ C
GND

R3808 GND
0
TBL3801
ALL DNP
C3806 C3805
U3801 0.1u 10V 0.1u 10V
0201S_P33-W39 0201S_P33-W39
R3802 15 TPM_SPI_CLK 19 1
[21] SPI_CLK SCLK VSB +1P8V_TPM
17 8 GND GND
[22,33,34,44] PLT_RST_BUF# RESET VHIO_8 22
2 VHIO_22
3 NC1
5 NC2 29 ALL
TPM_PP Z_PP_NUVO_NC NC3 SDA/GIO0 TP3803SP_TP_SMDP58
R3809 TBL3801 0 7 30 R3813
NC4 SCL/GIO1 TP3804SP_TP_SMDP58
DNP 9 18 4.99K
NC5 SPI_IRQ/GPIO2 PCH_SERIRQ [10]
C3804 10 6 0201S_P28-W35
NC6 GPIO3 TP3801SP_TP_SMDP58
22p 11 13
0201S_P33 NC7 GPIO4/SINT TP3802SP_TP_SMDP58 SPI_TPM_CS# [21]
12 20
25V 14 NC8 SCS/GPIO5 4 NUVO_PP_Z_NC R3805 TBL3801 0 TPM_PP
B NC9 PP/GPIO6 B
15 21 TPM_SPI_MOSI R3803 15
NC10 MOSI/GPIO7 SPI_MOSI [21]
GND 25 24 TPM_SPI_MISO R3801 15
NC11 MISO SPI_MISO [21]
26 DNP
27 NC12 16 R3814
28 NC13 GND1 23 4.99K
31 NC14 GND2 0201S_P28-W35
32 NC15 33
NC16 MPAD
NPCT750SABYX
M1041056-002 GND

R3804 R3806 R3807 TBL3801

GND
0 0 0
TBL3801 TBL3801 TBL3801

GND GND GND

A A

W x H 357 x 231 mm
Title: TPM
<OrgName> Engineer: <OrgAddr1>
Size Project Name Rev
Custom EDAN_A_EV1 1.00
Date: Tuesday, May 21, 2019 Sheet 38 of 82
5 4 3 2 1
 5 4 3 2 1

+5V_FAN
Imax=0.7A
Trace Width>30mil
+5V_FAN

J3901

MTG1
7 THERMAL_MODULE_DET
1
2 1 FAN Connector LOW: AAC
2
D 3
4 3 HIGH: DELTA D

+1P8VSB 5 4 +5V_FAN
C3903 6 5
22u 6.3V 6 8
MTG2

K
0603

R3906 D3901
499K 1N4148WS-R2
MTP3902 75V

A
+1P8VAS
[34] THERMAL_MODULE_DET Fan Supplier Detect

CFAN_PWM_R_1 R3903 100

FAN1_PWM [37]
0603
FAN_TACH1 [34]
D3903
+3P3V C3906
MTP3904 RB520CS3002L close to J39001
K A R3902 4.99K 0.1u +5V_FAN MTP3901 C3901
+1P8VAS +3P3VAS_SIL
0201 DNP 0.1u
MTP3903
C3907

0.1u GND R3916 R3905

100K 100K
C GND
250uA for 32conv/sec C
U3901
SAM_SEN_SCL 1 5 Q3901
SCL V+
SAM_SEN_SDA 6 3 R3904 0 TEM_DEVICE_RST# S D
SDA ALERT 0201S_P28-W35 DEVICE_RST# [58]
+1P8VAS
4 2
250uA for 32conv/sec ADD0 GND SOTFL-3_1P3XP9XP55_P4

G
U3903
SN1608035
1 5
[33,35] SAM_SEN_SCL SCL V+ +1P8VAS
6 3 R39180201S_P28-W350 TEM_DEVICE_RST#
[33,35] SAM_SEN_SDA SDA ALERT DNP
4 2
ADD0 GND Skin1
SN1608035 GND
GND

C3904
7-bit I2C Address = 0x48
0.1u
Skin4
7-bit I2C Address = 0x4A
GND +1P8VAS
250uA for 32conv/sec
U3902
SAM_SEN_SCL 1 5
B SCL V+ B
SAM_SEN_SDA 6 3 R39190201S_P28-W350 TEM_DEVICE_RST#
SDA ALERT DNP
4 2
ADD0 GND
+1P8VAS SN1608035
250uA for 32conv/sec GND
U3904 C3902
SAM_SEN_SCL 1 5
SCL V+ 0.1u
SAM_SEN_SDA 6
SDA ALERT
3 R39170201S_P28-W350 TEM_DEVICE_RST# Skin2
DNP
4
ADD0 GND
2 7-bit I2C Address = 0x49
GND
SN1608035
VDD_U3904 GND

C3905

0.1u
Skin3
7-bit I2C Address = 0x 4B
GND
temp sensor for the right location testing

A A

20170908sjs1321
title is: Temp Sensor/ System Fan

Title: Temp Sensor/System Fan

<OrgName> Engineer: <OrgAddr1>
Size Project Name Rev
A3 1.00
EDAN_A_EV1
Date: Tuesday, May 21, 2019 Sheet 39 of 82

5 4 3 2 1
 E D C B A

+1P8V_AUDIO_DVDD +1P8V_AUDIO +5V_AUDIO

+1P8V_AUDIO_DVDD 0 R4014
+5V_AUIDO_AVDD 0 R4034

C4003 C4010 10V

0.1u 10u 0402
C4029 C4020
C4015 C4013
0.1u 10u 0.1u 10u AGND AGND

GND GND GND GND

+1P8V_AUDIO

4 C4021 4
R4018 C4025
C4002 C4033 100K 10u C4022 C4008 0.1u
C4016 C4023 10u
10u 0.1u 0.1u 10u 0.1u
U4009 DNP
H11 GND GND
DVDD F1 AGND AGND AGND AGND
DVDD_IO AGND AGND AGND
C8
PCBEEP C12
AVDD1
E4 D3 +5VSB +5V_AUDIO
[20] MHDA_SDOUT SDATA_OUT AVDD2
D5 A12 CODEC_LDO1
[20] MHDA_SYNC SYNC LDO1_CAP CODEC_LDO2
D1
R4003 22 E6 LDO2_CAP E2 CODEC_LDO3 R4036 R4035
[20] MHDA_BCLK BCLK LDO3_CAP
10K 10K
HPOUT_JD_R D7 D11 DNP
C4006 JD1 VREF
22p F11 A8 ALC3260_VD5STB
+1P8V_AUDIO DNP JD2 5VSTB
G10 B5 CPVEE
100K R4019 [54,76] DMIC_CLK_CODEC GPIO1/DMIC_CLK CPVEE AUDIO_VREF
GND F9
[54,76] DMIC_DATA1_CODEC GPIO0/DMIC_DATA12 B3 C4001
HPVDD C4030 C4019
200K R4006 2.2u 0.1u 2.2u
[41,76] HPOUT_JD
A6
HPOUT_L HPOUT_L [41]
E12 A4
[42] CODEC_AMP_OUTL LINE2_L HPOUT_R HPOUT_R [41]
E10 AGND AGND AGND
[42] CODEC_AMP_OUTR LINE2_R +1P8V_AUDIO_DVDD
C4026
G2 SDATA_IN_R R4004 22
0.1u SDATA_IN MHDA_SDIN [20]
B9
[41] HP_MIC_L MIC2_L/RING2
ALL A10 R4001
[41] HP_MIC_R MIC2_R/SLEEVE C6 10K
MIC2_VREFO_L HP_MIC_VREFO_L [41]
AGND H9 B7
[41] COMBO_JACK GPIO2/I2S_EN/SPDIF_OUT/DMIC_DATA34 MIC2_VREFO_R
G6 F3
I2S_BCLK EAPD CODEC_PD_N [42]
D9 G12 R4002 10K
3 F5 I2S_IN TEST G4 3
I2S_LRCK SCAN
H7 G8
H5 I2C_CLK I2S_OUT1 F7
I2C_DATA I2S_MCLK/I2S_OUT2 GND

C10 B11
MIC2_CAP AVSS1 C2
B1 AVSS2
A2 CBP C4
C4009 2.2u CODEC_CBN1_R CBN CPGND
H3
CODEC_CBP1_R E8 DGND_1 H1
RESETB DGND_2 AGND
ALC3300-GRT
JP4001
C4017
1 2 10u
GND
0201 SHUNT
JP4002 AGND

1 2

0201 SHUNT

JP4003
1 2

0201 SHUNT

GND AGND

2 2

1 1

W x H 427 x 276 mm
Title: REALTEK ALC3269C_81BGA
<OrgName>
Engineer: <OrgAddr1>
Size Project Name Rev
A2 EDAN_A_EV1 1.0.0.1
Date: Tuesday, May 21, 2019 Sheet 40 of 82
E D C B A
 E D C B A

HP/MIC1 Combo Jack

[40] HP_MIC_VREFO_L

R4104 L4101 place close to CON4101

2.2K
L4101 GBK160808T-121Y
120 OHM,100MHZ
C4104 4.7u MIC1_CR R4101 1K MIC1_CR_F R4107 0 [76] HP_MIC_LR_CON This is the
[40] HP_MIC_R Lynx combo
4 4
[76] HPOUT_R_CON jack.
Schematic
[76] HPOUT_L_CON symbol is only
C4105 4.7u R4105 used for the
[40] HP_MIC_L
22K C4103 GND AGND footprint
100p (Screw on
C4107 connector). DNP
Therefore, it
is DNP. J4103
4700p
1
MIC
AGND AGND
AGND 3
RIGHT
R4106 22K 4
[40] COMBO_JACK DET
5
LEFT
C4106 R4102 10 HPOUT_L_F L4102 GBK160808T-121Y 2
[40] HPOUT_L 120 OHM,100MHZ GND
10u
R4103 10 HPOUT_R_F GBK160808T-121Y
[40] HPOUT_R 120 OHM,100MHZ
L4103
AGND

A2

A2

A2
AGND R4110 R4111
10K 10K D4104 D4102 D4103

V5.5MLA0402NR
V5.5MLA0402NR
V5.5MLA0402NR C4108
3 3

A1

A1

A1
C4101 C4102 CDS2C05GTA CDS2C05GTA CDS2C05GTA 100p
AGND AGND 100p 100p

AGND AGND GND GND GND GND

[40,76] HPOUT_JD

A2
D4101
CDS2C05GTA
V5.5MLA0402NR

A1
GND

[76] SPK_L+_CON LYNX Speaker Connector

J4101

CONN_B2B_2-X872411-001
X872411-001
R4114 0 SPK_L+_CON 1
2 [42] SPK_L+ 1 2

2
2
C4121 SPK_L-_CON
1000p 3
MTG1

A1
D4105 4
MTG2

A1
GND D4106
V18MLA0402NR
C4122 V18MLA0402NR

A2
R4115 0 1000p GND
[42] SPK_L-

A2
LYNX Speaker Connector
[76] SPK_L-_CON

GND
[76] SPK_R+_CON
GND J4102

CONN_B2B_2-X872411-001
X872411-001
R4116 0 SPK_R+_CON 1
[42] SPK_R+ 1
2
2
C4123 SPK_R-_CON
1000p 3
MTG1

A1

A1
D4108 D4107 4
MTG2
GND
V18MLA0402NR V18MLA0402NR
1 C4124 GND 1

A2

A2
R4117 0 1000p
[42] SPK_R- [76] SPK_R-_CON

Title: Universal Jack / Speaker HDR /DMIC HDR

GND GND <OrgAddr1>
<OrgName> Engineer:
Size Project Name Rev
Custom EDAN_A_EV1 1.00
Date: Tuesday, May 21, 2019 Sheet 41 of 82
E D C B A
 5 4 3 2 1

+VSYS R4224
E1 SENS E2
PTP4203 PTP4204
I1 I2
Inductor may be changed based on placement constraints
L4201
LOAD +V_AUDIOBOOST R4210 R4212
U4202 0.01
R4215 0.02 11 6 DBG_S
C4223 SW VOUT
1.5uH 0.1u 10 3 VBOOST_FB R4221 DNP 681K
DNP
C4221 DBG_D 0201 VBOOST_BOOT BOOT FB
22u R4219 150K VBOOST_FSW 1 4 VBOOST_COMP C4225 C4226 C4222
DBG_D FSW COMP
25V R4222 22u 22u 22u
D DBG_D DBG_D 9 8VBOOST_ILIM 100K 25V 25V 25V D
VIN ILIM R4218 DBG_D DBG_D DBG_D
CODEC_PD_N R4223 DNP 0 VBOOST_EN 7 4.99K
EN R4220 C4220
VBOOST_VCC 2 DBG_D
R4225 5 127K
PTP4202 100K VCC GND 10p C4224
DBG_D
C4227 TPS61089RN
DNP
PTP4201 DBG_D 0.01u
DBG_D
2.2u Peak current at 3A Need to confirm with TI for compensation
DBG_D Switching frequency set to roughly 1 MHz
DBG_D boost output voltage = 9.375V
DBG_D 15dB
SPK_L- [41]
SPK_L+ [41]
SPK_R+ [41]
SPK_R- [41]
OUTPR OUTNR OUTNL OUTPL

R4211 C4212 C4201 R4202 R4203 C4218 C4214 R4204

0201 0201 330p

10 330p 330p 10 10 330p 10
0201 0201 0201 Close IC Close IC 0201 0201 0201 15dB
25V 25V 25V 25V

C4219 C4210 C4206 C4208

0.33u 0.33u 0.33u 0.33u

C Close IC 0201 0201 0201 0201 Close IC C
25V 25V 25V 25V
+V_AUDIOBOOST AMP_VCC

24

23

22

21

20

19

18

17
AMP_VCC

BSNL

OUTNL
GND

OUTNR

BSNR

GND

GND

GND
AMP_VCC AMP_VCC

25
OUTPR 16
C4217 OUTPL C4202
10u C4207 C4213 26 C4204 C4205 10u
0603 BSPR 15 0603
0.1u 1000p BSPL 1000p 0.1u
16V 0201 0201 0201 0201 16V
16V 25V 27 25V 16V
PVCC 14
+1P8V_AUDIO
Close IC Shut-down Control PVCC Close IC
U4201
Hi : Normal 28
+5V_AUDIO Low: shut-down PVCC ALC1304 13
PVCC AM Avoidance Setting
R4205 100K AMP_PD_N 29
R4201 0201 SDZ 12 GVDD
10K AVCC
0201 30 R4213
FAULTZ 11
Sync 10K
0201
31 DNP
INPR
G

10
AM0
B 32 B
S D
[40] CODEC_PD_N INNR 9 R4209
C4216 AM1 R4214

PBTL/BTL
10K
Gain/SLV
0.1u 33 10K 0201
EPAD
GVDD

MUTE
0201 C4209 BTL/PBTL Setting 0201
Plimit

Q4201

INNL

INPL
16V GND DNP
[40] CODEC_AMP_OUTR 0.1u
0201 R4217
16V 10K
1

8
0201
DNP R4208
10K
R4216 10K GVDD AGND Gain/SLV Setting 0201
0201
C4203 R4207
R4206 C4215 0.1u 10K
AGND 0 1u 0201 C4211 R4210 0201
0201 0201 16V 0.1u 54.9K
DNP 10V 0201 0201
Close IC 16V
GAIN / SLV

AGND CODEC_AMP_OUTL [40]

AGND
R4212
34.8K
0201

A A
AGND
AGND

Title: ALC1304 AMP

<OrgName> Engineer: <OrgAddr1>
Size Project Name Rev
A3 EDAN_A_EV1 1.00
Date: Tuesday, May 21, 2019 Sheet 42 of 82
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

W x H 737 x 477 mm
Title:
<OrgName> Engineer:
<OrgAddr1>
Size Project Name Rev
Custom EDAN_A_EV1 1.00
Date: Tuesday, May 21, 2019 Sheet 43 of 82
5 4 3 2 1
 5 4 3 2 1

2 1 PCIECLK_SSD_N_F
[20] M2_PCIECLK_N
3 4 DLP11TB800UL2L PCIECLK_SSD_P_F
[20] M2_PCIECLK_P
L4402

2 3
1 4
RN4405 DNP 0

D D

2 1 PCIE_SSD_TN1_F
C4414 0.22u PCIE_SSD_TN1_C C4410 0.22u PCIE_SSD_TN2_C 2 1 PCIE_SSD_TN2_F
[24] PCIE_SSD_TX1_DN [24] PCIE_SSD_TX2_DN
3 4 DLP11TB800UL2L PCIE_SSD_TP1_F
C4404 0.22u PCIE_SSD_TP1_C L4403 C4415 0.22u PCIE_SSD_TP2_C 3 4 DLP11TB800UL2L PCIE_SSD_TP2_F
[24] PCIE_SSD_TX1_DP [24] PCIE_SSD_TX2_DP
L4401
2 3
1 4 2 3
RN4403 DNP 0 1 4
RN4404 DNP 0

C4406 0.22u PCIE_SSD_TN0_C 2 1 PCIE_SSD_TN0_F

[24] PCIE_SSD_TX0_DN PCIE_SSD_TN3_C PCIE_SSD_TN3_F
C4405 0.22u 2 1
[24] PCIE_SSD_TX3_DN
C4408 0.22u PCIE_SSD_TP0_C 3 4 DLP11TB800UL2L PCIE_SSD_TP0_F
[24] PCIE_SSD_TX0_DP
L4404 C4409 0.22u PCIE_SSD_TP3_C 3 4 DLP11TB800UL2L PCIE_SSD_TP3_F
[24] PCIE_SSD_TX3_DP
L4405
2 3
1 4 2 3
RN4402 DNP 0 1 4
RN4401 DNP 0

+3P3VAS_SIL

R4419
1M
+3P3VSB 0201
1%
CON4401
+3P3V_SSD_CON 74 75 R4417 0
3.3V_1 GND1 DET_A# [58]
72 73
70 3.3V_2 GND2 71
C C4402 68 3.3V_3 GND3 69 C
C4407 SUSCLK(32KHZ) PEDET(NC-PCIE/GND-SATA) 67
NC22

K
0.1u C4413 C4416 C4417
R4412 47u 0.1u 100p 10p D4401
100K
DNP GND
Connector Key
GND GND GND GND NO PINS

A
+3P3V_SSD_CON
U4401 58 57
5 R4416 10K 56 NC1 GND4 55 PCIECLK_SSD_P_C R4408 0 PCIECLK_SSD_P_F
VCC GND NC2 REFCLKP
1 PESD3V3U1UL315 54 53 PCIECLK_SSD_N_C R4415 0 PCIECLK_SSD_N_F
[22,33,34,38] PLT_RST_BUF# A PEWAKE#/NC3 REFCLKN
2 4 52 51
[10] PCIE_SSD_PERST# B O [20] M2_PCIECLK_REQ# SSD_RESET_N CLKREQ#/NC4 GND5 PCIE_SSD_TP0_F
50 49
3 48 PERST#/NC5 PETP0/SATA-A+ 47 PCIE_SSD_TN0_F
GND 46 NC6 PETN0/SATA-A- 45
SN74LV1T08DCKR 44 NC7 GND6 43 PCIE_SSD_RP0_C R4402 0
NC8 PERP0/SATA-B- PCIE_SSD_RN0_C PCIE_SSD_RX0_DP [24]
ALL R4407 42 41 R4409 0
NC9 PERN0/SATA-B+ PCIE_SSD_RX0_DN [24]
100K 40 39
GND 38 NC10 GND7 37 PCIE_SSD_TP1_F
DNP 36 DEVSLP PETP1 35 PCIE_SSD_TN1_F
R4406 DNP 0 34 NC11 PETN1 33
32 NC12 GND8 31 PCIE_SSD_RP1_C R4403 0
NC13 PERP1 PCIE_SSD_RN1_C PCIE_SSD_RX1_DP [24]
30 29 R4401 0
NC14 PERN1 PCIE_SSD_RX1_DN [24]
GND 28 27
26 NC15 GND9 25 PCIE_SSD_TP2_F
+3P3V_SSD_CON 24 NC16 PETP2 23 PCIE_SSD_TN2_F
22 NC17 PETN2 21 +3P3VAS_SIL
20 NC18 GND10 19 PCIE_SSD_RP2_C R4410 0
NC19 PERP2 PCIE_SSD_RN2_C PCIE_SSD_RX2_DP [24]
18 17 R4411 0
3.3V_4 PERN2 PCIE_SSD_RX2_DN [24]
16 15 R4420
14 3.3V_5 GND11 13 PCIE_SSD_TP3_F
12 3.3V_6 PETP3 11 PCIE_SSD_TN3_F 1M
10 3.3V_7 PETN3 9 0201
8 DAS/DSS#/LED1# GND12 7 PCIE_SSD_RP3_C R4404 0 1%
NC20 PERP3 PCIE_SSD_RN3_C PCIE_SSD_RX3_DP [24]
6 5 R4405 0
NC21 PERN3 PCIE_SSD_RX3_DN [24]
4 3
2 3.3V_8 GND13 1 R4418 0
3.3V_9 GND14 DET_B# [58]
76 77
C4411 78 MTG1 MTG2 79
C4403 C4401 C4412 80 MTG3 MTG4 81
MTG5 MTG6
K2

K2

B 47u 0.1u 100p 10p 82 83 B

D4421 D4422 84 MTG7 MTG8 85
86 MTG9 MTG10 87
GND GND GND 88 MTG11 MTG12 89
GND PESD5V0H1BSF
PESD5V0H1BSF MTG13 MTG14

K2

K2

K2

K2

K2

K2

K2

K2

K2

K2

K2

K2

K2

K2

K2

K2

K2

K2

K2

K2
90 91
92 MTG15 MTG16 D4420 D4402 D4403 D4404 D4405 D4406 D4407 D4408 D4409 D4410 D4411 D4412 D4413 D4414 D4415 D4416 D4417 D4418 D4419 D4423
MTG17
K1

K1

M1108459-002 PESD5V0H1BSF
PESD5V0H1BSF
PESD5V0H1BSF
PESD5V0H1BSF
PESD5V0H1BSF
PESD5V0H1BSF
PESD5V0H1BSF
PESD5V0H1BSF
PESD5V0H1BSF
PESD5V0H1BSF
PESD5V0H1BSF
PESD5V0H1BSF
PESD5V0H1BSF
PESD5V0H1BSF
PESD5V0H1BSF
PESD5V0H1BSF
PESD5V0H1BSF
PESD5V0H1BSF
PESD5V0H1BSF
PESD5V0H1BSF

K1

K1

K1

K1

K1

K1

K1

K1

K1

K1

K1

K1

K1

K1

K1

K1

K1

K1

K1

K1
GND
GND

GND
GND

A A

M.2 SSD CONNECTOR

Title:
<OrgName> Engineer: <OrgAddr1>
Size Project Name Rev
A2 EDAN_A_EV1 1.00
Date: Tuesday, May 21, 2019 Sheet 44 of 82
5 4 3 2 1
 5 4 3 2 1

E E

+3P3VSB

R4510
10V 10K +5VSB
C4504 0.1u
[24] USB3_USBA_TX_DN C4514 C4507
[24] USB3_USBA_TX_DP 10u 0.1u
C4526 0.1u R4536
U4503 10V 10V E1 E2
10V PMTP4504 SENS PMTP4503 J4501
3 6 GND GND CON2_VBUS
[24] USB3_USBA_RX_DN [24] USBA_OVCUR# 4 FLAG# IN I1 I2 21
0.01
[24] USB3_USBA_RX_DP [10] USBA_EN 5 EN 1 1 MTG12 20
D GND1 OUT LOAD VBUS MTG11 D

K
7 2 2 19
[24] USB2_USBA_DN GND2 C4505
ILIM + 3 Dm MTG10 18
R4501 C4517 DBG_S
[24] USB2_USBA_DP 0.1u Dp MTG9
90 Ohm, Differential Pair 499K NCP380HMUAJAATBG 150u D4504 4 17
GND GND MTG8
ALL R4520 10V 5 16
6 StdA_SSRXm MTG7 15

A
11.5K GND StdA_SSRXp MTG6
GND 7 14
0201 GND GND_DRAIN MTG5
GND GND 8 13
GND 1% GND 9 StdA_SSTXm MTG4 12
StdA_SSTXp MTG3 11
U4503 Min VIH = 1.2V MTG2 10
MTG1

M1015489-005
R = 11.5 K
I(Max) = 2.05 A
I(Typ) = 1.78 A [76] USB2_USBA_DN_CONN
[76] USB2_USBA_DP_CONN
I(Min) = 1.5 A GND

D4503
A1 DP_O DP_I A2
B1 DM_I B2
DM_O C2
ID 90 Ohm, Differential Pair
C1
GND
GND

USB3_USBA_TX_DN_C 4 3 USB3_USBA_TX_DN_CONN
0nH
USB3_USBA_TX_DP_C 1 2 USB3_USBA_TX_DP_CONN
L4506

90 Ohm, Differential Pair

C C

K1

K1

K1

K1
D4509 D4510 D4511 D4512
PESD5V0H1BSF PESD5V0H1BSF PESD5V0H1BSF PESD5V0H1BSF

K2

K2

K2

K2
GND

B B

A A

Title: USB3.0 Port

<OrgName> Engineer: <OrgAddr1>
Size Project Name Rev
A1 EDAN_A_EV1 1.00
Date: Tuesday, May 21, 2019 Sheet 45 of 82
5 4 3 2 1
 5 4 3 2 1

D D

+3P3V
+3P3V +3P3V

R4606 R4607 U4601 R4602

2.2K 2.2K TS3USB30E +3P3VSB 100K
0201S_P3 0201S_P3 qfn10_1p8x1p4xp55_p4mm 0201S_P28-W35
0201S_P33-W39 9
C4603 0.1u 10V 1 VCC
[10] SLDP_AUX_DP
2 D1+ 3
[10] SLDP_CTRL_CLK D2+ D+ SL_AUX_DP [71]
C 0201S_P33-W39 C
C4602 0.1u 10V 7
[10] SLDP_AUX_DN D1-
6 5
[10] SLDP_CTRL_DATA D2- D- SL_AUX_DN [71]
10
[71] SL1_CONFIG1 8 S 4 C4608
C4605 +3P3VSB OE GND 0.1u 10V C4604 C4601 R4605

0201S_P35-W35
0.1uF DNP 0201S_P33-W390.1u 0.1u 100K
25V R4601 10K SL1_DP_EN GND 0201S_P28-W35
DNP DNP
0201S_P28-W35
GND
R4616 GND GND
GND 0 GND
0201S_P28-W35

GND

B
TS3USB30E B

EN S Connection
L L AUX for DP [D1 to D]
L H DDC for HDMI [D2 to D]
H X HI-Z

A A

W x H 337 x 218 mm
Title: DP Dongle Control
<OrgName> Engineer: <OrgAddr1>
Size Project Name Rev
A4 EDAN_A_EV1 1.00
Date: Tuesday, May 21, 2019 Sheet 46 of 82
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

W x H 392 x 254 mm
Title: mDP
<OrgName> Engineer: <OrgAddr1>
Size Project Name Rev
Custom EDAN_A_EV1 1.00
Date: Tuesday, May 21, 2019 Sheet 47 of 82
5 4 3 2 1
 5 4 3 2 1

E E

D D

C C

B B

A A

<Core Design>

uSD
This drawing contains information which is proprietary of Microsoft Corporation. This drawing is received
in confidence and its contents may not be disclosed without the prior written consent of Microsoft Corp.

Date: Tuesday, May 21, 2019 Engineer: <OrgName> Sheet 48 of 82 Rev

5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

W x H 402 x 260 mm
Title: Camera IR
<OrgName> Engineer: <OrgAddr1>
Size Project Name Rev
Custom EDAN_A_EV1 2.89.6
Date: Tuesday, May 21, 2019 Sheet 49 of 82
5 4 3 2 1
 5 4 3 2 1

+1V8_HRP_PMU_GPIO_LDO_OUT

C5019
10%
U5001B 0.1u
HrP_MS_BT
J16
VDD1V8_BT_OTA_BIAS
LAYOUT NOTE: H17 +1P8V_WIFI_FLTR
WIFI*D50 and WIFI*S50 routed with impedance control WiFi Harrison Peak VDD1V8_BT_RF

VSS_BT_PA
G16 L5007
+1P8V_RADIO

Non-50-Ohm System -> Follow Intel Layout H15

VSS_BT_1 1800Ohm@100MHz
K15 0402
VSS_BT_2 C5020 C5021
BT ON CHA LB 2 OF 8 M1045895-001
0.1u 22u
AX-WCS22560 B3 6.3V 10% 6.3V 20%
Filters and switches need to be reviewed by RF team and ME M1072227-003 X811795-001 0603
X869827-001
U5001C
HrP_MS_WIFI_CHA L5001
A17 A15 WIFI_HB_CHA_P_D50 2 1 WIFI_HB_CHA_S50
VSS_WIFI_TX_PA_CHA_1 WIFI_HB_RF_CHA_P A16 WIFI_HB_CHA_N_D50 B2 UB1
B15 WIFI_HB_RF_CHA_N
VSS_WIFI_TX_PA_CHA_2 J5003
D B16 U5003 D
VSS_WIFI_TX_PA_CHA_3 C17 WIFI_LB_CHA_P_D50 3 4 1 CONN_COAX_4_2P1X2X1P0MM
C16 WIFI_LB_BT_CHA_P D17 WIFI_LB_CHA_N_D50 B3 GND H-BAND PROBE CR5002
VSS_WIFI_TX_MX_CHA WIFI_LB_BT_CHA_N LDM155G4205FC009 5 R5006 0 WIFI_DIPLEX_CHA_D_S50 1 2 WIFI_CHA_ANT1_S50 SIG
CMN-PORT IN OUT
M1045933-001
3 C5003 0201 4 3
E16 B14 L5002 L-BAND 2 C5048 GND4 GND3
VSS_WIFI_RX_CHA_1 VDD1V8_WIFI_TX_MX_CHA 2 1 WIFI_LB_CHA_S50 GND2 4 DNP 0.2p
B2 UB1 GND4

A1
F15 B17 6 DNP 0.2p D5005 GND 2,3,4
X867338-001
VSS_WIFI_RX_CHA_2 VDD1V8_WIFI_TX_PA_CHA GND6
G14 F17 C5047 LFD212G45DS8D893
VSS_WIFI_RX_CHA_3 VDD1V8_WIFI_RX_CHA
M1064609-001

A2
D15 E12 3 4 DNP 0.2p
VSS_WIFI_ADC_CHA VDD1V8_WIFI_ADC_CHA B3 GND
GND
+1P8V_RADIO +1P8V_RADIO LDM152G4505FC011
3 OF 8
M1045932-001
AX-WCS22560 B3 DIO_0402_P33MM-AA Right antenna connector
M1072227-003 X935756-001
LXES15AAA1-153 J5001

CONN_COAX_4_2P1X2X1P0MM
C5001 C5002 C5045 TP5013 PROBE
BOT_COAX_NET 1 2
2.2u 2.2u 100p IN OUT
20% 4V 0402 Single Pad 4 3
X892237-001 GND4 GND3

X867338-001
DNP
J5001 added for bottom side study

Non-50-Ohm System -> Follow Intel Layout

U5001D
HrP_MS_WIFI_CHB L5003
A1 A3 WIFI_HB_CHB_P_D50 2 1 WIFI_HB_CHB_S50
VSS_WIFI_TX_PA_CHB_1 WIFI_HB_RF_CHB_P A2 WIFI_HB_CHB_N_D50 B2 UB1 J5004
A4 WIFI_HB_RF_CHB_N U5004
VSS_WIFI_TX_PA_CHB_2 3 CONN_COAX_4_2P1X2X1P0MM
B2 HB 5.6p C5044 PROBE MP5004
VSS_WIFI_TX_PA_CHB_3 3 4 5 WIFI_PROBE_CHB_S50 1 2 WIFI_CHB_ANT1_S50 R5017 0 WIFI_CHB_ANT2 R5016 0 WIFI_CHB_ANT3 R5015 0 WIFI_CHB_ANT4 1 J5005 J5006 J5007
B3 B3 GND COMM IN OUT
VSS_WIFI_TX_PA_CHB_4 C1 WIFI_LB_CHB_P_D50 LDM155G4205FC009 1 4 3 0402 0402
C2 WIFI_LB_CHB_P D1 WIFI_LB_CHB_N_D50 LB 2 C5013 C5004 GND4 GND3
M1045933-001 M1075199-001
VSS_WIFI_TX_MX_CHB WIFI_LB_CHB_N GND_2 4 L5010 FCAOS14B02G1PC
GND_4

A1
L5004 6 DNP 0.2p DNP 0.2p D5006 X867338-001 L5011 FCAOS08A07G1PC FCAOS08A07G1PC FCAOS08A07G1PC

1
2 1 WIFI_LB_CHB_S50 GND_6 0.6pF
B2 UB1 0.5p
E2 B4 LFD212G45DS9D894 0402 0402 MP5005
VSS_WIFI_RX_CHB_1 VDD1V8_WIFI_TX_MX_CHB C5051 M1064610-001 DNP DNP 1

A2
F3 B1 GND GND GND
VSS_WIFI_RX_CHB_2 VDD1V8_WIFI_TX_PA_CHB DNP 0.2p GND GND
GND
F1 3 4 M1075199-001
VDD1V8_WIFI_RX_CHB B3 GND DIO_0402_P33MM-AA FCAOS14B02G1PC
GND
C D3 E6 LDM152G4505FC011 X935756-001 C
VSS_WIFI_ADC_CHB VDD1V8_WIFI_ADC_CHB LXES15AAA1-153
M1045932-001
4 OF 8 MP5006
1
AX-WCS22560 B3 +1P8V_RADIO
+1P8V_RADIO
M1072227-003
M1075199-001
GND FCAOS14B02G1PC

C5038 C5009 C5010 C5011 C5042 Left antenna spring clip

100p
25V 5% 2.2u 2.2u 2.2u 100p
X813058-001 4V 20%
X892237-001

+1P8V_RADIO
U5001A
HrP_MS_GNSS
K1
GNSS_RF_IN R5014 200
H1 U5001E WIFI_XTAL_X1 WIFI_XTAL_X1_R
VDD1V8_GNSS
HrP_MS_XTL/SYNT/BG/NTC
A7
XTL_X1 Y5001
M1 LNA_EN TP5016 B8 WIFI_XTAL_X2 1 3
VDD1V6_LNA_GNSS_LDO_VOUT XTL_X2 2 4
GND M1073240-001
U5001F 60MHz 3225
J2 R5007 HrP_MS_WIFI_TMUX C9 B6
VSS_GNSS_RF B10 VSS_XTL XO_SENS
0 WIFI_LB_EPA_DET_CHA_TM1_P
G2 A9 D10
VSS_GNSS_MS WIFI_HB_EPA_DET_CHA_TM1_N VSS_WIFI_SYNT_DPLL_VCO
1 OF 8 D8 C10
VSS_WIFI_SYNT_DPLL_RING VDD1V8_XTL_LDO +1P8V_RADIO
Confirm CNV strapping for ICL-HrP only AX-WCS22560 B3
M1072227-003
WIFI_LB_EPA_DET_CHB_TM2_P
WIFI_HB_EPA_DET_CHB_TM2_N
A14
B12
C8
VSS_WIFI_SYNT_DPLL_TDC VDD1V8_WIFI_BG
G4

G8 A11
VSS_WIFI_BG VDD1V8_WIFI_SYNT_DPLL_CORE

+1V8_HRP_PMU_GPIO_LDO_OUT
5 OF 8
G10 C5022 C5023
WIFI_ADC_ANATST_CLK AX-WCS22560 B3 2.2u 4.7u
U5001H 4V 20% 6.3V 10%
LAYOUT NOTE:
M1072227-003
HrP_MS_JFP DIGITAL X892237-001 0603 PLACE C5022 at A11
P3 T9 E9 X809153-001
POWER_GOOD DIG_BRI_DT CNV_BRI_DT [23] VDD1V8_WIFI_OTA
M15 P10 CNV_BRI_RSP_HRP R5010 22
PLACE 4.7UF C5023 as close as possible to A11
DIG_VPP_OTP DIG_BRI_RSP CNV_BRI_RSP [23] 6 OF 8
AX-WCS22560 B3 +3P3V_WWAN_RADIO
M1072227-003
L2 N2 20.57mOhm C5025
DIG_SPI_DI DIG_RGI_DT CNV_RGI_DT [23]
2.7A 4.7u 0402
M3 P1 CNV_RGI_RSP_HRP R5011 22 6.3V 20% +1P8V_RADIO
B DIG_SPI_CLK DIG_RGI_RSP CNV_RGI_RSP [23] L5008 B
CLKREQ used for init C5024 C5040 X855058-001
H3 TP5005 U5001G 10u +1P8V_RADIO_CAP
+3P3V_WWAN_RADIO +3P3V_WWAN_RADIO DIG_SPI_DO 6.3V 20% 100p TP5012
HrP_MS_PMU 1uH
T6 M12 P17 0603 C5028
DIG_SPI_CS_B DIG_CLKREQ0 MODEM_CLKREQ [20,33] VDD_VBAT_1V8_PMU M1008872-001 C5029
X859524-001 4.3u 0402

3
K14 U16 2016 2.5V 20% 4.3u
DIG_CLKREQ1 VDD_VBAT_PMU_SD1V8 M1064905-001
K3 K10 CNV_RF_RESET_R# V17 +1V8V_RADIO_LX
DIG_GPIO0 DIG_RF_RESET_B CNV_RF_RESET# [20,33] PMU_SD1V8_LX1_1

2
R5001 R5005 +1P8V_RADIO Y17
130K 130K PMU_SD1V8_LX1_2

1
DNP DNP M9 M6 WIFI_DIG_I2C_ALERT_B TP5001 TP5006 R5002 R16
VDD1V8_PLL_REFCLK DIG_I2C_ALERT_B 75K PMU_SD1V8_FB
TP5007 K4 WIFI_DIG_I2C_SCL TP5002 +3P3V_WWAN_RADIO
R5004 0 DIG_I2C_SCL
BT_KILL_R K17 K8 WIFI_DIG_I2C_SDA TP5003 U2
[24,33] BT_DISABLE# BT_RFKILLN DIG_I2C_SDA VDD_VBAT_SD1V1
R5003 0
WLAN_KILL_R J9 V1 +1P1V_RADIO_LX L5009 +1P1V_RADIO TP5010
[24,33] WLAN_DISABLE# WIFI_RFKILLN SD1V1_LX1_1 1uH
Y9 +3P3V_WWAN L5012 +3P3V_WWAN_RADIO Y1
DPHY_WGR_CLK_P V10 CNV_WR_CLK_DP_D100 [23] SD1V1_LX1_2
TP5008 M1008872-001
L16 DPHY_WGR_CLK_N CNV_WR_CLK_DN_D100 [23] R2 TP5009
DIG_BT_LED Y11 SD1V1_FB
J12 DPHY_WGR_D0_P V12 CNV_WR_D0_DP_D100 [23] 30 OHM T17 +1V8_HRP_PMU_GPIO_LDO_OUT
WIFI_LED DPHY_WGR_D0_N CNV_WR_D0_DN_D100 [23] 0402 VSS_PMU_SD1V8
REFCLK not used by ICL-HrP C5018 C5035 C5030
Y13 2.2A 10u 10% 0.01u 10% T15 V16 22u
DPHY_WGR_D1_P V14 CNV_WR_D1_DP_D100 [23] VSS_PMU_SD1V8_ISO VDD1V8_PMU_GPIO_LDO_OUT
25V 25V 6.3V 20%
WIFI_DIG_REFCLK0 DPHY_WGR_D1_N CNV_WR_D1_DN_D100 [23]
TP5004 M17 0805 T1 T12 C5026 0603
DIG_REFCLK0 Y3 0201 VSS_SD1V1 PMU_CLK_32K_IO 1u X869827-001 C5027 C5041
N16 DPHY_WT_CLK_P V4 CNV_WT_CLK_DP_D100 [23] T3 P14 10V 10% 10u 100p
DIG_REFCLK1 DPHY_WT_CLK_N CNV_WT_CLK_DN_D100 [23] VSS_SD1V1_ISO VDD3V2_PMU_FEM_CLDO
GND GND 0402 X859524-001 25V 5%
Y5 7 OF 8 X868173-001 X813058-001
DPHY_WT_D0_P CNV_WT_D0_DP_D100 [23]
V6
+1P1V_RADIO P4 DPHY_WT_D0_N CNV_WT_D0_DN_D100 [23]
AX-WCS22560 B3 TP5011
VDD1V0_DIG_1 Y7
DPHY_WT_D1_P CNV_WT_D1_DP_D100 [23] M1072227-003
P8 V8
VDD1V0_DIG_2 DPHY_WT_D1_N CNV_WT_D1_DN_D100 [23]

U9
J6 VSS_DPHY
P15 VSS_DIG_1
VSS_DIG_2 LAYOUT NOTE: +3P3V_WWAN
U11
U13 VSS_DIG_3
VSS_DIG_4 CNV*D100 nets routed as 85-Ohm differential pairs 3.3V +/- 0.165V SUSCLK [20]
U15
U3 VSS_DIG_5 R5013
U5 VSS_DIG_6 200 mVPP, 10-500kHz 150K
V2 VSS_DIG_7 DNP
Y15 VSS_DIG_8 300 mVpp -- allowed power rail noise
U7 VSS_DIG_9
VSS_DIG_10 TRISE (0-3.3V) < 10mSec
8 OF 8
AX-WCS22560 B3
RISING EDGE SHALL BE WITHOUT GLITCHES OR STEPS
M1072227-003 LAYOUT NOTE: RIPPLE SHALL NOT DIP MORE THAN 0.3V; OTHERWISE MAY BE INTERPRETED AS POR
PLACE CNV_WT* TPS NEAR U5001;
A
Stubbs should be minimized and limited to just a VIA for access A

Consider removing CNV_WT* TPs in later builds

Title: Wi-Fi_BT Coex

<OrgName> Engineer: <OrgAddr1>
Size Project Name Rev
A1 EDAN_A_EV1 1.00
Date: Tuesday, May 21, 2019 Sheet 50 of 82
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

W x H 377 x 244 mm
Title: Empty
Engineer: <OrgAddr1>
Size Project Name Rev
Custom EDAN_A_EV1 1.00
Date: Tuesday, May 21, 2019 Sheet 51 of 82
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

W x H 387 x 250 mm
Title: Camera power
<OrgName> Engineer: <OrgAddr1>
Size Project Name Rev
Custom EDAN_A_EV1 2.89.6
Date: Tuesday, May 21, 2019 Sheet 52 of 82
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

Place close to pin 23,25

A A

W x H 437 x 328 mm
Title: Blank
<OrgName> Engineer: <OrgAddr1>
Size Project Name Rev
Custom EDAN_A_EV1 2.89.6
Date: Tuesday, May 21, 2019 Sheet 53 of 82
5 4 3 2 1
 5 4 3 2 1

Sensor Connector to IR and RGB Cameras, Left and Right Microphones, and ALS Sensor
+1P8VSB

+VSYS C5410 0.01u

L5407 220 OHM 25V
C5411 0201S_P33
ALL 0.1u 10V 2A CAM_IR_LED_IN
U5404 0805S_1P1
[54,76] CAM_IR_STB 74AUP1G08GX C5416 C5409
5 10u 16V 0.1u 16V U5403 L5401 4.7uH100KHz
R5406 2 VCC 4 0603S_1-W 1000201S_P33 IR_BST 6 1 IR_SW 1.5A IR_OUT
A Y BST SW IRLED_A_P [54,76]
137K 1 IND_2P5X2X1_1P9MM
B 3 2 4 IR_FB
GND GND GND IN FB
DNP
CAM_IR_STB_R

1K
R5410 2.05K 3 5

0201S_P33

0402S_P7-W70

0201S_P28-W35
DIO_DSN2_1P45XP65XP31
CAM_IR_STB_1.8V EN GND 7

49.9K
0 DNP

0201S_P28-W35
EPAD

K
D C5414 C5408 C5419 D

150K
R5409 D5402 MP2370DG-Z D5403 0.01u 4.7uF 10p

1/20W
CAM_IR_STB_R [76]

R5401
DNP 1000mA 10V 10V 0201S_P33

0201S_P26
RB520CS3002L

R5413
GND NSR10F30NXT5G
30V 50V
R5407 +3P3V GND GND GND

A
165K GND

R5425
DNP

0201S_P33-W39
GND

220K
DNP
GND

0201S_P28-W35
C5402
0.1u
10V R5420 100K IR_FB_R R5419 1K
IRLED_C_N [54,76]
U5401 R5415 0201S_P28-W 35 0201S_P28-W 35

R5421
TLV3011 0 R5408

0201S_P33
GND GND
SC70-6_2X1P25X1P1_P65MM-2

DNP
0201S_P28-W 35 C5418 R5423 0.25
CAM_IR_STB_ERR_INM 4 6 220p 7.5K 1206S_P7
IN- V+ 25V 0201S_P3-W 35 0.5W
R5426 4.99K CAM_IR_STB_ERR_REF 5 1 CAM_IR_STB_ERR
0201S_P28-W35 REF OUT
GND
CAM_IR_STB_ERR_INP 3 2 GND GND
IN+ V-

6.3V
0201S_P35-W35
C5405 1u

10K

DNP
0201S_P28-W35
GND

R5414
+3P3VSB
U5402 GND GND

A2 A1 +3P3V_CAM_OUT
VIN VOUT

[25,76] RTD3_CAM_PW REN R5404 0 B2 B1 C5406

EN GND Layout Note: J54001 Pin 1 and Odd Pins along North Edge
C5404 0.1u L5404 Place close to pin 23
NX3P1108UK 1.3A
1u GND 3P3_CAM [76]
120 Ohm 100MHz0402
C5407 C5413
GND GND 0.1u 6.3V 10u 6.3V
0201 0402 J5401

2 1
[54,76] CAM_IR_STB 2 1 IRLED_C_N SEN_HALL_INT#_S [34,76]
C 4 3 C
L5402 CAM_USB_DP 4 3 IRLED_C_N [54,76]
2 1 6 5
[24] CAM_USB_DP_SOC CAM_USB_DM 6 5
0nH 2.5GHZ 8 7
3 4 IRLED_A_P 10 8 7 9 CHIMERA_DET_CON_A# R5416 0
[24] CAM_USB_DM_SOC [54,76] IRLED_A_P 10 9 CHIMERA_DET_A# [58]
C5403 12 11
Place 0.1u 6.3V 14 12 11 13
3 2 +1P8VA C54003 near 0201 16 14 13 15
16 15
K1

K1

4 1 connector 18 17
18 17 DMIC_DATA1_CODEC [40,76]
0 DNP RN5401 D5401 D5404 C5401 20 19
20 19 DMIC_CLK_CODEC [40,76]
PESD5V0H1BSF 0.1u R5402 0 22 21
[25,76] PCH_SENSOR_I2C_SDA 22 21 CHIMERA_23
PESD5V0H1BSF R5403 0 24 23 R5430 1K
[25,76] PCH_SENSOR_I2C_SCL 24 23 ISP_FW _LOCK# [20]
R5412 0 CHIMERA_DET_CON_B# 26 25 CHIMERA_25 R5431 0
[58] CHIMERA_DET_B# 26 25 ACS_INT# [25]
28 27 R5432 ALL 0
28 27 TDM_DET [35]
K2

K2

30 29
[34,76] SEN_HALL_INT#_N 30 29 RGB_LED_EN [54]
GND +5VSB +3P3VSB
Q5401B DF40C-30DS-0.4V +1P8VSB

4 3 R5417 3.48K R5434 R5405

RGB_LED_A_P [76]
0402 100K 100K
R5418 DNP
10K +1P8VSB
0201 ACS_INT#
5

GND ISP_FW _LOCK#

R5428 R5429
GND R5411
Q5401A 100K 100K 100K
Pullups for I2C are on the Camera Flex.
6

1% 1%
0201 0201
PCH_SENSOR_I2C_SDA DNP DNP
2 PCH_SENSOR_I2C_SCL
[54] RGB_LED_EN
1

GND
ALS 7-bit I2C Address = 0x44

B B

Check with Camera/RF/Power team for regulation, filtering, and component info
Power regulation, Privacy LED and sensors moved locally on
sensor board. IRLED Buck regulation local to mb
Odd side of the J54001 connector faces the North edge of the PCB

A A

W x H 392 x 254 mm
Title: Camera Front
<OrgName> Engineer: <OrgAddr1>
Size Project Name Rev
A2 EDAN_A_EV1 2.89.6
Date: Tuesday, May 21, 2019 Sheet 54 of 82
5 4 3 2 1
 5 4 3 2 1

+V_ALWAYS_ON
Iin=0.28A
+VSYS
Trace Width>30mil +V_ALWAYS_ON

D5502
40V DBG_S
A K R5521 0.02 +V_ALWAYS_ON
0603S_P6-W100
RB520CS3002L C5506
0.1uF 25V
0201S_P35-W35
D D
Effective Capacitance
2.2uF_0.55mm => @15V=0.255uF
GND 2.2uF_0.55mm => @20V=0.194uF
22 uF_1.45mm => @20V =2.566uF

100K
+3P3VAS
Imax<=0.175A

R5501
C5507
+3P3VAS
PWR_SL1_F TP5501
10u
Q5505 25V IND,PMC,6.8uH,330mOhm,1.2A,SM,3.2X2.5X1.
TRA-P CNL,SM,DFN1010D-3,120 mOHM,30 V,2. 0805S_1P2 L5501 6.8uH DBG_S
D5507 +3P3VAS_SW
40V D2 GND R5512 0.1
A K PWR_SL1_F_S S D1 U5501 0603S_P65-W95

S
2 9 C5512 C5505 C5508

D
R5517 DNP VIN1 SW 22u 10V 22u 10V PMTP5503 PMTP5504
1u

G
RB520CS3002L
100K R5532 1 25V 0603S_1-W100 0603S_1-W100 SP-TP-C0P381 SP-TP-C0P381
C5510

G
0201S_P28-W35 1K MODE +3P3VAS_BST
10 C5513 R5514
0.01u 25V BST
0201S_P33 4 1M
EN 5.6p GND GND
PWR_SL1_F_S_DRI 6 +3P3VAS_FB
14
MODE PG FB
FLOAT PFM/PWM 7
BIAS
R5516
200K PU PWM INT_LDO_5VCC 11
VCC
R5510
0201S_P3 324K
5 15 +3P3VAS_FREQ
NC FRQ

3
C Q5507A 10V C5520 12 13 +3P3VAS_SS C
AGND SS
6

5 8 R5515
20% 1u 3 PGND-8 C5521 165K
[70] SL1_PWR_GOOD

4
2 PGND-3
DNP MP2269GD-Z 12n
fs = 86500/(R+6.5)
1

R5518 C5509 Q5507B

249K
DNP
0.1u 10V
0201S_P33-W39
GND 500KHz R5507
3P3VA_GND 3P3VA_GND GND 3P3VA_GND 3P3VA_GND3P3VA_GND 2 1
GND
0201 SHUNT
+VBUS_P0_CONN GND
GND

D5504
40V 3P3VA_GND GND
A K +3P3VAS +3P3VAS
+1P8VA

RB520CS3002L
R5529
100K U5505 DBG_S
0201S_P28-W35 4 1 1P8VA_REG R5520 0.1
DNP VIN VOUT 0603S_P65-W95
3
[58] 3P3VA_EN EN
2 5 C5518 +1P8VA
GND EPAD
C5501 C5502 NCP170AMX180TCG
10u 10V Imax=0.08A
0603S_1-W100
B B
0.1u 10V 1u 6.3V GND
0201S_P33-W39 0201S_P35-W35 GND

GND
+3P3VAS GND GND +3P3VA
U5506
A2 A1 +3P3VA_REG R5505 0.1
+3P3VAS_BATLDO VIN VOUT
D5501
DBG_S
A K 3P3VA_EN R5506 0 B2 B1 C5504 PTP5502 PTP5501
[70] BAT_LDO EN GND
C5503
0.1u
RB520CS3002L 1u NX3P1108UK
GND
+3P3VA
+3P3VAS
200mA
+VCC_RTC
+3P3VAS +3P3VAS
Imax=0.01A
+1P8VAS
GND GND
D5503
R5530 U5502
A K R5502 1.5K 100K DBG_S
0201S_P28-W35 4 1 1P8VAS_REG R5533 0.1
VIN VOUT
0201S_P33-W39

0603S_P65-W95
RB520CS3002L C5511 R5508 R5522 3
0.1u 200K EN
10V
0
0201S_P3 2 5 C5524 +1P8VAS
DNP DNP +VCC_RTC GND EPAD 10u 10V Imax=???A
Imax=0.0002A C5523 C5522 NCP170AMX180TCG 0603S_1-W100
D

0.1u 10V 1u 6.3V GND

A A
GND GND 0201S_P33-W39 0201S_P35-W35 GND
R5503 499 VCCRTC_RST_R G Q5501
[35] VCCRTC_RST
GND
GND GND

W x H 447 x 289 mm
R5504
S

100K
0201S_P28-W35 SOTFL-3_1P3XP9XP55_P4
Title: VA AND VCCRTC
<OrgName> Engineer: <OrgAddr1>
GND GND
Size Project Name Rev
Custom EDAN_A_EV1 1.00
Date: Tuesday, May 21, 2019 Sheet 55 of 82
5 4 3 2 1
 5 4 3 2 1

DNP
R5606 0
+VCCSTG
+5VSB +VCC1.05_OUT_FET

U5601
D D
1
+3P3VSB VDD
2 5-6 +VCCSTG_REG R5601 0.02
3-4 D1 S1 7 0603S_P6-W100
C5602 C5604 +3P3VSB D2 S2 C5603 DBG_S
0.1u 10V 1u 6.3V 9 8 1u 6.3V PMTP5601 PMTP5602
R5604 0201S_P33-W39 0201S_P35-W35 ON GND 0201S_P35-W35 SP-TP-C0P381 SP-TP-C0P381
100K C5605 0201S_P3 C5606
0201S_P28-W35 0.1u 10V DBG_D GND GND 0.1u 10V SLG5NT1477VTR GND
DBG_D U5602 0201S_P33-W39
R5609 0201S_P33-W39 +VCCSTG
R5607 0
1 NC
2 A
VCC 6
NC 5 GND
DBG_D 499K
U5603
DBG_D ON IS 1.8V LOGIC
GND
Imax=0.3A
[18,34] XDP_PRESENT# DBG_D 3 GND Y 4 XDP_PRESENT R5602 0 1 6 GND
DBG_D 2 A VCC 5
3 B NC 4
74LVC1G06GM GND Y
DBG_D
GND DBG_D
SN74AUP1G32DRYR
GND SON6_1P5X1P05XP6_P5-2
R5605 0 R5603 0 DBG_N
[22,33,60,62] CPU_C10_GATE#

C C

+VCCST_CPU

+VCC1.05_OUT_FET

R5621 0.01
0603S_P6-W100
C5612 DBG_S
1u 6.3V PMTP5621 PMTP5620
0201S_P35-W35 SP-TP-C0P381 SP-TP-C0P381

GND
+VCCST_CPU
Imax=1.2A

B B

A A

W x H 377 x 244 mm
Title: +VCCSTG
<OrgName> Engineer: <OrgAddr1>
Size Project Name Rev
Custom EDAN_A_EV1 1.00
Date: Tuesday, May 21, 2019 Sheet 56 of 82
5 4 3 2 1
 5 4 3 2 1

R5709 0 EDP_I2C_SDA
[25,33,57] PANEL_I2C_SDA
0201S_P28-W35
R5710 0 EDP_I2C_SCL
[25,33,57] PANEL_I2C_SCL
0201S_P28-W35

10V
0201S_P33-W39

0201S_P33-W39
10V
C5725 0.1u

0.1u
DNP

DNP
+3P3V_PANEL +1P8V_PANEL

C5724
U5705
B2 B1
VIN VOUT
A2 A1 GND GND
C5728 C5729 EN GND C5727 R5729
D 0.1u 1u LD39115J18R_1p8V 1u 10K D
[30] EDP_SPI_MISO +3P3V_PANEL +3P3V_PANEL
6.3V 6.3V X867741-001 GND 6.3V DNP [30] EDP_SPI_CLK

GND GND ALL J5701

GND GND 4 0 1 RN5702A
3 0 2 RN5702B TP5704 MFG_SDA 1 2 MFG_SCL TP5705
ALL 3 1 2 4
M57L3 3 4
0201S_P33-W39 2 3 5 6
EDP_TX3_DN_C [76] EDP_I2C_SDA 7 5 6 8
M57C3 0.1u 10V
[10] EDP_TX3_DN 7 8
1 4 9 10
M57C4 0.1u 10V EDP_TX3_DP_C DNP 0 R5704 EDP_FPC_CONN_DET_B# 11 9 10 12 TP5701
[10] EDP_TX3_DP [58] EDP_FPC_DET_B# 11 12
0201S_P33-W39 13 14
+VCC_EDP_BKLT_OUT 13 14 EDP_I2C_SCL [76]
15 16
ALL 17 15 16 18 DEPROM_RESET_N PTP5701 EDP_I2C_INT [10,76]
4 0 1 RN5703A 19 17 18 20 DEPROM_TWP PTP5702
3 0 2 RN5703B 21 19 20 22 DEPROM_I2C_SDA PTP5703
21 22

0805S_1P45
C5705 C5711 C5707 ALL 23 24
M57L4 EDP_TXN3_R 23 24 DEPROM_I2C_SCL PTP5704 TCON_VENDOR_ID [24,76]

0805S_1P45
0.47u 50V 0.1u 35V 0.1u 35V 0201S_P33-W39 2 3 25 26
EDP_TX2_DN_C EDP_TXP3_R 25 26

2.2u 50V
0805S_1P45 0201S_P33 0201S_P33 C5706 M57C7 0.1u 10V DNP 27 28
[10] EDP_TX2_DN 27 28

2.2u 50V
C5719
1 4 29 30
EDP_TX2_DP_C EDP_TXN2_R 29 30 EDP_HPD [10]
GND M57C8 0.1u 10V 31 32
[10] EDP_TX2_DP EDP_TXP2_R 31 32 PANEL_BIST
GND GND 0201S_P33-W39 4 0ALL 1 RN5704A 33 34 TP5712
3 0 2 RN5704B 35 33 34 36
ALL EDP_TXN1_R 37 35 36 38 PANEL_LOGO [35] TP5713
M57L5 37 38 EDP_SPI_CS# [30]
GND GND 0201S_P33-W39 2 3 EDP_TXP1_R 39 40 PANEL_VSYNCH
EDP_TX1_DN_C 39 40 PANEL_VSYNCH [30]
M57C9 0.1u 10V 41 42 EDP_SPI_INT# [30]
[10] EDP_TX1_DN EDP_TXN0_R 41 42 EDP_AUXP_R
1 4 43 44
M57C10 0.1u 10V EDP_TX1_DP_C DNP EDP_TXP0_R 45 43 44 46 EDP_AUXN_R
[10] EDP_TX1_DP 45 46 EDP_FPC_CONN_DET_A# R5703
0201S_P33-W39 47 48 0
47 48 EDP_FPC_DET_A# [58]
49 50
[72,76] BKLT_FB8 49 50 BKLT_FB7 [72,76]
ALL 51 52
[72,76] BKLT_FB6 51 52 BKLT_FB5 [72,76] +VCC_EDP_BKLT_OUT
4 0 1 RN5701A 53 54
+VCC_EDP_BKLT_OUT [72,76] BKLT_FB4 53 54 BKLT_FB3 [72,76]
3 0 2 RN5701B 55 56
[72,76] BKLT_FB2 57 55 56 58 BKLT_FB1 [72,76]
ALL
EDP_TX0_DN_C M57L2 57 58
M57C6 0.1u 10V 2 3 59 60
+3P3V_PANEL +3P3V_PANEL +3P3V_PANEL [10] EDP_TX0_DN 59 60
M57C5 0.1u 10V EDP_TX0_DP_C 1 4 61 62
C [10] EDP_TX0_DP MT1 MT2 C
DNP C5708 63 64 C5709
C5704 C5702 C5712 0.1u MT3 MT4 0.1u
0.47u 6.3V 1u 6.3V 0.1u 10V 10V 10V
0201S_P33 0201S_P35-W35 0201S_P33-W39 ALL
RN5705A 1 0 4
GND GND RN5705B 2 0 3
GND GND GND GND GND ALL 0201S_P33-W39
L5701
3 4 10V 0.1u M57C1
EDP_AUX_DP [10]
2 1 10V 0.1u M57C2
EDP_AUX_DN [10]
DNP 0201S_P33-W39
[25,33,57] PANEL_I2C_SCL 0uH

PANEL_BIST

R5716
100K

U5701
3 6 DEPROM_I2C_SCL
4 SCL1 SCL2 5 DEPROM_I2C_SDA
1.8V logic 2
SDA1 SDA2
7
GND

+1P8V_PANEL VREF1 VREF2

1 8
GND EN
PCA9306DQER
X867878-001 DEPROM_RESET_N_R R5702 DNP 0 DEPROM_RESET_N
C5703

D
C5701 0.1u
0.1u
GND
6.3V Q5702
REMOVE 0ohm to avoid resetting tcon durign programming
6.3V G
B [25,33,57] PANEL_I2C_SDA B

GND

S
GND

[21] DEPROM_PROG GND

DEPROM_TWP

D
Q5701
3.3V logic R5706
137K
G

S
U5701_EN_1.8

R5701
165K GND

GND

The SCL switch conducts if EN is = 1 V higher than SCL1

The SDA switch conducts if EN is = 1 V higher than SDA1
A VIO(Max) = 5V A
200K PU not needed when VREF1 = VREF2
If EN > Vref1+0.7V => device will NOT properly isolate the two sides when both sides are high

W x H 602 x 390 mm
Title: eDP connector
<OrgName> Engineer: <OrgAddr1>
Size Project Name Rev
Custom EDAN_A_EV1 1.00
Date: Tuesday, May 21, 2019 Sheet 57 of 76
5 4 3 2 1
 5 4 3 2 1

+1P8VAS +1P8VAS

+1P8VAS
R5825 R5815
1M 1M
0201 0201 U5806 +1P8VAS
C5806
1% 1% 5 0.1u
2 VCC 4 10V
[54] CHIMERA_DET_A# A Y U5807
[54] CHIMERA_DET_B# 1 ALL C5807
B 3 5 0.1u +1P8VAS
+1P8VAS +1P8VAS GND 2 VCC 4 10V +1P8VAS
74LVC1G32GX 1 A Y ALL +1P8VAS
B 3 C5813 +1P8VAS
ALL GND
R5817 R5822 0.1u
+1P8VAS 74LVC1G32GX 10V C5804
D 1M 1M U5803 is BYPASS IN CASE WE WANT OD 0.1u 10V D
ALL C5812
0201 0201 U5811 GND R5832 0.1u 10V DNP
U5808 U5803
1% 1% C5809 ALL 100K U5810
5 0.1u +1P8VAS 5 74AUP1G08GX 5
2 VCC 4 10V 2 VCC 5 VCC
[74] KIP_FPC_DET_A# A Y A VCC
[74] KIP_FPC_DET_B# 1 ALL 4 R5829 150K 2 4 2 4
B U5805 Y A Y I O
3 C5805 1 1
+1P8VAS +1P8VAS GND 5 0.1u B 3 B 3 1
74LVC1G32GX 2 VCC 4 10V +1P8VAS GND C5814 GND NC1 3
1 A Y ALL 74AUP1G86GX GND
ALL B 2.2u
+1P8VAS 3
R5826 R5827 GND 74AUP1G07GX
1M 1M 74LVC1G32GX R5828 3P3VA_EN_SILEGO DNP
U5809 GND
0201 0201 C5811 100K
ALL
1% 1% 5 0.1u R5833 ALL 0 3P3VA_EN [55]
2 VCC 4 10V
[57] EDP_FPC_DET_A# A Y
[57] EDP_FPC_DET_B# 1 ALL [33,76] FPC_DET_LOGIC_OVERRIDE# R5818 0201 0
B 3 DNP
GND In RAFLA this Signal will be pulled "LOW" via 1K resistor R5818 IS BYPASS for 3P3VA_EN_SILEGO
74LVC1G32GX R5834
ALL 0402
0
DNP

R5809 0201 0
ALL +3P3VSB +VCCST_CPU
PIN17=PIN2*PIN12*PIN3*PIN6
TP5806
SP_TP_SMDP58 ALL_SYS_PWRGD [66] C5803
+3P3VAS +3P3VAS_BATLDO 0.1u 10V
0201S_P33-W39 R5802
C
[35,58,65] SLP_S3_DRV# Silego Controller U5804
1K C
5 0201S_P28-W35
R5810 R5813 VCC GND
0 0 2 4
I O VCCST_PWRGD [22]
DNP 0201
0201 ALL R5830 1
100K NC1 3
R5831 +3P3VAS_SIL 0201 GND
100K DNP
74AUP1G07GXGND

TP5807
SP_TP_SMDP58 C5802
0.1u 10V
0201 SP_TP_SMDP58 TP5816
R5831 need change back to 100K after SAM PU disable TP5811 SP_TP_SMDP58 SP_TP_SMDP58 TP5812
TP5810 SP_TP_SMDP58 SP_TP_SMDP58 TP5813
[58,76] DDR_PGD_SIL SP_TP_SMDP58 TP5814
TP5808 SP_TP_SMDP58 SP_TP_SMDP58 TP5815
U5801
TP5803 SP_TP_SMDP58
SIL_SLP_S3_DRV# DDR_PGD_SIL [58,76]
12 1
+VCCST_CPU +3P3V +3P3VSB SPL_3_DRV VDD
R5811 0201 0 SUS_PGD_SIL 2 R5816 IO_PGD @ pin 4 for Skyway 3
[34,69] VCCIN_AUX_PG SUS_PGD SYS_PWGD_SIL
17 R5804 0201 0 0
VCORE_EN 0201
C5801 R5812 0201 0 VRM_PGD_SIL 10 DNP Optional BAT_SHUTDOWN# PU on pg70.
[34,66] VRM_PWRGD VRM_PGD SSD_BATSHUTDN#_SIL
0.1u 10V 4 R5808 0201 10K
DDR_PGD_SIL BAT_SHUTDOWN BAT_SHUTDOWN# [33,70,76]
0201S_P33-W39 R5801 R5814 R5821 0201 0 3
U5802 [60] +0P6V_DDR_PG DDR_PGD
DNP 1K 1K
5 0201S_P28-W35 0201S_P28-W35 R5805 0201 0 SLP_3#_SIL 6 16 SAM_RST#_SIL R5824 0201 0
VCC [22,33,34] SLP_S3# SLP_3 FORCE_OFF SAM_RESET# [29,33,34,76]
GND DNP ALL
2 4 H_THERMTRIP#_BUFF R5806 0201 0 H_THERMTRIP#_SIL 20
[10] H_THERMTRIP# I O THERMTRIP 18 BATEN_PULSE [34,70]
B 1 R5803 0201 0 PLT_RST#_SIL 19 START_ONESHOT B
NC1 [22] PLTRST# PLT_RST
3 13 3P3VA_EN_SILEGO
GND SLG_PWRBTN# 14 MCU_PWR_CTRL
START 15 SAM_DBG_MODE_R R5823 0
74AUP1G07GXGND R5844 0201 0 DET_A#_SIL 5 S_DBG-MCU_DBG SAM_DBG_MODE [29]
[44] DET_A# DET_A
DNP 9 SSD_LS_EN_SIL R5820 0
R5845 0201 0 DET_B#_SIL 8 SSD_LS_EN SIL_SSD_VR_EN [65]
[44] DET_B# DET_B
DNP R5840
DEVICE_RST#_SIL 7 11 100K
TP5805 RST GND 0201
R5841 R5842 SLG4U42544 DNP
100K 100K
SP_TP_SMDP58 0201 0201
DNP DNP GND R5843
I2C control from SAM 100K
+3P3VSB
R5819 0201
100 DNP
0201
R5807
[31,74] PWRBTN#_3V3 SLG_PWRBTN# [76] Both of these BOM install options 100K
ALL keep SSD ON during modern stdby 0201
C5810 DNP
0.1u R5837 [35,60,62] SLP_S4_DRV# R5849 0
0201 0
C5808 10V 0201 DNP
0.1u 10V ALL
0201
[35,58,65] SLP_S3_DRV# R5852 0

ALL
[39] DEVICE_RST#

A A

20160727sjs0530
title is: Silego Controller

W x H 542 x 351mm
Title: Silego Controller
<OrgName> Engineer: <OrgAddr1>
Size Project Name Rev
Custom EDAN_A_EV1 1.00
Date: Tuesday, May 21, 2019 Sheet 58 of 82
5 4 3 2 1
 5 4 3 2 1

PM_5VSB_IN+ [28]

PM_5VSB_IN- [28]
10u C5951

DBG_T

R5947 0
47 R5948
DBG_T DBG_T

+VSYS

D +5VSB_VIN D
DBG_TS
0.005 R5910
+5VSB
PMTP5913 PMTP5914
C5930
10u 16V
C5922
10u 16V
C5921
0.1u 16V
Imax=7.5A

R5932 GND GND GND

0
+5VSB
C5920
R5901 ALL 0 DNP U5904 R5909 0.22u
[35] +5VSB_EN
1 10 2.2 IND,PMC,1.5uH,20mOhm,8A TYP,SM,7.1X6.6X2
VIN BST L5904
7.1X6.6X2.4
16 9 +5VSB_SW
MODE2 SW
14 13 +5VSB_FB 1.5uH
MODE1 FB
R5908 0 SB_PWR_ON R5907 0 +5VSB_EN_R 15 12 SUS_PWRGD_3V3_5VSB 274K
[35,62,69] VSUS_ON EN PG R5929 C5946 220p
DNP 3
3V3 C5926 C5927 C5923 C5924 C5925 C5950 R5911
DNP
For NB502 11 2 R5928 R5912 10p 0.1u 47u 47u 47u 47u 100K
R5906 C5919 CLM PGND_1 4 499 18.7K 50V 10V 6.3V 6.3V 6.3V 6.3V DNP
10K 0.1u R5933 PGND_2 5 DNP 5.1V
DNP 10V 0 PGND_3 6
R5927 8 PGND_4 7
R5931 0 NC PGND_5
232K NB502 GND
GND GND DNP GND GND GND GND GND GND GND
R5913
10.2K

GND GND GND

PM_3P3VSB_IN+ [28]
C C
PM_3P3VSB_IN- [28] +1P8VA GND
CLM MODE1 MODE1
10u C5952 0 7 A 700 kHz < 3 V
90k 10 A 1 MHz < 3 V R5904 +3P3VA +1P8VA
150K 13 A 1 MHz >= 3 V
DBG_T 230k or floating 16.5 A 700 kHz >= 3 V 499K +3P3VSB

R5949 R5902 ALL 0 SUS_PWRGD_5VSB [34] DNP

0 R5953
47
DBG_T R5950 R5905 10K
U5905
DBG_T 100K
5
VCC
R5957 0 SUS_PWRGD_3V3 2 4
I O SUS_PWRGD [34]
DNP 1 C5948
NC1 3 0.1u 10V
+3P3VSB_VIN C5931 C5901 R5954 GND
+VSYS 1u 1u 1M 74AUP1G07GX
10V 10V DNP DNP

0.01 R5917
GND GND
DBG_TS C5933 C5934 C5932 R5956 0
10u 16V 10u 16V 0.1u 16V
0201
PMTP5904 PMTP5903 +3P3VSB
GND
Imax=5.25A
GND GND

U5902
2.2
8 7 R5916 C5935 0.22u +3P3VSB
VCC BST
B IND,PMC,2.2uH,35mOhm,7A,SM,6.6X7X1.8 B

C5903 L5902
C5902 1u 1 6 +3P3VSB_PHASE1_S
1u 10V VIN SW
10V 0201 2.2uH
R5938 C5937 C5936 C5909 C5910 C5911 C5904 R5903
C5947 220p 10p 50V 0.1u 10V 47u 6.3V 47u 6.3V 47u 6.3V 100K
For NB502 47u
422K DNP DNP
DNP

GND
SB_PWR_ON 11 GND GND GND GND GND GND
EN

2 R5937
PGND_1 3 499 R5940
PGND_2 4 200K
PGND_3

SUS_PWRGD_3V3 5
PG GND

10
FB

R5939
43.2K

A A

GND
9
AGND
NB691GG-Z

W x H 577 x 373 mm
Title: +5VSB & +3P3VSB
GND
<OrgName> Engineer: <OrgAddr1>
Size Project Name Rev
Custom EDAN_A_EV1 1.00
Date: Tuesday, May 21, 2019 Sheet 59 of 82
5 4 3 2 1
 5 4 3 2 1

PM_1P1V_DDR_VDD2_IN- [28]

PM_1P1V_DDR_VDD2_IN+ [28]

C6001 10u

DBG_T
0 R6006
+1P8VSB +VSYS R6007 47
D Iin=2.25 A DBG_T
R6016
DBG_T
+VSYS
D

+1P1V_DDR_VDD2_VIN Trace Width>150mil E2 SENSE E1

C6007 DBG_TS
DFN5_P85XP85XP4_P48 0.1u 10V I2 LOAD I1
U6004 0201S_P33-W 39
74AUP1G08GX TP6007 C6020 C6021 C6010 C6014 C6013 0.02
5 SP_TP_SMDP58
10u 16V 10u 16V 10u 16V 10u 16V 0.1u 16V PMTP6010 PMTP6009
2 VCC 4 SLP_S4_AND# 0603S_1-W 100 0603S_1-W 100 0603S_1-W 100 0603S_1-W 100 0201S_P33 SP-TP-C0P381 SP-TP-C0P381
[22,33,34] SLP_S4# A Y
1
[35,58,62] SLP_S4_DRV# B 3 R6019
GND 0 GND
GND GND GND GND
0201
+1P1V_DDR_VDD2
R6010
DNP
0 R6009
1
U6001
10 R6013 2.2
0.22u
C6012 25V
Iin=10.8 A
0 VIN BST 0402S_P55 5.4X5.2X1.5 Trace Width>150mil
16 9 +1P1V_DDR_VDD2_SW +1P1V_DDR_VDD2
MODE2 SW L6001
14 13 +1P1_DDR_FB
MODE1 FB
C6038 0.01u 10V 1P1V_DDR_VDD2_EN 15 12 R6023 0.68uH
GND EN PG DNP 1% C6009 220p
3 0201 274K 0402S_P55
3V3
11 2 R6012 R6022 R6014
R6020 R6018 CLM PGND_1 4 499 10K C6019 C6018 C6015 C6016 C6017 100K
0 PGND_2 5 0201 0201 10p 0.1u 47u 47u 47u 0201S_P28-W 35
0 PGND_3
DNP R6011 6 1% 50V 10V 6.3V 6.3V 6.3V DNP
0201 150K 8 PGND_4 7 0805S_1P45 0805S_1P45
0805S_1P45
NC PGND_5
NB502 +3P3VSB GND

R6017 5.1 R6021

GND GND GND 0402 11.8K GND GND GND GND GND
GND C6002 C6011 R6021
1u 1u
10V 10V
CLM MODE1 MODE1 0201 0201 +3P3VSB
0 7 A 700 kHz < 3 V GND GND GND
90k 10 A 1 MHz < 3 V R6002 100K
150K 13 A 1 MHz >= 3 V
C C
230k or floating 16.5 A 700 kHz >= 3 V
+1P1V_DDR_PG [76]

+3P3VSB +0P6V_DDR_VDDQ

+VCCPLL_OC
+5VSB +1P1V_DDR_VDD2 U6005
Iin=0.170 A R6001 R6003
SLG5NT1533V Trace Width>20mil 100K 31.6
DFN8_1P65X1P05XP6_P4 +VCCPLL_OC +3P3VSB
1 DBG_S
VDD 5-6 +VCCPLL_OC_REG R6005 0.05 PMTP6015
2 S1-S2 0603S_P6-W 105 SP-TP-C0P381
ON

D
B B
7 PMTP6006 PMTP6005 R6036
C6034 3-4 CAP SP-TP-C0P381 SP-TP-C0P381 0P6V_DDR_VDDQ_RI_EN G Q6002 G Q6001
D1-D2 0.1
0.1u 10V 8 C6035 C6036 DBG_S
0201S_P33-W 39 GND 1u 6.3V 10u 10V 0603S_P65-W 95
C6037 C6008 0201S_P35-W 35 0603S_1-W 100

S
1u 6.3V GND 100p
GND 0201S_P35-W 35
GND GND
GND PMTP6016
GND SP-TP-C0P381
[22,33,56,62] CPU_C10_GATE#

+3P3VSB +1P1V_DDR_PG R6037 0 0P6V_DDR_VDDQ_RI_EN

0201S_P28-W 35
C6031 C6039
R6024 10u +0P6V_DDR_VDDQ
100K
0201S_P28-W 35 U6006 20%
0.1u Iin= 0.43 A
5 8 6.3V +0P6V_DDR_VDDQ
VOS VIN
0402
R6038 0 6 1
[58] +0P6V_DDR_PG PGOOD EN
0201S_P28-W 35
3 7 L6003 0.47uH
AGND LX
2 4
9 PGND1 FB R6034
PGND2 13K C6040 C6041 C6042
RT5715GQW 10p 50V 22u 10V 22u 10V
0201S_P33 0603S_1-W 100 0603S_1-W 100
GND DNP

R6035
38.3K
A A

GND

Title: +1P2V_DUAL&+VTT
<OrgName> Engineer: <OrgAddr1>
Size Project Name Rev
A2 EDAN_A_EV1 1.00
Date: Tuesday, May 21, 2019 Sheet 60 of 82
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

W x H 402 x 260 mm
Title: VNN BYPASS Rails
<OrgName> Engineer: <OrgAddr1>
Size Project Name Rev
Custom EDAN_A_EV1 1.00
Date: Tuesday, May 21, 2019 Sheet 61 of 82
5 4 3 2 1
 5 4 3 2 1

PM_1P8VSB_IN+ [28]
PM_1P8VSB_IN- [28]
+VSYS
C6203 10u
U6204
Iin=2 A
DBG_T
R6218 Trace Width>100mil
R6220 8 7 C6254 0.22u
C6219 VCC BST
47 0
DBG_T 10u 16V 0201S_P33
+VSYS R6221 +1P8VSB_VIN 0603S_1-W100 2.2
DBG_T 0402S_P4
R6203 DBG_TS 0.02 GND 1 6
D
VIN SW D
C6207 C6208 C6205
PMTP6201 PMTP6202 10u 16V 10u 16V 0.1u 16V +1P8VSB
SP-TP-C0P381 SP-TP-C0P381 0603S_1-W100 0603S_1-W100 0201S_P33 Imax=4A
GND GND GND need to update R6216=887K +1P8VSB
IND_4P2X4P2X2-3
+1P8VA L6201 Idc=5.8A/Isat=8.7A
+1P8VSB_SW R6213 0.005
0603S_P75-W100
+1P8VSB_EN 11 1uH
EN DBG_S
C6202 C6211 C6255 C6204 C6218 PMTP6207 PMTP6208
DFN5_P85XP85XP4_P48 0.1u 10V R6216 10p 50V 47u 47u 0.1u 10V SP-TP-C0P381 SP-TP-C0P381
U6201 0201S_P33-W39 2 C6253 220p 0201S_P33 6.3V 6.3V 0201S_P33-W39
74AUP1G08GX PGND_1 3 887K 0201S_P33
5 PGND_2 4
2 VCC 4 PGND_3 R6217
[35,59,69] VSUS_ON A Y GND
1 499
[22,34] SLP_SUS# B 3
GND 0402S_P4 R6219
5 43.2K
+1P8VSB PG GND 1%
R6202 0 0201
+3P3VSB DNP
R6201
100K 10 +1P8VSB_FB
0201S_P28-W35 FB +5VSB
C C
R6230
150K
[69] 1P8VSB_PG
DNP R6215
20.5K C6201
R6232 0 0201 0.1u 10V
DNP 1% 0201S_P33-W39

R6231 GND +VCC1P8A

U6206
51.1K
DNP 9 1 DBG_S
+1P8VSB AGND VDD 5-6 VCC1P8A_REG R6211 0.02
NB691GG-Z R6212 0 VCC1P8A_REG_EN 2 S1-S2 0603S_P6-W100
[22,33,56,60] CPU_C10_GATE# ON
0201S_P28-W35 C6214
GND 7 0.1u 10V PMTP6212
C6212 +1P8VSB 3-4 CAP 0201S_P33-W39 SP-TP-C0P381
D1-D2
1u 6.3V 8 GND PMTP6211
0201S_P35-W35 +1P8V_AUDIO GND SP-TP-C0P381
+VCC1P8A
U6202 SLG5NT1533V
A2 A1 +1P8V_AUD_REG
DBG_S
R6206 0.05
C6215
1u 6.3V
GND C6251 Imax=0.3A
VIN VOUT 100p
0603S_P6-W105 0201S_P35-W35
C6206
R6207 0 +1P8V_AUD_REG_EN B2 B1 0.1u 10V PMTP6204 PMTP6203 GND
[25] RTD3_AUD_PWR_1P8 EN GND
0201S_P28-W35 0201S_P33-W39 SP-TP-C0P381 SP-TP-C0P381 GND
NX3P1108UK
B
GND +1P8V_AUDIO B

Imax=0.3A
GND

+1P8VSB

C6209
1u 6.3V
0201S_P35-W35 U6205 +1P8V_TS
+1P8VSB NX3P1108UK +1P8V_TS_REG
BGA4_2X2_P98XP98XP59_P5 DBG_TS
GND A2 A1 0.05 R6205
VIN VOUT 0603S_P6-W105
C6213
1u 6.3V [25,64] RTD3_TPANEL_PWR R6204 0 +1P8V_TS_REG_EN B2 B1 C6210 PMTP6209
0201S_P35-W35 +1P8V_DDR_VDD1 0201S_P28-W35 EN GND 0.1u 10V SP-TP-C0P381
U6203
DBG_S 0201S_P33-W39 PMTP6210
A2 A1 +1P8V_DUAL_REG R6209 0.01 SP-TP-C0P381
VIN VOUT 0603S_P6-W100
GND +1P8V_TS
R6210 0 +1P8V_DUAL_REG_EN B2 B1
C6250
0.1u 10V PMTP6206
GND Imax=0.455A
[35,58,60] SLP_S4_DRV# EN GND
0201S_P28-W35 0201S_P33-W39 SP-TP-C0P381 PMTP6205
SP-TP-C0P381
A
NX3P1108UK A
GND +1P8V_DDR_VDD1
Imax=1A

W x H 422 x 273 mm
GND

Title: +1.8VSB & Load SW

<OrgName> Engineer: <OrgAddr1>

Size Project Name Rev
Custom EDAN_A_EV1 1.00
Date: Tuesday, May 21, 2019 Sheet 62 of 82
5 4 3 2 1
 5 4 3 2 1

+3P3VAS

PW R_SL1_F

EXT_DC_IN

+1P8VSB
C6343
D C6345 U6301 D
R6314 A1 B2 10u
10u B1 VINT1 VBUS1 C2
100K VINT2 VBUS2 R6319 TP6301
C1 D2
1% D1 VINT3 VBUS3 E1 100K
0201 VINT4 VBUS4 E2 1%
B3 VBUS5 0201
OVLO
SL1_EN_N SL1_ACK# PM_VSYS+ [28]
A3 A2 R6327 0
EN_N ACK
R6313 0 C3
D3 GND1 10u C6318
R6315

D
GND2 PM_VSYS- [28]
E3
D Q6301 GND3 1M
DBG_T
NX3008NBKMB 0201
R6334 0 SAM_SL1_PW R_EN_R G G NX20P5090 1% R6312
[35,79] SAM_SL1_PW R_EN 0
SL1_EN_N [76] 47
S DBG_T R6311
U6301_OVLO OVLO: 17.44V to 19.29V DBG_T

S
R6328
100K PTP6301
PTP6302 +VSYS
R6335 R6330
71.5K E1 E2
1%
0201 Q6302 I1 I2

D1 1
2 Q6304 0.005
R6328 need change back to 100K after SAM PU disable
Q1 9 C6340 C6329 C6334 DBG_TS
1 D1 C6316 C6337 C6338 + +
2 0.01u 22u 22u 22u
8 G1 9 Q1 47u 47u
EXT_DC_IN
GND GND GND GND
D2S1
5
6
G1 8
+VSYS: 6V(TBD) to 8.75V
7 GND GND
Q2
Place L6302 close to L6301 56as D2S1
place holder for larger inductor.
C 7 C
3 G2 4 Q2
R6303 0.01 10
S2
1508 AONP36376 4 G2 3
C6304 C6301 L6301 10
C6324 C6323 C6320 C6311 GND 2.2uH S2
+ C6333 + C6315 C6332 C6321 C6322 R6306 0.01u 1000p AONP36376
22u 22u 22u 0.022u 0.022u 22u 22u R6308 10 25V 25V 0.022u 0.022u GND
25V 25V 25V 25V 25V 0201
20% 20%
25V 25V 10
0201 GND GND
25V 25V
C6330
PWR_SL1_F MAX Voltage: 17.2V
330p PSU_VOLT MAX Voltage: 0.697V
GND GND DNP C6310
330p
GND GND GND GND GND GND GND DNP PW R_SL1_F
C6335 R6317

A
C6341 C6342 56 R6325 C6336
100p DNP +VDD_BATA_PACK D6301
56 Q6303
0.01u C6305 0.1u 0.01u DNP 180p RB520CS3002L
25V 25V R6304 0.01
DNP 3

K
5,6,7,8
GND GND GND GND GND 2 1508
GND 1 5
U6302

D
S
0.047u C6313

2
C6302 CHG_BTST1 30 25 CHG_BTST2 C6331 0.047u R6321

G
BTST1 BTST2 1u
PJP6303 PJP6304 C6317 C6314 C6339 130K

4
CHG_SW 1 32 23 CHG_SW 2 Q6308A
SW1 SW2 0201 SHUNT 0201 SHUNT 10u 10u 10u
C6344 DNP DNP
1u CHG_LODRV1 29 26 CHG_LODRV2 1 6
[35] PSU_VOLT

1
25V LODRV1 LODRV2
CHG_HIDRV1 31 24 CHG_HIDRV2 GND
HIDRV1 HIDRV2 C6309 0.1u +1P8VA R6322
GND

2
+1P8VA +1P8VA CHG_VBUS 1 22 CHG_VSYS GND GND GND
VBUS VSYS 5.49K
CHG_ACN 2 21 CHG_BATDRV_A
ACN BATDRV
CHG_ACP 3 20 CHG_SRP_A_R R6332 10 CHG_SRP_A
ACP SRP [35] EXT_VOLT_ADC_EN
CHG_REGN_D 10 R6307 CHG_VCCA 7 19 CHG_SRN_A_R R6318 10 CHG_SRN_A
R6331 R6333 VDDA SRN R6323

3
200K 10K 100K
B B
CHG_ILIM_HIZ 6 28 CHG_REGN_D 5
R6305 C6326 ILIM_HIZ REGN

4
+1P8VA 499K 1u CHG_VCCA Q6308B
C6307 C6312 GND
C6303 1800pCHG_COMP1_R R6320 40.2K CHG_COMP1 16 17 CHG_COMP2 R6302 10K CHG_COMP2_R 680p 2.2u
33p C6306 COMP1 COMP2 C6308 15p R6310 GND
GND
R6338 R6316 348K
2K 2K GND
GND R6329 100 CHG_PROCHOT#11 18 CHG_CELL_BATPRES GND
[10,26,66,76] H_PROCHOT# PROCHOT CELL_BATPRESZ
13
[35] CHARGER_SCL SCL
12 8 CHG_IADPT
[35] CHARGER_SDA SDA IADPT R6309
4 9 CHG_IBAT 249K
[34] CHRG_OK CHRG_OK IBAT
CHG_OTG_EN 5 10 PMON_R R6336 0
OTG/VAP PSYS PMON [66]
15 27 GND
CMPOUT PGND
R6301 14 33 C6327 C6319 R6337
R6341 CMPIN MPAD C6328
120K 100p 100p 137K
10K 100p R6340
DNP BQ25713RSNR 18.7K
DNP

GND GND GND GND GND

GND
GND GND

ILIM_HIZ current limit equation - (VILIM_HIZ – 1 V ) / 40 = ACP - ACN

7-bit I2C Address = 0x6B

A A

Title: CHARGER
<OrgName> Engineer:
<OrgAddr1>
Size Project Name Rev
A2 EDAN_A_EV1 1.00
Date: Tuesday, May 21, 2019 Sheet 63 of 82
5 4 3 2 1
 5 4 3 2 1

D D

+5VSB +5V_TS
+5V_TS_REG

U6407 DBG_TS
A2 A1 R6417 0.1
B2 IN_A2 OUT_A1 B1 0603S_P65-W95
C6415 IN_B2 OUT_B1 C6414
6.3V 1u PMTP6413 PMTP6414
0201S_P35-W35 C2 C1 6.3V 10u SP-TP-C0P381 SP-TP-C0P381
EN GND
NCP451AFCT2G 0402S_P7-W70
GND
+5V_TS
Iin=0.25A
GND GND Trace Width>20mil
R6425 0 +5V_TS_EN
[25,62] RTD3_TPANEL_PWR
C6413
0.1u 10V
0201S_P33-W39

+5VSB +5V_KIP
GND +5V_KIP_REG

U6403 DBG_TS
A2 A1 0.05 R6412
C B2 IN_A2 OUT_A1 B1 0603S_P6-W105 C
C6412 IN_B2 OUT_B1 C6417
6.3V 1u PMTP6401 PMTP6402
0201S_P35-W35 C2 C1 6.3V 10u SP-TP-C0P381 SP-TP-C0P381
EN GND
NCP451AFCT2G 0402S_P7-W70
GND
+5V_KIP
Iin=???A
GND GND Trace Width>20mil
R6415 1K KIP_EN
[35] SAM_KBTP_PWR_EN KIP_EN [76]
C6411
0.1u 10V
0201S_P33-W39

GND

+5VSB

+5V_AUDIO

C6408
1u 6.3V U6404 DBG_S
0201S_P35-W35 A2 A1 +5V_AUDIO_REG R6413 0.05
B2 IN_A2 OUT_A1 B1 0603S_P6-W105
B IN_B2 OUT_B1 B
PMTP6410 PMTP6411
R6423 0 ON_+5V_AUDIO_REG C2 C1 SP-TP-C0P381 SP-TP-C0P381
[25] RTD3_AUD_PWR_5P0 EN GND
0201S_P28-W35
NCP451AFCT2G C6420
10u 6.3V +5V_Audio
GND 0402S_P7-W70
TMAX=0.65mm
Iin=0.66A
GND Trace Width>20mil

+5VSB

+5V_FAN

C6416
1u 6.3V R6420 0.02
0201S_P35-W35 U6408 0603S_P6-W100
A2 A1 +5V_FAN_REG DBG_S
B2 IN_A2 OUT_A1 B1 PMTP6408 PMTP6409
IN_B2 OUT_B1 SP-TP-C0P381 SP-TP-C0P381

R6408 1K ON_+5V_FAN_REG C2 C1 +5V_Fan

[35] +5V_FAN_EN EN GND
A 0201S_P28-W35
NCP451AFCT2G
C6418
10u 6.3V
Iin=0.5A A

MTP6402 0402S_P7-W70 Trace Width>20mil

GND TMAX=0.65mm
GND

Title: +5V Load SW

<OrgName> Engineer: <OrgAddr1>
Size Project Name Rev
A3 EDAN_A_EV1 1.00
Date: Tuesday, May 21, 2019 Sheet 64 of 82

5 4 3 2 1
 5 4 3 2 1

PM_3P3V_PANEL_IN+ [28] PM_3P3V_PANEL_IN- [28]

C6521 10u

DBG_T

R6557
0
+3P3V_PANEL 47
DBG_T R6558
Imax=0.433A DBG_T

Trace Width> mil +3P3V_PANEL

D D

+3P3VSB DBG_TS
U6504 +3P3V_PANEL_REG
A2 A1 R6508 0.02
+1P8VSB B2 IN_A2 OUT_A1 B1
IN_B2 OUT_B1
PTP6501 PTP6502
C2 C1
C6501 EN GND
C6503 NCP451AFCT2G C6502
0.1u 1u GND 1u
R6544
U6503 47
GND +3P3VSB
GND
5 GND
2 VCC 4+3P3V_PANEL_EN_R R6519 1K +3P3V_PANEL_EN
[10,30] PCH_VDD_PANEL_EN A Y
1
[35] SAM_VDD_PANEL_EN B DSG_+3P3V_PANEL
3
GND R6548
+3P3V_PANEL_EN [76]
74AUP1G32GX +3P3V_PANEL_EN_R [10] 499K

6
R6501 R6529
100K 47K Q6501A
+3P3V +3P3V_PANEL_DISC_CTRL 2
GND

1
3
R6510 0.01
GND GND Q6501B
DBG_S 5
GND
C PTP6506 PTP6505 C

4
+3P3V
Imax=0.02A GND
Trace Width> mil
+3P3VSB
PM_3P3V_SSD+ [28]
U6511
PM_3P3V_SSD- [28]
A2 A1
VIN VOUT C6517 10u

[35,58] SLP_S3_DRV# R6564 0 B2 B1 C6513 DBG_T

EN GND
C6514 0.1u R6516
NX3P1108UK
1u GND 47 0
DBG_T
R6515
GND GND DBG_T

+3P3V_SSD_CON
+3P3V_REG
+3P3V_SSD_CON
R6511 0.02 Imax=2.25A
DBG_TS Trace Width>100mil
+3P3VSB PTP6504 PTP6503
U6502
B A2 A1 B
+3P3VSB
B2 IN_A2 OUT_A1 B1
IN_B2 OUT_B1
PM_3P3V_WWAN+ [28]

[58] SIL_SSD_VR_EN C2 C1 R6554 R6555 R6556 PM_3P3V_WWAN- [28]

EN GND 200K 140 140
C6511 NCP451AFCT2G C6512 0402 0402 C6522 10u
1u GND 1u 1/16W 1/16W
3P3V_SSD_DCH DBG_T

Q6505B Q6505A R6553

GND
3

GND 47 0
DBG_T
D

R6552
5 2 DBG_T
G G
+3P3VSB +3P3V_WWAN
S

S
4

R6514 0.02

DBG_TS
PTP6510 PTP6509
+3P3V_WWAN
GND C6508 Imax=2A
1u
+3P3VSB Trace Width>60mil
A U6509 A

A2 A1 GND
VIN VOUT +3P3V_TBT_BB0_REG +3P3V_BB0

[79] BB0_PD_LS_EN R6559 0 B2

BB0_PD_LS_EN_R B1 C6525 R6560 0.02
EN GND
C6524 0.1u +3P3V_BB0
1u
NX3P1108UK
GND Imax=0.22A
DBG_TS
PTP6513 PTP6514 Title: +3P3V Load SW
<OrgAddr1>
Trace Width> mil <OrgName> Engineer:
GND GND Size Project Name Rev
A3 EDAN_A_EV1 1.00
Date: Tuesday, May 21, 2019 Sheet 65 of 82
5 4 3 2 1
 1

+3P3VSB

R6604
0402 VDD33_VCCIN

4.7 C6603
4.7uF
10V
R6634
0 GND
[67] TEMP_VCCIN

Scale to 0.80V for Psys Max.

6.3V
[63] PMON PWM_VCCIN1 [67]

1u
R6635
PWM_VCCIN2 [67]
49.9K
C6601 R6601 R6636

C6612
8.06K 2M
4700p VCCIN_SEN
+VSYS
ALL

GND GND R6603

GND GND 133K
C6602 +3P3VSB +3P3VSB
0.01u

GND +3P3VSB

R6623

R6622

R6624
GND R6602 499K PE_VCCIN R6637 0

29

28
27
26
25
24
23
22
[67] CS_VCCIN2 U6601 ALL DNP

PSYS
TEMP
VDD33
PWM1
PWM2
PWM3
MPAD

VIN_SEN
[67] CS_VCCIN1
C6613 DNP

2K

2K

10K
1 21 GND
CSSUM_VCCIN CS3 EN ALL_SYS_PWRGD [58]
R6626 1.5K 2 20
R6627 1.5K 3 CS2 PE 19 IMVP_PROGRAM_ENABLE [35]
R6607 806 4 CS1 STB 18 IMVP_SCL_VCCIN SYNC_VCCIN [67] R6612 0
VFB_VCCIN VDIFF SCL_P IMVP_SCL_P [33,35]
R6608 0 0.1u C6606 5 17 IMVP_SDA_VCCIN R6615 0
VFB SDA_P VR_HOT#_VCCIN IMVP_SDA_P [33,35]
DNP DNP 6 16 R6638 100
A 7 VOSEN VRHOT# 15 VR_READY_VCCIN 0 R6639 H_PROCHOT# [10,26,63,76] A
VORTN VRRDY VRM_PWRGD [34,58]

SCLK/VID0
SDIO/VID1
GND R6609 100

CSSUM
+VCCIN

VDD18
IMON

ALT#
IREF
R6610 0 VOSEN_VCCIN
[13] VCCIN_VIN_SENSE
R6611 0 VORTN_VCCIN
[13] VCCIN_VSS_SENSE +VCCST_CPU
MP2940AGRT-002A-Z

8
9
10
11
12
13
14
R6613 100

R6605

R6606
GND

CSSUM_VCCIN
IMONA_CORE
IREF_VCCIN
VDD1V8_CORE

100

45.3
R6621 SVID_ALERT#_R 0 R6614
VIDSOUT_R SVID_ALERT# [13]
C6608 R6631 61.9K 0 R6616
VIDSCLK_R VIDSOUT [13]
220p 53.6K 0 R6617
VIDSCLK [13]
1% GND C6604
1u
70A
GND GND GND

W x H517 x 335 mm
Title: CONTROLLER: CORE, SA
<OrgName> Engineer: <OrgAddr1>
Size Project Name Rev
Custom EDAN_A_EV1 1.00
Date: Tuesday, May 21, 2019 Sheet 66 of 82
1
 1

[28] PM_VCCIN_IN+
Need to find 1.5W Sense resistor
+VCCIN_IN
C6703 10u
[28] PM_VCCIN_IN-
Place at DrMOS
DBG_T

U6701 C6730 C6731 R6703

C6714 C6704 C6705 0 +VSYS
47
[66] PWM_VCCIN1 15 BST 21 1u 10u 10u + + R6702
R6701
DBG_T
PWM 0402 16V 16V DBG_T
[66] SYNC_VCCIN 16 VIN1 1 25V 0603 0603 47u 47u E1 E2
SYNC VIN14 14 GND GND GND PMTP6702 PMTP6704
17 C6701 I1 I2
[66] TEMP_VCCIN VTEMPFLT +VCCIN
+3P3VSB HSFET
1u
L6704 0.005

DRIVE CONTROL
0201 VCCIN1_SW DBG_TS
20 SW2 2
VCC 3
SW3
4 0.15uH
SW4

1K
C6721 30A
18 470p IND_6P8X6P8X2P4-3 R6724 TP6702
CS LSFET
C6702 DNP
6.3V 0201S_P28-W35 TP6701
1u PGND13 13 R6721 DNP
GND PGND12 12 0
19 PGND511 5-11 DNP
[66] CS_VCCIN1 AGND GND

MP86902B GND GND

GND

Place at DrMOS + C6712

U6702
C6732 C6733 C6743 C6744 C6709 C6706
ICCMAX: 70A 180uF

[66] PWM_VCCIN2
SYNC_VCCIN
15

16
PWM

SYNC
BST

VIN1 1
21 C6713
1u
25V
10u
16V
10u
16V
+
47u
+
47u
+
47u
+
47u
ITDC: 39A
VIN14 14 0402 0603 0603 DNP DNP GND
TEMP_VCCIN 17 C6707
VTEMPFLT 1u 10V
A
+3P3VSB HSFET A
0201S_P4-W40
L6703
DRIVE CONTROL

20 SW2 2 VCCIN2_SW
VCC 3
SW3
4 C6723 0.15uH
SW4
C6711 470p 50V 30A

DNP
6.3V 18 0402S_P55
CS LSFET
1u
GND R6723
PGND13 13 0
PGND12 12 0603S_P6-W95

DNP
19 PGND511 5-11
[66] CS_VCCIN2 AGND

MP86902B

<Core Design>

W x H 357 x 241 mm
Title
IA and SA

Size Document Number Rev

CustomEDAN_A_EV1 <RevCod

Date: Tuesday, May 21, 2019 Sheet 67 of 82

1
 1

A A

<Core Design>

Title
<Title>

Size Document Number Rev

CustomEDAN_A_EV1 <RevCode

Date: Tuesday, May 21, 2019 Sheet 68 of 82

1
 1

PM_VCCIN_AUX_IN+ [28]

10u C6907
PM_VCCIN_AUX_IN- [28] +1P8VSB
DBG_T

R6903
0
47 C6904
DBG_T R6902 10V0.1u
DBG_T 0201S_P33-W39 U6902
PMTP6901 74AUP1G08GX
R6901
PMTP6902 5
+VSYS E1 SENSE E2 +VCCIN_AUX_IN VCCIN_AUX_EN 4 VCC 2
Y A 1 VSUS_ON [35,59,62]
B 1P8VSB_PG [62]
I1 LOAD I2 3
GND
C6903 C6909 C6908 C6910
0.02 + 1u
DBG_TS 10u 10u 25V 0 R6911
0603S_P94-W95
47u 16V 16V R6920 DNP
0603 0603 0603 100K
GND GND 0201S_P28-W35

+3P3VSB +1P8VSB

R6924 0
100K

100K

100K

100K

13
8
U6901 C6901 Idc 30A/Isat 40A
DNP DNP 0.22u +VCCIN_AUX

EN

BST1
L6905
VCCIN_AUX1_SW
R6921

R6905

R6918

R6913
2 12
R6919 VIN SW1
0 CORE_VID1_R 5 0.15uH
[26] CORE_VID1 VID1 31A IND_6P8X6P8X2 +
11 C6906
0 CORE_VID0_R 6 SW2 C6905
[26] CORE_VID0 VID0 220u
0.22u
R6910 9 10 R6923
A PG BST2 A

100
+3P3VSB
10K

10K

R6906
VOSEN_VCCIN_AUX
R6912

18 16 VCCIN_AUX_VIN_SENSE [26]
DNP 3V3 VOUT 0
DNP C6902 R6904 GND
VORTN_VCCIN_AUX
R6922

1u 6.3V 1 17 VCCIN_AUX_VSS_SENSE [26]

0201S_P35-W35 3 PGND1 RGND
4 PGND2 0
19 PGND3 R6908
PGND4

MODE
GND GND GND 100

CLM
FS
+3P3VSB +1P8VSB
MP2941GL
ICCMAX: 26A

15

14
GND
R6909 R6907
100K 100K GND

[34,58] VCCIN_AUX_PG
R6915
0
DNP
ITDC: 10A
R6914 R6917 R6916
150K 0 150K
DNP

GND GND GND

W x H 357 x 241 mm
Title: GT Controller
<OrgName> Engineer: <OrgAddr1>
Size Project Name Rev
Custom EDAN_A_EV1 1.00
Date: Tuesday, May 21, 2019 Sheet 69 of 82
1
 5 4 3 2 1

+VSYS PWR_SL1_F

R7043
+3P3VAS 249K

A1

A2
K
D7011
BAT54CW D7010
D BAT54CW D
DNP
+3P3VA +3P3V_HPD

A2

A1

K
U7000 R7000 100 SL1_HPD2 [71,76]
9
VDD R7002 SL1_HPD1A_O R7040
140 100 SL1_HPD1A [71,76]
7 SL1_HPD1B_U R7004 140 SL1_HPD1B_O R7039 100
HSD1p SL1_HPD1B [71,76]
1
[37] SAM_SL1_TX Dp 5 SL1_HPD1A_U
[37] SAM_SL1_RX 8 HSD2p R7042 C7000
Sp +3P3VA

DIO-ESD,SM,PESD24VS1UL,24 V,50 pF,1X.6X.

DIO-ESD,SM,PESD24VS1UL,24 V,50 pF,1X.6X.

DIO-ESD,SM,PESD24VS1UL,24 V,50 pF,1X.6X.

6 100K 1 6 4 3 100p

K PESD24VS1UL

K PESD24VS1UL

K PESD24VS1UL
2 HSD1m S D S D C7001 C7002 25V
Dm 4 100p DNP 100p
10 HSD2m 25V
DNP
25V
Q7006A Q7005B
[35] SL1_RX_SEL# Sm 3
GND

G
6

3
R7007 R7005
200K DG2723DN-T1-E4

D
200K

5
R7008 QFN10_1P85X1P45XP6_P4
C7003
R7006 4.32K
499K 0.1u 2 5
10V G G
Q7005A Q7006B

D7008

D7000

D7001
C7022

S
0.1uF

A
25V

4
TP7009
R7035 0
[35] SL1_ADC

[34,35] ADC_RD_EN
R7010
+3P3VA PSU Voltage Comparator PWR_SL1
D SL1_ADC_RD_EN_R

5.49K
PWR_SL1_F
D7004 (9.4V-17.2V) D7005
X865917-001 70 OHM
C A K PWR_SL1_F_COMP_VDD K A PWR_SL1_F L7000 3A C
0805S_1P1

PESD24VS1UL
RB520CS3002L RB520CS3002L

DIO-ESD,SM,PESD24VS1UL,24 V,50 pF,1X.6X.

G C7006 R7014 R7015 R7016 R7017 X865917-001 70 OHM
Q7000 +1P8VA R7021 100p 8.06 8.06 8.06 8.06 L7001 3A C7008
SOTFL-3_1P3XP9XP55_P4
C7015 499K C7009 25V 0201S_P33 0805S_1P1
C7010 100p R7019
0201S_P3

K
R7011 0.1uF 0.1uF 0.1uF 25V 499K
S

X865917-001 70 OHM
100K 25V 25V0201S_P35-W35 PWR_SL1_F_C L7007 3A C7007 25V C7012
R7023 SL1_20v0 0805S_1P1
100p 0.1uF
R7022 DNP

D7003
499K C7013 25V 25V
150K
U7004 1u

A
2 R7024 25V
6 VDD 4
0603S_P94-W95

OUTA INA+ 10K

1 C7016
5 OUTB 3
D7006 0.022u 1K 120 OHM
BATEN_PULSE_CONN [76]
GND INB- SL1_5v5 25V0201S_P33 BATEN_PULSE_R
0402S_P55
BATEN_PULSE_CONN
1.2A
[34,58] BATEN_PULSE +VDD_BATA_PACK
R7026 330 SL1_PSU_DETr A K TPS3700DSER L7006
[34,76] SL1_PSU_DET SON6_1P55X1P55XP8_P5 R7003
C7005 C7004
INA+ <400mV OUTA=Low R7027 100p 100p
RB520CS3002L 25V 25V
INB+ >400mV OUTB=Low 12.1K R7050

1
R7018 100 499K
[55] SL1_PWR_GOOD POS
0201S_P3
TP7007
NO-MSPN-00270
+1P8VA

A
SHUNT-NO-MSPN-00270
R7030 R7031 D7013
33K 1K
0603S_P6-W95 Red
NEG

RED
R7034

2
R7099 150K +VDD_BATA_PACK
SL1_PWR_GOOD#
SL1 port discharger

SL1_DISCHARGER

K
D

8.66K
B
D limits PSU anti-arc pulse voltage B
Q7001

3
SL1_PWR_GOODg G G NX3008NBKMB
R7001 1 Q7002 R7029
249K S 200K
[33,58,76] BAT_SHUTDOWN#
SC70-3_2P2X1P35X1_P65
DNP

2
S

R7033 120 OHM @100MHz

0402S_P55
51K 1.2A
DNP
[33,35] POWER_SMB_SDA
L7003
GND C7017
[33,35] POWER_SMB_SCL
100p [76] BAT_SMDATA
BAT_SMDATA
25V DNP
BAT_SMCLK
[76] BAT_SMCLK M1106392-001
[34] BAT_DET#
8 4
120 OHM @100MHz
BATA_DET#_CON 7 8 4 3
0402S_P55
1.2A 6 7 3 2
L7004 5 6 2 1
Present State Trigger Output 5 1
C7018
SL1_UART_TX SL1_UART_RX 1W/2W Initial 100p [76] BATA_DET#_CON N3 P3
25V DNP
N2 N3 P3 P2
Detect A/D read SL1_UART_TX_SEL_N SL1_UART_RX_SEL_N SL Polarity +3P3VAS_SIL N1 N2 P2 P1
N1 P1
Low Low Detach n/a Low Low Detach J7001
120 OHM @100MHz
1K 0402S_P55
Low High 1W n/a High Low Straight up +VSYS BATA_DET#rr
1.2A
L7005
R7037
High Low 1W n/a Low High Reversed R7044 C7020 C7021
1M 100p 100p C7019
25V 25V 0.1uF
High High 2W Valid Low Low Straight up
R7046 R7045
High High 2W Invalid High High Reversed 1.5K 1.5K
120 OHM
0402S_P55
[55] BAT_LDO 1.2A BAT_LDO_PACK [76]
A Q7003A Q7003B L7002 A
6

C7011
100p
D

25V
2 5BAT_SHUTDOWN#
G G
20160823sjs0632 : SL1 Power, Battery Connector Report errors to Steven
S

WxH 502 x 325 mm

Title: SL1 Power, Battery Conn
1

<OrgName> Engineer: <OrgAddr1>

Size Project Name Rev
Custom EDAN_A_EV1 1.00
Date: Tuesday, May 21, 2019 Sheet 70 of 82
5 4 3 2 1
 5 4 3 2 1

SL1_LANE1N_R SL1_LANE3P_R

SL1_LANE0P_R

SL1_LANE0N_R SL1_LANE2P_R

SL1_LANE1P_R SL1_LANE3N_R SL1_LANE2N_R

K1

K1

K1

K1

K1

K1
D7103 D7108 D7113 D7116

K1

K1
PESD5V0H1BSF
PESD5V0H1BSF
PESD5V0H1BSF
PESD5V0H1BSF D7107 D7118
PESD5V0H1BSF PESD5V0H1BSF D7112 D7105
PESD5V0H1BSF
PESD5V0H1BSF

K2

K2

K2

K2

K2

K2

K2

K2
GND GND
GND GND
D GND GND D

PW R_SL1

Same IPEX connector as LANCELOT

J7101
1
2 1
3 2
[70,76] SL1_HPD1A 3
4
USB3_SL1_RXP4_R 5 4
USB3_SL1_RXN4_R 6 5
7 6
USB3_SL1_TXP4_R 8 7
USB3_SL1_TXN4_R 9 8
10 9
SL1_LANE3P_R 11 10
SL1_LANE3N_R 12 11
13 12
SAM_DBG2_SL1_DP_HPD_CON 14 13
SAM_DEBUG_UART_RX_CON 15 14
USB2_SL1_D+_R 16 15
USB2_SL1_D-_R 17 16
18 17
[70,71,76] SL1_HPD2 18
19 62
20 19 MTG22 61
21 20 MTG21 60
22 21 MTG20 59
23 22 MTG19 58
[70,71,76] SL1_HPD2 SL1_LANE4N_R 23 MTG18
C 24 57 C
SL1_LANE4P_R 25 24 MTG17 56
SAM_DEBUG_UART_TX_CON 26 25 MTG16 55
SAM_DBG4_SL1_CONFIG1_CON 27 26 MTG15 54
28 27 MTG14 53
SL1_LANE2N_R 29 28 MTG13 52
3 4 SL1_LANE0P_R SL1_LANE2P_R 30 29 MTG12 51
[10] SL_DATA0_DP 30 MTG11
0nH 31 50
[10] SL_DATA0_DN 2 1 SL1_LANE0N_R SL1_LANE1N_R 32 31 MTG10 49
SL1_LANE1P_R 33 32 MTG9 48
[10] SL_DATA1_DP L7101 33 MTG8
34 47
[10] SL_DATA1_DN SL1_LANE0N_R 35 34 MTG7 46
SL1_LANE0P_R 36 35 MTG6 45
37 36 MTG5 44
38 37 MTG4 43
[70,76] SL1_HPD1B 38 MTG3
39 42
3 4 SL1_LANE1P_R 40 39 MTG2 41
0nH 40 MTG1
2 1 SL1_LANE1N_R
L7102

3 4 SL1_LANE2P_R
[10] SL_DATA2_DP
[10] SL_DATA2_DN 0nH
2 1 SL1_LANE2N_R
L7103

3 4 SL1_LANE3N_R
[10] SL_DATA3_DN
0nH
2 1 SL1_LANE3P_R
[10] SL_DATA3_DP
L7104
B B

U7104
A1 DP_O DP_I A2 SL1_LANE4N_R
[46] SL_AUX_DN
B1 DM_I B2 SL1_LANE4P_R
[46] SL_AUX_DP
DM_O C2
ID +5VSB
C1
GND

R7102
10K
GND
Note: IP3319CX6 D+ and D- is interchageable
SL1_HPD_DP_G
U7109

G
3 4 USB3_SL1_RXN4_R TP7101 R7101 0 SAM_DBG_RX_FILT 1 8 SAM_DEBUG_UART_RX_CON
[24] USB3_SL1_RXN4 [29,33,34,76] SAM_DBG_RX I1 O1
0nH R7103 0 SAM_DBG_TX_FILT 2 I O
7 SAM_DEBUG_UART_TX_CON
USB3_SL1_RXP4_R [29,33,34,76] SAM_DBG_TX SL1_DP_HPD_BUF 3 I2 O2
2 1 S D 6SAM_DBG2_SL1_DP_HPD_CON
[24] USB3_SL1_RXP4 [10] SL1_DP_HPD I3 O3
L7105 4 5SAM_DBG4_SL1_CONFIG1_CON
[46] SL1_CONFIG1 I4 GND PAD O4 9
GND
Q7102 R7125 R7113
12p
100K 1M GND

C7101 0.1u USB3_SL1_TXN4_C 3 4 USB3_SL1_TXN4_R

[24] USB3_SL1_TXN4
0nH
C7102 0.1u USB3_SL1_TXP4_C 2 1 USB3_SL1_TXP4_R
[24] USB3_SL1_TXP4
L7106 GND GND

A USB3_SL1_RXP4_R A

USB3_SL1_TXN4_R
2 L7107 1 USB2_SL1_D-_R
[24] USB2_SL1_DN USB3_SL1_TXP4_R
0nH 2.5GHZ
3 4 USB2_SL1_D+_R
[24] USB2_SL1_DP USB3_SL1_RXN4_R

3 2
K1

K1

K1

K1

K1

K1

4 1
0 DNP RN7107 D7119 D7106 D7117 D7102 D7104 D7109
PESD5V0H1BSF
PESD5V0H1BSF PESD5V0H1BSF
PESD5V0H1BSF
PESD5V0H1BSF
PESD5V0H1BSF

Title: SL1 SINGNALS

<OrgAddr1>
K2

K2

K2

K2

K2

K2

<OrgName> Engineer:
Size Project Name Rev
GND GND GND
A2 EDAN_A_EV1 1.00
Date: Tuesday, May 21, 2019 Sheet 71 of 82
5 4 3 2 1
 5 4 3 2 1

+3P3VA +3P3V_HPD
R7202 0.01
PTP7202
+3P3V_HPD_VIN
Imax=165uA
07132016
PTP7201
C7201 +3P3V_HPD_OCFLAG TP7204
1u
+3P3VA
+3P3V_HPD

GND
R7201 U7201
499K A1 A3
B1 VIN_A1 VOUT_A3 B3
VIN_B1 VOUT_B3
+3P3V_HDP_EN C3 C1
ON OCFLAGB
D A2 C7202 R7239 D
+3P3V_HPD_ILIMIT C2 GND_A2 B2
ISET GND_B2 1u 499K

FPF2495UCX

D
R7204 GND
G Q7201 20K
[35,76] SL1_HPD2_EN#
GND
S GND

R7206
GND
499K

GND
GND

+VCC_EDP_BKLT_IN +VCC_EDP_BKLT_OUT
Imax=0.16A
07132016
R7227 0 0603 +VCC_EDP_BKLT_IN
L7201
+VCC_EDP_BKLT_OUT
+5VSB BKLT_SW
C 1/10W C
10uH F7201 0.75A
DNP
R7228 0 0603 C7210 C7213 C7205
10u 10u 10u

1/10W
C7206 C7207 C7208
GND GND GND
+VCC_BKLT C7209 2.2u 2.2u 2.2u
0.22u 50V 50V 50V

C7204

BKLT_BST_SW
1u GND GND GND

GND
U7202

R7207 10 R7226 DNP 0 1 18

R7233 VCC OUT
10K 24
C7218 VIN 20 R7229
L_BKLT_CTRL_R R7209 1K BKLT_PW M_R 5 SW 47
1u PWM
21 BKLT_BST
[76] BKLT_PW M_R BST
[76] BKLT_EN
GND
BKLT_EN_R R7208 1K BKLT_EN 2 8 BKLT_FB8_R R7231 0
EN LED8 BKLT_FB8 [57,76]
2

9 BKLT_FB7_R R7230 0
LED7 BKLT_FB6_R BKLT_FB7 [57,76]
6 10 R7223 0
G

A0 LED6 BKLT_FB6 [57,76]

5

7 11 BKLT_FB5_R R7222 0
Q7204A A1 LED5 BKLT_FB4_R BKLT_FB5 [57,76]
12 R7221 0
G

LED4 BKLT_FB3_R BKLT_FB4 [57,76]

13 R7220 0
Q7204B BKLT_SCL LED3 BKLT_FB2_R BKLT_FB3 [57,76]
6 1 R7203 0 4 14 R7219 0
[35] SAM_PANEL_SCL D S BKLT_SDA SCL LED2 BKLT_FB1_R BKLT_FB2 [57,76]
R7210 0 3 15 R7218 0
SDA LED1 BKLT_FB1 [57,76]
3 4
[35] SAM_PANEL_SDA D S 23 22
FT NC22 19
NC19 17
B 25 NC17 B
R7224 AGND_EP 16
R7225 PGND
0
0 DNP
ALL
C7203 GND MP3376AGR-0300 GND
2.2u
DNP
10V

7-bit I2C Address = 0x28

GND GND

PM_BKLT_IN+ [28]
DG2723 AND MP3376 ARE 1.8V LOGIC ON EN, PWM AND I2C
PM_BKLT_IN- [28]
C7221 10u

DBG_T
R7240 +VCC_EDP_BKLT_IN
47 0 R7234
+VSYS DBG_T 0
Q7203 +VCC_EDP_BKLT_IN_REG PTP7204 R7241 +3P3VSB ALL
DBG_T
PTP7203
2 3 R7217 0.02
S D C7220
DBG_TS
0.1u
G

R7213 C7215 U7204

1

DNP
200K 1000p R7216 R7215 9
VDD
5.1K 5.1K GND
C7216 7
+VCC_EDP_BKLT_IN_DRI [35] SAM_LCD_BKLT_EN HSD1p BKLT_EN_MUX 0 BKLT_EN_R
0.1uF +3P3VSB +1P8VSB 1 DNP R7250
DNP 5 Dp
[10,34,72] PCH_LCD_BKLT_EN HSD2p 8
R7214 Q7202B +VCC_EDP_BKLT_IN_DISC 6 Sp
GND [35] SAM_BKLT_CTRL_PW M HSD1m
3

SAM_LCD_BKLT_EN 100K R7238 R7242 2 L_BKLT_CTRL_MUX 0DNP R7251 L_BKLT_CTRL_R

4 Dm
0 0
D

A [10,72] PCH_BKLT_CTRL_PW M HSD2m A

DNP 10 R7237 DNP 0
+VCC_EDP_BKLT_IN_DRI_R Sm PCH_SAM_INST_ON [23,34]
R7235 5 3
Q7202A G R7205 R7232 GND
0
6

+3P3V_PANEL ALL 100K 100K DG2723DN-T1-E4 R7236

S

U7205 DNP DNP 47K

D

74AUP1G08GX DNP
4

R7211 DNP 22K +VCC_EDP_BKLT_IN_R 2 5

G 2 VCC 4 R7256 ALL 0 L_BKLT_CTRL_R
[10,34,72] PCH_LCD_BKLT_EN A Y GND
1 GND GND
[10,72] PCH_BKLT_CTRL_PW M B
S

3 C7211 GND
R7212 C7214 GND 0.1u
+3P3V_HPD/LCD backlight
1

GND R7255 R7254 10V

100K
DNP 0.1u 100K 100K Title:
DNP ALL <OrgAddr1>
<OrgName> Engineer:
Size Project Name Rev
GND
GND GND GND GND
A2 EDAN_A_EV1 1.00
Date: Tuesday, May 21, 2019 Sheet 72 of 82

5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Title: PCIe GPU

<OrgName> Engineer:
<OrgAddr1>
Size Project Name Rev
A2 EDAN_A_EV1 1.00
Date: Tuesday, May 21, 2019 Sheet 73 of 82

5 4 3 2 1
 5 4 3 2 1

KBTP CONNECTOR +1P8VA +1P8VSB

Pin1 Top Left [76] 1P8V_KIP

R7414
0
R7415
0
J7401 +5V_KIP ALL
D D
PINS REVERSED DNP
0 R7403 KIP_FPC_CONN_DET_B# 2 1
[58] KIP_FPC_DET_B# 2 1 1P8V_KIP
4 3 R7418 ALL 0
[29,76] KIP_SW D_CLK 4 3
6 5
6 5 KIP_SW D_DIO [29]

K
8 7 SAM_KIP_RST# [29,35]
[29] KIP_TRACE_SW O 8 7 KIP_FPC_CONN_DET_A#
10 9 R7401 0
[34,74,76] SAM_KIP_UART_TX KIP_PW R_SW _N 10 9 KIP_FPC_DET_A# [58]
R7427 100 12 11 D7414 C7404
[31,58] PW RBTN#_3V3 12 11 SAM_KIP_UART_RX [34,74]
PESD5V0F1USF315 6.3V 1u

D7408
R7421 U7402

A
K
14 13

D7407
499K NX3P1108UK
MTG2 MTG1 DNP

K
16 15

D7405
C7405 ALL BGA4_2X2_P98XP98XP59_P5
MTG4 MTG3

K
A1 A2

D7409
1000p R7417 0 GND
VOUT VIN

D7413

A
DF40B-12DS-0.4V(51)
DNP

PESD3V3U1UL315
A
C7403 B1 B2 1K R7416

PESD3V3U1UL315
A

A
GND EN KIP_LS_EN [35]
10V 0.1u

A
DBG_D
GND
DNP
DNP GND [76] KIP_LS_EN_R
DNP
DNP
DNP

C C

+1P8VSB

C7435
0.1u
U7410
6.3V
DBG_D 8
VCC
+1P8VSB GND
1
1Y SAM_KIP_UART_RX_DBG [29,33]
7
[34,74] SAM_KIP_UART_RX 1A
R7402 6
100K 1B 5
2Y SAM_KIP_UART_TX_DBG [29,33]
DBG_D
3
[34,74,76] SAM_KIP_UART_TX 2A
2
[34] BLADE_UART_DBG_EN 2B 4
GND

SN74AUP2G08RSER
GND
X912843-001

DBG_D

KIP UART Debug gated Sniffer (Dual AND gate, )

Place U7410 close to J7401 UART lines to minimize stubs

B B

A A

Title: Blade Interface

<OrgName> Engineer: <OrgAddr1>
Size Project Name Rev
A2 EDAN_A_EV1 1.00
Date: Tuesday, May 21, 2019 Sheet 74 of 82
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

W x H 357 x 231 mm
Title: Power Protect
<OrgName> Engineer: <OrgAddr1>
Size Project Name Rev
Custom EDAN_A_EV1 1.00
Date: Tuesday, May 21, 2019 Sheet 75 of 82
5 4 3 2 1
 5 4 3 2 1

MTP7606
RGB_LED_A_P [54]
MTP7674 +5V_KIP
XDP_TCK [10,18]
MTP7631 MTP7635
XDP_TDI [10,18] PWR_SL1
MTP7669
XDP_TDO [10,18] +VDD_BATA_PACK
MTP7607 PWR_SL1_F
XDP_TMS [10,18]
MTP7655
XDP_TRST# [10,18]
MTP7626 MTP76154 MTP76162
MTP76155 MTP76163
MTP7619 +1P1V_DDR_VDD2 MTP7691 MTP7633 MTP7959 MTP76156 MTP76164
SPI_CLK_R1 [21] RTD3_CAM_PWREN [25,54]
MTP7656 MTP7650 MTP7610 MTP76157 MTP76165
MTP7657 SPI_MOSI_R1 [21] MTP7604 MTP7688 MTP7660 MTP76158 MTP76166
MTP7639 SPI_MISO_R1 [21] MTP7614 MTP7643 MTP7680 MTP76159 MTP76167
SPI_WP_IO2_R1 [21] IRLED_C_N [54]
D MTP7613 MTP7668 MTP76112 MTP76160 MTP76168 D
MTP7671 SPI_HOLD#_IO3_R1 [21] +0P6V_DDR_VDDQ MTP76111 MTP76113 MTP76161 MTP76169
SPI_CS#0_R [21] MTP7644 MTP7618 MTP7605
IRLED_A_P [54]
MTP7679 MTP7640 MTP7622

MTP7672 Place close to J7101

+VCCPLL_OC 3P3_CAM [54]
MTP7690 Place close to J7702
EDP_I2C_INT [10,57]
MTP7659 MTP7625 MTP7661
KIP_SWD_CLK [29,74] CAM_IR_STB [54]
MTP7684 +3P3VSB
1P8V_KIP [74]
MTP7664
CAM_IR_STB_R [54]
MTP7667 MTP7681
SAM_KIP_UART_TX [34,74]
MTP7645
SL1_EN_N [63] GND MTP Close to J5401 Place Close(Under) to JP4001
MTP7616 MTP76190
MTP7638 +5VSB
MTP7687 PCH_TRST# [10,18] MTP7620 MTP7685 GND MTP Close to J5401
PCH_JTAG_TCK [10,18] SEN_HALL_INT#_S [34,54]
MTP7651 MTP7648
PCH_JTAG_TDI [10,18] GND MTP close to U5505
MTP7612 MTP76131 AGND
PCH_JTAG_TDO [10,18]
MTP7675 MTP7677
PCH_JTAG_TMS [10,18] SEN_HALL_INT#_N [34,54] GND MTP close to J5701
MTP7629 MTP76132
PCH_JTAGX [10,18] +VCCSTG
MTP76133 GND MTP close to J5701
MTP7682 MTP7627
SAM_UEFIROM_EN [21,35] GND MTP close to J5401
MTP7628 MTP76134
+VCC_RTC PWRBTN#_1V8_FILT [31]
C MTP7654 MTP76100 MTP76135 GND MTP close to J7701 MTP76197 C
PMI_I2C_SDA [25,28,33] VOL_UP#_FILT [31] H_PROCHOT# [10,26,63,66]
MTP7647
PMI_I2C_SCL [25,28,33] GND MTP close to J7701
MTP76101 MTP76136
VOL_DOWN#_FILT [31]
MTP7636
MTP76137 GND MTP close to J7701

+1P8VSB MTP76110 MTP76138 GND MTP close to J7701

SAM_SWD_SWO [29,33,34]
MTP7642
SAM_SWD_CLK [29,33,34] GND MTP close to J7701
MTP7658 MTP7652 MTP7663 MTP76139
BKLT_PWM_R [72] SAM_SWD_DIO [29,33,34]
MTP7608
BKLT_EN [72] GND MTP close to J7701
MTP7617 MTP76140
+VCC1P8A SL1_HPD2 [70,71]
MTP7697
SL1_HPD1A [70,71]
MTP7694 MTP76104
BKLT_FB8 [57,72] SL1_HPD1B [70,71]
MTP7695
BKLT_FB7 [57,72]
MTP7696 MTP7693 MTP76170
BKLT_FB6 [57,72]
MTP7923 MTP76173 BAT_LDO_PACK [70]
BKLT_FB5 [57,72]
MTP7649 MTP76171
BKLT_FB4 [57,72]
MTP7699
BKLT_FB3 [57,72]
MTP7670 MTP76172
BKLT_FB2 [57,72] +1P8V_DDR_VDD1 SL1_HPD2_EN#_MTP R7601
MTP7927 MTP76174 1K
BKLT_FB1 [57,72] SL1_HPD2_EN# [35,72]
MTP7634

MTP7653 MTP7646
PMI1_I2C_SCL_R [28] +3P3V_PANEL DDR_PGD_SIL [58]
MTP7676
PMI1_I2C_SDA_R [28] +VBUS_P0_CONN GND
+VSYS MTP7698
B
EXT_DC_IN +1P1V_DDR_PG [60] B
MTP76114 MTP76176
MTP7609 MTP76115 MTP76182
+3P3V_PANEL_EN [65] MTP76116 MTP76183 +3P3VA MTP76102
+3P3V EDP_I2C_SCL [57]
MTP7602 MTP76117 MTP76184 MTP7662
PIO5_20 [33,35] +3P3V_SSD_CON EDP_I2C_SDA [57]
MTP76118 MTP76185
MTP7666 MTP76119 MTP76186 +3P3V_BB0 MTP76103
PIO5_21 [33,35] SAM_PIO0_3 [34]
MTP76187 MTP76105
SAM_PIO0_4_ISP0 [34]
MTP7673 MTP76106
SLG_PWRBTN# [58] +VCC_EDP_BKLT_OUT SAM_PIO0_5_ISP1 [34]
MTP76107
SAM_PIO0_6_ISP2 [34]
MTP7630 MTP7615
PCH_SENSOR_I2C_SDA [25,54] SAMRTS_PCHCTS [25,29,33,34]
MTP76120 MTP76108
TCON_VENDOR_ID [24,57]
MTP7683 MTP76121 MTP7689
PCH_SENSOR_I2C_SCL [25,54] PCHRTS_SAMCTS [25,29,33,34]
MTP76109
TP_CATERR#_R [10]
+1P8V_AUDIO

MTP7603 MTP76141
SAM_RESET# [29,33,34,58]
MTP76175
+VCCST_CPU SL1_PSU_DET [34,70]
MTP76122
MTP76123 HP_MIC_LR_CON [41] MTP76126
HPOUT_R_CON [41] USB2_USBA_DN_CONN [45]
MTP76124 MTP7621 MTP76127 MTP76177
HPOUT_L_CON [41] USB2_USBA_DP_CONN [45] BATEN_PULSE_CONN [70]
MTP76125 MTP76178
HPOUT_JD [40,41] BAT_SMCLK [70]
CON2_VBUS MTP76179
+VCCIN BAT_SMDATA [70]
MTP76128 MTP76180
BATA_DET#_CON [70]
MTP76129 MTP76181
DMIC_DATA1_CODEC [40,54] BAT_SHUTDOWN# [33,58,70]
MTP76130 MTP7637 MTP76188
DMIC_CLK_CODEC [40,54] +VCCIN_AUX MTP76146 KIP_LS_EN_R [74]
TCP0_CONN_CC1 [77] MTP76189
KIP_EN [64]
A MTP76147 USB2_TCP0_CONN_A_DP [77] A
MTP76142 MTP7665 MTP76148 USB2_TCP0_CONN_A_DN [77]
SPK_R+_CON [41]
MTP76143 MTP76149 TCP0_CONN_SBU1 [77] MTP76191
SPK_R-_CON [41] PCH_DBG_TX [25,29,33]
MTP76144 +5V_KIP MTP76192
SPK_L+_CON [41] PCH_DBG_RX [25,29,33]

W x H 427 x 276 mm
MTP76145 MTP76193
SPK_L-_CON [41] SAM_DBG_TX [29,33,34,71]
MTP7632 +1P8VA MTP76150 MTP76194
MTP76151
MTP76152
TCP0_CONN_SBU2
USB2_TCP0_CONN_B_DN
[77]
[77]
SAM_DBG_RX [29,33,34,71]
Title: Frames, Holes, & Mechanical
MTP7692 MTP76153
USB2_TCP0_CONN_B_DP
TCP0_CONN_CC2
[77]
[77] MTP76196
FPC_DET_LOGIC_OVERRIDE# [33,58]
<OrgName> Engineer: <OrgAddr1>
Size Project Name Rev
+5V_AUDIO In RAFLA this Signal will be pulled "LOW" via 1K resistor
MTP7624 Custom EDAN_A_EV1 1.00
Date: Tuesday, May 21, 2019 Sheet 76 of 82
5 4 3 2 1
 5 4 3 2 1

+3P3VSB U7700C +3P3V_PD_OUT

TP7714 +3P3V_BB0 A12
TP7715 R7717 0 VCCP3P3_SVR_TCP0 J5 NC1 F3
U7700A TP7716
J6 NC2 VSS_1 F5
TCP0_EE_DI NC3 VSS_2

R7710
C6 C9 TCP0_I2C_SCL_R R7704 0 PD_I2C2_SCL [21,79] L3 G5
EE_DI I2C_SCL NC4 VSS_3

0201S_P35-W35
TCP0_EE_DO

10K

100K

100K
B4 E7 TCP0_I2C_SDA_R R7705 0 PD_I2C2_SDA [21,79] C7708
TCP0_EE_CS# B6 EE_DO I2C_SDA A10 TCP0_I2C_INT#_R R7706 0 B1 F12 1u 6.3V
PD_BB_I2C2_INT# [22,79]
TCP0_EE_CLK C7 EE_CS I2C_INT B12 VSS_ANA_1 VSS_ANA_12 G7

0201S_P28-W35

0201S_P28-W35
EE_CLK B10 BB0_FORCE_PWR_R R7757 0 D1 VSS_ANA_2 VSS_ANA_13 H1
BB_FORCE_PWR [10,79]
FORCE_PWR VSS_ANA_3 VSS_ANA_14

R7709

R7711
A9 D2 H11
+VCC3P3_LC_TCP0 TP7702 FLASH_BUSY D11 VSS_ANA_4 VSS_ANA_15 H12
TP7707 TCP0_TDI A3 B9 BB0_POC_GPIO_5 D12 VSS_ANA_5 VSS_ANA_16 H2 U7703
10K R7727 TCP0_TMS C3 TDI POC_GPIO_5 A8 BB0_POC_GPIO_6 F1 VSS_ANA_6 VSS_ANA_17 J9 A3
TCP0_TCK B5 TMS POC_GPIO_6 A4 BB0_FLASH_SHARE_EN F2 VSS_ANA_7 VSS_ANA_18 K1 VSYS
10K R7747 TCP0_TDO C5 TCK POC_GPIO_10 A5 BB0_FLASH_MASTER F7 VSS_ANA_8 VSS_ANA_19 K11 A2 A1 TCP0_CONN_CC1
TDO POC_GPIO_11 VSS_ANA_9 VSS_ANA_20 [79] TCP0_CC1 CC1 CON_CC1
A6 BB0_POC_GPIO_12 F9 K12
10K R7744 POC_GPIO_12 B8 BB0_PERST#_R R7765
0 0201S_P28-W35
F11 VSS_ANA_10 VSS_ANA_21 K2 B2 B1 TCP0_CONN_CC2
TP7701 PERST BB_PERST# [22] VSS_ANA_11 VSS_ANA_22 [79] TCP0_CC2 CC2 CON_CC2
M11
D 10K R7734 TP7708 THERMDA A7 QUTZ 9999HF C2 C1 TCP0_CONN_SBU1 D
TP7706 SMBUS_SCL PD_SML0_SCL [25] [29] TCP0_SBU1 SBU1 CON_SBU1
M12 B7 PD_SML0_SDA [25] M1111477-001
B2 TEST_EDM SMBUS_SDA D2 D1 TCP0_CONN_SBU2
FUSE_VQPS_64 [29] TCP0_SBU2 SBU2 CON_SBU2
TCP0_SBUEN D3 C3 TCP0_FLG
A11 SBUEN FLAG
L12 MONDC B3
MONDC_SVR GND

1M

1M
0201S_P28-W35

0201S_P28-W35

0201S_P28-W35
L11 BB0_RESET# R7761 0 BB0_PD_RESET# [79]
R7766 RESET NX20P0407UK
100 1% BB0_TEST_PWR_GOOD B3 L9
B11 TEST_PWR_GOOD XTAL_25_IN M9 TCP0_XTAL_25_OUT C7712
TEST_EN XTAL_25_OUT

R7708

R7702
0201S_P28-W35 10u 6.3V

1M
0201S_P28-W35
Y7701 0402S_P7-W70 GND
TP7703 SP_TP_SMDP58 DNP
A1 L5 TCP0_XTAL_25_IN 1 3 R7755 100
A2 ATEST_P RSENSE L4 2 4
ATEST_N RBIAS GND +VBUS_P0_CONN

R7701

C7713
TP7705

C7707
SP_TP_SMDP58
QUTZ 9999HF ALL
+3P3VSB

4.75K
M1111477-001 18p 25MHz J7701
ALL
18p A1
D7701 0201S_P33
ALL TCP0_TX_CONN_P0 A2 GND_A1
A K 3P3V_RT_FLASH
0201S_P33
TCP0_TX_CONN_N0 A3 TX1p
TX1m

R7712
A4
TCP0_CONN_CC1 A5 VBUS_A4
RB520CS3002L [76] TCP0_CONN_CC1 CC1
USB2_TCP0_CONN_A_DP A6
C7709

C7747 [76] USB2_TCP0_CONN_A_DP

USB2_TCP0_CONN_A_DN Dp_A
2.2K

2.2K

R7722 3.32K

3.32K
0.22u A7
[76] USB2_TCP0_CONN_A_DN Dm_A
TCP0_CONN_SBU1
2.2u

10V [76] TCP0_CONN_SBU1 A8

TP7712
A9 SBU_A
TCP0_TXRX_CONN_N1 VBUS_A9
R7721

R7713

SP_TP_SMDP58
GND A10
TCP0_TXRX_CONN_P1 A11 RX2m
RX2p
R7720

TP7710
0 U7702 A12
TCP0_EE_CS# R7725
1 8 SP_TP_SMDP58 GND_12
0201S_P28-W35
0 CS# VCC
TCP0_EE_DO R7726
2 7 B12
0201S_P28-W35 SO/SIO1 HOLD# TCP0_TXRX_CONN_P0 B11 GND_B12 1
3 6 R7723
0 TCP0_EE_CLK TCP0_TXRX_CONN_N0 B10 RX1p MTG1 2
WP# SCLK 0201S_P28-W35
B9 RX1m MTG2 3
4 5 R7724
0 TCP0_EE_DI TCP0_CONN_SBU2 B8 VBUS_B9 MTG3 4
GND SI/SIO0 [76] TCP0_CONN_SBU2 SBU_B MTG4
9 0201S_P28-W35 USB2_TCP0_CONN_B_DN B7 5
C EPAD [76] USB2_TCP0_CONN_B_DN Dm_B MTG5 C
USB2_TCP0_CONN_B_DP B6 6
[76] USB2_TCP0_CONN_B_DP Dp_B MTG6
TP7711 SP_TP_SMDP58 TCP0_CONN_CC2 B5 7
MX25L8006EZUI-12G [76] TCP0_CONN_CC2 CC2 MTG7
B4 8
TP7713 TCP0_TX_CONN_N1 B3 VBUS_B4 MTG8 9
SP_TP_SMDP58 TCP0_TX_CONN_P1 B2 TX2m MTG9 10
B1 TX2p MTG10 11
Use 25V cap on the connector side to protect pin short to VBUS GND_B1 MTG11

C7725

C7724
U7700D DNP DNP M1084960-001
TCP0_TX_C_P0 J1 TCP0_TXRX_RT_P0 R7768 TCP0_TXRX_RT_P0_RC

100p

100p
[10] TCP0_TX_P0 C7734 0.22u J12 2.2 C7719 0.33u 25V 0201
C7730 TCP0_TX_C_N0 J2 ASSRXP1 BSSRXP1 J11 TCP0_TXRX_RT_N0 R7769 2.2 TCP0_TXRX_RT_N0_RC C7721 0.33u 25V 0201
[10] TCP0_TX_N0 0.22u
ASSRXN1 BSSRXN1

10%

10%
[10] TCP0_TXRX_P0 C7736 0.22u TCP0_TXRX_C_P0 G1 G12 TCP0_TX_RT_P0 R7770 2.2 TCP0_TX_RT_P0_RC C7720 0.22u 25V 0201
ASSTXP1 BSSTXP1
0.22u TCP0_TXRX_C_N0 G2 TCP0_TX_RT_N0 TCP0_TX_RT_N0_RC

C7710

C7717

C7711

C7706
[10] TCP0_TXRX_N0 C7733 G11 R7771 2.2 C7718 0.22u 25V 0201
ASSTXN1 BSSTXN1

PTVS24VS1UR
K
TCP0_TX_C_P1 C1 TCP0_TXRX_RT_P1 R7772 TCP0_TXRX_RT_P1_RC

0.1u

0.1u

0.1u
C7722 0.22u C12 2.2 C7738 0.33u 25V 0201
+3P3V [10] TCP0_TX_P1 ASSRXP2 BSSRXP2
C7732 0.22u TCP0_TX_C_N1 C2 C11 TCP0_TXRX_RT_N1 R7773 2.2 TCP0_TXRX_RT_N1_RC C7745 0.33u 25V 0201 R7756
[10] TCP0_TX_N1 ASSRXN2 BSSRXN2

D7717
39.2K
0.22u TCP0_TXRX_C_P1 E1 TCP0_TX_RT_P1 TCP0_TX_RT_P1_RC

0.1u
BB0_POC_GPIO_6 R7714 10K [10] TCP0_TXRX_P1 C7729 E12 R7774 2.2 C7737 0.22u 25V 0201 0201 1% 35V 35V 35V
ASSTXP2 BSSTXP2
C7726 0.22u TCP0_TXRX_C_N1 E2 E11 TCP0_TX_RT_N1 R7775 2.2 TCP0_TX_RT_N1_RC C7743 0.22u 25V 0201

A
[10] TCP0_TXRX_N1 ASSTXN2 BSSTXN2 35V

K1
220K

220K

220K

220K

220K

220K

220K

220K
[10] TBT_LSX0_TXD M7 M10 TCP0_BB_SBU1 [29]
PA_LSTX_SBU1 BSBU1

K1

K1

K1
L7 L10
+3P3V_BB0 [10] TBT_LSX0_RXD PA_LSRX_SBU2 BSBU2 TCP0_BB_SBU2 [29]

D7702

PESD24VF1BL

PESD24VF1BL
0 TCP0_AUX_DP_R L8

D7708

D7709

D7715
[10] TCP0_AUX_DP R7748 D7703 D7710 D7716 D7718 D7712 D7714 PESD24VF1BL
PA_AUX_P
0 TCP0_AUX_DN_R M8

ALL

ALL

ALL
R7779

R7776

R7777

R7778

R7780

R7781

R7784

R7783
[10] TCP0_AUX_DN R7707 D7707 D7711 PESD24VF1BL
PA_AUX_N

A2

A2

A2

A2

A2

A2

A2

A2

K2
BB_FORCE_PWR

ALL
R7743 0201S_P28-W35
R7739 10K DNP 1M QUTZ 9999HF
DNP DNP DNP DNP

K2

K2

K2
R7703 0201S_P28-W35
DNP 1M

ESDL2011PFCT5G

ESDL2011PFCT5G

ESDL2011PFCT5G

ESDL2011PFCT5G

ESDL2011PFCT5G

ESDL2011PFCT5G

ESDL2011PFCT5G

ESDL2011PFCT5G
M1111477-001
BB0_FLASH_SHARE_EN

A1

A1

A1

A1

A1

A1

A1

A1
R7738 10K ALL

BB0_FLASH_MASTER BB0_POC_GPIO_12: Has internal PU

R7719 10K DNP BB_FORCE_PWR:

'0' - By default
'1' - For debug only/FW update TCP0_DBG0_A_DP_R USB2_TCP0_CONN_A_DP
BB0_POC_GPIO_12 R7749 0 4 L7708 3
[29] TCP0_DBG0_A_DP
B BB0_FLASH_SHARE_EN (internal-PU) B
R7767 10K DNP '0' - Flash isn't shared, 1 flash per re-timer R7750 0 TCP0_DBG1_A_DN_R 1 2 USB2_TCP0_CONN_A_DN
[29] TCP0_DBG1_A_DN
'1' - Flash is shared between 2 re-timers DLP11TB800UL2L
R7737 DNP
BB0_POC_GPIO_5 10K ALL D7721 PESD5V0H1BSF
BB0_FLASH_MASTER (internal-PU) 2 3 K2 K1
R7752 10K '0' - Set re-timer to be slave on shared flash SPI I/F 1 4
'1' - Set re-timer to be master on shared flash SI I/F D7720 PESD5V0H1BSF
RN7704 0 DNP K2 K1

+3P3V_BB0 +VCC3V3_TCP0 +VCC3V3A_TCP0 TCP0_DBG2_B_DP_R 4 3 USB2_TCP0_CONN_B_DP

R7753 0 L7707
[29] TCP0_DBG2_B_DP
R7732 0603 0 R7754 0 TCP0_DBG3_B_DN_R 1 2 USB2_TCP0_CONN_B_DN
[29] TCP0_DBG3_B_DN
DLP11TB800UL2L
+VCC3P3_LC_TCP0 +VCC0V9_SVR_TCP0 ALL D7719 PESD5V0H1BSF
2 3
C7731

C7748 K2 K1
U7700B 0.22u 1 4
2.2u

+VCC3P3_ANA_TCP0 L2 E6 10V D7722 PESD5V0H1BSF

VCC3P3_ANA VCC3P3_SX RN7703 0 DNP K2 K1
E5 M4 GND
C7705 VCC3P3_LC VCC3P3_SVR_1 M5
C7701 E3 VCC3P3_SVR_2 J7 +3P3V_DEBUG
2.2u G3 VCC0P9_SVR_1 VCC3P3A C7750
C7735

C7714

C7704

VCC0P9_SVR_2
0805S_1P45
C7759

2.2u 0.1u
6.3V
47u

2.2u

2.2u

2.2u

E9 U7704
G9 VCC0P9_SVR_PB_ANA_1 9 10V
VCC0P9_SVR_PB_ANA_2 0201S_P39-W39 +VCC0V9_SVR_TCP0 1 VCC
0201S_P39-W39 0201S_P39-W39
2 D1+ 3
L7706 D2+ D+ USB2_TCP0_DP [24]
F6
G6 VCC0P9_SVR_ANA_1 7
VCC0P9_SVR_ANA_2 0.68uH 6 D1- 5
D2- D- USB2_TCP0_DN [24]
C7758

L1
C7727

C7739

C7740

C7741

C7742

C7744

C7746

+VCC0P9_SVR_TCP0_PHASE

+VCC0P9_LC_TCP0 J3 SVR_IND_1 M1 10
VCC0P9_LC SVR_IND_2 [79] PD_USB2_MUX_FLIP S
47u

2.2u

2.2u

2.2u

2.2u

2.2u

2.2u

8 4
+3P3V_DEBUG OE GND
18p

+VCC0P9_LVR_TCP0 L6 M2 0603
M6 VCC0P9_LVR SVR_VSS_1 M3
C7715

A
TS3USB30E A
VCC0P9_LVR_SENSE SVR_VSS_2
C7723

C7749
2.2u

10u 6.3V QUTZ 9999HF R7758 U7704 Layout Short during PV/DV
2.2u

0402S_P7-W70 M1111477-001 100K

1%
+VCC3V3_TCP0 +VCC3V3A_TCP0 USB2_TCP_MUX_EN#
0201
D

R7782 0603 0 20160609sjs1551

G Report errors to Steven
[29] MUX0_EN# title is: Blank_602x390

WxH 602 x 390mm

C7703

C7702

C7752 Q7701 Report errors to Steven

10u 6.3V
R7759 Title: Blank_602x390
S

0402S_P7-W70
2.2u

100K
<OrgName> <OrgAddr1>
18p

DNP
1% Engineer:
20%
0201 Size Project Name Rev
Custom EDAN_A_EV1 1.00
Date: Tuesday, May 21, 2019 Sheet 77 of 94
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

WxH 602 x 390mm

Title:Blank
<OrgName> Engineer: <OrgAddr1>
Size Project Name Rev
Custom EDAN_A_EV1 1.00
Date: Tuesday, May 21, 2019 Sheet 78 of 94
5 4 3 2 1
 5 4 3 2 1

+5VSB EXT_DC_IN +VBUS_P0_CONN

DBG_TS 0603S_P6-W100
R7957 0.01

K
+3P3VSB +3P3VA +

C7906

C7913
C7943 C7909 D7905
150u 4.7u RB520CS3002L
20%
+ C7919 C7944 1u 1u
10V
22u 25V 25V

A
25V 10u
DNP 35V
+5VSB
PLACE
D ONE CAP Place C7919 close to U7902 D
U7902
PER PIN 4.7u
+3P3V_PD_OUT +1P8V_PD_OUT
R7973 0 R7975 0 11-12 13-14
10V PP_HV1 VBUS1 ALL
20%
1-2 3-4

C7911
R7974 0 DNP R7962 0.01
PP_HV2 VBUS2 0402S_P5-W65
DNP
U7907 25 35
A2 A1 R7960 DBG_TS 0.1 PP_CABLE LDO_1V8 C7901
+1P8VA VIN VOUT 0603 3P3V_PD_VIN_R 5 9 C7910
VIN_3V3 LDO_3V3 10u 6.3V 4.7u
0402S_P65-W65
DBG_N B2 B1 C7908 [35] SAM_PD_HRESET 44 0402S_P7-W70
C7921 EN GND 10u 6.3V HRESET 20% 10V

R7985 0 1u NX3P1108UK 0402S_P7-W70

TCP0_CC1 [77]
C7945 0201 PD_ADCIN1 6 TCP0_CC2 [77]
0.1u 20% PD_ADCIN2 10 ADCIN1
U7908 ADCIN2
10V
5 DBG_D TP7909 [35,63] SAM_SL1_PWR_EN R7931 DNP 0 SAM_SL1_PWR_EN_PD 16 24
2 VCC 4 +1P8V_PD_OUT 17 GPIO0 C_CC1 26 R7930 to guarantee MISO is
[35] SAM_3P3V_PD_EN A Y [77] BB0_PD_RESET# GPIO1 C_CC2 high for PD controller to +3P3V_PD_OUT
1 3P3V_PD_EN R7977 1K 18
[29,37,79] PD_SAM_DBG_ACC_MODE B GPIO2 detect SPI flash
3 TP7902 30
GND 0201S_P28-W35 TP7901 31 HPD/GPIO3
21 GPIO4

C7903

C7912
74LVC1G32GX R7970 R7904 R7905
M1004687-001 10K 10K [65] BB0_PD_LS_EN TP7912 22 I2C3_SCL/GPIO5 50
100K I2C3_SDA/GPIO6 C_USB_P/GPIO18

R7930

R7906

R7910
DBG_D 0201S_P28-W35 23 53 C7920
1% [29,37,79] PD_SAM_DBG_ACC_MODE I2C3_IRQ*/GPIO7 C_USB_N/GPIO19

10K

10K

10K
220p

220p
0.1u

R7903
R7983 R7982 0201 [18,29,33,35] SAM_PD_SDA 28 54 ALL ALL 10V
I2C1_SDA GPIO20

10K
27 55 U7901
100K 100K [18,29,33,35] SAM_PD_SCL I2C1_SCL GPIO21 PD_SPI_SS# 1 8
1% 1% 33 CS# VCC
[21,77] PD_I2C2_SDA I2C2_SDA
0201 0201 32 7 PD_SPI_MISO 2 7
DBG_D DBG_D [21,77] PD_I2C2_SCL I2C2_SCL DRAIN2_1 52 SO/SIO1 HOLD#
+1P8VA +3P3V_PD_OUT 29 DRAIN2_2 56 3 6 PD_SPI_CLK
34 I2C1_IRQ* DRAIN2_3 57 WP# SCLK
[22,77] PD_BB_I2C2_INT# I2C2_IRQ* DRAIN2_4 PD_SPI_MOSI

R7902
4 5
PD_SPI_MISO P0_SPI_MISO_R GND SI/SIO0

10K
R7913 0 36 8 9
R7981 PD_SPI_MOSI R7908 0201S_P28-W35
0 P0_SPI_MOSI_R 37 SPI_MISO/GPIO8 DRAIN1_1 15 EPAD
R7980 SPI_MOSI/GPIO9 DRAIN1_2
R7925 19
C 10K 100K DRAIN1_3 W25X05CLUXIGTR C
PD_SPI_CLK R7909 0 P0_SPI_CLK_R 38 58
1% PD_SPI_SS# P0_SPI_SS#_R 39 SPI_CLK/GPIO10 DRAIN1_4 DNP
10K ALL R7907 0
0201 SPI_SS*/GPIO11 20
GND1
G

TP7904 R7956 0 45
TP7908 [77] PD_USB2_MUX_FLIP 40 GND2 46
D S TP7906 41 GPIO12 GND3 47
[34] PD_SAM_INT# TP7907 [24] TCP0_OC# R7918 0 PD_PROCHOT# 42 GPIO13 GND4 51
[26] BC_PROCHOT# 43 GPIO14/PWM GND5
[10,77] BB_FORCE_PWR GPIO15/PWM
Q7901 TP7910 USB_PD_GPIO16 48
SOTFL-3_1P3XP9XP55_P4 TP7911 USB_PD_GPIO17 49 GPIO16/PEXT1 59
GPIO17/PEXT2 MPAD_GND

PTPS65987DDJRSHR

+3P3V_PD_OUT

R7945
R7901
2K 100K
need double check ADCIN1 setting DNP

PD_ADCIN1

PD_ADCIN2

B B

R7912 R7911
12.1K 0

+3P3V_BB0
+3P3VSB

BB0_PD_RESET# R7919 10K ALL ADCIN1: EXTERNAL BUS POWER

R7921 49.9K DNP
ADCIN2: I2C SETTINGS
7-BIT I2C ADDRESS
I2C1 - 0X20
I2C2- 0X38
PD_BB_I2C2_INT# R7933 10K ALL

SAM_PD_HRESET R7953 10K ALL

TCP0_OC# R7920 10K ALL

R7952 DNP
49.9K

BB0_PD_LS_EN R7934 10K ALL

R7924 DNP
49.9K

A A

PD_USB2_MUX_FLIP R7968 49.9K ALL

WxH 602 x 390mm

Title:Type C Power
<OrgName> Engineer: <OrgAddr1>
Size Project Name Rev
Custom EDAN_A_EV1 1.00
Date: Tuesday, May 21, 2019 Sheet 79 of 82
5 4 3 2 1
 5 4 3 2 1

H8009
D D
MP8003 MP8004
1
MP8005 1 1 1
M1100762-001 1 1

M1110434-001 M1110435-001 3.00X6.00 MM SLOT

H8001
1 MP8001 MP8002
MH3.8x2.5d H8010
1 1
1 1
1
1
M1110434-001 M1110435-001

H8003 3.00X5.00 MM SLOT

H8011
1
1
1
1
MTG_HOLE_4.3padx3drill
X8003
H8002 H8007 SHIELD 3.00X4.90 MM SLOT
X8002 1
X8001 SHIELD 2
1 1 SHIELD 1 3
1 1 1 2 4
2 3 5
3 4 6 H8012
MTG_HOLE_4.3padx3drill MTG_HOLE_4.3padx3drill 4 5 7
8
NP
H8004 H8008 M1110426-001 M1110427-001 9 NO-MSPN-00324

1
ZID = 000 ZID = 000 10
ZOD = 000 ZOD = 000
1 1 SHIELD,FENCE,SM,T1 SHIELD,FENCE,SM,T2
C 1 1 M1110429-001 C
ZID = 000
ZOD = 000
MTG_HOLE_4.3padx3drill MTG_HOLE_4.3padx3drill SHIELD,FENCE,SM,T3
H8005
X8004 X8005 X8006
1 SHIELD SHIELD SHIELD
1 1 1 1

MTG_HOLE_4.3padx3drill M1110432-001 M1110815-001 M1110816-001

ZID = 00 ZID = 00 ZID = 00
ZOD = 00 ZOD = 00 ZOD = 00
SHIELD,FENCE,SM,T4 SHIELD,FENCE,T5,SM SHIELD,FENCE,T6,SM

X8007 X8008
SHIELD SHIELD
1 1
2
3
M1110425-001
M1110431-001
ZID = 000 ZID = 00
ZOD = 000 ZOD = 00
SHIELD,FENCE,SM,T7 SHIELD,FENCE,SM,B1

B B

A A

WxH 602 x 390mm

Title:Mechanical
<OrgName> Engineer: <OrgAddr1>
Size Project Name Rev
Custom EDAN_A_EV1 1.00
Date: Tuesday, May 21, 2019 Sheet 80 of 82
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Title: ACC Radio

<OrgName> Engineer: <OrgAddr1>
Size Project Name Rev
A2 EDAN_A_EV1 1.00
Date: Tuesday, May 21, 2019 Sheet 81 of 82
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

WxH 602 x 390mm

Title:Holes, Shields & Fences
<OrgName> Engineer: <OrgAddr1>
Size Project Name Rev
Custom EDAN_A_EV1 1.00
Date: Tuesday, May 21, 2019 Sheet 82 of 82
5 4 3 2 1