Synthesis Lectures on Electrical Engineering

Farzin Asadi

Digital Circuits
Laboratory
Manual
Synthesis Lectures on Electrical
Engineering
This series of short books covers a broad spectrum of titles of interest in electrical
engineering that may not specifically fit within another series. Books will focus on
fundamentals, methods, and advances of interest to electrical and electronic engineers.
Farzin Asadi

Digital Circuits Laboratory

Manual
Farzin Asadi
Department of Electrical and Electronics
Engineering
Maltepe University
Istanbul, Türkiye

ISSN 1559-811X ISSN 1559-8128 (electronic)

Synthesis Lectures on Electrical Engineering
ISBN 978-3-031-41515-9 ISBN 978-3-031-41516-6 (eBook)
https://doi.org/10.1007/978-3-031-41516-6

© The Editor(s) (if applicable) and The Author(s), under exclusive license to Springer Nature
Switzerland AG 2024

This work is subject to copyright. All rights are solely and exclusively licensed by the Publisher, whether the whole
or part of the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations, recitation,
broadcasting, reproduction on microfilms or in any other physical way, and transmission or information storage
and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or
hereafter developed.
The use of general descriptive names, registered names, trademarks, service marks, etc. in this publication does
not imply, even in the absence of a specific statement, that such names are exempt from the relevant protective
laws and regulations and therefore free for general use.
The publisher, the authors, and the editors are safe to assume that the advice and information in this book are
believed to be true and accurate at the date of publication. Neither the publisher nor the authors or the editors give
a warranty, expressed or implied, with respect to the material contained herein or for any errors or omissions that
may have been made. The publisher remains neutral with regard to jurisdictional claims in published maps and
institutional affiliations.

This Springer imprint is published by the registered company Springer Nature Switzerland AG
The registered company address is: Gewerbestrasse 11, 6330 Cham, Switzerland

Paper in this product is recyclable.

In loving memory of my father Moloud Asadi and
my mother Khorshid Tahmasebi, always on my
mind, forever in my heart.
Preface

Digital technology pervades almost everything in our daily lives. For example, cell phones
and other types of wireless communications, laptops, television, radio, process controls,
automotive electronics, consumer electronics, and aircraft navigation, to name only a few
applications that depend heavily on digital electronics.
A strong grounding in the fundamentals of digital technology will prepare you for the
highly skilled jobs of the future. Understanding the core fundamentals is very important
since it enables you to go anywhere.
This book can be used as a laboratory manual for any standard textbook on digital
electronics. You can make the circuits on breadboard or you can use a simulation software
like Proteus® to simulate the circuits.
This book is composed of 11 chapters. Here is a brief summary of each chapter:
Chapter 1 is an Introduction to Digital Systems.
Chapter 2 contains experiments related to Logic Gates and Combinational Logic
Circuits.
Chapter 3 contains experiments related to Digital Arithmetic.
Chapter 4 contains experiments related to Multiplexers and De-multiplexers.
Chapter 5 contains experiments related to Encoders and Decoders.
Chapter 6 contains experiments related to Display Information on Seven Segments.
Chapter 7 contains experiments related to Latches, Flip Flops and Shift Registers.
Chapter 8 contains experiments related to Frequency Division with Flip Flops.
Chapter 9 contains experiments related to Counter Circuits.
Chapter 10 contains experiments related to Oscillator Circuits.
Chapter 11 contains experiments related to Analog-to-Digital and Digital-to-Analog
Conversion.
I hope that this book will be useful to the readers, and I welcome comments on the
book.

Istanbul, Türkiye Farzin Asadi

vii
Contents

1 An Introduction to Digital Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Logic Technologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.3 Transistor Transistor Logic (TTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.4 Complementary Metal Oxide Semiconductor (CMOS) . . . . . . . . . . . . . . 5
1.5 Emitter Coupled Logic (ECL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.6 Pin Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.7 CMOS and TTL Logic Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.8 Schematic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.9 Generation of High and Low Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.10 Bouncing Problem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.11 De-bouncing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.12 Output Status Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.13 Measurement with Cell Phones . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.14 Power Supply for Digital Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.15 Open Collector Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
References for Further Study . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2 Logic Gates and Combinational Logic Circuits . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.2 Implementation of Logic Gates with Diode and Transistor . . . . . . . . . . . 28
2.3 Behavior of Inverter (Not Gate) with Schmitt Trigger Inputs . . . . . . . . . 31
2.4 Measurement of Lower and Upper Trigger Points
with Potentiometer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.5 Behavior of Inverter Without Schmitt Trigger Inputs . . . . . . . . . . . . . . . . 35
2.6 Measurement of Output Impedance of Gates in High State . . . . . . . . . . 38
2.7 Measurement of Output Impedance of Gates in Low State . . . . . . . . . . . 39
2.8 Connecting a Relay to Logic Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2.9 Simple Logic Analyzer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
2.10 Buffer ICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

ix
x Contents

2.11 Bus Transceiver ICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

2.12 Behavior of Basic Logic Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
2.13 De Morgan’s Rule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
2.14 Implementation of Basic Logic Gates with NAND Gate . . . . . . . . . . . . . 60
2.15 Implementation of Basic Logic Gates with NOR Gate . . . . . . . . . . . . . . 63
2.16 Conversion of Sine Wave to Square Wave . . . . . . . . . . . . . . . . . . . . . . . . . 64
References for Further Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
3 Digital Arithmetic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
3.2 Adder IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
3.3 BCD Adder Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
3.4 2-Bit Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
3.5 Magnitude Comparator IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
3.6 ALU IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
References for Further Study . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
4 Multiplexer and De-multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
4.2 Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
4.3 De-multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
4.4 Analog Multiplexer and De-multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
4.5 Measurement of Switch Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
4.6 Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
4.7 Digitally Controlled Voltage Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
References for Further Study . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
5 Encoder and Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
5.2 Decimal to Binary Coded Decimal (BCD) Priority Encoder . . . . . . . . . 105
5.3 Reading a Keypad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
5.4 8-Line to 3-Line Binary (Octal) Priority Encoder . . . . . . . . . . . . . . . . . . . 109
5.5 3 × 8 Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
5.6 BCD to Decimal Decoder (TTL IC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
5.7 BCD to Decimal Decoder (CMOS IC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
5.8 BCD-to-Binary and Binary-to-BCD Converters . . . . . . . . . . . . . . . . . . . . 121
References for Further Study . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
6 Display Information on Seven Segments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
6.2 TTL BCD to Common Cathode 7-Segment Decoder . . . . . . . . . . . . . . . . 126
6.3 Counter from 0 to 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
6.4 TTL BCD to Common Anode 7-Segment Decoder . . . . . . . . . . . . . . . . . 130
Contents xi

6.5 CMOS BCD to 7-Segment Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

6.6 Binary to BCD and BCD to Binary Converter IC . . . . . . . . . . . . . . . . . . 133
References for Further Study . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
7 Latch, Flip Flop and Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
7.2 Commonly Used JK Flip Flops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
7.3 Commonly Used D Flip Flops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
7.4 Commonly Used D Type Data Latches . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
7.5 Commonly Used SR Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
7.6 SR Latch with Transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
7.7 Active High SR Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
7.8 Active Low SR Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
7.9 De-bouncing with SR Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
7.10 Behavior of JK Flip Flops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
7.11 Conversion of JK Flip Flop to T Flip Flop . . . . . . . . . . . . . . . . . . . . . . . . 156
7.12 Conversion of JK Flip Flop to D Flip Flop . . . . . . . . . . . . . . . . . . . . . . . . 158
7.13 Conversion of D Flip Flop to T Flip Flop . . . . . . . . . . . . . . . . . . . . . . . . . 160
7.14 De-bouncing with D Flip Flops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
7.15 4-Bit Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
7.16 8-Bit Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
7.17 Edge Detector Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
7.18 Edge Detection with D Flip Flops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
7.19 Shift Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
7.20 74595 Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
References for Further Study . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
8 Frequency Division with Flip Flops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
8.2 Frequency Division with D Flip Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
8.3 Frequency Division with 4017 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
8.4 Frequency Division with 7490 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
8.5 Frequency Division with 555 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
References for Further Study . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
9 Counter Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
9.2 Low Frequency Clock Pulse Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
9.3 Single Clock Pulse Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
9.4 4-Bit Binary Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
9.5 8-Bit Binary Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
9.6 14-Bit Binary Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
9.7 4-Bit Up/Down Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
xii Contents

9.8 CMOS Counter/Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

References for Further Study . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
10 Oscillator Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
10.2 Square Wave Generation with Transistor . . . . . . . . . . . . . . . . . . . . . . . . . . 225
10.3 Square Wave Generation with 555 IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
10.4 Square Wave Generation with NOT Gates . . . . . . . . . . . . . . . . . . . . . . . . . 228
10.5 Pulse Generation with 555 IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
10.6 Non Retriggerable Monostable with 555 IC . . . . . . . . . . . . . . . . . . . . . . . 232
10.7 Non Retriggerable Monostable with 74121 IC . . . . . . . . . . . . . . . . . . . . . 236
10.8 Servomotor Tester with 555 IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
References for Further Study . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
11 Analog-to-Digital and Digital-to-Analog Converters . . . . . . . . . . . . . . . . . . . . 241
11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
11.2 Analog to Digital Conversion with ADC0804 . . . . . . . . . . . . . . . . . . . . . . 243
11.3 Increasing the Analog to Conversion Accuracy . . . . . . . . . . . . . . . . . . . . 245
11.4 Voltage Level Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
11.5 Digital to Analog Conversion with DAC0808 . . . . . . . . . . . . . . . . . . . . . . 248
References for Futher Study . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
An Introduction to Digital Systems
1

1.1 Introduction

A digital signal is a signal that represents data as a sequence of binary values. In each
instant of time the signal can take only one of the two values. The allowed two values
are called high and low or 1 and 0. A digital system is a system which works with digital
signals.
This chapter introduces the basic concepts of digital systems.

1.2 Logic Technologies

Small and medium scale (SSI and MSI) Logic IC families are currently made in a wide
range of sub-families and a variety of package types, using three basically different
technologies:

(A) TTL (Transistor Transistor Logic)

(B) CMOS (Complementary Metal Oxide Semiconductor)
(C) ECL (Emitter Coupled Logic).

1.3 Transistor Transistor Logic (TTL)

TTL gates use a 5 V (±0.25 V) supply, and are capable of high-speed operation. Over
600 different logic ICs are available, covering a very wide range of digital functions. Due
to the use of bipolar transistors, TTL has much higher power consumption than similar

© The Author(s), under exclusive license to Springer Nature Switzerland AG 2024 1

F. Asadi, Digital Circuits Laboratory Manual, Synthesis Lectures on Electrical
Engineering, https://doi.org/10.1007/978-3-031-41516-6_1
2 1 An Introduction to Digital Systems

CMOS types, when working at relatively low frequencies. As the frequency of signals
handled increases however, this difference decreases as the power consumption of CMOS
increases and TTL power consumption remains nearly constant.
TTL has various subfamilies: Bipolar TTL families, CMOS and BiCMOS fami-
lies, Low-Voltage CMOS and BiCMOS families, Very-Low-Voltage CMOS families and
Limited families for special applications.
Table 1.1 introduces the Bipolar TTL family. The headings in Table 1.1 are: VCC—
power supply voltage; tpd—maximum gate delay; IOL—maximum output current at low
level; IOH—maximum output current at high level.

Table 1.1 Bipolar TTL families

Code Family VCC tpd Year Description
74 Standard TTL 5 V ± 5% 22 ns 1966 The original 7400 logic
family. Contains no
characters between the “74”
and the part number
74H High-speed 5 V ± 5% 10 ns 1967 Higher speed than the
original 74 series, at the
expense of power
dissipation. TTL logic levels
74L Low-power 5 V ± 5% 60 ns 1967 Same technology as the
original 74 family, but with
larger resistors to lower
power consumption at the
expense of gate speed. TTL
logic levels. Now obsolete
74S Schottky 5 V ± 5% 5 ns 1969 Implemented using
Schottky diode. High
current draw. TTL logic
levels
74LS Low-power 5 V ± 5% 15 ns 1971 Same technology as the 74S
Schottky family, but with lower
power consumption (2 mW)
at the expense of gate speed.
TTL logic levels
74F Fast 5 V ± 5% 3.9 ns 1979 Originally Fairchild’s
version of the 74AS family.
TTL logic levels
74ALS Advanced 5 V ± 10% 11 ns 1980 Same technology as the
Low-power 74AS family, but with lower
Schottky power consumption at the
expense of gate speed. TTL
logic levels
1.3 Transistor Transistor Logic (TTL) 3

Newer TTL series, more or less compatible in function and logic level with the original
parts, use CMOS technology or a combination of the two (BiCMOS). An integrated cir-
cuit made in CMOS is not a TTL chip, since it uses field-effect transistors (FET) and not
bipolar junction transistors (BJT), but similar part numbers are retained to identify sim-
ilar logic functions and electrical (power and I/O voltage) compatibility in the different
subfamilies. Table 1.1 introduces the CMOS and BiCMOS families.

Table 1.2 CMOS and BiCMOS families

Code Family VCC tpd Year Description
74C CMOS 3.0–15 V 60 ns 1975 74C is standard CMOS, similar to buffered 4000
(4000B) series. Input levels not compatible with
TTL families. The 4000A series was introduced
in 1968, the 4000B around 1975
74HC High-speed 2.0–6.0 V 15 ns 1983 Similar performance to 74LS. CMOS logic levels
CMOS
74HCT High-speed 5 V ± 10% 15 ns 1983 Similar performance to 74LS. TTL logic levels
CMOS
74HCTLS High-speed 5 V ± 10% 15 ns 1988 Samsung’s version of the 74HCT series. TTL
CMOS logic levels
74HCS Schmitt-trigger 2.0–6.0 V 13 ns 2019 Schmitt triggers on all inputs. CMOS logic levels
integrated
high-speed
CMOS
74AHC Advanced 2.0–5.5 V 5.5 ns Up to three times as fast as the 74HC family. 5 V
high-speed tolerant inputs. CMOS logic levels. Equivalent to
CMOS 74VHC
74AHCT Advanced 5 V ± 10% 6.9 ns 1986 Up to three times as fast as the 74HCT family.
high-speed TTL logic levels. Equivalent to 74VHCT
CMOS
74VHC Very 2.0–5.5 V 5.5 ns 1992 5 V tolerant inputs. Equivalent to 74AHC.
high-speed CMOS logic levels
CMOS
74VHCT Very 5 V ± 10% 6.9 ns 1995 Equivalent to 74AHCT. TTL logic levels
high-speed
CMOS
74AC Advanced 2.0–6.0 V 8 ns 1985 CMOS logic levels. Outputs may cause ground
CMOS bounce
74ACT Advanced 5 V ± 10% 8 ns 1985 TTL logic levels. Outputs may cause ground
CMOS bounce
74ACQ Advanced 2.0–6.0 V 6.5 ns 1989 Fairchild’s “Quiet Series” offering lower ringing
CMOS with and ground bounce on state transitions. Bus
“quiet” outputs interface circuits only in this family. CMOS logic
levels
(continued)
4 1 An Introduction to Digital Systems

Table 1.2 (continued)

Code Family VCC tpd Year Description
74ACTQ Advanced 5 V ± 10% 7.5 ns 1989 Fairchild’s “Quiet Series” offering lower ringing
CMOS with and ground bounce on state transitions. TTL
“quiet” outputs logic levels
74ABT Advanced 5 V ± 10% 3.6 ns 1991 TTL logic levels
BiCMOS
74LVCE Low-voltage 1.4–5.5 V 3.6 ns 2010 CMOS logic levels. 5 V tolerant inputs. Extented
CMOS supply voltage range and higher speed compared
to 74LVC

TTL ICs start with 74 can work in 0 °C up to 70 °C. ICs start with 54 can work in −
55 °C up to +125 °C. For most applications the 74 series is perfectly acceptable and this
series will be found in consumer devices. VCC for 54 series can have a 10% tolerance,
i.e., 5 V ± 10%. Most (but not all!) of the TTL ICs have the GND and VCC pins in the
left bottom and right top pins (Fig. 1.1).

Fig. 1.1 Common position of

VCC and ground pins

The power pins (i.e., VCC and ground pins) are not shown in the schematics of this
book. Keep this point in mind and connect the power pins of the ICs to the power supply
when you want to make the circuits in the laboratory.
The experiments of this book can be done with all of the families shown in Tables 1.1
and 1.2. For instance, you can use 74LS04, 74HC04 or 74HCT04 to do the experiments.
1.4 Complementary Metal Oxide Semiconductor (CMOS) 5

1.4 Complementary Metal Oxide Semiconductor (CMOS)

CMOS ICs can operate from a wide range of supply voltages (typically 3–18 V, and
lower with some sub families), with very low power consumption. The name CMOS
(Complementary Metal Oxide Semiconductor) is used because opposite types, both P
type and N type MOSFETs are used in the construction of these gates.
The 4000 series is a CMOS logic family of ICs first introduced in 1968 by Radio
Corporation of America (RCA). Some of the commonly used CMOS ICs are shown in
Table 1.3.

Table 1.3 Commonly used CMOS ICs

Application CMOS IC
Flip-flop 4013—Dual D-type flip-flop. Each flip-flop has independent data, Q, /Q, clock,
reset, set
40,174—Hex D-type flip-flop. Each flip-flop has independent data and Q. All
share clock and reset
40,175—Quad D-type flip-flop. Each flip-flop has independent data, Q, /Q. All
share clock and reset
Counter 4017—Decade counter with 10-output decoder
4026—Decade counter with 7-segment digit decoded output
40,110—Up/down decade counter with 7-segment display decoder with 25 mA
output drivers
40,192—Up/down decade counter with 4-bit BCD preset
40,193—Up/down binary counter with 4-bit binary preset
Decoder 4028—4-bit BCD to 10-output decoder (can be used as 3-bit binary to 8-output
decoder)
4511—4-bit BCD to 7-segment display decoder with 25 mA output drivers
Timer 4047—Monostable/astable multivibrator with external RC oscillator
4060—14-bit ripple counter with external RC or crystal oscillator (long duration)
(schmitt-trigger inputs) (can be used with 32.768 kHz crystal)
4541—16-bit ripple counter with external RC oscillator (long duration)
Analog 4051—Single 8-channel analog mux
switch 4066—Quad SPST analog switch

CMOS ICs have extremely thin insulating layer. This makes thm hypersensitive to
electrostatic charge. Specifically, discrete CMOS components or ICs in or out of a circuit
board can be destroyed by a sufficiently high static charge reaching one of their terminals.
CMOS logic has a very high input impedance, any open input might result in a false
output value due to the influence of a surrounding electric field. Because of this, all unused
inputs of a CMOS IC should be tied to either VDD or GND (Fig. 1.2).
6 1 An Introduction to Digital Systems

Fig. 1.2 Unused input pins must be tied to ground or VDD

1.5 Emitter Coupled Logic (ECL)

ECL is a high-speed integrated circuit bipolar transistor logic family. In ECL, the tran-
sistors are never in saturation, the input and output voltages have a small swing (0.8 V),
the input impedance is high and the output impedance is low. As a result, the transistors
change states quickly, gate delays are low, and the fanout capability is high. In addition,
the essentially constant current draw of the differential amplifiers minimizes delays and
glitches due to supply-line inductance and capacitance, and the complementary outputs
decrease the propagation time of the whole circuit by reducing inverter count.
ECL’s major disadvantage is that each gate continuously draws current, which means
that it requires (and dissipates) significantly more power than those of other logic families,
especially when quiescent.

1.6 Pin Numbering

Most of IC vendors show the first pin of the IC with a small circle. Figures 1.3 and 1.4
show how IC pins are numbered.
1.7 CMOS and TTL Logic Levels 7

Fig. 1.3 Numbering of pins in

DIP packages

Fig. 1.4 Numbering of pins in

QFP packages

1.7 CMOS and TTL Logic Levels

Logic levels are represented by different voltages. For CMOS ICs low logic level is
defined as 0 V to 30% of VCC and high level is defined as 70% VDD to VDD. VDD
shows the supply voltage. Standard 5 V TTL logic levels are shown in Fig. 1.5.
8 1 An Introduction to Digital Systems

Fig. 1.5 Standard 5 V TTL

levels

Here is the definition of VOH, VIH, VOL and VIL parameters shown in Fig. 1.5.
VOH: Minimum output voltage level a TTL device will provide for a high signal,
VIH: Minimum input voltage level to be considered a high,
VOL: Maximum output voltage level a device will provide for a low signal,
VIL: Maximum input voltage level to still be considered a low.

1.8 Schematic Conventions

In this book the symbols shown in Fig. 1.6 are used to show pass of two wires over each
other without any connection. Figure 1.7 shows that two wires are connected to each
other.
1.9 Generation of High and Low Signals 9

Fig. 1.6 There is no contact between w1 and w2

Fig. 1.7 There is a contact

between w1 and w2

1.9 Generation of High and Low Signals

The simple circuits shown in Fig. 1.8 can be used to generate high and low signals. In
Fig. 1.8a, the output is normally at low logic level. When the push button is pressed, a
high logic level is generated. In Fig. 1.8b, the output is normally at high logic level. When
the push button is pressed, a low logic level is generated.

Fig. 1.8 a When the push

button is pressed, a high signal
is generated b When the push
button is pressed a low signal
is generated
10 1 An Introduction to Digital Systems

In Fig. 1.9 an LED is added to the circuit to show the status of the output. The LED
turns on when the output is high.

Fig. 1.9 The LED turns on

when the push button is
pressed

You can use a Single Pole Double Throw (SPDT) switch to generate a high and low
signals (Fig. 1.10). In Fig. 1.10 the output is high when the switch is at position A and is
low when the switch is at position B.

Fig. 1.10 High and low signal

generation with SPDT
1.11 De-bouncing 11

1.10 Bouncing Problem

Bouncing problem is common problem of mechanical buttons and switches. Let’s study
a simple example to understand the nature of the bouncing problem. Consider the switch
shown in Fig. 1.11. In this figure the output is normally at 0 V. When you press the push
button, the output goes toward 5 V. However, some fluctuations happen before settling on
the final 5 V value. The fluctuations are generated by the metal contacts of the switch.
Digital circuits sense the fluctuations as several press to the push button. In other words,
the user presses the button once, but bouncing cause the digital system connected to the
button consider it several times. All of the circuits studied in Sect. 1.9 suffer from the
bouncing problem. Next section suggests some solutions to the bouncing problem.

Fig. 1.11 Bouncing problem

1.11 De-bouncing

De-bouncing is removing unwanted input noise from mechanical buttons and switches.
Figures 1.12 and 1.13 suggests two circuits to de-bounce the push buttons. In Fig. 1.12,
the output is normally at low level, when the push button is pressed it becomes high. In
Fig. 1.13, the output is normally at high level, when the push button is pressed it becomes
low.
12 1 An Introduction to Digital Systems

Fig. 1.12 RC de-bouncing

circuit (output is high when
push button is pressed)

Fig. 1.13 RC de-bouncing

circuit (output is low when the
push button is pressed)

The diodes in Figs. 1.12 and 1.13 are optional. You can remove it and obtain a simpler
circuit. For instance, if we remove the diode from Fig. 1.12, the circuit shown in Fig. 1.14
is obtained.

Fig. 1.14 RC de-bouncing

without diode
1.11 De-bouncing 13

The circuits shown in Figs. 1.15 and 1.16 can be used to de-bounce a SPDT switch.
In Fig. 1.15 position A gives high output and position B gives low output. In Fig. 1.16
position S gives high output and position R gives low output. The diode in Fig. 1.16
shows the status of the output.

Fig. 1.15 A simple solution to

de-bounce a SPDT switch
14 1 An Introduction to Digital Systems

Fig. 1.16 Use of SR latches to de-bounce SPDT switches

1.11 De-bouncing 15

The MC14043/14044 chips consist of four SR flip flops, so might be an attractive

solution for de-bouncing multiple switches. Internal structure of MC14043 and MC14044
are shown in Figs. 1.17 and 1.18, respectively.

Fig. 1.17 Internal structure of

MC14043B
16 1 An Introduction to Digital Systems

Fig. 1.18 Internal structure of

MC14044B

Another way to de-bounce switches in hardware is to take advantage of application-

specific integrated circuits. Semiconductor manufacturers such as Maxim Integrated offer
switch de-bouncers like the MAX6816 in very small packages, with built-in ESD pro-
tection. Although they are extremely easy to use, they are more expensive and offer less
flexibility and customization than designing your own RC filter.

1.12 Output Status Monitoring

Status of an output can be shown with the simple circuit shown in Fig. 1.19. When the
LED turns on the output is high.
1.12 Output Status Monitoring 17

Fig. 1.19 Output monitoring

with LED

You can use the circuit shown in Fig. 1.20 as well. When the output is high, the green
LED turns on. When the output is low, the red LED turns on.

Fig. 1.20 Output monitoring

with two different color LEDs

Logic probes (Fig. 1.21) can be used to see an output is high or low. Just connect
the black wire of the logic probe to the circuit under test ground and connect the tip pf
the probe to the output that you want. The logic probe’s LED’s show the status of the
output. Logic probes can be used to generate pulses as well. Pulse generation is quite
useful during the circuit troubleshooting.
18 1 An Introduction to Digital Systems

Fig. 1.21 A Typical logic

probe

1.13 Measurement with Cell Phones

Digital Multi Meters (DMM) and oscilloscopes are important tools when you want to
design or troubleshoot a circuit. You can convert your cell phone, tablet or even your
smart watch into a digital multimeter, digital oscilloscope or a logger with the aid of
Pokit® meter (Figs. 1.22 and 1.23) or Pokit pro (Fig. 1.24). More information about
these measurement devices can be found on https://www.pokitinnovations.com/.

Fig. 1.22 Pokit meter

1.14 Power Supply for Digital Circuits 19

Fig. 1.23 Pokit meter

Fig. 1.24 Pokit pro

1.14 Power Supply for Digital Circuits

Digital circuits implemented with TTL ICs require a regulated 5 V supply. You can use a
7805 linear voltage regulator for this purpose. Pinout of 7805 is shown in Fig. 1.25.

Fig. 1.25 Pinout of 7805

voltage regulator IC

The circuit shown in Fig. 1.26 shows how to make a 5 V regulated power supply.
20 1 An Introduction to Digital Systems

Fig. 1.26 A simple 5 V power supply

You can convert the generated +5 V to −5 V with the aid of TL7660 CMOS voltage
converter. Purely digital circuits don’t require negative voltages to work. However, if you
are working with a mixed signal circuits (i.e., circuits which have both analog and digital
parts) then having negative voltages may be necessary.

1.15 Open Collector Gates

Consider the circuit shown in Fig. 1.27. The collector pin is not connected to anywhere.
Therefore, no current can pass from the transistor.

Fig. 1.27 Collector terminal is

left open

Now assume that we added a resistor between VCC and collector as shown in Fig. 1.28.
In this case the circuit is completed and current can pass from the transistor. In this circuit
the output voltage takes VCC − RC IC and 0 based on the status of the transistor. The
resistor RC in Fig. 1.28 is called pull-up resistor.
1.15 Open Collector Gates 21

Fig. 1.28 Collector terminal is

connected to VCC using a
pull-up resistor

Some ICs have an output stage like the one shown in Fig. 1.27. Such an output is
called open collector output. Open collector outputs require a pull-up resistor to work
correctly.
Output stage of ICs implemented in CMOS technology is made from field effect tran-
sistors. Sometimes the output stage transistor’s drain is left open. Such an output stage is
called open drain output. Open drain outputs require pull-up resistors to work properly.
Let’s study an example. 78HC05 provides 6 independent inverters with open drain
outputs. Consider the circuit shown in Fig. 1.29.

Fig. 1.29 A simple circuit to

test 7405 open drain NOT gate
22 1 An Introduction to Digital Systems

In Figs. 1.30 and 1.31 low and high signals are applied to the input, respectively.
However, the voltmeter shows 0 V in both cases, which is not expected correct response.

Fig. 1.30 Output is low when

input is low

Fig. 1.31 Output is high when

input is high

In Figs. 1.30 and 1.31 wrong result is obtained since pull-up resistor in not used.
Let’s connect a 10 ku resistor between the output of the gate and positive voltage rail
(Fig. 1.32).
1.15 Open Collector Gates 23

Fig. 1.32 Pull-up resistor is

added to the circuit

In Figs. 1.33 and 1.34 low and high signals are applied to the input, respectively. Now
the generated output is correct.

Fig. 1.33 Output is high when

input is low
24 1 An Introduction to Digital Systems

Fig. 1.34 Output is low when

input is high

References for Further Study

1. Asadi F (2022) Essential circuit analysis using proteus® . Springer. https://doi.org/10.1007/978-

981-19-4353-9
2. Asadi F (2022) Essential circuit analysis using NI multisim™ and MATLAB® . Springer. https://
doi.org/10.1007/978-3-030-89850-2
3. Asadi F (2022) Essential circuit analysis using LTspice® . Springer. https://doi.org/10.1007/978-
3-031-09853-6
4. Asadi F (2023) Analog electronic circuits laboratory manual. Springer. https://doi.org/10.1007/
978-3-031-25122-1
5. Asadi F, Eguchi K (2021) Electronic measurements. Springer. https://doi.org/10.1007/978-3-
031-02021-6
6. Asadi F, Eguchi K (2022) Electric and electronic circuit simulation using TINA-TI®, River
Publishers. https://doi.org/10.13052/rp-9788770226851
7. Asadi F, Eguchi K (2021) Power electronics circuit analysis with PSIM®. De Gruyter. https://
doi.org/10.1515/9783110740653
8. https://my.eng.utah.edu/~cs5780/debouncing.pdf
9. https://www.eejournal.com/article/ultimate-guide-to-switch-debounce-part-5/
10. https://en.wikipedia.org/wiki/List_of_7400-series_integrated_circuits
11. https://en.wikipedia.org/wiki/List_of_4000-series_integrated_circuits
Logic Gates and Combinational Logic Circuits
2

2.1 Introduction

Logic gates are building blocks of digital systems. Logic gates perform basic logic func-
tions like: AND, OR, XOR, NOT, NAND, NOR, and XNOR. Some of the important
digital ICs are shown in Figs. 2.1, 2.2, 2.3, 2.4, 2.5, 2.6, 2.7 and 2.8.

Fig. 2.1 Pinout of 7400

Fig. 2.2 Pinout of 7404

© The Author(s), under exclusive license to Springer Nature Switzerland AG 2024 25

F. Asadi, Digital Circuits Laboratory Manual, Synthesis Lectures on Electrical
Engineering, https://doi.org/10.1007/978-3-031-41516-6_2
26 2 Logic Gates and Combinational Logic Circuits

Fig. 2.3 Pinout of 7407

Fig. 2.4 Pinout of 7434

Fig. 2.5 Pinout of 7408

2.1 Introduction 27

Fig. 2.6 Pinout of 7410

Fig. 2.7 Pinout of 7432

Fig. 2.8 Pinout of 7486

28 2 Logic Gates and Combinational Logic Circuits

A combinational circuit is one whose output at any time is based only on the present
combination of inputs at that point of time. This chapter focus on logic gates and
combinational logic circuits.

2.2 Implementation of Logic Gates with Diode and Transistor

This experiment shows how logic gates can be implemented with diodes and transistors.
Make the circuit shown in Fig. 2.9.

Fig. 2.9 Implementation of a

logic function with two diodes
and a resistor

Apply low (=0 V) and high (=5 V) voltage signals to the circuit shown in Fig. 2.9 and
fill the Table 2.1. You can connect a DC voltmeter to node Out to determine whether it
is high or low. Behavior of this circuit is similar to which logic gate?

Table 2.1 Input–output

Input A Input B Output
relationship for circuit shown
in Fig. 2.9 Low Low
High High
Low Low
High High

Now make the circuit shown in Fig. 2.10.

2.2 Implementation of Logic Gates with Diode and Transistor 29

Fig. 2.10 Implementation of a

logic function with two diodes
and a resistor

Apply low and high voltage signals to the circuit shown in Fig. 2.10 and fill the
Table 2.2. Behavior of this circuit is similar to which logic gate?

Table 2.2 Input–output

Input A Input B Output
relationship for circuit shown
in Fig. 2.10 Low Low
High High
Low Low
High High

Make the circuit shown in Fig. 2.11.

30 2 Logic Gates and Combinational Logic Circuits

Fig. 2.11 Implementation of a logic function with three transistors and a resistor

Apply low and high voltage signals to the circuit shown in Fig. 2.11 and fill the
Table 2.3. Behavior of this circuit is similar to which logic gate?

Table 2.3 Input–output

Input A Input B Input C Output
relationship for circuit shown
in Fig. 2.11 Low Low Low
Low Low High
Low High Low
Low High High
High Low Low
High Low High
High High Low
High High High

Make the circuit shown in Fig. 2.12.

2.3 Behavior of Inverter (Not Gate) with Schmitt Trigger Inputs 31

Fig. 2.12 Implementation of a

logic function with diodes,
resistors and a transistor

Apply low and high voltage signals to the circuit shown in Fig. 2.12 and fill the
Table 2.4. Behavior of this circuit is similar to which logic gate?

Table 2.4 Input–output

Input A Input B Output
relationship for circuit shown
in Fig. 2.12 Low Low
High High
Low Low
High High

2.3 Behavior of Inverter (Not Gate) with Schmitt Trigger Inputs

The 7414 IC is a hex (six) inverter with Schmitt trigger inputs. Pinout diagram of this IC
is shown in Fig. 2.13. Transfer function (i.e., relationship between input and output) of
these inverters is shown in Fig. 2.14. In this experiment you will measure the lower and
upper trigger points of this IC.
32 2 Logic Gates and Combinational Logic Circuits

Fig. 2.13 Pinout of 7414

Fig. 2.14 Input–output

transfer function for 7414

Prepare the circuit shown in Fig. 2.15. Waveform generated by signal generator V1 is
shown in Fig. 2.16.

Fig. 2.15 Circuit to study the

input–output relation of 7414
2.3 Behavior of Inverter (Not Gate) with Schmitt Trigger Inputs 33

Fig. 2.16 Input voltage

waveform

Observe the input and output simultaneously. Values of A and B can be measured as
shown in Fig. 2.17.

Fig. 2.17 Typical output waveform for the circuit shown in Fig. 2.15
34 2 Logic Gates and Combinational Logic Circuits

2.4 Measurement of Lower and Upper Trigger Points

with Potentiometer

In the previous section an oscilloscope is used to measure the lower and upper trigger
points of the 7414 IC. You can measure the lower and upper trigger points without an
oscilloscope as well. In this section you will measure the lower and upper trigger points
without oscilloscope.
Make the circuit shown in Fig. 2.18.

Fig. 2.18 Measurement of A

and B with potentiometer

Turn the potentiometer knob until you read a small voltage (around 0 V) on the volt-
meter. In this case the green LED (D2) turns on. Turn the potentiometer knob slowly to
increase the voltage applied to input of the inverter. Stop turning the potentiometer knob
when green LED turns off and red LED (D1) turn on. The voltage that voltmeter shows
is value of point B in Fig. 2.19.
2.5 Behavior of Inverter Without Schmitt Trigger Inputs 35

Fig. 2.19 Input–output

transfer function for 7414

Now turn the potentiometer knob until you read a voltage around 5 V on the voltmeter.
In this case the red LED (D1) turns on. Turn the potentiometer knob slowly to decrease
the voltage applied to input of the inverter. Stop turning the potentiometer knob when red
LED turns off and green LED (D2) turn on. The voltage that voltmeter shows is value of
point A in Fig. 2.19.

2.5 Behavior of Inverter Without Schmitt Trigger Inputs

The 7404 IC is a hex inverter without Schmitt trigger inputs. Pinout diagram of this IC is
shown in Fig. 2.20. Note that 7404 has no Schmitt trigger in its inputs. Transfer function
of these inverters are shown in Fig. 2.21. In Fig. 2.21 no hysteresis exists and transition
takes place at one level. In Fig. 2.19 hysteresis exists and transition takes place at two
different levels A and B.

Fig. 2.20 Pinout of 7404

36 2 Logic Gates and Combinational Logic Circuits

Fig. 2.21 Input–output

transfer function for 7404

In this experiment you will measure the transition point of the curve shown in Fig. 2.21.
Make the circuit shown in Fig. 2.22. Waveform generated by signal generator V1 is shown
in Fig. 2.23.

Fig. 2.22 Circuit to study the

input–output relation of 7404
2.5 Behavior of Inverter Without Schmitt Trigger Inputs 37

Fig. 2.23 Input voltage

waveform

Observe the input and output simultaneously. Transition point (points A and B in
Fig. 2.21) can be measured as shown in Fig. 2.24.

Fig. 2.24 Typical output waveform for the circuit shown in Fig. 2.22
38 2 Logic Gates and Combinational Logic Circuits

You can use the technique explained in Sect. 2.4 to measure the transition point of
these inverters as well.

2.6 Measurement of Output Impedance of Gates in High State

This section shows how to measure the output impedance (resistance) of gates when
output is in high state (i.e., +5 V).
Simple model of the gate is shown in Fig. 2.25. VO is around 5 V when output of
the gate is in high state. This section shows how to measure the RO. The measurement
procedure is explained for a NOT gate but it can be used for any other type of gates.

Fig. 2.25 Simple model for

output of a gate

Let’s get started. Make the circuit shown in Fig. 2.26. Input of the NOT gate is con-
nected to ground, therefore, the output of the gate is in high state. The voltage shown by
the voltmeter in Fig. 2.26 is called Voc. Voc is the open circuit voltage (Voc equals to VO
in Fig. 2.25).

Fig. 2.26 Measurement of

output voltage
2.7 Measurement of Output Impedance of Gates in Low State 39

Now connect a 100 y load to the output of the gate and measure the voltage drop
across the 100 y load resistor (Fig. 2.27). Let’s call the measured voltage VR1.

Fig. 2.27 Measurement of

voltage drop across the 100 y
resistor

Simplified model of Fig. 2.27 is shown in Fig. 2.28. According to Fig. 2.28 V R1 =
R1
R1 +R O × VOC ⇒ R O = ( VVOC R1
− 1)R1 .

Fig. 2.28 Simple model for a

gate connected to a 100 y
resistor

2.7 Measurement of Output Impedance of Gates in Low State

This section shows how to measure the output impedance of gates when output is in low
state (i.e., 0 V). Note that the output impedance in high and low output states are not
equal necessary. The measurement procedure in this section is explained for a NOT gate
but it can be used for any other type of gates.
Let’s get started. Make the circuit shown in Fig. 2.29. Input of the NOT gate is con-
nected to +5 V, therefore, the output of the gate is in low state. Simplified model of this
circuit is shown in Fig. 2.30. RO’ shows the output impedance of the gate in output low
state.
40 2 Logic Gates and Combinational Logic Circuits

Fig. 2.29 Supplying the 7404

with a high signal

Fig. 2.30 Simple model for a

gate when output is low

Now connect a 100 y resistor and a voltmeter to the circuit (Fig. 2.31). Simplified
model of this circuit is shown in Fig. 2.32. The voltmeter ( reading )is shown by VO’.
O' V O'
According to Fig. 2.32, V O ' = R OR' +100 × 5 ⇒ R O ' = 100 × 5−V O ' . Use this formula
to calculate the value of RO’.

Fig. 2.31 The Circuit used to

measure the output resistance
RO’
2.8 Connecting a Relay to Logic Gates 41

Fig. 2.32 Simple model for

circuit shown in Fig. 2.31

2.8 Connecting a Relay to Logic Gates

You can connect a relay to output of the gates to turn on and off a load which requires a
high current. For instance, in Fig. 2.33 a relay is connected to the output of a 7404 NOT
gate. RB is the external resistor which set the base current. D1 is free-wheeling diode and
protects the transistor Q1 against the high voltage spikes that relay coil generates when it
turns off. Vrelay is a separate voltage source that supply the relay.

Fig. 2.33 Connecting a relay

to a gate

Simple equivalent circuit model of Fig. 2.33 is shown in Figs. 2.34 and 2.35.
42 2 Logic Gates and Combinational Logic Circuits

Fig. 2.34 Model for high

output

Fig. 2.35 Model for low

output

Let’s study an example. Assume that you have a 12 V relay which require 150 mA of
current to be activated. In this case resistance of the coil (Rrelay in Figs. 2.34 and 2.35) is
12/0.15 = 80 y and Vrelay = 24 V. RB is determined with respect to Fig. 2.34. According
to BC 107 datasheet, minimum current gain is around 110. Let’s be conservative and take
the minimum current gain as 75. The transistor Q1 must be in saturation when the output
of the NOT gate is high. Let’s write the KVL for Fig. 2.34: −5 + (R O + R B) × βImin C
+
2.9 Simple Logic Analyzer 43

0.7 = 0 ⇒ R B = 4.3 × βIminC

− R O. For R O = 150y, R B = 4.3 × 150m 75
A − 150 = 2 ky.
When R B is less than 2 ky, the transistor in Fig. 2.34 saturates and relay is activated.
In Fig. 2.35 the transistor is off for all values of R B. Therefore, it doesn’t apply any
limitation on value of R B.

2.9 Simple Logic Analyzer

You can use the schematic shown in Fig. 2.36 to make a simple logic analyzer. When
the probe P is connected to a high node, the green LED turns on. When the probe P is
connected to a low node, the red LED turns on. Note that the ground of logic analyzer
must be connected to the ground of circuit under test (Fig. 2.37).

Fig. 2.36 Making a simple logic analyzer

44 2 Logic Gates and Combinational Logic Circuits

Fig. 2.37 Connecting the logic analyzer to a circuit

2.10 Buffer ICs

A buffer circuit is a circuit which isolate an input from an output. Input of the buffer
circuit draws a very small negligible amount of current. In other words, the input of the
buffer circuit does not load the circuit which it is connected to.
Symbol and simple model of a buffer is shown in Fig. 2.38. When input is high, switch
is in position H and when input is low it is in the position L. In other words, the logic
state of output equals to the logic state of input.
You will study the behavior of a buffer IC in this experiment.
2.10 Buffer ICs 45

Fig. 2.38 Symbol and simple

model of a buffer gate

7407 is a hex buffer IC. Output of buffers are open collector therefore you need external
pull-up resistors when you use this IC. Pinout of this IC is shown in Fig. 2.39. The
maximum voltages that can be applied to VCC pin and inputs of buffers are 7 V and
5.5 V, respectively.

Fig. 2.39 Pinout of 7407

46 2 Logic Gates and Combinational Logic Circuits

Prepare the circuit shown in Fig. 2.40 and fill the Table 2.5.

Fig. 2.40 Circuit for studying

the behavior of 7407

Table 2.5 Output voltage versus input voltage

Case Output voltage shown by the voltmeter
When push button is pressed (input voltage = 5 V)
When push button is not pressed (input voltage = 0 V)

Fig. 2.41 The circuit does not

work correctly when the
pull-up resistor is removed
2.11 Bus Transceiver ICs 47

Note that resistor R2 in Fig. 2.40 is the pull-up resistor and its presence is necessary for
correct operation of the circuit. In other words, a circuit like the one shown in Fig. 2.41
doesn’t work correctly.
The pull-up resistor can be connected to voltages bigger than 5 V as well. In 7407, the
pull-up resistor can be connected to any positive voltage less than 30 V. Let’s change the
pull-up resistor voltage and observe the behavior of the circuit.
Connect the pull-up resistor to 10 V supply (Fig. 2.42) and fill the Table 2.6.

Fig. 2.42 Pull-up resistor is

connected to 10 V

Table 2.6 Output voltage versus input voltage

Case Output voltage shown by the voltmeter
When push button is pressed (input voltage = 5 V)
When push button is not pressed (input voltage = 0 V)

2.11 Bus Transceiver ICs

Previous experiment studied the behavior of buffer circuits. Output of the buffer gates
can’t be tied together. Let’s see why? For instance, consider the circuit shown in Fig. 2.43.
In this case we have a single wire and two data sources. We want to use this single wire
to transfer the two sources data. When both sources generate the same data (i.e., when
output of both buffers have the same logic level) no trouble exists. However, when one
source generates high and the other one generates low, a short circuit happens in the
output. Therefore, output of normal two state buffers can’t be tied together.
48 2 Logic Gates and Combinational Logic Circuits

Fig. 2.43 Outputs are

connected to each other

You can use tri-state buffers to transfer data on a shared data bus without the risk of
generating short circuit. Symbol and simplified model of a tri-state buffer is shown in
Fig. 2.44. When input is high the switch S1 is in the H position. When input is low the
switch S1 is in the L position. Switch S2 is controlled with Enable pin. When Enable

Fig. 2.44 Symbol and simple

model of a three state buffer
gate
2.11 Bus Transceiver ICs 49

pin is low the switch S2 is open and the tri-state buffer is in the high impedance (open
circuit) mode. Therefore, the tri-state buffer’s output can take three different states: High
state, low state and high impedance state. Output of tri-state buffers can be connected to
each other without the risk of generating short circuit.
74245 is an octal (=eight) bus transceiver with three state buffers. Pin out of this IC is
shown in Fig. 2.45. The data can be transferred from Ai to Bi pin or from Bi to Ai pin (i
= 0, 1, 2, …, 7).

Fig. 2.45 Pinout of 74245

Figures 2.46 and 2.47 show how to transfer data from the bus to the device and from
the device to the bus. Note that the pin 1 determines the direction of data transfer.

Fig. 2.46 Transfer of data

from the data bus to the device
50 2 Logic Gates and Combinational Logic Circuits

Fig. 2.47 Transfer of data

from the device to the data bus

When Chip Enable (pin 19) is high (Figs. 2.48 and 2.49), the IC is in the high-
impedance mode and no data transfer happens. For instance, in Fig. 2.50, the upper 74245
is active and the device connected to its Ai pins receives data from the data bus. But the
lower 74245 is disabled and no data transfer happens. Let’s summarize: C E and AB/B A
pins permits you to determine which device speaks or listens to the bus.

Fig. 2.48 C E pin is high and

the IC is in the high impedance
mode
2.11 Bus Transceiver ICs 51

Fig. 2.49 C E pin is high and

the IC is in the high impedance
mode

Fig. 2.50 Upper 74HC245 is

active and the lower one is
disabled
52 2 Logic Gates and Combinational Logic Circuits

This experiment studies the 74245 IC. Make the circuit shown in Fig. 2.51. Use a
voltmeter to measure the voltage of Bi (i = 0, 1, 2, …, 7) pins and ensure that voltage of
Bi pin equals to Ai pin.

Fig. 2.51 Transfer of data

from Ai to Bi

Change the circuit to what shown in Fig. 2.52. Use a voltmeter to measure the voltage
of Ai pins and ensure that voltage of Ai pin equals to voltage of Bi pin.

Fig. 2.52 Transfer of data

from Bi to Ai
2.12 Behavior of Basic Logic Gates 53

Now connect the pin 19 to +5 V (Fig. 2.53) and remeasure the voltage of Ai pins.
This time no data transfer happens since the IC is in high impedance mode.

Fig. 2.53 The IC is in high

impedance state

2.12 Behavior of Basic Logic Gates

In this experiment you will study the behavior of basic logic gates and you will extract
truth table of studied gates.
Let’s get started. Make the circuit shown in Fig. 2.54. This circuit studies the behavior
of AND gate. When you press the push buttons, the logic high (1) is applied to the input.
When the push buttons are not pressed, the logic low (0) is applied to the inputs. Fill the
Table 2.7. Does it match the expected values?
54 2 Logic Gates and Combinational Logic Circuits

Fig. 2.54 Circuit used to study the behavior of an AND gate

Table 2.7 Truth table for

Input 1 (pin 1) Input 2 (pin 2) Output (pin 3)
AND gate
0 0
0 1
1 0
1 1

Make the circuit shown in Fig. 2.55. This circuit studies the behavior of NAND gate.
Fill the Table 2.8. Does it match the expected values?
2.12 Behavior of Basic Logic Gates 55

Fig. 2.55 Circuit used to study the behavior of a NAND gate

Table 2.8 Truth table for

Input 1 (pin 1) Input 2 (pin 2) Output (pin 3)
NAND gate
0 0
0 1
1 0
1 1

Make the circuit shown in Fig. 2.56. This circuit studies the behavior of OR gate. Fill
the Table 2.9. Does it match the expected values?
56 2 Logic Gates and Combinational Logic Circuits

Fig. 2.56 Circuit used to study the behavior of an OR gate

Table 2.9 Truth table for OR

Input 1 (pin 1) Input 2 (pin 2) Output (pin 3)
gate
0 0
0 1
1 0
1 1

Make the circuit shown in Fig. 2.57. This circuit studies the behavior of NOR gate.
Fill the Table 2.10. Does it match the expected values?
2.12 Behavior of Basic Logic Gates 57

Fig. 2.57 Circuit used to study the behavior of a NOR gate

Table 2.10 Truth table for

Input 1 (pin 1) Input 2 (pin 2) Output (pin 3)
NOR gate
0 0
0 1
1 0
1 1

Make the circuit shown in Fig. 2.58. This circuit studies the behavior of XOR gate.
Fill the Table 2.11. Does it match the expected values?
58 2 Logic Gates and Combinational Logic Circuits

Fig. 2.58 Circuit used to study the behavior of a XOR gate

Table 2.11 Truth table for

Input 1 (pin 1) Input 2 (pin 2) Output (pin 3)
XOR gate
0 0
0 1
1 0
1 1

2.13 De Morgan’s Rule

This experiment studies the De Morgan rule. Let’s get started. Make the circuit shown in
Fig. 2.59. Then fill the truth Table 2.12. For instance, to fill the A = 1, B = 0 and C = 1
row, connect the A, B and C inputs to +5 V, GND and + 5 V, respectively. Figure 2.59
implements the OUT1 = A + B.C Boolean function.

Fig. 2.59 Implementation of

OUT1 = A + B.C Boolean
function
2.13 De Morgan’s Rule 59

Table 2.12 Truth table for

A B C OUT1
circuit shown in Fig. 2.59
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

Now make the circuit shown in Fig. 2.60 and fill the truth Table 2.13. Figure 2.60
implements the OUT2 = A’.(B’ + C’) Boolean function.

Fig. 2.60 Implementation of OUT2 = A’.(B’ + C’) Boolean function

60 2 Logic Gates and Combinational Logic Circuits

Table 2.13 Truth table for

A B C OUT2
circuit shown in Fig. 2.60
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

According to De Morgan rule, OUT2 must be complement of OUT1. Compare the

truth Tables 2.13 with 2.12 and see whether OUT2 is complement of OUT1?

2.14 Implementation of Basic Logic Gates with NAND Gate

A universal gate is a gate which can implement any Boolean function without need to
use any other gate type. The NAND and NOR gates are universal gates. This experiment
shows how logic gates can be made with NAND gate.
7400 contains 4 NAND gates. Pinout of this IC is shown in Fig. 2.61.

Fig. 2.61 Pinout of 7400

Implementation of NOT, AND, OR, NOR, XOR and XNOR with NAND gates are
shown in Figs. 2.62, 2.63, 2.64, 2.65, 2.66 and 2.67, respectively. Make these circuits and
extract the truth table of each one. Ensure that the truth table matches expected function.
2.14 Implementation of Basic Logic Gates with NAND Gate 61

Fig. 2.62 Implementation of NOT gate with NAND gate

Fig. 2.63 Implementation of AND gate with NAND gate

Fig. 2.64 Implementation of OR gate with NAND gate

Fig. 2.65 Implementation of NOR gate with NAND gate

62 2 Logic Gates and Combinational Logic Circuits

Fig. 2.66 Implementation of XOR gate with NAND gate

Fig. 2.67 Implementation of XNOR gate with NAND gate

2.15 Implementation of Basic Logic Gates with NOR Gate 63

2.15 Implementation of Basic Logic Gates with NOR Gate

Previous experiment studied the implementation of basic gates with NAND gate. This
experiment studies the implementation of basic logic gates with NOR gates. 7402 contains
4 NOR gates. Pinout of this IC is shown in Fig. 2.68.

Fig. 2.68 Pinout of 7402

Implementation of NOT, AND, NAND, OR and XOR with NOR gates are shown in
Figs. 2.69, 2.70, 2.71, 2.72 and 2.73, respectively. Make these circuits and extract the
truth table of each one. Ensure that the truth table matches expected function.

Fig. 2.69 Implementation of NOT gate with NOR gate

Fig. 2.70 Implementation of AND gate with NOR gate

64 2 Logic Gates and Combinational Logic Circuits

Fig. 2.71 Implementation of NAND gate with NOR gate

Fig. 2.72 Implementation of OR gate with NOR gate

Fig. 2.73 Implementation of XOR gate with NOR gate

2.16 Conversion of Sine Wave to Square Wave

Assume that you want to make a clock pulse from attenuated version of grid voltage. In
this case you need to convert the attenuated sine voltage into a square wave. Conversion
of a sine wave to square wave can be done with the aid of circuit shown in Fig. 2.74. RS
shows the output impedance of the signal generator V1. Diode D1 and D2 protects the
Op Amp against high voltages.
2.16 Conversion of Sine Wave to Square Wave 65

Fig. 2.74 Conversion of sine wave into a square wave

Output of circuit in Fig. 2.74 has both positive and negative voltages. If you add a
diode to the output (Fig. 2.75), you can limit the negative portion of the output to around
−0.3 V.

Fig. 2.75 Diode D3 is added to limit the negative level of output

Another option to convert a sine wave to square wave is the Schmitt trigger circuit
shown in Fig. 2.76. The upper trigger point and lower trigger points of circuit shown in
Fig. 2.76 are R1R+R
2
× VCC = 10+1
1
× 5 = 0.45V and − R1R+R 2
× VCC = − 10+1 1
×5 =
2 2
−0.45V , respectively.
66 2 Logic Gates and Combinational Logic Circuits

Fig. 2.76 Schmitt trigger circuit

Let’s get started. Make the circuits shown in Figs. 2.74, 2.75 and 2.76 and observe the
input and output waveforms for a sinusoidal input signal with peak value and frequency
of 2 V and 1 kHz, respectively.

References for Further Reading

1. Asadi F (2022) Essential circuit analysis using proteus®. Springer. https://doi.org/10.1007/978-

981-19-4353-9
2. Asadi F (2022) Essential circuit analysis using NI Multisim™ and MATLAB®. Springer. https://
doi.org/10.1007/978-3-030-89850-2
3. Asadi F (2022) Essential circuit analysis using LTspice®. Springer. https://doi.org/10.1007/978-
3-031-09853-6
4. Asadi F (2023) Analog electronic circuits laboratory manual. Springer. https://doi.org/10.1007/
978-3-031-25122-1
5. Asadi F, Eguchi K (2021) Electronic measurements. Springer. https://doi.org/10.1007/978-3-031-
02021-6
6. https://en.wikipedia.org/wiki/List_of_7400-series_integrated_circuits
7. https://en.wikipedia.org/wiki/List_of_4000-series_integrated_circuits
Digital Arithmetic
3

3.1 Introduction

This chapter shows how basic arithmetic operations can be done with digital ICs. Adder,
multiplier and magnitude comparator circuits are studied in this chapter.

3.2 Adder IC

In this experiment you will use a 7483 IC to do binary addition. 7483 is a high-speed
4-bit binary full adder with an internal carry look ahead. Pinout of this IC is shown in
Fig. 3.1. Figure 3.2 shows how this IC can be used to add two 4 bit numbers together.

Fig. 3.1 Pinout of 7483

© The Author(s), under exclusive license to Springer Nature Switzerland AG 2024 67

F. Asadi, Digital Circuits Laboratory Manual, Synthesis Lectures on Electrical
Engineering, https://doi.org/10.1007/978-3-031-41516-6_3
68 3 Digital Arithmetic

Fig. 3.2 7483’s pins function

Let’s get started. Make the circuit shown in Fig. 3.3.

Fig. 3.3 Test circuit with 7483

3.2 Adder IC 69

Assume that we want to add A = 1000 to B = 0111 with input carry of Cin = 0.
Using binary addition, we expect 1000 + 0111 + 0 = 0 1111. In this case output carry
(cout) is zero. Let’s see whether the 7483 generates the same result.
The circuit shown in Fig. 3.4 adds A = 1000 to B = 0111 with input carry of Cin =
0. In this Fig. 3.1 means connecting to +5 V and 0 means connecting to ground. Make
the circuit and see whether it generates the expected result.

Fig. 3.4 Applying the inputs to the circuit (Cin = 0)

Now assume that we want to add A = 1000 to B = 0111 with input carry of Cin = 1.
Using binary addition, we expect 1000 + 0111 + 1 = 1 0000. In this case output carry
is 1.
The circuit shown in Fig. 3.5 adds A = 1000 to B = 0111 with input carry of Cin =
1. Similar to the previous figure, 1 means connecting to +5 V and 0 means connecting
to ground. Make the circuit and see whether it generates the expected result.
70 3 Digital Arithmetic

Fig. 3.5 Applying the inputs to the circuit (Cin = 1)

Figure 3.6 shows how to use two 7483 IC’s to add two 8-bit numbers
A7 A6 A5 A4 A3 A2 A1 A0 and B7 B6 B5 B4 B3 B2 B1 B0 together.
3.3 BCD Adder Circuit 71

Fig. 3.6 8-bit adder IC

3.3 BCD Adder Circuit

In the previous experiment you learned how to add two binary 4-bit numbers together. In
this experiment you will see how to add two BCD numbers together.
72 3 Digital Arithmetic

Fig. 3.7 BCD adder circuit

3.3 BCD Adder Circuit 73

Fig. 3.8 BCD adder circuit

with A = 1000 and B = 1000
inputs
74 3 Digital Arithmetic

The circuit shown in Fig. 3.7 can be used to add two BCD numbers together. The BCD
inputs are entered to the Ai and Bi pins with the weights shown in Fig. 3.7. Outputs are
taken from Si (i = 1, 2, 3, 4) and B2 (or B3) pins.
Assume that we want to add two BCD numbers A = 1000 to B = 1000. In this case
A = B = 8 and A + B = 16. Therefore, we expect the circuit to set the output carry
and generate (6)10 = (0101)2 on S4, S3, S2 and S1 outputs. The circuit shown in Fig. 3.8
adds to BCD number A = 1000 and B = 1000 together. Make it and observe the outputs.
Compare the outputs witch expected corrected results.
Apply some other values to the circuit and ensure that it works correctly.

3.4 2-Bit Multiplier

In this experiment you will test the 2-bit multiplier circuit. The 2-bit multiplier circuit is
shown in Fig. 3.9.

Fig. 3.9 2-bit multiplier block diagram

Make the circuit shown in Fig. 3.10 and fill the Table 3.1. Compare the “C3C2C1C0 (in
decimal)” and “B1B0 × A1A0 (in decimal)” columns together to ensure that it generates
the product of inputs.
3.4 2-Bit Multiplier 75

Fig. 3.10 2-bit multiplier circuit

76 3 Digital Arithmetic

Table 3.1 Truth table for circuit shown in Fig. 3.10

B1 B0 B1B0 A1 A0 A1A0 B1B0 × C3 C2 C1 C0 C3C2C1C0
(in decimal) (in decimal) A1A0 (in decimal)
(in decimal)
0 0 0 0 0 0 0
0 0 0 0 1 1 0
0 0 0 1 0 2 0
0 0 0 1 1 3 0
0 1 1 0 0 0 0
0 1 1 0 1 1 1
0 1 1 1 0 2 2
0 1 1 1 1 3 3
1 0 2 0 0 0 0
1 0 2 0 1 1 2
1 0 2 1 0 2 4
1 0 2 1 1 3 6
1 1 3 0 0 0 0
1 1 3 0 1 1 3
1 1 3 1 0 2 6
1 1 3 1 1 3 9

3.5 Magnitude Comparator IC

The 7485 IC can be used to compare the magnitude of two 4-bit binary numbers. Pinout
7485 IC is shown in Fig. 3.11.
3.5 Magnitude Comparator IC 77

Fig. 3.11 Pinout of 7485

Let’s get started. Make the circuit shown in Fig. 3.12 and fill the Table 3.2. You can
apply other values to inputs A and B and observe the output.
78 3 Digital Arithmetic

Fig. 3.12 4-bit comparator circuit

Table 3.2 Output for some

Input A Input B Which LED turns on?
sample inputs
(1011)2 = (11)10 (1001)2 = (9)10
(1001)2 = (9)10 (1011)2 = (11)10
(1011)2 = (11)10 (1011)2 = (11)10

Figure 3.13 shows how to cascade two 7485 to make an 8-bit magnitude comparator.
3.5 Magnitude Comparator IC 79

Fig. 3.13 8-bit comparator

circuit
80 3 Digital Arithmetic

3.6 ALU IC

74181 is a 4-bit Arithmetic Logic Unit (ALU) IC introduced in 1970 by Texas Instrument.
74181 is a compact solution for projects which require arithmetic operations.

References for Further Study

1. Asadi F (2022) Essential circuit analysis using proteus®. Springer. https://doi.org/10.1007/978-

981-19-4353-9
2. Asadi F (2022) Essential circuit analysis using NI Multisim™ and MATLAB®. Springer. https://
doi.org/10.1007/978-3-030-89850-2
3. Asadi F (2022) Essential circuit analysis using LTspice®. Springer. https://doi.org/10.1007/978-
3-031-09853-6
4. Asadi F (2023) Analog electronic circuits laboratory manual. Springer. https://doi.org/10.1007/
978-3-031-25122-1
5. Asadi F, Eguchi K (2021) Electronic measurements. Springer. https://doi.org/10.1007/978-3-031-
02021-6
6. https://en.wikipedia.org/wiki/List_of_7400-series_integrated_circuits
7. https://en.wikipedia.org/wiki/List_of_4000-series_integrated_circuits
Multiplexer and De-multiplexer
4

4.1 Introduction

Multiplexer (or Mux) is a device that selects between several digital (or analog) input
signals and forwards the selected input to a single output line. The selection is directed
by a separate set of digital inputs known as select lines.
A multiplexer makes it possible for several input signals to share one device or
resource, for example, one analog-to-digital converter or one communications transmis-
sion medium, instead of having one device per input signal. Multiplexers can also be used
to implement Boolean functions of multiple variables.
Conversely, a de-multiplexer (or Demux) is a device taking a single input and selecting
signals of the output of the compatible mux, which is connected to the single input, and
a shared selection line. A multiplexer is often used with a complementary demultiplexer
on the receiving end.
This chapter studies the multiplexer and demultiplexers.

4.2 Multiplexer

Multiplexer is a combinational circuit that has maximum of 2n data inputs, n selection

lines and single output line (Fig. 4.1). One of these data inputs will be connected to
the output based on the values of selection lines. Table 4.1 shows how a sample 8 × 1
multiplexer works.

© The Author(s), under exclusive license to Springer Nature Switzerland AG 2024 81

F. Asadi, Digital Circuits Laboratory Manual, Synthesis Lectures on Electrical
Engineering, https://doi.org/10.1007/978-3-031-41516-6_4
82 4 Multiplexer and De-multiplexer

Fig. 4.1 Block diagram of a multiplexer

Table 4.1 Truth table for a 8

S2 S1 S0 Y=?
× 1 multiplexer
0 0 0 Y = D0
0 0 1 Y = D1
0 1 0 Y = D2
0 1 1 Y = D3
1 0 0 Y = D4
1 0 1 Y = D5
1 1 0 Y = D6
1 1 1 Y = D7

Symbol of a 8 × 1 multiplexer is shown in Fig. 4.2.

4.2 Multiplexer 83

Fig. 4.2 Multiplexer symbol

Internal structure of a 4 × 1 multiplexer and its truth table are shown in Fig. 4.3 and
Table 4.2, respectively. Verify the given truth table and ensure that it is correct.

Fig. 4.3 Internal structure of a

4×1 multiplexer

Table 4.2 Truth table for a 4

S1 S0 Y=?
× 1 multiplexer
0 0 Y = D0
0 1 Y = D1
1 0 Y = D2
1 1 Y = D3

74151 is an 8-input multiplexer. Pinout of this IC is shown in Fig. 4.4.

84 4 Multiplexer and De-multiplexer

Fig. 4.4 Pinout of 74151

74153 is a dual 4-input multiplexer. Pinout of this IC is shown in Fig. 4.5.

4.2 Multiplexer 85

Fig. 4.5 Pinout of 74153

In this experiment you will see how a multiplexer works. Let’s get started. Make the
circuit shown in Fig. 4.6 and fill the Table 4.3. Note that logic high is given to the
associated address line when the push button is pressed. When the push button is not
pressed logic low is given to the associated address line.
86 4 Multiplexer and De-multiplexer

Fig. 4.6 Simple test circuit with 74153

Table 4.3 Output versus

S1 S0 Output
different inputs
0 0
0 1
1 0
1 1

Analyze the obtained result and see whether it matches the expected result.

4.3 De-multiplexer

De-multiplexer performs the reverse operation of multiplexer. De-multiplexer has a single

input, n selection lines and maximum of 2n outputs. The input will be connected to one
of these outputs based on the values of selection lines. A sample 1 × 4 de-multiplexer is
shown in Fig. 4.7. Operation of this 1 × 4 de-multiplexer is shown in Fig. 4.8.
4.3 De-multiplexer 87

Fig. 4.7 Block diagram of a de-multiplexer

Fig. 4.8 Data transfer paths for different values of S1 and S2

Internal structure of a 1 × 4 de-multiplexer and its truth table are shown in Fig. 4.9 and
Table 4.4, respectively. Verify the given truth table and ensure that it is correct. Symbol
of a 1 × 4 de-multiplexer is shown in Fig. 4.10.

Fig. 4.9 Internal structure of 1

× 4 de-multiplexer
88 4 Multiplexer and De-multiplexer

Table 4.4 Truth table for a 1 × 4 de-multiplexer

S1 S0 Input Din goes to …
0 0 Y0, i.e., Y0 = Din
0 1 Y1, i.e., Y1 = Din
1 0 Y2, i.e., Y2 = Din
1 1 Y3, i.e., Y3 = Din

Fig. 4.10 De-multiplexer symbol

Standard available de-multiplexer IC’s are the 74138 (1X8 TTL de-multiplexer), 74139
(dual 1X4 TTL de-multiplexer), 74154 (1 × 16 TTL de-multiplexer) or the CD4514 (1
× 16 CMOS de-multiplexer).
In this experiment you will study the behavior of de-multiplexers. This experiment
uses the 74139 IC. Pinout of this IC is shown in Fig. 4.11. Note that enable and output
pins are active low.
4.3 De-multiplexer 89

Fig. 4.11 Pinout of 74139

Fig. 4.12 Simple test circuit with 74139

Let’s get started. Make the circuit shown in Fig. 4.12 and fill the Table 4.5. Note that
when push buttons are pressed logic high is given to the associated input pin of the IC.
90 4 Multiplexer and De-multiplexer

Table 4.5 Truth table for circuit shown in Fig. 4.12

A (S0) B (S1) E (Din) Y0 Y1 Y2 Y3
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

When the push buttons are not pressed the logic low is given to the associated input pins
of the IC.
Analyze the obtained result and see whether it matches the expected result.

4.4 Analog Multiplexer and De-multiplexer

The CD405xB is a CMOS single channel analog multiplexer or de-multiplexer. Functional

diagram and pinout of this IC are shown in Figs. 4.13 and 4.14, respectively. Position of
switches shown in Fig. 4.13 is controlled by pins A, B and C pins. For instance, in
CD4053B when INH = 0 and A = 0, ax OR ay pin (pin 14) is connected to the ax pin
(pin 12). When INH = 0 and A = 1, ax OR ay pin is connected to the ay pin (pin 13).
When INH = 1, no connection exists between ax OR ay pin and ax or ay pins.
4.4 Analog Multiplexer and De-multiplexer 91

Fig. 4.13 Functional diagrams

of CD405xB
92 4 Multiplexer and De-multiplexer

Fig. 4.14 Pinout of CD405xB

The CD405xB can be used as multiplexer or de-multiplexer for analog or digital data.
For instance, in Figs. 4.15 and 4.16a CD4051B is used as multiplexer and de-multiplexer,
respectively.
4.4 Analog Multiplexer and De-multiplexer 93

Fig. 4.15 Multiplexing with CD4051

94 4 Multiplexer and De-multiplexer

Fig. 4.16 De-multiplexing

with CD4051

In this experiment you will use the CD4051B to multiplex analog voltages. Let’s get
started. Make the circuit shown in Fig. 4.17 and measure the voltage of pin 13 and 14.
From theoretical point of view, voltage of pin 13 and 14 must be around 23 × 5 = 3.33V
and 13 × 5 = 1.67V , respectively.
4.4 Analog Multiplexer and De-multiplexer 95

Fig. 4.17 Simple test circuit with 4051

Connect the A, B and C to ground (Fig. 4.18). Note the reading of voltmeter. Is it
close to the potential of pin 13?
96 4 Multiplexer and De-multiplexer

Fig. 4.18 A, B and C pins are connected to the ground

Now connect A to +5 V (Fig. 4.19). Note the reading of voltmeter. Is it close to the
potential of pin 14?
4.5 Measurement of Switch Resistance 97

Fig. 4.19 Pin A is connected

to 5 V

4.5 Measurement of Switch Resistance

Functional block diagram of CD405xB is reshown in Fig. 4.20. The switches shown in
this block diagram are not ideal switches, i.e., they have a finite on and off resistances.
The off resistance is very large so behavior of an off switch is quite close to the ideal
case. In this experiment you will measure the on resistance of the switches.
98 4 Multiplexer and De-multiplexer

Fig. 4.20 Functional diagrams

of CD405xB
4.5 Measurement of Switch Resistance 99

Let’s get started. Make the circuit shown in Fig. 4.21. Note the voltmeter reading and
call it VR4.

Fig. 4.21 Measurement of switch resistance

Figure 4.22 shows the simplified model of the circuit shown in Fig. 4.21. VTH and
RTH shows Thevenin voltage and resistance,
( respectively.
) ( to Fig.)4.22, V R4 =
According
R4 VT H
RT H +Rswitch +R4 × VTH ⇒ R switch = V R4 − 1 R 4 − R TH = 560 V R4 − 1 − 667. Use
3.33

this formula to calculate the switch resistance.

100 4 Multiplexer and De-multiplexer

Fig. 4.22 Simple model for

Fig. 4.21

4.6 Analog Switch

4016 is a CMOS quad bilateral switch. You likely find the IC 4016 marked as CD 4016,
NTE 4016, MC 14,016, HCF 4016, TC 4016, or HEF 4016. The 4066 is pin-compatible
with the 4016, but has a significantly lower on impedance and more constant on resistance
over the full range of input voltage. Therefore, the 4066 is preferable to the 4016 in most
cases. Pinout of 4016 is shown in Fig. 4.23. The on resistance of 4066 switches is around
125 y.

Fig. 4.23 Pinout of 4016/4066

The circuit shown in Fig. 4.24 is a simple test circuit for 4016 or 4066 IC. Pin 13 is
connected to ground through resistor R2. When you close the switch S1, pin 13 becomes
high and closes the analog switch between pin 1 and 2. This turns on the LED. Make the
circuit shown in Fig. 4.24 and ensure that it works as expected.
4.7 Digitally Controlled Voltage Gain 101

Fig. 4.24 Test circuit for 4016 or 4066

4.7 Digitally Controlled Voltage Gain

4016 (or 4066) can be used to make variable gain amplifiers. Let’s see how. Consider
the simple inverting amplifier shown in Fig. 4.25. Voltage gain of this amplifier is A =
Vout Rf
Vin = − R1 . Gain of this amplifier is constant since R f and R1 are constant.
102 4 Multiplexer and De-multiplexer

Fig. 4.25 Inverting amplifier

Now consider the schematic shown in Fig. 4.26. Assume that switch A is closed and
R
other switches are open. In this case the gain of amplifier is A1 = VVout
in
= − R1f . If switches
R
A and B are closed and other switches are open, the gain changes to A2 = VVout
in
= − R1 ||R
f
.
2
By selection of different values for R1 , R2 , R3 and R4 we can obtain up to 16 different
gains. Role of the switch in Fig. 4.26 can be played by 4016 or 4066 IC.

Fig. 4.26 Different gains can be obtained with the aid of switches

The circuit shown in Fig. 4.27 used the simple idea explained above to make a variable
gain amplifier. Gain of the amplifier changes by opening or closing the switches SW1,
SW2, SW3 and SW4. Make the circuit and compare the measured gains with values
predicted by theory. Use a sine wave with frequency of 1 kHz and peak-to-peak value of
200 mV as input.
References for Further Study 103

Fig. 4.27 Variable gain amplifier

References for Further Study

1. Asadi F (2022) Essential circuit analysis using proteus®. Springer. https://doi.org/10.1007/978-

981-19-4353-9
2. Asadi F (2022) Essential circuit analysis using NI Multisim™ and MATLAB®. Springer. https://
doi.org/10.1007/978-3-030-89850-2
3. Asadi F (2022) Essential circuit analysis using LTspice®. Springer. https://doi.org/10.1007/978-
3-031-09853-6
104 4 Multiplexer and De-multiplexer

4. Asadi F (2023) Analog electronic circuits laboratory manual. Springer. https://doi.org/10.1007/

978-3-031-25122-1
5. Asadi F, Eguchi K (2021) Electronic measurements. Springer. https://doi.org/10.1007/978-3-031-
02021-6
6. https://en.wikipedia.org/wiki/List_of_7400-series_integrated_circuits
7. https://en.wikipedia.org/wiki/List_of_4000-series_integrated_circuits
Encoder and Decoder
5

5.1 Introduction

An encoder is a combinational circuit that converts binary information in the form of a

2n input lines into n output lines, which represent n bit code for the input. For simple
encoders, it is assumed that only one input line is active at a time.
A priority encoder is an encoder circuit in which inputs are given priorities. When
more than one inputs are active at the same time, the input with higher priority takes
precedence and the output corresponding to that is generated.
A decoder is a combinational logic circuit that converts binary information from the n
coded inputs to a maximum of 2n unique outputs.
This chapter studies the encoders and decoders.

5.2 Decimal to Binary Coded Decimal (BCD) Priority Encoder

74147 can be used to encode 10-line decimal to 4-line BCD. Pinout of this IC is shown in
Fig. 5.1. Pin 15 has no function and just increase the number of pins to 16. Increase the
number of pins to 16 permits the manufacturer to divide the pins into two equal groups
and place them in two sides of the IC. This experiment studies the 74147 IC.

© The Author(s), under exclusive license to Springer Nature Switzerland AG 2024 105
F. Asadi, Digital Circuits Laboratory Manual, Synthesis Lectures on Electrical
Engineering, https://doi.org/10.1007/978-3-031-41516-6_5
106 5 Encoder and Decoder

Fig. 5.1 Pinout of 74147

Let’s get started. Make the circuit shown in Fig. 5.2, apply the inputs shown in
Table 5.1 to the circuit and fill the Table 5.1. For instance, Fig. 5.3 shows the required
connections to generate the input shown in the second row. Note that LED’s turns on
when the outputs are low.

Fig. 5.2 Test circuit for 74147

5.2 Decimal to Binary Coded Decimal (BCD) Priority Encoder 107

Table 5.1 Function table for 74147 decimal to BCD encoder

1 2 3 4 5 6 7 8 9 D C B A
(pin 11) (pin 12) (pin 13) (pin 1) (pin 2) (pin 3) (pin 4) (pin 5) (pin 10)
1 1 1 1 1 1 1 1 0
1 1 1 1 1 1 1 0 1
1 1 1 1 1 1 0 1 1
1 1 1 1 1 0 1 1 1
1 1 1 1 0 1 1 1 1
1 1 1 0 1 1 1 1 1
1 1 0 1 1 1 1 1 1
1 0 1 1 1 1 1 1 1
0 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1
0 0 1 1 1 1 1 1 1
1 1 0 0 1 1 1 1 1
1 1 1 1 0 1 0 1 1

Fig. 5.3 Circuit associated with second row of Table 5.1

Compare the first ten rows of the Table 5.1 with the function table shown in the
manufacturer’s datasheet. Use 11th, 12th and 13th row of Table 5.1 to explain why 74147
is a priority encoder.
108 5 Encoder and Decoder

5.3 Reading a Keypad

Fig. 5.4 Circuit to read a

keypad
5.4 8-Line to 3-Line Binary (Octal) Priority Encoder 109

The 74147 IC can be used to read a keypad. The circuit shown in Fig. 5.4 used a 74147
IC to generate a BCD code (generated code depends on the pressed button) and used a
7447 IC to show the generated BCD code on a common anode seven segment display.
Make the circuit shown in Fig. 5.4 and test it. Explain how the circuit works in detail.
You can use a 74C922 (or 74C923) to read a keypad as well. The 74C922 is a 16 key
to binary encoder. This IC is responsible for debouncing the keypad and encoding the
keypad data. The 74C922 also has a data available line (DA in Fig. 5.5), which goes high
whenever a key is pressed on the keypad. This can be used to signal when data is ready
for the UART. Output of this IC is taken from A, B, C and D pins.

Fig. 5.5 Reading a keypad with 74922

5.4 8-Line to 3-Line Binary (Octal) Priority Encoder

74148 can be used to encode 8 data lines to 3-line binary (octal). Pinout of this IC is
shown in Fig. 5.6. This experiment studies the 74148 IC.
110 5 Encoder and Decoder

Fig. 5.6 Pinout of 74148

Let’s get started. Make the circuit shown in Fig. 5.7, apply the inputs shown in
Table 5.2 to the circuit and fill the Table 5.2.

Fig. 5.7 Test circuit for 74148

5.5 3 × 8 Decoder 111

Table 5.2 Function table for 74148 8-line to 3-line binary (octal) priority encoder
EI 0 1 2 3 4 5 6 7 A2 A1 A0
0 1 1 1 1 1 1 1 0
0 1 1 1 1 1 1 0 1
0 1 1 1 1 1 0 1 1
0 1 1 1 1 0 1 1 1
0 1 1 1 0 1 1 1 1
0 1 1 0 1 1 1 1 1
0 1 0 1 1 1 1 1 1
0 0 1 1 1 1 1 1 1
0 0 0 1 1 1 1 1 1
0 1 1 0 0 1 1 1 1
0 1 1 1 1 0 0 1 1
0 1 1 1 1 1 1 0 0

Compare the first eight rows of the Table 5.2 with the function table shown in the
manufacturer’s datasheet. Use 9th, 10th, 11th and 12th row of Table 5.2 to explain why
74148 is a priority encoder.

5.5 3 × 8 Decoder

This experiment studies the 74138 IC. 74138 is a 3 × 8 decoder IC. Pinout of 74138 is
shown in Fig. 5.8. Note that outputs of this IC are active low.
112 5 Encoder and Decoder

Fig. 5.8 Pinout of 74138

Let’s get started. Make the circuit shown in Fig. 5.9 and fill the Table 5.3. Compare
your table with the function table given by the manufacturer.
5.5 3 × 8 Decoder 113

Fig. 5.9 Test circuit for 74138

Table 5.3 Function table for 74138 3 × 8 decoder

C B A Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

In Fig. 5.10, output of an 8 × 3 encoder is connected to a 3 × 8 decoder. Make the

circuit shown in Fig. 5.10 and fill the Table 5.4. Explain how the circuit works in detail.
114 5 Encoder and Decoder

Fig. 5.10 Feeding a decoder

with an encoder
5.6 BCD to Decimal Decoder (TTL IC) 115

Table 5.4 Input–output relation for circuit shown in Fig. 5.10

EI I0 I1 I2 I3 I4 I5 I6 I7 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
0 1 1 1 1 1 1 1 0
0 1 1 1 1 1 1 0 1
0 1 1 1 1 1 0 1 1
0 1 1 1 1 0 1 1 1
0 1 1 1 0 1 1 1 1
0 1 1 0 1 1 1 1 1
0 1 0 1 1 1 1 1 1
0 0 1 1 1 1 1 1 1
0 0 0 1 1 1 1 1 1
0 1 1 0 0 1 1 1 1
0 1 1 1 1 0 0 1 1
0 1 1 1 1 1 1 0 0

5.6 BCD to Decimal Decoder (TTL IC)

This experiment studies the 7442 IC. 7472 is a BCD to decimal decoder. Pinout of this
IC is shown in Fig. 5.11. Note that outputs of this IC are active low.
116 5 Encoder and Decoder

Fig. 5.11 Pinout of 7442

Let’s get started. Make the circuit shown in Fig. 5.12 and fill the Table 5.5. Compare
your table with the function table given by the manufacturer.
5.6 BCD to Decimal Decoder (TTL IC) 117

Fig. 5.12 Test circuit for 7442

118 5 Encoder and Decoder

Table 5.5 Function table for 7442 BCD to decimal decoder

D C B A Pin 0 Pin 1 Pin 2 Pin 3 Pin 4 Pin 5 Pin 6 Pin 7 Pin 8 Pin 9
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1

5.7 BCD to Decimal Decoder (CMOS IC)

This experiment studies the CD 4028 IC. CD 4028 can be used for BCD to decimal
decoding or binary to octal decoding applications. Pinout of 4028 is shown in Fig. 5.13.
5.7 BCD to Decimal Decoder (CMOS IC) 119

Fig. 5.13 Pinout of 4028

Let’s get started. Make the circuit shown in Fig. 5.14 and fill the Table 5.6. Compare
your table with the function table given by the manufacturer.
120 5 Encoder and Decoder

Fig. 5.14 Test circuit for 4028

5.8 BCD-to-Binary and Binary-to-BCD Converters 121

Table 5.6 Function table for 4028 BCD to decimal decoder

D C B A Pin 0 Pin 1 Pin 2 Pin 3 Pin 4 Pin 5 Pin 6 Pin 7 Pin 8 Pin 9
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1

5.8 BCD-to-Binary and Binary-to-BCD Converters

74184 and 74185A IC’s can be used for BCD-to-Binary and Binary-to-BCD conversions,
respectively. Pinout of these IC’s are shown in Fig. 5.15. Boolean functions of 74185A
are shown in Fig. 5.16.
122 5 Encoder and Decoder

Fig. 5.15 Pinout of 74184 and 74185A IC’s

Fig. 5.16 Boolean functions of 74185

Conversion of a 6-bit and 8-bit binary numbers to BCD code is shown in Figs. 5.17
and 5.18, respectively.
5.8 BCD-to-Binary and Binary-to-BCD Converters 123

Fig. 5.17 6-Bit

binary-to-BCD converter

Fig. 5.18 8-Bit

binary-to-BCD converter
124 5 Encoder and Decoder

Figure 5.19 converts a 6-bit binary number to a BCD code and display the generated
BCD code on common cathode seven segment displays. Make the circuit and test it for
different inputs. Explain how this circuit works in detail.

Fig. 5.19 Displaying a 6-bit binary number on two seven segments

References for Further Study

1. Asadi F (2022) Essential circuit analysis using Proteus®. Springer. https://doi.org/10.1007/978-

981-19-4353-9
2. Asadi F (2022) Essential circuit analysis using NI Multisim™ and MATLAB®. Springer. https://
doi.org/10.1007/978-3-030-89850-2
3. Asadi F (2022) Essential circuit analysis using LTspice®. Springer. https://doi.org/10.1007/978-
3-031-09853-6
4. Asadi F (2023) Analog electronic circuits laboratory manual. Springer. https://doi.org/10.1007/
978-3-031-25122-1
5. Asadi F, Eguchi K (2021) Electronic measurements. Springer. https://doi.org/10.1007/978-3-031-
02021-6
6. https://en.wikipedia.org/wiki/List_of_7400-series_integrated_circuits
7. https://en.wikipedia.org/wiki/List_of_4000-series_integrated_circuits
8. https://circuitverse.org/simulator/conversor-binario-a-bcd-74185
Display Information on Seven Segments
6

6.1 Introduction

Seven segment is a device to display decimal numerals. Seven segments are composed
of seven (or sometimes eight) LEDs. A typical seven segment is shown in Fig. 6.1.
Seven LEDs are used to display decimals numbers. The DP LED displays decimal point.
Figure 6.2 shows how different digits are displayed on a seven segment display.

Fig. 6.1 A typical seven

segment display

© The Author(s), under exclusive license to Springer Nature Switzerland AG 2024 125
F. Asadi, Digital Circuits Laboratory Manual, Synthesis Lectures on Electrical
Engineering, https://doi.org/10.1007/978-3-031-41516-6_6
126 6 Display Information on Seven Segments

Fig. 6.2 Displaying numbers

on seven segment displays

Seven segment displays are divided into two groups: Common cathode displays and
common anode displays. Internal structure of common anode and common cathode
displays are shown in Fig. 6.3.

Fig. 6.3 Structure of common anode and common cathode displays

This chapter studies the seven segment displays and related ICs.

6.2 TTL BCD to Common Cathode 7-Segment Decoder

In this experiment you will work with 7448 IC. 7448 IC is a BCD to common cathode
7-segment decoder. BCD codes for 0–9 are shown in Table 6.1.
6.2 TTL BCD to Common Cathode 7-Segment Decoder 127

Table 6.1 BCD 8421 code for

Decimal number BCD 8421 code
decimal numbers 0–9
0 0000
1 0001
2 0010
3 0011
4 0100
5 0101
6 0110
7 0111
8 1000
9 1001

Pinout of 7448 IC is shown in Fig. 6.4. Common cathode 7-segment displays can be
driven with the aid of 74248 IC as well. 74248 is electrical and functionally compatible
with 7448 IC. Additionally, pinout of 74248 is the same as 7448.

Fig. 6.4 Pinout of 7448

Let’s get stated. Make the circuit shown in Fig. 6.5 (use a common cathode 7-segment
display) and fill the Table 6.2. Compare the obtained results with the function table given
in the datasheet.
128 6 Display Information on Seven Segments

Fig. 6.5 Test circuit for 7448

Table 6.2 Function table for 7448 BCD to common cathode 7-segment decoder IC
D C B A What displayed on the 7-segment
(Weight = 8) (Weight = 4) (Weight = 2) (Weight = 1)
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
6.3 Counter from 0 to 9 129

Let’s see what Lamp Test (LT) pin does for us. When LT push button is pressed, pin 3
is connected to ground and all of the segments are turned on despite of the data entered
to pins 6, 2, 1 and 7. This helps you to test the 7-segment and see whether all of the
segments works. Study the datasheet of the IC to see what is the purpose of B I /R B O
and R B I pins.

6.3 Counter from 0 to 9

The 7490 IC can be used to make a binary counter which counts from 0 to 9 (i.e.,
0000, 0001, 0010, 0011, 0100, 0101, 0110, 0111, 1000, 1001). The circuit studied in the
previous section can be used to show the output of the counter on a 7-segment.
The circuit shown in Fig. 6.6 is a binary counter which counts from 0 to 9. Connect
the pin 14 to a low frequency clock pulse, for instance, 1 Hz. The counting is done on
the falling edge of the clock pulse. The counting cycle is 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0, 1,
2, 3, … Pinout of 7490 is shown in Fig. 6.7.

Fig. 6.6 Binary counter from 0000 to 1001

130 6 Display Information on Seven Segments

Fig. 6.7 Pinout of 7490

Make the circuit shown in Fig. 6.8 and see whether it counts from 0 to 9. Explain how
circuit works in detail.

Fig. 6.8 0–9 counter

6.4 TTL BCD to Common Anode 7-Segment Decoder

In this experiment you will work with 7447 IC. 7447 IC is a BCD to common anode
7-segment decoder. Pinout of 7447 IC is shown in Fig. 6.9. Common anode 7-segment dis-
plays can be driven with the aid of 74247 IC as well. 74247 is electrical and functionally
compatible with 7447 IC. Additionally, pinout of 74247 is the same as 7447.
6.4 TTL BCD to Common Anode 7-Segment Decoder 131

Fig. 6.9 Pinout of 7447

Make the circuit shown in Fig. 6.10 (use a common anode 7-segment display). Connect
the pin 14 of 7490 to a low frequency clock pulse, for instance, 1 Hz and see whether it
counts from 0 to 9. Explain how the circuit works in detail.

Fig. 6.10 0–9 counter with common anode display

132 6 Display Information on Seven Segments

6.5 CMOS BCD to 7-Segment Decoder

4511 is a CMOS version of 7448. This IC can work with voltages between 3 and 15 V.
Some versions even support up to 20 V. Check the datasheet of your version of the chip
for exact values. Pinout of 4511 is shown in Fig. 6.11.

Fig. 6.11 Pinout of 4511

Pins D0, D1, D2, D3 are the BCD inputs. Pins a to g are the output pins that you
connect to your 7-segment display. The LT (Lamp Test) pin is there to test that all the
segments of the display work. Set LOW to test the segments. Set HIGH for normal oper-
ation. The BL (Blanking Test) pin turns off all segments when LOW. You can use it to
control the brightness of the display with pulse-width modulation (PWM). Set to HIGH
for normal operation. The LE (Latch Enable) pin, also called store, is used to store the
current value. When HIGH, the last data is displayed regardless of the changes to the
BCD inputs. Set this pin LOW for normal operation.
Make the circuit shown in Fig. 6.12 and see whether it counts from 0 to 9. Explain
how the circuit works in detail.
6.6 Binary to BCD and BCD to Binary Converter IC 133

Fig. 6.12 0–9 counter with common cathode display

6.6 Binary to BCD and BCD to Binary Converter IC

74184 and 74185 can be used to BCD to binary and binary to BCD conversion,
respectively. Pinout of these IC’s are shown in Fig. 6.13.

Fig. 6.13 Pinout of 74184 and

74185

Datasheet of these IC’s contains a lot of schematics to show how these IC’s can be
used in different situations. For instance, Figs. 6.14 and 6.15 shows how 74185 can be
used to covert a 6-bit and 8-bit binary number to BCD, respectively. Three 74185 IC’s
are required in the 8-bit case.
134 6 Display Information on Seven Segments

Fig. 6.14 6-bit binary to BCD

converter

Fig. 6.15 8-bit binary to BCD

converter
References for Further Study 135

References for Further Study

1. Asadi F (2022) Essential circuit analysis using Proteus®. Springer. https://doi.org/10.1007/978-

981-19-4353-9
2. Asadi F (2022) Essential circuit analysis using NI Multisim™ and MATLAB®. Springer. https://
doi.org/10.1007/978-3-030-89850-2
3. Asadi F (2022) Essential circuit analysis using LTspice®. Springer. https://doi.org/10.1007/978-
3-031-09853-6
4. Asadi F (2023) Analog electronic circuits laboratory manual. Springer. https://doi.org/10.1007/
978-3-031-25122-1
5. Asadi F, Eguchi K (2021) Electronic measurements. Springer. https://doi.org/10.1007/978-3-031-
02021-6
6. https://en.wikipedia.org/wiki/List_of_7400-series_integrated_circuits
7. https://en.wikipedia.org/wiki/List_of_4000-series_integrated_circuits
8. https://www.ti.com/lit/ds/symlink/cd4511b.pdf
Latch, Flip Flop and Shift Register
7

7.1 Introduction

Latches and flip flops are circuits that have two stable states that can store state infor-
mation. Flip flops have clock input and change state on the clock pulse rising or falling
edges. Therefore, flip flop is an edge triggered device. Latches have no clock pulse input
and are level triggered devices. A Flip flop or a latch can be used to store one bit of data.
A shift register is a type of digital circuit using a cascade of flip-flops where the output
of one flip-flop is connected to the input of the next. They share a single clock signal,
which causes the data stored in the system to shift from one location to the next.
A shift register can shift the bits either to the left or to the right. Shift registers can
have both parallel and serial inputs and outputs. These are often configured as “serial-in,
parallel-out” (SIPO) or as “parallel-in, serial-out” (PISO). There are also types that have
both serial and parallel input and types with serial and parallel output. There are also
“bidirectional” shift registers, which allow shifting in both directions: L → R or R → L.
The serial input and last output of a shift register can also be connected to create a
“circular shift register”.
This chapter studies the latches, flip flops and shift registers.

7.2 Commonly Used JK Flip Flops

Commonly used JK flip flops are shown in Figs. 7.1, 7.2, 7.3, 7.4, 7.5 and 7.6.

© The Author(s), under exclusive license to Springer Nature Switzerland AG 2024 137
F. Asadi, Digital Circuits Laboratory Manual, Synthesis Lectures on Electrical
Engineering, https://doi.org/10.1007/978-3-031-41516-6_7
138 7 Latch, Flip Flop and Shift Register

Fig. 7.1 Pinout of 7473

Fig. 7.2 Pinout of 7476

7.2 Commonly Used JK Flip Flops 139

Fig. 7.3 Pinout of 74107

Fig. 7.4 Pinout of 74109

140 7 Latch, Flip Flop and Shift Register

Fig. 7.5 Pinout of 74112

Fig. 7.6 Pinout of 4027

7.3 Commonly Used D Flip Flops 141

7.3 Commonly Used D Flip Flops

Commonly used D flip flops are shown in Figs. 7.7, 7.8, 7.9, 7.10, 7.11 and 7.12.

Fig. 7.7 Pinout of 7474

Fig. 7.8 Pinout of 74174

142 7 Latch, Flip Flop and Shift Register

Fig. 7.9 Pinout of 74175

Fig. 7.10 Pinout of 74273

7.3 Commonly Used D Flip Flops 143

Fig. 7.11 Pinout of 74374

Fig. 7.12 Pinout of 4013

144 7 Latch, Flip Flop and Shift Register

7.4 Commonly Used D Type Data Latches

Commonly used D type data latch IC’s are shown in Figs. 7.13 and 7.14.

Fig. 7.13 Pinout of 7475

Fig. 7.14 Pinout of 74373

7.6 SR Latch with Transistors 145

Fig. 7.15 Pinout of 74279

7.5 Commonly Used SR Latch

SR latches are simple to implement using standard NAND gates. The 74279 IC contains
four individual active low latches as well. Its pinout is shown in Fig. 7.15.

7.6 SR Latch with Transistors

Circuit of a SR latch is shown in Fig. 7.16. Explain how this circuit works. Then, make
the circuit and fill the Table 7.1. Apply the inputs in the order shown in Table 7.1. Pinout
of 2N3904 is shown in Fig. 7.17.
146 7 Latch, Flip Flop and Shift Register

Fig. 7.16 Transistor SR latch

Table 7.1 Function table for the circuit shown in Fig. 7.16
No S R Q Q
1 1 0
2 0 0
3 0 1
4 0 0
5 1 1
7.7 Active High SR Latch 147

Fig. 7.17 Pinout of 2N3904

7.7 Active High SR Latch

In this experiment you will study the active high SR latches (An active high SR latch is
a type of latch which is set when S = 1). The active high SR latch circuit is shown in
Fig. 7.18.

Fig. 7.18 Active high SR

latch

Table 7.2 shows the function table of circuit shown in Fig. 7.18.
148 7 Latch, Flip Flop and Shift Register

Table 7.2 Function table for active high SR latch

S R Q Q Description
1 0 1 0 Set
0 0 NC NC No change (NC)
0 1 0 1 Reset
1 1 ? ? Undefined

Symbol of an active high SR latch is shown in Fig. 7.19.

Fig. 7.19 Active high SR

latch symbol

Let’s get started. Make the circuit shown in Fig. 7.20 and fill the Table 7.3. Give the
inputs in the order shown in the table. Compare the filled table with the Table 7.2. Are
these tables consistent?

Fig. 7.20 Active high SR latch circuit

7.8 Active Low SR Latch 149

Table 7.3 Function table for the circuit shown in Fig. 7.20
No S R Q Q
1 1 0
2 0 0
3 0 1
4 0 0
5 1 1

7.8 Active Low SR Latch

In this experiment you will study the active low SR latches (An active low SR latch is
a type of latch which is set when S = 0). The active low SR latch circuit is shown in
Fig. 7.21.

Fig. 7.21 Active low SR latch

Table 7.4 shows the function table of circuit shown in Fig. 7.21.

Table 7.4 Function table for active low SR latch

S R Q Q Description
0 1 1 0 Set
1 1 NC NC No change (NC)
1 0 0 1 Reset
0 0 ? ? Undefined
150 7 Latch, Flip Flop and Shift Register

Symbol of an active low SR latch is shown in Fig. 7.22.

Fig. 7.22 Active low SR latch

symbol

Let’s get started. Make the circuit shown in Fig. 7.23 and fill the Table 7.5. Give the
inputs in the order shown in the table. Compare the filled table with the Table 7.4. Are
these tables consistent?

Fig. 7.23 Active low SR latch

7.9 De-bouncing with SR Latch 151

Table 7.5 Function table for the circuit shown in Fig. 7.23
No S R Q Q
1 0 1
2 1 1
3 1 0
4 1 1
5 0 0

7.9 De-bouncing with SR Latch

The SR latch can be used to de-bounce the Single Pole Double Throw (SPDT) switches.
Figures 7.24 and 7.25 show how to use the active high and active low latches for de-
bouncing purposes.

Fig. 7.24 De-bouncing with active high SR latch (Fig. 7.20)

152 7 Latch, Flip Flop and Shift Register

Fig. 7.25 De-bouncing with active low SR latch (Fig. 7.23)

Let’s study one of these circuits and see how it works. For instance, consider the circuit
shown in Fig. 7.26. Assume that we put the SPDT switch in the position 2. In this case
the output is high (Fig. 7.26). Now the bounce problem causes the pole of the switch to
be float (Fig. 7.27). In this case the R = S = 1 and the latch is in the no change mode.
Therefore, the latch holds the high output and the bounce problem can’t make any change
in the output.

Fig. 7.26 Switch is in the

position 2
7.10 Behavior of JK Flip Flops 153

Fig. 7.27 Switch is float

7.10 Behavior of JK Flip Flops

This section studies the function table of 704107 IC which is a JK flip flop (Fig. 7.28).
Function table of JK flip flop which works with rising edge is shown in Table 7.6.

Fig. 7.28 Pinout of 74107

154 7 Latch, Flip Flop and Shift Register

Table 7.6 Function table of JK flip flop which works with rising edge
J K Clock Q Q
0 0 ↑ No change No change
1 0 ↑ 1 0
0 1 ↑ 0 1
1 1 ↑ Toggle Toggle

Let’s get started. Make the circuit shown in Fig. 7.29. The reset pin (pin 13) is deac-
tivated by connecting it to a high logic level. When the reset pin is connected to ground
the flip flop’s output is Q = 0 and Q = 1 despite of its inputs. Reset pin is used for
resetting (clearing) the output. Apply a 10 Hz clock pulse to pin 12 of 74107. Required
10 Hz clock pulse can be made using the circuit shown in Fig. 7.30. Pinout of 555 is
shown in Fig. 7.31.

Fig. 7.29 74107 JK flip flop test circuit

7.10 Behavior of JK Flip Flops 155

Fig. 7.30 10 Hz generator

Fig. 7.31 Pinout of 555

Follow the following instructions in order:

1. Press the J button only. In this case J = 1 and K = 0. Pay attention to the output.
What do you observe?
2. Don’t press any of the buttons. In this case J = K = 0. Pay attention to the output.
What do you observe? Compare the outputs with step 1. Are they the same?
3. Press the K button only. In this case J = 0 and K = 1. Pay attention to the output.
What do you observe?
156 7 Latch, Flip Flop and Shift Register

4. Don’t press any of the buttons. In this case J = K = 0. Pay attention to the output.
What do you observe? Compare the outputs with step 3. Are they the same?
5. Press the J and K push buttons. When J and K push buttons are pressed simultaneously
J = K = 1. Pay attention to the output. What do you observe?

Compare your answers with Table 7.6 and see whether they are consistent.

7.11 Conversion of JK Flip Flop to T Flip Flop

You can make a T flip flop from a JK flip flop by connecting the J and K inputs together
(Fig. 7.32). Function table of this flip flop is shown in Table 7.7.

Fig. 7.32 Conversion of JK

flip flop to T flip flop

Table 7.7 Function table of a

T CLK Q
T flip flop which works with
rising edge 0 ↑ No change
1 ↑ Q

Let’s make a T flip flop with 7473 IC. Pinout of 7473 is shown in Fig. 7.33.

Fig. 7.33 Pinout of 7473

7.11 Conversion of JK Flip Flop to T Flip Flop 157

Make the circuit shown in Fig. 7.34 and apply a 10 Hz square wave to the clock pin
(pin 1). Required 10 Hz can be made with the aid of the circuit shown in Fig. 7.35. Output
LED in Fig. 7.34 starts to blink since T = 1 and T flip flop toggles in this mode. What
is the relationship between frequency of the waveform of pin 12 and frequency of input
clock pulse?

Fig. 7.34 T flip flop test circuit

Fig. 7.35 10 Hz generator

158 7 Latch, Flip Flop and Shift Register

Now connect the reset pin to ground and apply the 10 Hz square wave to pin 1
(Fig. 7.36). In this case the reset pin is activated and force the output to remain at low
state despite of the flip flop inputs.

Fig. 7.36 Rest pin is connected to ground

7.12 Conversion of JK Flip Flop to D Flip Flop

You can make a D flip flop from a JK flip flop using the circuit shown in Fig. 7.37.
Function table of D flip flop is shown in Table 7.8.

Fig. 7.37 Conversion of JK to

D flip flop

Table 7.8 Function table of a

D CLK Q
D flip flop which works with
rising edge 0 ↑ 0
1 ↑ 1

Let’s make a D flip flop with 7473 IC. Pinout of 7473 is shown in Fig. 7.38.
7.12 Conversion of JK Flip Flop to D Flip Flop 159

Fig. 7.38 Pinout of 7473

Make the circuit shown in Fig. 7.39 and apply a 10 Hz square wave to the clock pin
(pin 1). Required 10 Hz can be made with the aid of circuit shown in Fig. 7.35. Put the
switch SW in high and low states and observe the output for each case.

Fig. 7.39 D flip flop test circuit

Connect the reset pin to ground (Fig. 7.40). Put the switch SW in high and low states
and observe the output for each case. Does the position of switch affect the output?
160 7 Latch, Flip Flop and Shift Register

Fig. 7.40 Reset pin is connected to the ground

7.13 Conversion of D Flip Flop to T Flip Flop

You can make a T flip flop from a D flip flop using the circuit shown in Fig. 7.41. Function
table of T flip flop is shown in Table 7.8.

Fig. 7.41 Conversion of D flip

flop to T flip flop

Let’s get started. Make the circuit shown in Fig. 7.42. Pinout of 7474 is shown in
Fig. 7.43. The R and S pins (pins 1 and 4) are deactivated. Therefore, the flip flop can
work based on the inputs. When the R is connected to ground, Q = 0 and Q = 1 despite
of inputs. When the S is connected to ground, Q = 1 and Q = 0 despite of inputs.
7.13 Conversion of D Flip Flop to T Flip Flop 161

Fig. 7.42 T flip flop test circuit

Fig. 7.43 Pinout of 7474

Apply a 10 Hz clock pulse to pin 3 and connect the T input to high state. Required
10 Hz can be made with the aid of circuit shown in Fig. 7.44. The LED in Fig. 7.44 starts
to blink since T = 1 puts the T flip flop in the toggle mode. What is the relationship
between frequency of the waveform of pin 5 and frequency of input clock pulse?
162 7 Latch, Flip Flop and Shift Register

Fig. 7.44 High signal is applied to the input

7.14 De-bouncing with D Flip Flops

Single pole double throw switches can be de-bounced with D flip flops. Figure 7.45 shows
how to de-bounce a SPDT switch with JK flip flop. Note that output Q is high when the
switch is in position A. Output Q is low when the switch is in the position B.
7.15 4-Bit Latch 163

Fig. 7.45 De-bouncing with

7474 D flip flop

7.15 4-Bit Latch

7475 contains 4 transparent D latches. It can be used to latch 4-bir of data. Pinout of this
IC is shown in Fig. 7.46. In this experiment you will see how this IC works.

Fig. 7.46 Pinout of 7475

164 7 Latch, Flip Flop and Shift Register

Consider the circuit shown in Fig. 7.47. When the switch is open, E0/1 = E2/3 = 1
and the latch is transparent. By transparent we mean that Q 0 = D0 , Q 1 = D1 , Q 2 = D2
and Q 3 = D3 . When the switch is close, E0/1 = E2/3 = 0 and the IC latch data. Let’s
see the behavior of the IC with a simple experiment.

Fig. 7.47 Simple test circuit for 7475

Follow the following instructions in order:

(A) Keep the switch open and give the 0111 as input data to the IC (Fig. 7.48) and fill
the Table 7.9.
7.15 4-Bit Latch 165

Fig. 7.48 0111 is applied to the input

Table 7.9 Outputs of Fig. 7.48

D3 D2 D1 D0 Switch Q3 Q2 Q1 Q0
0 1 1 1 Open

(B) Keep the switch open and give the 0011 as input data to the IC (Fig. 7.49) and fill
the Table 7.10.
166 7 Latch, Flip Flop and Shift Register

Fig. 7.49 0011 is applied to the input

Table 7.10 Outputs of Fig. 7.49

D3 D2 D1 D0 Switch Q3 Q2 Q1 Q0
0 0 1 1 Open

(C) Close the switch (Fig. 7.50) and fill the Table 7.11. The IC is no longer “transparent”
when 0 is given to E0/1 and E2/3 inputs. The D0, D1, D2 and D3 inputs have no
effect on the output when the IC is in the latch mode (i.e., when E0/1 = E2/3 = 0).
7.15 4-Bit Latch 167

Fig. 7.50 Input data 0011 is latched

Table 7.11 Outputs of Fig. 7.50

D3 D2 D1 D0 Switch Q3 Q2 Q1 Q0
0 0 1 1 Close

(D) Keep the switch closed and give the 0111 as input data to the IC (Fig. 7.51). Then
fill the Table 7.12.
168 7 Latch, Flip Flop and Shift Register

Fig. 7.51 0111 is applied to the input

Table 7.12 Outputs of Fig. 7.51

D3 D2 D1 D0 Switch Q3 Q2 Q1 Q0
0 1 1 1 Close

(E) Keep the switch closed and give the 0000 as input data to the IC (Fig. 7.52). Then
fill the Table 7.13.
7.16 8-Bit Latch 169

Fig. 7.52 0000 is applied to the input

Table 7.13 Outputs of Fig. 7.52

D3 D2 D1 D0 Switch Q3 Q2 Q1 Q0
0 0 0 0 Close

7.16 8-Bit Latch

The IC 74373 contains eight D flips and it can be used as an 8-bit latch. Pinout and
internal structure of this IC is shown in Figs. 7.53 and 7.54, respectively. Input data is
applied to D0 , D1 , D2 , . . . , D7 pins. O0 , O1 , O2 , . . . , O7 are output pins.
170 7 Latch, Flip Flop and Shift Register

Fig. 7.53 Pinout of 74373

Fig. 7.54 Internal structure of 74373

When O E pin (pin 1) is low and L E pin (pin 11) is high, the IC is in the transparent
mode (i.e., On = Dn where n = 0, 1, 2, . . . , 7). When O E and L E pins are low, the IC
latches the data. When L E pin (pin 11) is high (status of L E pin is not important in this
case), the IC is in the high impedance mode and there is no connection between outputs
On and outputs of flip flops.

7.17 Edge Detector Circuits

Edge detector circuits are used to detect the transition from low to high (rising edge) or
high to low (falling edge). Rising and falling edge detectors are shown in Figs. 7.55 and
7.56, respectively.
Figures 7.57 and 7.58 show how these circuits work.
7.17 Edge Detector Circuits 171

Fig. 7.55 Rising edge detector

Fig. 7.56 Falling edge detector

Fig. 7.57 Working principle

of rising edge detector

Fig. 7.58 Working principle

of falling edge detector
172 7 Latch, Flip Flop and Shift Register

Let’s get started. Make the rising edge detector circuit shown in Fig. 7.59. Use a signal
generator to apply a 10 kHz square wave to the circuit and observe the input and output
wave forms.

Fig. 7.59 Rising edge detector circuit

Make the falling edge detector circuit shown in Fig. 7.60. Use a signal generator to
apply a 10 kHz square wave to the circuit and observe the input and output wave forms.

Fig. 7.60 Falling edge detector circuit

7.18 Edge Detection with D Flip Flops

Edge detection can be done with D flip flops as well. Figures 7.61 and 7.62 show the
rising and falling edge detector circuits, respectively. Explain how these circuits work.
7.18 Edge Detection with D Flip Flops 173

Fig. 7.61 Rising edge detector

Fig. 7.62 Falling edge detector

Let’s get started and test the circuits. Make the circuit shown in Fig. 7.63. The 555 IC
generates a square wave around 1 kHz. Use a signal generator to apply a 100 Hz square
wave to pin 2 and observe the input and output simultaneously on the oscilloscope screen.
174 7 Latch, Flip Flop and Shift Register

Fig. 7.63 Rising edge detector

circuit
7.18 Edge Detection with D Flip Flops 175

Now make the circuit shown in Fig. 7.64. The 555 IC generates a square wave around
1 kHz. Use a signal generator to apply a 100 Hz square wave to pin 2 and observe the
input and output simultaneously on the oscilloscope screen.

Fig. 7.64 Falling edge

detector circuit
176 7 Latch, Flip Flop and Shift Register

7.19 Shift Registers

Register in digital electronics stores binary numbers. It is a collection of flip-flops which

stores digital data as binary numbers. One flip-flop can store 1-bit data. In shift registers
always D flip-flop is used.
A shift register, as name suggests, shifts data (numbers) which is stored in flip-flops
at every clock pulse. It has one or more input(s) depending upon type of input. It can be
one in serial input and more than one in parallel input. Just like input, it can be one or
more output(s) depending upon type of output. Depending on type of input and output,
there are four types of shift register:

(A) Serial input serial output (SISO)

(B) Serial input parallel output (SIPO)
(C) Parallel input serial output (PISO)
(D) Parallel input parallel output (SISO).

A “Universal” shift register is a special type of register that can load the data in a parallel
way and shift that data in both directions, i.e., right and left.
Shift registers are used for: Serial to parallel or parallel to serial data conversion,
shift data to left/right, store data and increase the number of input/output pins of any
microcontroller.
Some of the famous shift registers are: 74164 (8-bit SIPO shift register), 74595 (8-bit
SIPO shift register), 74194 (4-bit universal shift register) and 74323 (8-bit universal shift
register).

7.20 74595 Shift Register

74595 is an 8-bit serial in parallel out shift register. Pinout of this IC is shown in Fig. 7.65.
7.20 74595 Shift Register 177

Fig. 7.65 Pinout of 74595

Transferring a serial data to Q7, Q6, Q5, …, Q0 output pins is done with SER, SRCLK
and RCLK pins (Fig. 7.66).

Fig. 7.66 Block diagram of

74595

8 clock pulses are required to transfer 8 bits into the shift register. Data is applied to
SER pin and clock pulses are applied to SRCLK pin. In Fig. 7.67, 11010100 is entered
into the shift register.
178 7 Latch, Flip Flop and Shift Register

Fig. 7.67 Serial data is applied to the SER pin

After entering the serial data to shift register, you need to give a high signal to RCLK
pin in order to latch the data. After giving a high signal to RCLK pin, the data appear in
the output Q7, Q6, Q5, …, Q0 output pins (Fig. 7.68).

Fig. 7.68 Applying a high signal to RCLK pin latches the data

The circuit shown in Fig. 7.69 can be used to see how 74595 IC works. When Data
push button is pressed, a high signal is applied to pin 14. When Data push button is not
pressed a low signal is applied to pin 14.
Let’s get started. Make the circuit shown in Fig. 7.69 and enter the 11100110 to the
shift register. In order to enter 11100110 to the shift register:
7.20 74595 Shift Register 179

Fig. 7.69 Test circuit for

74595
180 7 Latch, Flip Flop and Shift Register

(A) Press the CLK push button once,

(B) Hold down the Data push button and press the CLK push button twice,
(C) Release the Data push button and press the CLK push button twice,
(D) Hold down the Data push button and press the CLK push button three times,
(E) Press the Latch push button once.

What happens when you press the Reset button?

References for Further Study

1. Asadi F (2022) Essential circuit analysis using Proteus®. Springer. https://doi.org/10.1007/978-

981-19-4353-9
2. Asadi F (2022) Essential circuit analysis using NI Multisim™ and MATLAB®. Springer. https://
doi.org/10.1007/978-3-030-89850-2
3. Asadi F (2022) Essential circuit analysis using LTspice®. Springer. https://doi.org/10.1007/978-
3-031-09853-6
4. Asadi F (2023) Analog electronic circuits laboratory manual. Springer. https://doi.org/10.1007/
978-3-031-25122-1
5. Asadi F, Eguchi K (2021) Electronic measurements. Springer. https://doi.org/10.1007/978-3-031-
02021-6
6. https://en.wikipedia.org/wiki/List_of_7400-series_integrated_circuits
7. https://en.wikipedia.org/wiki/List_of_4000-series_integrated_circuits
8. https://www.youtube.com/watch?v=Ys2fu4NINrA&t=1227s
Frequency Division with Flip Flops
8

8.1 Introduction

The frequency divider circuit is a kind of circuit widely used in the digital system. Its
function is to divide and drop the frequency of the high frequency signal to get the lower
frequency signal. Flip flops can be used to make frequency divider circuits.
This chapters shows how frequency divider circuits can be made with flip flops and
other related ICs.

8.2 Frequency Division with D Flip Flop

A D flip flop can be used to divide the frequency of an input pulse by factor of two
(Fig. 8.1). Figure 8.2 shows how to cascade D flip flops to obtain a bigger reduction
coefficient.

© The Author(s), under exclusive license to Springer Nature Switzerland AG 2024 181
F. Asadi, Digital Circuits Laboratory Manual, Synthesis Lectures on Electrical
Engineering, https://doi.org/10.1007/978-3-031-41516-6_8
182 8 Frequency Division with Flip Flops

Fig. 8.1 Frequency division by 2

Fig. 8.2 Frequency division by 2, 4 and 8

7474 is composed of two positive edge triggered D flip flops with preset and clear.
Pinout and function table of 7474 are shown in Figs. 8.3 and 8.4, respectively.
8.2 Frequency Division with D Flip Flop 183

Fig. 8.3 Pinout of 7474

Fig. 8.4 Function table for

7474
184 8 Frequency Division with Flip Flops

74174 and 74175 contain D flip flops as well. 74174 has 6 D flip flops (Fig. 8.5) while
74175 has 4 D flip flops (Fig. 8.6). D flip flops in these IC’s are positive edge triggered
flip flops. Flips of 74174 don’t have the Q output while 74175 flip flops have the have
the Q output. Function table of these flip flops are shown in Fig. 8.7.

Fig. 8.5 Pinout of 74174

Fig. 8.6 Pinout of 74175

8.2 Frequency Division with D Flip Flop 185

Fig. 8.7 Function table for 74174/74175 flip flops

Let’s get started. Make the circuit shown in Fig. 8.8. Apply a square wave with ampli-
tude of 5 V and frequency of 1 kHz (Fig. 8.9) to the input and measure the output
frequency. Explain how this circuit works in detail.

Fig. 8.8 Frequency division by 2

186 8 Frequency Division with Flip Flops

Fig. 8.9 Square wave with

amplitude of 5 V

Now change the circuit to what shown in Fig. 8.10. Apply the 1 kHz square wave to
the input and measure the output frequency. Explain how this circuit works in detail.

Fig. 8.10 Frequency division by 4

8.3 Frequency Division with 4017

The 4017 can be used for frequency division by 2, 3, 4, 5, 6, 7, 8, 9 and 10. Pinout of
4017 is shown in Fig. 8.11.
8.3 Frequency Division with 4017 187

Fig. 8.11 Pinout of 4017

Let’s get started. Make the circuit shown in Fig. 8.12 and apply a 1 kHz square wave
to it. Change the location of rotary switch and measure the output frequency.

Fig. 8.12 Frequency division with 4017

Figures 8.13, 8.14 and 8.15 shows sample outputs for the circuit shown in Fig. 8.12.
188 8 Frequency Division with Flip Flops

Fig. 8.13 Sample output for connecting Q2 to MR

Fig. 8.14 Sample output for connecting Q4 to MR

Fig. 8.15 Sample output for connecting Q6 to MR

Following circuits (Figs. 8.16 and 8.17) show how to use the 4017 to divide the input
frequency by 10 and 100. Make these circuits and test them.
8.3 Frequency Division with 4017 189

Fig. 8.16 Frequency division 10

190 8 Frequency Division with Flip Flops

Fig. 8.17 Frequency division 100

8.4 Frequency Division with 7490 191

8.4 Frequency Division with 7490

You can use the 7490 for frequency division purposes as well. Pinout of this IC is shown
in Fig. 8.18.

Fig. 8.18 Pinout of 7490

Figure 8.19 shows how to divide the input frequency by 2 using 7490. Sample input
and output for this circuit is shown in Fig. 8.20. Make this circuit and test it (apply a
square wave with frequency of 1 kHz and measure the output frequency).

Fig. 8.19 Frequency division by 2

192 8 Frequency Division with Flip Flops

Fig. 8.20 Sample output for circuit shown in Fig. 8.19

Figure 8.21 shows how to divide the input frequency by 5 using 7490. Sample input
and output for this circuit is shown in Fig. 8.22. Make this circuit and test it.

Fig. 8.21 Frequency division by 5

8.4 Frequency Division with 7490 193

Fig. 8.22 Sample input output for circuit shown in Fig. 8.21

Figure 8.23 shows how to divide the input frequency by 10 using 7490. Sample input
and output for this circuit is shown in Fig. 8.24. Note that the output waveform is not
symmetric although the input is symmetric (i.e., square wave). Make this circuit and test
it.

Fig. 8.23 Frequency division by 10

194 8 Frequency Division with Flip Flops

Fig. 8.24 Sample input output for circuit shown in Fig. 8.23

Figure 8.25 shows another way to divide the input frequency by 10 using 7490. Sample
input and output for this circuit is shown in Fig. 8.26. Note that the output waveform is
symmetric. Make this circuit and test it.

Fig. 8.25 Frequency division by 10

8.5 Frequency Division with 555 195

Fig. 8.26 Sample input output for circuit shown in Fig. 8.25

8.5 Frequency Division with 555

A continuously triggered monostable circuit when triggered by a square wave generator

can be used as a frequency divider, if the timing interval is adjusted to be longer than the
period of the triggering square wave input signal.
Make the circuit shown in Fig. 8.27. Input frequency is a square wave with frequency
of 1 kHz. C2 = 10 nF and POT = 1 Mu. Turn the potentiometer knob and measure the
minimum and maximum frequency of the output.
196 8 Frequency Division with Flip Flops

Fig. 8.27 Frequency division with 555

References for Further Study

1. Asadi F (2022) Essential circuit analysis using Proteus®. Springer. https://doi.org/10.1007/978-

981-19-4353-9
2. Asadi F (2022) Essential circuit analysis using NI Multisim™ and MATLAB®. Springer. https://
doi.org/10.1007/978-3-030-89850-2
3. Asadi F (2022) Essential circuit analysis using LTspice®. Springer. https://doi.org/10.1007/978-
3-031-09853-6
4. Asadi F (2023) Analog electronic circuits laboratory manual. Springer. https://doi.org/10.1007/
978-3-031-25122-1
5. Asadi F, Eguchi K (2021) Electronic measurements. Springer. https://doi.org/10.1007/978-3-031-
02021-6
6. https://en.wikipedia.org/wiki/List_of_7400-series_integrated_circuits
7. https://en.wikipedia.org/wiki/List_of_4000-series_integrated_circuits
Counter Circuits
9

9.1 Introduction

Counter is a logic circuit made up of a series of flip-flops that are used to count the number
of inputs in the form of negative or positive edge transitions. The counter is classified
into synchronous and asynchronous counters. The difference between the synchronous
and asynchronous counter can be identified according to the flip-flops that are triggered.
A Synchronous counter is the counter in which the clock input with all the flip-flops
uses the same source and produces the output at the same time. If the flip-flops do not
receive the same clock signal, then that counter is called as Asynchronous counter. In
Asynchronous counters, the clock pulse is applied only to first flip-flop. The remaining
flip-flops receive the clock signal from output of its previous stage flip-flop.
The synchronous counter provides a more reliable circuit for counting purposes, and
for high-speed operation, as the clock pulses in this circuit are fed to every flip-flop in
the chain at exactly the same time. Synchronous counters therefore eliminate the clock
ripple problem, as the operation of the circuit is synchronized to the clock pulses, rather
than flip-flop outputs.
This chapter focused on the counters. You will learn how to make and test different
types of counters in this chapter.

9.2 Low Frequency Clock Pulse Generation

Low frequency clock pulses are very useful in testing the counter circuits. A low fre-
quency clock pulse causes the counter to count slowly and permits the user to observe
the change of outputs more easily.
The circuit show in Fig. 9.1 generates a 3.7 Hz clock pulse. If you replace the C1 with
a 10 µF capacitor you will have an output frequency around 5 Hz.

© The Author(s), under exclusive license to Springer Nature Switzerland AG 2024 197
F. Asadi, Digital Circuits Laboratory Manual, Synthesis Lectures on Electrical
Engineering, https://doi.org/10.1007/978-3-031-41516-6_9
198 9 Counter Circuits

Fig. 9.1 3.7 Hz clock pulse generator

Fig. 9.2 5.37 Hz clock pulse generator

9.3 Single Clock Pulse Generation 199

Amplitude of the output for the circuits shown in Figs. 9.1 and 9.2 is around 3.5–4 V.
Add a buffer to the output to have a clean clock pulse with an amplitude around 5 V
(Fig. 9.3).

Fig. 9.3 Increasing the 555 output amplitude

9.3 Single Clock Pulse Generation

The circuits given in this section are very useful for testing the counter circuits. These
circuits force the counter to go one by one when you press a push button. Therefore, you
can clearly see how the circuit counts.
From theoretical point of view, the simple circuits shown in Fig. 9.4 can be used to
generate single clock pulses. For instance, in circuit Fig. 9.4a: When you press the push
button the output goes from high to low and when you release the push button the output
goes from low to high. However, these circuits can’t be used to generate single clock
pulses because of the switch bounce problem. The bounce problem causes the counter to
count more than once although the user push (or release) the button once. Therefore, we
need a bounceless solution.
200 9 Counter Circuits

Fig. 9.4 Pulse generation with

push buttons

The circuit shown in Fig. 9.5 generates a single clock pulse each time the push button
is pressed and released. You can increase the amplitude of the output with the aid of
technique shown in Fig. 9.3.
9.3 Single Clock Pulse Generation 201

Fig. 9.5 Single clock pulse generation with 555

You can use the simple circuit shown in Fig. 9.6 as well. When you press the push
button the capacitor starts to charge toward +5 V. When you release the push button the
capacitor starts to discharge and goes toward 0 V.

Fig. 9.6 Single clock pulse generation with RC circuit

202 9 Counter Circuits

Another option is the circuit shown in Fig. 9.7. When you press the push button the
output goes from low to high. When you release the push button output goes from high
to low. The LED D1 shows the status of output.

Fig. 9.7 Single clock pulse generation with RC circuit

Another option for single clock pulse generation is shown in Fig. 9.8. Output is high
when the switch is in the S position and is low when the switch in the R position. When
the switch is in the S position and you put it in the R position, output goes from high to
low. When the switch is in the R position and you put it in the S position, output goes
from low to high. Therefore, moving the switch from one position to the other one and
returning it to the initial position genrates a complete single clock pulse. The LED D1
shows the status of output.
9.4 4-Bit Binary Counter 203

Fig. 9.8 Single clock pulse generation

The required clock pulses for counter circuits studied in this chapter can be generated
using the circuits studied in this section and Sects. 9.2 and 9.3.

9.4 4-Bit Binary Counter

You can make a 4-bit binary counter with the aid of 7493 IC. Pinout of 7493 is shown in
Fig. 9.9.
204 9 Counter Circuits

Fig. 9.9 Pinout of 7493

Let’s get started. Make the circuit shown in Fig. 9.10. Give a low frequency clock
pulse to the circuit (or use one of the single clock pulse generator circuits) and observe
the counting of the circuit. What happens when you press the reset button? Explain how
the circuit works in detail.
9.5 8-Bit Binary Counter 205

Fig. 9.10 4-bit counter

9.5 8-Bit Binary Counter

You can make an 8-bit binary counter with the aid of 7493 IC. Pinout of 74393 is shown
in Fig. 9.11.
206 9 Counter Circuits

Fig. 9.11 Pinout of 74393

Let’s get started. Make the circuit shown in Fig. 9.12. Give a low frequency clock
pulse to the circuit (or use one of the single clock pulse generator circuits) and observe
the counting of the circuit. What happens when you press the reset button?
9.5 8-Bit Binary Counter 207

Fig. 9.12 8-bit counter with 74393

Now change the circuit to what shown in Fig. 9.13. This circuit counts from 00000000
up to 00011110. Test the circuit and explain how it works in detail.
208 9 Counter Circuits

Fig. 9.13 Counter counts from 00000000 up to 00011110

9.6 14-Bit Binary Counter

Pinout of 744020 is shown in Fig. 9.14. You can use the 744020 (or CD 4020 B) to make
a 14-bit counter (Fig. 9.15).
9.6 14-Bit Binary Counter 209

Fig. 9.14 Pinout of 744020

Fig. 9.15 Counter with 744020

210 9 Counter Circuits

9.7 4-Bit Up/Down Counter

The 74192 is an up/down BCD decade counter and the 74193 is an up/down modulo-16
binary counter. Pinout of these IC’s is shown in Fig. 9.16.

Fig. 9.16 Pinout of 74192/93

Table 9.1 gives a brief description of each pin.

Table 9.1 Description of

Pin name Description
74192/93 pins
CPU Count up clock pulse input
CPD Count down clock pulse input
MR Asynchronous master reset (clear) input
PL Asynchronous parallel load (active low) input
PN Parallel data inputs
Qn Flip-flop outputs
TCD Terminal count down (borrow) output
TCU Terminal count up (carry) output
9.7 4-Bit Up/Down Counter 211

Let’s get started and see how 74193 works. Make the circuit shown in Fig. 9.17. When
you press the load button the data on the D0, D1, D2 and D3 lines will be transferred
(loaded) to the Q0, Q1, Q2 and Q3 outputs. This circuit shows how to load a data into
the IC.

Fig. 9.17 Loading the data to output

Circuit shown in Fig. 9.18 is an up counter. A low frequency clock pulse is applied to
pin 5. You can reset the counter by pressing the Reset push button. Make the circuit and
see how it counts. Pay attention to the behavior of TCU and TCD outputs. Parallel load
is disabled in this circuit.
212 9 Counter Circuits

Fig. 9.18 Up counter with 74193

Circuit shown in Fig. 9.19 is a down counter. A low frequency clock pulse is applied
to pin 4. You can reset the counter by pressing the Reset push button. Make the circuit
and see how it counts. Pay attention to the behavior of TCU and TCD outputs. Parallel
load is disabled in this circuit.
9.7 4-Bit Up/Down Counter 213

Fig. 9.19 Down counter with 74193

Circuit shown in Fig. 9.20 counts from 0000 up to 0110. Make the circuit and test it.
Explain how this circuit works.

Fig. 9.20 4-bit counter counts up to 0110

214 9 Counter Circuits

The required clock pulses can be generated with the aid of push buttons as well. Circuit
shown in Fig. 9.21 shows how to count up/down using two push buttons. Note that the

Fig. 9.21 Up/down counter

9.8 CMOS Counter/Divider 215

push buttons are followed by a de-bounce circuit for correct operation. A circuit like the
one shown in Fig. 9.22 may not work correctly (For instance, when you press the up
button once, output may increase by say 3).

Fig. 9.22 Push buttons are not de-bounced

9.8 CMOS Counter/Divider

4017 is a CMOS counter/divider. Pinout of this IC is shown in Fig. 9.23. The Clock pin
increases the counter with one every time the pin goes from low to high. And as the count
increases, the output pins (Q0–Q9) get high one by one. After the 10th input pulse, the
counter resets and starts from 0 again.
216 9 Counter Circuits

Fig. 9.23 Pinout of 4017

The Clock Inhibit (CI) pin disables the counter so that any clock pulse on the CLK
pin is ignored. Set this pin to low to enable the counter. The Carry-out (CO) pin goes
from low to high when the counter reaches 10 and resets back to 0. It stays high for 5
clock pulses, then goes low again. Connect this pin to the clock input of another decade
counter if you want to count higher than 10.
Let’s get started. Make the circuit shown in Fig. 9.24 and pay attention to output
pattern.
9.8 CMOS Counter/Divider 217

Fig. 9.24 Test circuit for 4017

218 9 Counter Circuits

Circuit shown in Fig. 9.25 counts from 0 to 5 (the circuit resets on the sixth time you
press the push button). Make the circuit and test it. Explain how the circuit works as well.

Fig. 9.25 Q6 is connected to

Master Reset (MR) pin
9.8 CMOS Counter/Divider 219

Figures 9.26 and 9.27 show how to cascade two or three 4017 IC’s to obtain a bigger
counter. Make these circuits and see how they work.

Fig. 9.26 Two 4017 ICs are cascaded

220 9 Counter Circuits

Fig. 9.27 Three 4017 ICs are cascaded

References for Further Study 221

References for Further Study

1. Asadi F (2022) Essential circuit analysis using Proteus®. Springer. https://doi.org/10.1007/978-

981-19-4353-9
2. Asadi F (2022) Essential circuit analysis using NI Multisim™ and MATLAB®. Springer. https://
doi.org/10.1007/978-3-030-89850-2
3. Asadi F (2022) Essential circuit analysis using LTspice®. Springer. https://doi.org/10.1007/978-
3-031-09853-6
4. Asadi F (2023) Analog electronic circuits laboratory manual. Springer. https://doi.org/10.1007/
978-3-031-25122-1
5. Asadi F, Eguchi K (2021) Electronic measurements. Springer. https://doi.org/10.1007/978-3-031-
02021-6
6. https://en.wikipedia.org/wiki/List_of_7400-series_integrated_circuits
7. https://en.wikipedia.org/wiki/List_of_4000-series_integrated_circuits
8. https://josephftaylor.com/projects/university/ttl-frequency-counter/
Oscillator Circuits
10

10.1 Introduction

Sequential logic circuits require a clock pulse for correct operation. This chapter shows
how required clock pulse can be generated with transistors, 555 timer IC and other related
ICs.
The 555 timer IC (Fig. 10.1) is used in a variety of timer, delay, pulse generation, and
oscillator applications. Block diagram of this IC is shown in Fig. 10.2. Reference [1] is a
good reference on analysis of 555 based circuits.

Fig. 10.1 555 timer IC

© The Author(s), under exclusive license to Springer Nature Switzerland AG 2024 223
F. Asadi, Digital Circuits Laboratory Manual, Synthesis Lectures on Electrical
Engineering, https://doi.org/10.1007/978-3-031-41516-6_10
224 10 Oscillator Circuits

Fig. 10.2 Block diagram of

555 timer IC

The 556 IC (Fig. 10.3) contains two 555 ICs. Pinout of 556 is shown in Fig. 10.4.

Fig. 10.3 556 dual precision

timers

Fig. 10.4 Pinout of 556

10.2 Square Wave Generation with Transistor 225

10.2 Square Wave Generation with Transistor

The circuit shown in Fig. 10.5 can be used to generate square waves. Output frequency
RC when R2 = R3 = R and C 1 = C 2 = C. For instance, output frequency for
is f = 0.73
circuit shown in Fig. 10.6 is around 9 Hz.

Fig. 10.5 Astable circuit

226 10 Oscillator Circuits

Fig. 10.6 Output frequency is around 9 Hz

Make the circuit shown in Fig. 10.6 and use an oscilloscope to observe the output
voltage (i.e., the transistor Q2 collector voltage). Pay attention to the rising edge. The
rising edge of the output voltage is curved and slow. This problem can be solved with the
aid of the modified circuit shown in Fig. 10.7 [1].
10.3 Square Wave Generation with 555 IC 227

Fig. 10.7 Modified astable oscillator

Make the circuit shown in Fig. 10.7 and see whether the rising edge problem of
Fig. 10.6 is solved.

10.3 Square Wave Generation with 555 IC

NI® Multisim™ provides a tool to design the 555 timer IC circuits. The tool is accessible
in the Tools > Circuit wizards >555 timer wizard path [2].
Figure 10.8 shows how to generate 1 Hz, 10 Hz, 100 Hz, 1 kHz and 10 kHz with 555
IC. The rotary switch Rs determines the output frequency. Make the circuit and test it.
Measure the amplitude and frequency of output voltage.
228 10 Oscillator Circuits

Fig. 10.8 555 clock pulse generator

10.4 Square Wave Generation with NOT Gates

Square wave can be generated with the aid of inverter (NOT gates) as well. The circuit
1
shown in Fig. 10.9 can be used for this purpose. Output frequency is around RC in
Fig. 10.9. This circuit gives an excellent performance in many simple applications, if a
stable frequency is an important factor in the choice of clock oscillator, there are of course
better options. You can make this circuit for R = 10 ky and C = 0.1 µF and observe the
output with an oscilloscope.
10.4 Square Wave Generation with NOT Gates 229

Fig. 10.9 Simple NOT gate

oscillator

Figure 10.10 shows another oscillator made with inverters. This circuit provides a
better frequency stability in comparison to Fig. 10.9. Any inverting CMOS gate can be
used here. Use of MM 74C04 IC is recommended. However, you can use MM 74C00,
MM 74C02, MM 74C10 or CD 4069 as well.

Fig. 10.10 Modified NOT

gate oscillator

In this circuit output frequency equals to:

1
f ∼
=
2 × C(0.405Req + 0.693R1 )

where Req = RR11+R

R2
2
. Let’s study three special cases:
if R1 = R2 = R ⇒ f ∼ = 0.559
RC
if R2 >> R1 ⇒ f ∼ = 0.455
R1 C
if R1 >> R2 ⇒ f ∼ = 0.722
R1 C
For instance, consider the circuit shown in Fig. 10.11. In this circuit the output
frequency is around 56 kHz.
230 10 Oscillator Circuits

Fig. 10.11 Modified NOT gate oscillator circuit

You can use the circuit shown in Fig. 10.12 to generate frequencies between 17 and
92 Hz. Frequency is set with the aid of 10 ky potentiometer. You can change the capacitor
and resistor values to obtain other ranges.

Fig. 10.12 17–92 Hz oscillator

10.5 Pulse Generation with 555 IC

In Sect. 10.3 you learned how a square wave (Fig. 10.13) can be generated with 555 IC. In
this section you will see how 555 can be used to generate a pulse waveform (Fig. 10.14).
10.5 Pulse Generation with 555 IC 231

Fig. 10.13 Square wave (Duty cycle = 50%)

Fig. 10.14 Pulse waveform

The circuit shown in Fig. 10.15 can be used to generate pulse waveforms. In this
circuit t1 = 0.693 × R2 × C and t2 = 0.693 × (R1 + R2 ) × C. Output frequency is
f = t1 +t
1
2
= (R1 +2R
1.44
2 )×C
.

Fig. 10.15 Pulse generation with 555

232 10 Oscillator Circuits

10.6 Non Retriggerable Monostable with 555 IC

Monostable or one-shot circuit is a digital circuit that is only stable in one state. This
means that the output is usually low (logic 0) but it can be triggered and the output will
go temporarily high (logic 1) for some predetermined length of time.
Monostable circuits are divided into two groups: Non retriggerable and retriggerable
one-shots. Non retriggerable one-shots do not respond to any triggers that occur during
the unstable state (Fig. 10.16).

Fig. 10.16 Non retriggerable one-shot

Retriggerable one-shots respond to any trigger, even if it occurs in the unstable state.
If it occurs during the unstable state, the state is extended by an amount equal to the pulse
width (Fig. 10.17).

Fig. 10.17 Retriggerable one-shot

An application for a retriggerable one-shot is a power failure detection circuit. Triggers

are derived from the AC power source, and continue to retrigger the one-shot. In the
event of a power failure, the one-shot is not triggered and an alarm can be initiated.
Retriggerable one-shot can be made with 74122, 74123 or 4047 IC’s (Fig. 10.18).
10.6 Non Retriggerable Monostable with 555 IC 233

Fig. 10.18 Power failure detection

Schematic of a retriggerable one-shot with 4047 is shown in Fig. 10.19. Pinout of 4047
is shown in Fig. 10.20. Duration of output pulse for Fig. 10.19 is 2.48 × R × C. Resistor
R is between 10 ky and 1 My and capacitor C is bigger than 1 nF. Output Q is initially
at low logic and it turns high when trigger pulse comes. Q is the complement of Q.

Fig. 10.19 Retriggerable one-shot with 4047

234 10 Oscillator Circuits

Fig. 10.20 Pinout of 4047

The 555 timer in Fig. 10.21 is configured as non retriggerable circuit. This means that
the output voltage becomes high for a set duration (t1 ) when a falling edge is detected on
pin 2 (Fig. 10.22). Value of t1 = 1.1 × R × C.

Fig. 10.21 One-shot with 555

10.6 Non Retriggerable Monostable with 555 IC 235

Fig. 10.22 A pulse with t1 = 1.1 × R × C is generated on the falling edge of trigger

For instance, consider the circuit shown in Fig. 10.23. In this circuit, the output is zero
volt when the push button is not pressed. When you press the push button, the output
becomes (around) 5 V for duration of t1 = 1.1 × 4.7k × 100μ = 0.517s. After 0.517s,
the output returns to zero volt again.

Fig. 10.23 Monostable circuit with t1 = 0.517s

236 10 Oscillator Circuits

10.7 Non Retriggerable Monostable with 74121 IC

The non retriggerable monostable circuit can be made with the aid of 74121 IC as well.
Pinout of 74121 IC is shown in Fig. 10.24. Pins 2, 8, 12 and 13 are not used in this IC.
Time delays from 40 ns up to 28 s can be generated with this IC.

Fig. 10.24 Pinout of 74121

Figure 10.25 shows a non retriggerable monostable made with 74121. In this circuit
t1 = 0.693 × (R + 2ky) × C = 0.693 × (33ky + 2ky) × 100µF = 2.425s. In this circuit
1.4ky < R < 40ky and C < 1000µF.
10.8 Servomotor Tester with 555 IC 237

Fig. 10.25 Non retriggerable monostable with 74121

10.8 Servomotor Tester with 555 IC

A servomotor is a special type of electric motors coupled to a sensor for position feedback.
Position of shaft is controllable in this type of motors. Servomotors are widely used in
digital cameras, robots, toys (for example, model cars/aircrafts/boats), …
The 555 IC can be used to test small servo motors as well. Circuits shown in
Figs. 10.26 and 10.27 can be used for this purpose.
You can rotate the servomotor shaft either in clockwise or counter clockwise directions
by pushing the push buttons shown in Fig. 10.26 or the potentiometer shown in Fig. 10.27.
238 10 Oscillator Circuits

Fig. 10.26 Position of servomotor shaft is controlled with the aid of two push buttons
References for Further Study 239

Fig. 10.27 Position of servomotor shaft is controlled with the aid of a potentiometer

References for Further Study

1. Bell DA (1988) Solid state pulse circuits. Prentice Hall

2. Asadi F (2022) Essential circuit analysis using NI Multisim™ and MATLAB®. Springer. https://
doi.org/10.1007/978-3-030-89850-2
3. Asadi F (2022) Essential circuit analysis using Proteus®. Springer. https://doi.org/10.1007/978-
981-19-4353-9
240 10 Oscillator Circuits

4. Asadi F (2022) Essential circuit analysis using LTspice®. Springer. https://doi.org/10.1007/978-

3-031-09853-6
5. Asadi F (2023) Analog electronic circuits laboratory manual. Springer. https://doi.org/10.1007/
978-3-031-25122-1
6. Asadi F, Eguchi K (2021) Electronic measurements. Springer. https://doi.org/10.1007/978-3-031-
02021-6
7. https://en.wikipedia.org/wiki/List_of_7400-series_integrated_circuits
8. https://en.wikipedia.org/wiki/List_of_4000-series_integrated_circuits
9. https://www.onsemi.com/pub/collateral/an-118.pdf
Analog-to-Digital and Digital-to-Analog
Converters
11

11.1 Introduction

An Analog-to-Digital converter (ADC or A/D or A-to-D) is a system that converts an

analog signal (i.e., a sound picked up by a microphone), into a digital signal. Some of the
commonly used analog to digital converters are: HX711, ADS1115 and ICL7106/7.
Digital multimeters use an analog to digital converter to measure and display voltage.
They most commonly used analog to digital IC in the digital multimeters is ICL7106
or ICL7107. Pinout and a sample circuit with this IC is shown in Figs. 11.1 and 11.2,
respectively.

© The Author(s), under exclusive license to Springer Nature Switzerland AG 2024 241
F. Asadi, Digital Circuits Laboratory Manual, Synthesis Lectures on Electrical
Engineering, https://doi.org/10.1007/978-3-031-41516-6_11
242 11 Analog-to-Digital and Digital-to-Analog Converters

Fig. 11.1 Pinout of ICL7106/7107

Fig. 11.2 ICL7107 test circuit with 7-segment display. Components selected for 200 mV full scale
11.2 Analog to Digital Conversion with ADC0804 243

A digital-to-analog converter (DAC, D/A, or D-to-A) is a system that converts a digital

signal into an analog signal. Some of the commonly used digital to analog converters are:
DAC080x and DAC0832.
This chapter studies the analog to digital and digital to analog conversion and related
ICs.

11.2 Analog to Digital Conversion with ADC0804

This section studies the ADC0804 IC. Pinout of ADC0804 is shown in Fig. 11.3.

Fig. 11.3 Pinout of ADC0804

Followings must be done in order to convert an analog data into a digital data with
ADC0804:

(1) Make Chip Select low to activate the ADC0804.

(2) Make Write pin low.
(3) Make Write pin high after some delay small delay. This low to high impulse at Write
pin starts the conversion.
(4) Check the Interrupt pin. If it is high, conversion is running. If it is low, the conversion
is over.
(5) Make Read low and after some time high. This will bring the converted value to the
8 data output pins (pins 11–18) of ADC0804.
244 11 Analog-to-Digital and Digital-to-Analog Converters

Let’s get started. Make the circuit shown in Fig. 11.4. The ADC in Fig. 11.4 configured in
continuous conversion mode (see the IC’s datasheet). In this mode the ADC continuously
convert the input analog signal to digital.

Fig. 11.4 Test circuit for

ADC0804
11.3 Increasing the Analog to Conversion Accuracy 245

Measure the voltage of VREF/2 pin (pin 9) with a digital multimeter. Multiply the read
value by two. The result gives you the value of VREF. VREF is the voltage associated
with 11111111.
Turn the potentiometer knob and apply the desired voltage to pin VIN + pin (pin
6) and pay attention to the output LEDs. Output times VREF/255 gives the value of
input analog voltage. For example, assume that output showed 10100111. (10100111)2
= (167)10 . Therefore, the analog voltage applied to the VIN + pin of the ADC is 167 ×
VREF/255. Assume that VREF/2 is around 2.5 V. Therefore, VREF = 5 V and voltage
given to the VIN + pin of the ADC is 167 × VREF/255 = 167 × 5/255 = 3.28 V.

11.3 Increasing the Analog to Conversion Accuracy

The VREF/2 pin (pin 9) of the ADC0804 can be used to decrease the step size of
conversion (increasing the accuracy of conversion).
When VREF/2 is not connected to anywhere, the VREF/2 potential is around 2.5 V.
Therefore, VREF is around 2 × 2.5 V = 5 V and step size is VREF/255 = 5 V/255 =
19.6 mV. In this case the full scale span is from 0 V to VREF = 5 V.
Now, assume that you connected the VREF/2 pin to 3.3+1 1
× 5 = 1.16V (Fig. 11.5).
The VREF is 2.32 V and full scale span is from 0 V to VREF = 2.32 V (this means that
you can give analog voltages in the [0, 2.32 V] range). The step size of conversion in this
case is 2.32 V/255 = 9.1 mV.
Let’s study an example. Assume that output showed 10,100,111 while VREF/2 =
1.16 V. VREF = 2.32 V and (10100111)2 = (167)10 . In this case the analog voltage
applied to VIN + pin of the ADC is 167 × VREF/255 = 167 × 2.32/255 = 1.52 V.
246 11 Analog-to-Digital and Digital-to-Analog Converters

Fig. 11.5 Voltage divider

circuit

Let’s get started. Make the voltage divider shown in Fig. 11.5 and connect it to pin 9
of ADC0804 shown in Fig. 11.4. Turn the potentiometer knob and apply a desired voltage
lies in the [0, 2.32 V] interval to the VIN + pin. Note the applied voltage and obtained
output. Use the above formulas to calculate the voltage applied to pin VIN+ and compare
the calculated value with the applied voltage value.

11.4 Voltage Level Monitor

The circuit shown in Fig. 11.6 reads an analog voltage between 0 and 5 V and displays
a digit between 1 and 9 based on the entered voltage value. Bigger number means bigger
input voltage. Analyse the circuit and determine the input voltage ranges for each digit.
Then make the circuit and see whether your predictions are correct.
11.4 Voltage Level Monitor 247

Fig. 11.6 Voltage level

monitor circuit
248 11 Analog-to-Digital and Digital-to-Analog Converters

11.5 Digital to Analog Conversion with DAC0808

The DAC0808 is an 8-bit digital to analog converter. Pinout of this IC is shown in

Fig. 11.7.

Fig. 11.7 Pinout of DAC0808

Required circuit is shown in Fig. 11.8. Output voltage is V0 = R0 × I0 = R0 × VRR14

EF
×
( A21 + A42 + A83 + · · · + 256
A8
) where An = 1 if An is high and An = 0 if An is low
(n = 1, 2, 3, . . . , 8). When R0 = R14 , V0 = V R E F × ( A21 + A42 + A83 + · · · + 256
A8
).
11.5 Digital to Analog Conversion with DAC0808 249

Fig. 11.8 Commonly used DAC0808 circuit

Let’s get started. Make the circuit shown in Fig. 11.9.

Fig. 11.9 Digital to analog circuit

Let’s give a sample digital data to the input pins of DAC0808. Connect the input
data pins to VCC and ground pins similar to what shown in Fig. 11.10. According to
Fig. 11.10, 11110000
( is entered to DAC.R0)= R14 = 4.7ky and V R E F = 5V . Therefore,
( )
V0 = V R E F × A21 + A42 + A83 + · · · + 256
A8
= 5 × 21 + 14 + 18 + 16
1
= 4.69V . Test the
250 11 Analog-to-Digital and Digital-to-Analog Converters

circuit and compare your measurement with predicted value. Repeat the experiment with
other input data.

Fig. 11.10 Digital to analog converter with 11110000 input

Sample and Hold IC

LF 398 is a sample and hold IC. Pinout of this IC is shown in Fig. 11.11. You can use
this IC for sampling of an analog signal.

Fig. 11.11 LF398 is a sample and hold IC

References for Futher Study 251

References for Futher Study

1. Asadi F (2022) Essential circuit analysis using Proteus®. Springer. https://doi.org/10.1007/978-

981-19-4353-9
2. Asadi F (2022) Essential circuit analysis using NI Multisim™ and MATLAB®. Springer. https://
doi.org/10.1007/978-3-030-89850-2
3. Asadi F (2022) Essential circuit analysis using LTspice®. Springer. https://doi.org/10.1007/978-
3-031-09853-6
4. Asadi F (2023) Analog electronic circuits laboratory manual. Springer. https://doi.org/10.1007/
978-3-031-25122-1
5. Asadi F, Eguchi K (2021) Electronic measurements. Springer. https://doi.org/10.1007/978-3-031-
02021-6
6. https://en.wikipedia.org/wiki/List_of_7400-series_integrated_circuits
7. https://en.wikipedia.org/wiki/List_of_4000-series_integrated_circuits