Please note that Cypress is an Infineon Technologies Company.

The document following this cover page is marked as “Cypress” document as this is the
company that originally developed the product. Please note that Infineon will continue
to offer the product to new and existing customers as part of the Infineon product
portfolio.

Continuity of document content

The fact that Infineon offers the following product as part of the Infineon product
portfolio does not lead to any changes to this document. Future revisions will occur
when appropriate, and any changes will be set out on the document history page.

Continuity of ordering part numbers

Infineon continues to support existing part numbers. Please continue to use the
ordering part numbers listed in the datasheet for ordering.

www.infineon.com
 S29CD032G
S29CD016G
32 Mbit (1M x 32-Bit), 16 Mbit (512K x 32-Bit),
2.5 V, Burst, Dual Boot Flash
This product family has been retired and is not recommended for designs. For new and current designs, the S29CD016J and
S29CD032J supercede S29CD016G and S29CD032G respectively. This is the factory-recommended migration path. Please refer
to the S29CD-J data sheet for specifications and ordering information. Availability of this document is retained for reference and
historical purposes only.

Distinctive Characteristics
Architecture Advantages – Standby mode: CMOS: 60 µA max
 Simultaneous Read/Write Operations  1 million write cycles per sector typical
– Read data from one bank while executing erase/program  20 year data retention typical
functions in other bank  VersatileI/O™ Control
– Zero latency between read and write operations – Generates data output voltages and tolerates data input voltages
– Two bank architecture: large bank/small bank 75% / 25% as determined by the voltage on the VIO pin

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 User-Defined x32 Data Bus – 1.65 V to 3.60 V compatible I/O signals

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 Dual Boot Block

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– Top and bottom boot sectors in the same device Software Features
 Flexible Sector Architecture  Persistent Sector Protection

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– CD032G: Eight 2K Double Word, Sixty-two 16K Double Word, and – Locks combinations of individual sectors and sector groups to
prevent program or erase operations within that sector (requires

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Eight 2K Double Word sectors
– CD016G: Eight 2K Double Word, Thirty-two 16K Double Word, only VCC levels)
and Eight 2K Double Word sectors  Password Sector Protection
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 Secured Silicon Sector (256 Bytes) – Locks combinations of individual sectors and sector groups to
– Factory locked and identifiable: 16 bytes for secure, random prevent program or erase operations within that sector using a
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factory Electronic Serial Number; Also know as Electronic Marking user-definable 64-bit password
 Manufactured on 170 nm Process Technology  Supports Common Flash Interface (CFI)
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 Unlock Bypass Program Command

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 Programmable Burst Interface

– Interfaces to any high performance processor – Reduces overall programming time when issuing multiple program
command sequences
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– Linear Burst Read Operation: 2, 4, and 8 double word linear burst

with or without wrap around  Data# Polling and Toggle Bits
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 Program Operation – Provides a software method of detecting program or erase

operation completion
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– Performs synchronous and asynchronous write operations of

burst configuration register settings independently
 Single Power Supply Operation
Hardware Features
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– Optimized for 2.5 to 2.75 volt read, erase, and program operations  Program Suspend/Resume & Erase Suspend/Resume
– Suspends program or erase operations to allow reading,
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 Compatibility with JEDEC standards (JC42.4)

programming, or erasing in same bank
– Software compatible with single-power supply Flash
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 Hardware Reset (RESET#), Ready/Busy# (RY/BY#), and Write

– Backward-compatible with AMD/Fujitsu Am29LV/MBM29LV and
Protect (WP#) Inputs
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Am29F/MBM29F flash memories

 ACC Input
Performance Characteristics – Accelerates programming time for higher throughput during
system production
 High Performance Read Access
– Initial/random access times of 48 ns (32 Mb) and 54 ns (16 Mb)  Package Options
– 80-pin PQFP
– Burst access times of 7.5 ns (32 Mb) or 9 ns (16Mb)
– 80-ball Fortified BGA
 Ultra Low Power Consumption
– Pb-free package option also available
– Burst Mode Read: 90 mA @ 75 MHz max
– Known Good Die
– Program/Erase: 50 mA max

General Description
The S29CD-G Flash Family is a burst mode, Dual Boot, Simultaneous Read/Write family of Flash Memory with VersatileI/O™
manufactured on 170 nm Process Technology.
The S29CD032G is a 32 Megabit, 2.6 Volt-only (2.50 V - 2.75 V) single power supply burst mode flash memory device that can be
configured for 1,048,576 double words.

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 002-01299 Rev. *B
 S29CD032G
S29CD016G

The S29CD016G is a 16 Megabit, 2.6 Volt-only (2.50 V - 2.75 V) single power supply burst mode flash memory device that can be
configured for 524,288 double words.
To eliminate bus contention, each device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls.
Additional control inputs are required for synchronous burst operations: Load Burst Address Valid (ADV#), and Clock (CLK).
Each device requires only a single 2.6 Volt-only (2.50 V – 2.75 V) for both read and write functions. A 12.0-volt VPP is not required
for program or erase operations, although an acceleration pin is available if faster programming performance is required.
The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. The software command set is
compatible with the command sets of the 5 V Am29F or MBM29F and 3 V Am29LV or MBM29LV Flash families. Commands are
written to the command register using standard microprocessor write timing. Register contents serve as inputs to an internal state-
machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the
programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices.
The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four.
The Simultaneous Read/Write architecture provides simultaneous operation by dividing the memory space into two banks. The

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device can begin programming or erasing in one bank, and then simultaneously read from the other bank, with zero latency. This

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releases the system from waiting for the completion of program or erase operations. See Simultaneous Read/Write Operations

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Overview on page 20.

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The device provides a 256-byte Secured Silicon Sector that contains Electronic Marking Information for easy device traceability.

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In addition, the device features several levels of sector protection, which can disable both the program and erase operations in
certain sectors or sector groups: Persistent Sector Protection is a command sector protection method that replaces the old 12 V
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controlled protection method; Password Sector Protection is a highly sophisticated protection method that requires a password
before changes to certain sectors or sector groups are permitted; WP# Hardware Protection prevents program or erase in the two
outermost 8 Kbytes sectors of the larger bank.
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The device defaults to the Persistent Sector Protection mode. The customer must then choose if the Standard or Password
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Protection method is most desirable. The WP# Hardware Protection feature is always available, independent of the other protection
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method chosen.
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The VersatileI/O™ (VCCQ) feature allows the output voltage generated on the device to be determined based on the VIO level. This
feature allows this device to operate in the 1.8 V I/O environment, driving and receiving signals to and from other 1.8 V devices on
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the same bus.

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The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, by reading the DQ7
(Data# Polling), or DQ6 (toggle) status bits. After a program or erase cycle is completed, the device is ready to read array data or
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accept another command.

The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other
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sectors. The device is fully erased when shipped from the factory.
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Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power
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transitions. The password and software sector protection feature disables both program and erase operations in any combination
of sectors of memory. This can be achieved in-system at VCC level.
The Program/Erase Suspend/Erase Resume feature enables the user to put erase on hold for any period of time to read data
from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved.
The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data.
The device offers two power-saving features. When addresses are stable for a specified amount of time, the device enters the
automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in
both these modes.
AMD’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality,
reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim
tunnelling. The data is programmed using hot electron injection.

Document Number: 002-01299 Rev. *B Page 2 of 78

 S29CD032G
S29CD016G

Contents
1. Product Selector Guide ............................................... 5 15.8 Chip Erase Command................................................... 41
15.9 Sector Erase Command................................................ 41
2. Ordering Information ................................................... 6
15.10Sector Erase and Program Suspend Command .......... 42
3. Block Diagram.............................................................. 7 15.11Sector Erase and Program Suspend Operation
4. Block Diagram of Simultaneous Read/Write Circuit. 8 Mechanics..................................................................... 42
15.12Sector Erase and Program Resume Command ........... 44
5. Connection Diagram - 80-Pin PQFP ........................... 9 15.13Configuration Register Read Command....................... 44
6. Physical Dimensions - PRQ080–80-Lead Plastic Quad 15.14Configuration Register Write Command....................... 44
Flat Package........................................................................ 10 15.15Common Flash Interface (CFI) Command ................... 44
15.16Password Program Command ..................................... 45
7. Connection Diagram - 80-Ball Fortified BGA .......... 11 15.17Password Verify Command .......................................... 45
7.1 Special Package Handling Instructions........................ 11 15.18Password Protection Mode Locking Bit Program
8. Physical Dimensions - LAA080–80-ball Fortified Ball Command ..................................................................... 45

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Grid Array (13 x 11 mm) ..................................................... 12 15.19Persistent Sector Protection Mode Locking Bit Program

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Command ..................................................................... 45
9. Pin Configuration....................................................... 13 15.20PPB Lock Bit Set Command......................................... 45

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10. Logic Symbols ........................................................... 13 15.21DYB Write Command ................................................... 46

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10.1 S29CD032G................................................................. 13 15.22Password Unlock Command ........................................ 46
10.2 S29CD016G................................................................. 14 15.23PPB Program Command .............................................. 46

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15.24All PPB Erase Command ............................................. 46
11. Memory Map and Sector Protect Groups ................ 15 15.25DYB Write..................................................................... 47
12. Device Operations ..................................................... 19
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15.26PPB Lock Bit Set .......................................................... 47
12.1 VersatileI/O™ (VIO) Control ......................................... 19 15.27DYB Status ................................................................... 47
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12.2 Requirements for Reading Array Data......................... 20 15.28PPB Status ................................................................... 47
12.3 Simultaneous Read/Write Operations Overview.......... 20 15.29PPB Lock Bit Status ..................................................... 47
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12.4 Writing Commands/Command Sequences.................. 21 15.30Non-volatile Protection Bit Program And Erase Flow ... 47
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12.5 Automatic Sleep Mode (ASM)...................................... 21 16. Write Operation Status ............................................... 51
12.6 RESET#: Hardware Reset Pin..................................... 22
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16.1 DQ7: Data# Polling ....................................................... 51

12.7 Output Disable Mode ................................................... 22 16.2 RY/BY#: Ready/Busy#.................................................. 51
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12.8 Autoselect Mode .......................................................... 22 16.3 DQ6: Toggle Bit I .......................................................... 53

12.9 Asynchronous Read Operation (Non-Burst) ................ 23 16.4 DQ2: Toggle Bit II ......................................................... 53
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12.10Synchronous (Burst) Read Operation ......................... 24 16.5 Reading Toggle Bits DQ6/DQ2..................................... 53
12.11Linear Burst Read Operations ..................................... 24 16.6 DQ5: Exceeded Timing Limits ...................................... 54
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12.12Configuration Register................................................. 27 16.7 DQ3: Sector Erase Timer.............................................. 54

12.13Initial Access Delay Configuration ............................... 29
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17. Absolute Maximum Ratings....................................... 55

13. Sector Protection ....................................................... 29
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13.1 Persistent Sector Protection ........................................ 29 18. Operating Ranges ....................................................... 56

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13.2 Persistent Sector Protection Mode Locking Bit............ 31 19. DC Characteristics...................................................... 57

13.3 Password Protection Mode .......................................... 31 19.1 CMOS Compatible ........................................................ 57
13.4 Password and Password Mode Locking Bit................. 32 19.2 Zero Power Flash.......................................................... 58
13.5 Write Protect (WP#) ..................................................... 32
13.6 Secured Silicon OTP Sector and Simultaneous 20. Test Conditions ........................................................... 59
Operation ..................................................................... 32 21. Test Specifications ..................................................... 59
13.7 Persistent Protection Bit Lock ...................................... 32
22. Key to Switching Waveforms..................................... 59
13.8 Hardware Data Protection............................................ 33
23. Switching Waveforms................................................. 59
14. Common Flash Memory Interface (CFI) ................... 34
24. AC Characteristics...................................................... 60
15. Command Definitions................................................ 37
24.1 VCC and VIO Power-up................................................ 60
15.1 Reading Array Data in Non-burst Mode....................... 37
24.2 Asynchronous Read Operations ................................... 60
15.2 Reading Array Data in Burst Mode .............................. 37
24.3 Burst Mode Read for 32 Mb & 16 Mb ........................... 62
15.3 Read/Reset Command ................................................ 38
24.4 Hardware Reset (RESET#)........................................... 64
15.4 Autoselect Command................................................... 38
24.5 Erase/Program Operations ........................................... 66
15.5 Program Command Sequence .................................... 38
24.6 Alternate CE# Controlled Erase/Program Operations .. 70
15.6 Accelerated Program Command.................................. 39
15.7 Unlock Bypass Command Sequence .......................... 39 25. Erase and Programming Performance ..................... 71

Document Number: 002-01299 Rev. *B Page 3 of 78

 S29CD032G
S29CD016G

26. Latchup Characteristics ............................................ 72

27. PQFP and Fortified BGA Pin Capacitance............... 72
28. Document History Page ............................................ 73

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Document Number: 002-01299 Rev. *B Page 4 of 78

 S29CD032G
S29CD016G

1. Product Selector Guide

S29CD-G Flash Family
Part Number
(S29CD032G, S29CD016G)
VCC = 2.5 – 2.75 V
Standard Voltage Range: Synchronous/Burst or Asynchronous
VIO = 1.65 – 2.75 V
0R
0P 0M 0J
Speed Option (Clock Rate) (75 MHz)
(66 MHz) (56 MHz) (40 MHz)
(32 Mb Only)
Max Initial/Asynchronous Access Time, ns (tACC) 48 54 64 67
9 FBGA/ 10 FBGA/
Max Burst Access Delay (ns) 7.5 FBGA 17
9.5 PQFP 10 PQFP
Max Clock Rate (MHz) 75 66 56 40
Min Initial Clock Delay (clock cycles) 3 3 3 2

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Max CE# Access, ns (tCE) 52 58 69 71

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Max OE# Access, ns (tOE) 20 28

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Document Number: 002-01299 Rev. *B Page 5 of 78

 S29CD032G
S29CD016G

2. Ordering Information
The order number (Valid Combination) is formed by the following:

S29CD032G 0J F A I 0 0 0
Packing Type
0 = Tray
2 = 7” Tape and Reel
3 = 13” Tape and Reel
Additional Ordering Options (16th Character) Top or Bottom Boot
0 = Top Boot
1 = Bottom Boot
Additional Ordering Options (15th Character) Mask Revision
0 = A
1 = A1 (16 Mb only) with 7E, 36, 01/00 Autoselect ID
2 = A1 (16 Mb only) with 7E, 08, 01/00 Autoselect ID

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Temperature Range and Quality Grade

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A = Industrial (–40°C to +85°C), GT grade

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I = Industrial (–40°C to +85°C)
M = Extended (–40°C to +125°C), GT grade

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N = Extended (–40°C to +125°C)
Material Set

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A = Standard
F = Pb-free Option
Package Type
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Q = Plastic Quad Flat Package (PQFP)
F = Fortified Ball Grid Array, 1.0 mm pitch package
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Clock Frequency
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0J = 40 MHz
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0M = 56 MHz
0P = 66 MHz
0R = 75 MHz (32 Mb Only)
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Device Number/description
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S29CD032G/S29CD016G
32 or 16 Megabit (1 M or 512 K x 32-Bit) CMOS 2.5 Volt-only Burst Mode,
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Dual Boot, Simultaneous Read/Write Flash Memory

Manufactured on 110 nm floating gate technology
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Valid Combinations
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Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm
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availability of specific valid combinations and to check on newly released combinations.

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Valid Combinations
QAI, QFI,
S29CD032G QAN, QFN
0R (32 MB Only), 0P, 0M, 0J 00, 01
S29CD016G
FAI, FFI, FAN, FFN

Notes
1. The ordering part number that appears on BGA packages omits the leading “S29”.
2. Contact your local sales representative for GT grade options.
3. Refer to the KGD data sheet supplement for die/wafer sales.

Document Number: 002-01299 Rev. *B Page 6 of 78

 S29CD032G
S29CD016G

3. Block Diagram
VCC
VSS DQmax–DQ0
Amax–A0

Erase Voltage VIO Input/Output

Generator Buffers

WE#
RESET# State
ACC Control

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WP#

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Command
WORD#

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Register PGM Voltage
Generator

D
Chip Enable Data
Latch

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CE# Output Enable
OE# Logic
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Y-Decoder
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Y-Gating
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VCC Timer
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Address Latch

Detector
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X-Decoder Cell Matrix

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ADV# Burst Burst

CLK State Address
IND/
Control Counter
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WAIT#
Amax–A0
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DQmax–DQ0
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Amax–A0
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Note
Address bus is A19–A0 for 32 Mb device, A18–A0 for 16 Mb device. Data bus is D31–DQ0.

Document Number: 002-01299 Rev. *B Page 7 of 78

 S29CD032G
S29CD016G

4. Block Diagram of Simultaneous Read/Write Circuit

VCC OE#
VSS

Latches and Control Logic

Amax–A0 Upper Bank Address

Y-Decoder
Upper Bank

DQmax–DQ0
Amax–A0

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X-Decoder
Amax–A0

D
STATE
RESET# CONTROL

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Status
WE# & DQmax–DQ0
CE# COMMAND
REGISTER rN
ADV# Control

DQmax–DQ0
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X-Decoder
Amax–A0

DQmax–DQ0
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Control Logic
Latches and
Y-Decoder

Lower Bank
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Amax–A0 Lower Bank Address

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Note
Address bus is A19–A0 for 32 Mb device, A18–A0 for 16 Mb device. Data bus is D31–DQ0.
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Document Number: 002-01299 Rev. *B Page 8 of 78

 S29CD032G
S29CD016G

5. Connection Diagram - 80-Pin PQFP

IND/WAIT#

RESET#
RY/BY#
ADV#

VCCQ
WE#
WP#
MCH

OE#
CE#

CLK
VCC

VSS
NC

NC

NC
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
DQ16 1 64 DQ15
DQ17 2 63 DQ14
DQ18 3 62 DQ13
DQ19 4 61 DQ12
VCCQ 5 60 VSS
VSS 6 59 VCCQ
DQ20 7 58 DQ11
DQ21 8 57 DQ10

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DQ22 9 56 DQ9
DQ23 10 55 DQ8

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DQ24 11 54 DQ7

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DQ25 12 53 DQ6
DQ26 13 80-Pin PQFP 52 DQ5
DQ27 14 51 DQ4

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VCCQ 15 50 VSS
VSS 16 49 VCCQ

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DQ28 17 48 DQ3
DQ29 18 47 DQ2
DQ30
DQ31
19
20
46
45
rN DQ1
DQ0
MCH 21 44 A19 (32 Mb) / NC (16 Mb)
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A0 22 43 A18
A1 23 42 A17
A2 24 41 A16
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25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
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A15
A3
A4
A5
A6
A7
A8
VSS
ACC
VCC
A9
A10
A11
A12
A13
A14
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Note
On 16 Mb device, pin 44 (A19) is NC.
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 S29CD032G
S29CD016G

6. Physical Dimensions - PRQ080–80-Lead Plastic Quad Flat Package

6
D
3
D1
PIN S 0.20 MIN. FLAT SHOULDER
D3 PIN R 7˚
TYP.
0˚MIN.
0.30 ± 0.05 R
PIN ONE I.D. A

GAGE 0.25
PLANE
L 7˚
E3 3 TYP. b 4 ccc C
E1 6 0˚-7˚
-A- -B- aa a M C A B S D S
E
DETAIL X

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SEE NOTE 3

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b

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PIN P

-D- PIN Q
c

D
SEE DETAIL X
e BASIC SECTION S-S

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A2 S 2
A
A1 -A-
rN SEATING PLANE
-C-
S
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PACKAGE PQR 080 NOTES:

JEDEC MO-108(B)CB-1 NOTES 1. ALL DIMENSIONS AND TOLERANCES CONFORM TO

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SYMBOL MIN NOM MAX ANSI Y14.5M-1982.

A -- -- 3.35 2. DATUM PLANE -A- IS LOCATED AT THE MOLD PARTING LINE

m

AND IS COINCIDENT WITH THE BOTTOM OF THE LEAD WHERE

A1 0.25 -- -- THE LEAD EXITS THE PLASTIC BODY.
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A2 2.70 2.80 2.90 3. DIMENSIONS "D1" AND "E1" DO NOT INCLUD MOLD PROTRUSION.
b 0.30 -- 0.45 SEE NOTE 4 ALLOWABLE PROTRUSION IS 0.25 mm PER SIDE.
DIMENSIONS "D1" AND "E1" INCLUDE MOLD MISMATCH AND
c 0.15 -- 0.23 ARE DETERMINED AT DATUM PLANE -A-
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D 17.00 17.20 17.40 4. DIMENSION "B" DOES NOT INCLUDE DAMBAR PROTRUSION.
D1 13.90 14.00 14.10 SEE NOTE 3 5. CONTROLLING DIMENSIONS: MILLIMETER.
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D3 -- 12.0 -- REFERENCE 6. DIMENSIONS "D" AND "E" ARE MEASURED FROM BOTH
e -- 0.80 -- BASIC, SEE NOTE 7 INNERMOST AND OUTERMOST POINTS.
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E 23.00 23.20 23.40 7. DEVIATION FROM LEAD-TIP TRUE POSITION SHALL BE WITHIN
±0.0076 mm FOR PITCH > 0.5 mm AND WITHIN ±0.04 FOR
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E1 19.90 20.00 20.10 SEE NOTE 3 PITCH < 0.5 mm.

E3 -- 18.40 -- REFERENCE 8. LEAD COPLANARITY SHALL BE WITHIN: (REFER TO 06-500)
aaa --- 0.20 --- 1 - 0.10 mm FOR DEVICES WITH LEAD PITCH OF 0.65 - 0.80 mm
2 - 0.076 mm FOR DEVICES WITH LEAD PITCH OF 0.50 mm.
ccc 0.10 COPLANARITY IS MEASURED PER SPECIFICATION 06-500.
L 0.73 0.88 1.03 9. HALF SPAN (CENTER OF PACKAGE TO LEAD TIP) SHALL BE
P 24 WITHIN ±0.0085".

Q 40
R 64
S 80

3213\38.4C

Document Number: 002-01299 Rev. *B Page 10 of 78

 S29CD032G
S29CD016G

7. Connection Diagram - 80-Ball Fortified BGA

80-Ball Fortified BGA

A8 B8 C8 D8 E8 F8 G8 H8 J8 K8
A2 A1 A0 DQ29 VCCQ VSS VCCQ DQ20 DQ16 MCH

A7 B7 C7 D7 E7 F7 G7 H7 J7 K7
A3 A4 MCH DQ30 DQ26 DQ24 DQ23 DQ18 IND/WAIT# NC

A6 B6 C6 D6 E6 F6 G6 H6 J6 K6

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A6 A5 A7 DQ31 DQ28 DQ25 DQ21 DQ19 OE# WE#

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A5 B5 C5 D5 E5 F5 G5 H5 J5 K5
VSS A8 NC NC DQ27 RY/BY# DQ22 DQ17 CE# VCC

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A4 B4 C4 D4 E4 F4 G4 H4 J4 K4
ACC A9 A10 NC DQ1
rN DQ5 DQ9 WP# NC VSS

A3 B3 C3 D3 E3 F3 G3 H3 J3 K3
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VCC A12 A11 A19 (32 Mb)/ DQ2 DQ6 DQ10 DQ11 ADV# CLK
NC (16 Mb)
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A2 B2 C2 D2 E2 F2 G2 H2 J2 K2
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A14 A13 A18 DQ0 DQ4 DQ7 DQ8 DQ12 DQ14 RESET#
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A1 B1 C1 D1 E1 F1 G1 H1 J1 K1
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A15 A16 A17 DQ3 VCCQ VSS VCCQ DQ13 DQ15 VCCQ
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Note
On 16 Mb device, ball D3 (A19) is NC.
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7.1 Special Package Handling Instructions

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Special handling is required for Flash Memory products in molded packages (BGA). The package and/or data integrity may be
compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time.

Document Number: 002-01299 Rev. *B Page 11 of 78

 S29CD032G
S29CD016G

8. Physical Dimensions - LAA080–80-ball Fortified Ball Grid Array (13 x 11

mm)
0.20 C D A D1
2X eD

K J H G F E D C B A

8
7
7
SE
6
eE
5
E E1
4

3
.50

2
φ0

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1

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1.00±0.5

A1 CORNER ID.
(INK OR LASER)

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B A1

D
0.20 C 6 NXφb SD CORNER
1.00±0.5 TOP VIEW 7
2X φ0.25 M C A B
A1

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CORNER φ0.10 M C

BOTTOM VIEW

A
rN 0.25 C

A2 SEATING PLANE
C 0.15 C
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A1
SIDE VIEW
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NOTES:
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PACKAGE LAA 080

JEDEC N/A 1. DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
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13.00 x 11.00 mm NOTE

PACKAGE 2. ALL DIMENSIONS ARE IN MILLIMETERS.
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3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010

SYMBOL MIN NOM MAX (EXCEPT AS NOTED).
A -- -- 1.40 PROFILE HEIGHT 4. e REPRESENTS THE SOLDER BALL GRID PITCH.
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A1 0.40 -- -- STANDOFF 5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE "D"
A2 0.60 -- -- BODY THICKNESS DIRECTION. SYMBOL "ME" IS THE BALL COLUMN MATRIX
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SIZE IN THE "E" DIRECTION. N IS THE TOTAL NUMBER OF

D 13.00 BSC. BODY SIZE SOLDER BALLS.
E 11.00 BSC. BODY SIZE 6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
ot

D1 9.00 BSC. MATRIX FOOTPRINT DIAMETER IN A PLANE PARALLEL TO DATUM C.

N

E1 7.00 BSC. MATRIX FOOTPRINT 7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
MD 10 MATRIX SIZE D DIRECTION BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER
ME 8 MATRIX SIZE E DIRECTION OF SOLDER BALLS IN THE OUTER ROW PARALLEL TO THE D
OR E DIMENSION, RESPECTIVELY, SD OR SE = 0.000.
N 80 BALL COUNT WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
φb 0.50 0.60 0.70 BALL DIAMETER OUTER ROW , SD OR SE = e/2
eD 1.00 BSC. BALL PITCH - D DIRECTION 8. N/A
eE 1.00 BSC. BALL PITCH - E DIRECTION 9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
SD/SE 0.50 BSC SOLDER BALL PLACEMENT

3214\38.12C

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9. Pin Configuration
A0–A19 20-bit address bus for 32 Mb device, (19-bit for 16 Mb). A9 supports 12 V autoselect inputs.
DQ0–DQ31 32-bit data inputs/outputs/float
CE# Chip Enable Input. This signal is asynchronous relative to CLK for the burst mode.
OE# Output Enable Input. This signal is asynchronous relative to CLK for the burst mode.
WE# Write enable. This signal is asynchronous relative to CLK for the burst mode.
VSS Device ground
NC Pin not connected internally
Ready/Busy output and open drain. When RY/BY# = VOH, the device is ready to accept read operations and
RY/BY# commands. When RY/BY# = VOL, the device is either executing an embedded algorithm or the device is executing a
hardware reset operation.
Clock Input that can be tied to the system or microprocessor clock and provides the fundamental timing and internal
CLK
operating frequency.

n
ig
ADV# Load Burst Address input. Indicates that the valid address is present on the address inputs.
IND# End of burst indicator for finite bursts only. IND is low when the last word in the burst sequence is at the data outputs.

es
WAIT# Provides data valid feedback only when the burst length is set to continuous.

D
Write Protect input. When WP# = VOL, the two outermost bootblock sector in the 75% bank are write protected
WP#
regardless of other sector protection configurations.

ew
Acceleration input. When taken to 12 V, program and erase operations are accelerated. When not used for
ACC
acceleration, ACC = VSS to VCC. rN
VIO (VCCQ) Output Buffer Power Supply (1.65 V to 2.75 V)
VCC Chip Power Supply (2.5 V to 2.75 V) or (3.00 V to 3.60 V)
fo

RESET# Hardware reset input

d

MCH Must Connect High (to VCC)

de
en

10. Logic Symbols

m
om

10.1 S29CD032G
ec

20
A0–A19 32
R

DQ0–DQ31
CLK
ot
N

CE#

OE#

WE#
IND/WAIT#
RESET#

ADV# RY/BY#
ACC

WP#

VIO (VCCQ)

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 S29CD032G
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10.2 S29CD016G

19
A0–A18 32
DQ0–DQ31
CLK
CE#

OE#

WE#
IND/WAIT#
RESET#

n
ADV# RY/BY#

ig
ACC

es
WP#

D
VIO (VCCQ)

ew
rN
fo
d
de
en
m
om
ec
R
ot
N

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11. Memory Map and Sector Protect Groups

The following tables lists the address ranges for all sectors and sector groups, and the sector sizes.

Table 11.1.32 Mb Memory Map and Sector Protect Groups for Ordering Option 00, Top Boot
Sector x32 Sector Sector x32 Sector
Sector Group Address Range Size Sector Group Address Range Size
(Note 4) (A19:A0) (KDwords) (Note 4) (A19:A0) (KDwords)
Bank 0, Small Bank (Note 2) Bank 1, Large Bank (Note 2)
SA0 (Note 1) SG0 00000h–007FFh 2 SA39 80000h–83FFFh 16
SA1 SG1 00800h–00FFFh 2 SA40 84000h–87FFFh 16
SG16
SA2 SG2 01000h–017FFh 2 SA41 88000h–8BFFFh 16
SA3 SG3 01800h–01FFFh 2 SA42 8C000h–8FFFFh 16
SA4 SG4 02000h–027FFh 2 SA43 90000h–93FFFh 16
SA5 SG5 02800h–02FFFh 2 SA44 94000h–97FFFh 16

n
SG17

ig
SA6 SG6 03000h–037FFh 2 SA45 98000h–9BFFFh 16
SA7 SG7 03800h–03FFFh 2 SA46 9C000h–9FFFFh 16

es
SA8 04000h–07FFFh 16 SA47 A0000h–A3FFFh 16

D
SA9 SG8 08000h–0BFFFh 16 SA48 A4000h–A7FFFh 16
SG18
SA10 0C000h–0FFFFh 16 SA49 A8000h–ABFFFh 16

ew
SA11 10000h–13FFFh 16 SA50 AC000h–AFFFFh 16
SA12 14000h–17FFFh 16 SA51 rN B0000h–B3FFFh 16
SG9
SA13 18000h–1BFFFh 16 SA52 B4000h–B7FFFh 16
SG19
SA14 1C000h–1FFFFh 16 SA53 B8000h–BBFFFh 16
fo

SA15 20000h–23FFFh 16 SA54 BC000h–BFFFFh 16

d

SA16 24000h–27FFFh 16 SA55 C0000h–C3FFFh 16

SG10
de

SA17 28000h–2BFFFh 16 SA56 C4000h–C7FFFh 16

SG20
SA18 2C000h–2FFFFh 16 SA57 C8000h–CBFFFh 16
en

SA19 30000h–33FFFh 16 SA58 CC000h–CFFFFh 16

SA20 34000h–37FFFh 16 SA59 D0000h–D3FFFh 16
m

SG11
SA21 38000h–3BFFFh 16 SA60 D4000h–D7FFFh 16
om

SG21
SA22 3C000h–3FFFFh 16 SA61 D8000h–DBFFFh 16
Bank 1, Large Bank (Note 2) SA62 DC000h–DFFFFh 16
ec

SA23 40000h–43FFFh 16 SA63 E0000h–E3FFFh 16

SA24 44000h–47FFFh 16 SA64 E4000h–E7FFFh 16
R

SG12 SG22
SA25 48000h–4BFFFh 16 SA65 E8000h–EBFFFh 16
ot

SA26 4C000h–4FFFFh 16 SA66 EC000h–EFFFFh 16

N

SA27 50000h–53FFFh 16 SA67 F0000h–F3FFFh 16

SA28 54000h–57FFFh 16 SA68 SG23 F4000h–F7FFFh 16
SG13
SA29 58000h–5BFFFh 16 SA69 F8000h–FBFFFh 16
SA30 5C000h–5FFFFh 16 SA70 SG24 FC000h–FC7FFh 2
SA31 60000h–63FFFh 16 SA71 SG25 FC800h–FCFFFh 2
SA32 64000h–67FFFh 16 SA72 SG26 FD000h–FD7FFh 2
SG14
SA33 68000h–6BFFFh 16 SA73 SG27 FD800h–FDFFFh 2
SA34 6C000h–6FFFFh 16 SA74 SG28 FE000h–FE7FFh 2
SA35 70000h–73FFFh 16 SA75 SG29 FE800h–FEFFFh 2
SA36 74000h–77FFFh 16 SA76 (Note 3) SG30 FF000h–FF7FFh 2
SG15
SA37 78000h–7BFFFh 16 SA77 (Note 3) SG31 FF800h–FFFFFh 2
SA38 7C000h–7FFFFh 16

Notes
1. Secured Silicon Sector overlays this sector when enabled.
2. The bank address is determined by A19 and A18. BA = 00 for Bank 0 and BA = 01, 10, or 11 for Bank 1.
3. This sector has the additional WP# pin sector protection feature.
4. Sector groups are for Sector Protection.

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Table 11.2.32 Mb Memory Map and Sector Protect Groups for Ordering Option 01, Bottom Boot
Sector x32 Sector Sector x32 Sector
Sector Group Address Range Size Sector Group Address Range Size
(Note 4) (A19:A0) (KDwords) (Note 4) (A19:A0) (KDwords)
Bank 0, Large Bank (Note 2) Bank 0, Large Bank (Note 2)
SA0 (Note 1) SG0 00000h–007FFh 2 SA43 90000h–93FFFh 16
SA1 (Note 1) SG1 00800h–00FFFh 2 SA44 94000h–97FFFh 16
SG17
SA2 SG2 01000h–017FFh 2 SA45 98000h–9BFFFh 16
SA3 SG3 01800h–01FFFh 2 SA46 9C000h–9FFFFh 16
SA4 SG4 02000h–027FFh 2 SA47 A0000h–A3FFFh 16
SA5 SG5 02800h–02FFFh 2 SA48 A4000h–A7FFFh 16
SG18
SA6 SG6 03000h–037FFh 2 SA49 A8000h–ABFFFh 16
SA7 SG7 03800h–03FFFh 2 SA50 AC000h–AFFFFh 16

n
SA8 04000h–07FFFh 16 SA51 B0000h–B3FFFh 16

ig
SA9 SG8 08000h–0BFFFh 16 SA52 B4000h–B7FFFh 16
SG19

es
SA10 0C000h–0FFFFh 16 SA53 B8000h–BBFFFh 16
SA11 10000h–13FFFh 16 SA54 BC000h–BFFFFh 16

D
SA12 14000h–17FFFh 16 Bank 1, Small Bank (Note 2)
SG9
SA13 18000h–1BFFFh 16 SA55 C0000h–C3FFFh 16

ew
SA14 1C000h–1FFFFh 16 SA56 C4000h–C7FFFh 16
SG20
SA15 20000h–23FFFh 16 SA57 rN C8000h–CBFFFh 16
SA16 24000h–27FFFh 16 SA58 CC000h–CFFFFh 16
SG10
SA17 28000h–2BFFFh 16 SA59 D0000h–D3FFFh 16
fo

SA18 2C000h–2FFFFh 16 SA60 D4000h–D7FFFh 16

SG21
d

SA19 30000h–33FFFh 16 SA61 D8000h–DBFFFh 16

de

SA20 34000h–37FFFh 16 SA62 DC000h–DFFFFh 16

SG11
SA21 38000h–3BFFFh 16 SA63 E0000h–E3FFFh 16
en

SA22 3C000h–3FFFFh 16 SA64 E4000h–E7FFFh 16

SG22
m

SA23 40000h–43FFFh 16 SA65 E8000h–EBFFFh 16

SA24 44000h–47FFFh 16 SA66 EC000h–EFFFFh 16
om

SG12
SA25 48000h–4BFFFh 16 SA67 F0000h–F3FFFh 16
SA26 4C000h–4FFFFh 16 SA68 SG23 F4000h–F7FFFh 16
ec

SA27 50000h–53FFFh 16 SA69 F8000h–FBFFFh 16

R

SA28 54000h–57FFFh 16 SA70 SG24 FC000h–FC7FFh 2

SG13
SA29 58000h–5BFFFh 16 SA71 SG25 FC800h–FCFFFh 2
ot

SA30 5C000h–5FFFFh 16 SA72 SG26 FD000h–FD7FFh 2

N

SA31 60000h–63FFFh 16 SA73 SG27 FD800h–FDFFFh 2

SA32 SG14 64000h–67FFFh 16 SA74 SG28 FE000h–FE7FFh 2
SA33 68000h–6BFFFh 16 SA75 SG29 FE800h–FEFFFh 2
SA35 70000h–73FFFh 16 SA76 SG30 FF000h–FF7FFh 2
SA36 74000h–77FFFh 16 SA77 (Note 3) SG31 FF800h–FFFFFh 2
SG15
SA37 78000h–7BFFFh 16
SA38 7C000h–7FFFFh 16
SA39 80000h–83FFFh 16
SA40 84000h–87FFFh 16
SG16
SA41 88000h–8BFFFh 16
SA42 8C000h–8FFFFh 16

Notes
1. This sector has the additional WP# pin sector protection feature.
2. The bank address is determined by A19 and A18. BA = 00, 01, or 10 for Bank 0 and BA = 11 for Bank 1.
3. Secured Silicon Sector overlays this sector when enabled.
4. Sector groups are for Sector Protection.

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Table 11.3.16 Mb, Memory Map and Sector Protect Groups for Ordering Option 00, Top Boot
x32 x32
Sector Sector Size Sector Sector Size
Sector Address Range Sector Address Range
Group (KDwords) Group (KDwords)
(A18:A0) (A18:A0)
Bank 0, Small Bank (Note 2) Bank 1, Large Bank (Note 2)
SA0 (Note 1) SG0 00000h–007FFh 2 SA15 20000h–23FFFh 16
SA1 SG1 00800h–00FFFh 2 SA16 24000h–27FFFh 16
SG10
SA2 SG2 01000h–017FFh 2 SA17 28000h–2BFFFh 16
SA3 SG3 01800h–01FFFh 2 SA18 2C000h–2FFFFh 16
SA4 SG4 02000h–027FFh 2 SA19 30000h–33FFFh 16
SA5 SG5 02800h–02FFFh 2 SA20 34000h–37FFFh 16
SG11
SA6 SG6 03000h–037FFh 2 SA21 38000h–3BFFFh 16
SA7 SG7 03800h–03FFFh 2 SA22 3C000h–3FFFFh 16

n
SA8 04000h–07FFFh 16 SA23 40000h–43FFFh 16

ig
SA9 SG8 08000h–0BFFFh 16 SA24 44000h–47FFFh 16
SG12

es
SA10 0C000h–0FFFFh 16 SA25 48000h–4BFFFh 16
SA11 10000h–13FFFh 16 SA26 4C000h–4FFFFh 16

D
SA12 14000h–17FFFh 16 SA27 50000h–53FFFh 16
SG9
SA13 18000h–1BFFFh 16 SA28 54000h–57FFFh 16

ew
SG13
SA14 1C000h–1FFFFh 16 SA29 58000h–5BFFFh 16
SA30 rN 5C000h–5FFFFh 16
SA31 60000h–63FFFh 16
SA32 64000h–67FFFh 16
fo
SG14
SA33 68000h–6BFFFh 16
d

SA34 6C000h–6FFFFh 16
de

SA35 70000h–73FFFh 16
SA36 SG15 74000h–77FFFh 16
en

SA37 78000h–7BFFFh 16
m

SA38 SG16 7C000h–7C7FFh 2

SA39 SG17 7C800h–7CFFFh 2
om

SA40 SG18 7D000h–7D7FFh 2

SA41 SG19 7D800h–7DFFFh 2
ec

SA42 SG20 7E000h–7E7FFh 2

R

SA43 SG21 7E800h–7EFFFh 2

SA44 (Note 2) SG22 7F000h–7F7FFh 2
ot

SA45 (Note 2) SG23 7F800h–7FFFFh 2

N

Notes
1. Secured Silicon Sector overlays this sector when enabled.
2. The bank address is determined by A18 and A17. BA = 00 for Bank 1 and BA = 01, 10, or 11 for Bank 2.
3. This sector has the additional WP# pin sector protection feature.
4. Sector groups are for Sector Protection.

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Table 11.4.16 Mb, Memory Map and Sector Protect Groups for Ordering Option 00, Bottom Boot
Sector x32 Sector Sector x32 Sector
Sector Group Address Range Size Sector Group Address Range Size
(Note 4) (A19:A0) (KDwords) (Note 4) (A19:A0) (KDwords)
Bank 0, Large Bank (Note 2) Bank 1, Small Bank (Note 2)
SA0 (Note 1) SG0 00000h–007FFh 2 SA35 70000h–73FFFh 16
SA1 (Note 1) SG1 00800h–00FFFh 2 SA36 SG15 74000h–77FFFh 16
SA2 SG2 01000h–017FFh 2 SA37 78000h–7BFFFh 16
SA3 SG3 01800h–01FFFh 2 SA38 SG16 7C000h–7C7FFh 2
SA4 SG4 02000h–027FFh 2 SA39 SG17 7C800h–7CFFFh 2
SA5 SG5 02800h–02FFFh 2 SA40 SG18 7D000h–7D7FFh 2
SA6 SG6 03000h–037FFh 2 SA41 SG19 7D800h–7DFFFh 2
SA7 SG7 03800h–03FFFh 2 SA42 SG20 7E000h–7E7FFh 2

n
SA8 04000h–07FFFh 16 SA43 SG21 7E800h–7EFFFh 2

ig
SA9 SG8 08000h–0BFFFh 16 SA44 SG22 7F000h–7F7FFh 2

es
SA10 0C000h–0FFFFh 16 SA45 SG23 7F800h–7FFFFh 2
SA11 10000h–13FFFh 16

D
SA12 14000h–17FFFh 16
SG9
SA13 18000h–1BFFFh 16

ew
SA14 1C000h–1FFFFh 16
SA15 20000h–23FFFh 16 rN
SA16 24000h–27FFFh 16
SG10
SA17 28000h–2BFFFh 16
fo

SA18 2C000h–2FFFFh 16
d

SA19 30000h–33FFFh 16
de

SA20 34000h–37FFFh 16
SG11
SA21 38000h–3BFFFh 16
en

SA22 3C000h–3FFFFh 16
m

SA23 40000h–43FFFh 16
SA24 44000h–47FFFh 16
om

SG12
SA25 48000h–4BFFFh 16
SA26 4C000h–4FFFFh 16
ec

SA27 50000h–53FFFh 16
R

SA28 54000h–57FFFh 16
SG13
SA29 58000h–5BFFFh 16
ot

SA30 5C000h–5FFFFh 16
N

SA31 60000h–63FFFh 16
SA32 64000h–67FFFh 16
SG14
SA33 68000h–6BFFFh 16
SA34 6C000h–6FFFFh 16

Notes
1. This sector has the additional WP# pin sector protection feature.
2. The bank address is determined by A18 and A17. BA = 00 for Bank 1 and BA = 01, 10, or 11 for Bank 2.
3. Secured Silicon Sector overlays this sector when enabled.
4. Sector groups are for Sector Protection.

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12. Device Operations

This section describes the requirements and use of the device bus operations, which are initiated through the internal command
register. The command register itself does not occupy any addressable memory location. The register is composed of latches that
store the commands, along with the address and data information needed to execute the command. The contents of the register
serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Table 12.1 lists the device
bus operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these
operations in further detail.

Table 12.1 Device Bus Operation

Data
Operation CE# OE# WE# RESET# CLK ADV# Addresses
(DQ0–DQ31)
Read L L H H X X AIN DOUT
Asynchronous Write L H L H X X AIN DIN

n
Synchronous Write L H L H AIN DIN

ig
Standby (CE#) H X X H X X X HIGH Z

es
Output Disable L H H H X X HIGH Z HIGH Z
Reset X X X L X X X HIGH Z

D
00000001h, (protected)
Sector Address,

ew
A6 = H
PPB Protection Status (Note 2) L L H H X X A9 = VID,
A7 – A0 = 02h 00000000h (unprotect)
rN A6 = L
Burst Read Operations
fo
Load Starting Burst Address L X H H AIN X
d

Advance Burst to next address

with appropriate Data presented L L H H H X Burst Data Out
de

on the Data bus

Terminate Current Burst
en

H X H H X X HIGH Z
Read Cycle
m

Terminate Current Burst

X X H L X X X HIGH Z
Read Cycle with RESET#
om

Terminate Current Burst

Read Cycle; L H H H AIN X
Start New Burst Read Cycle
ec

Legend
R

L = Logic Low = VIL

H = Logic High = VIH
ot

X = Don’t care.
N

Notes
1. WP# controls the two outermost sectors of the top boot block or the two outermost sectors of the bottom boot block.
2. DQ0 reflects the sector PPB (or sector group PPB) and DQ1 reflects the DYB

12.1 VersatileI/O™ (VIO) Control

The VersatileI/O (VIO) control allows the host system to set the voltage levels that the device generates at its data outputs and the
voltages tolerated at its data inputs to the same voltage level that is asserted on the VIO pin.
The output voltage generated on the device is determined based on the VIO (VCCQ) level. For the 2.6 V VCC Mask Option, a VIO of
1.65 V – 1.95 V allows the device to interface with I/Os lower than 2.5 V. Vcc = VIO (2.5 V to 2.75V) make the device appear as a 2.5
V only.

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12.2 Requirements for Reading Array Data

To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power control and selects the
device. OE# is the output control and gates array data to the output pins. WE# should remain at VIH.
The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no
spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array
data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the
device data outputs. The device remains enabled for read access until the command register contents are altered.
Address access time (tACC) is the delay from stable addresses to valid output data. The chip enable access time (tCE) is the delay
from stable addresses and stable CE# to valid data at the output pins. The output enable access time (tOE) is the delay from the
falling edge of OE# to valid data at the output pins (assuming the addresses were stable for at least tACC–tOE time and CE# is
asserted for at least tCE–tOE time).
See Reading Array Data in Non-burst Mode on page 37 and Reading Array Data in Burst Mode on page 37 for more information.
Refer to Asynchronous Read Operations on page 60 for timing specifications and to Figure 24.2 on page 61 for the timing diagram.

n
ICC1 in DC Characteristics on page 57 represents the active current specification for reading array data.

ig
es
12.3 Simultaneous Read/Write Operations Overview

D
ew
12.3.1 Overview
The Simultaneous Read/Write feature allows embedded program or embedded erase operation to be executed in the Small Bank,
rN
while reading from the Large Bank. The opposite case is not valid.
fo
Table 12.1 Allowable Conditions for Simultaneous Operation
d

Small Bank Large Bank

de

Embedded Erase Burst (Synchronous) Read or Asynchronous Read

Embedded Program Burst (Synchronous) Read or Asynchronous Read
en

Note
Please refer to the Memory Map Table 11.1 on page 15, Table 11.2 on page 16, Table 11.3 on page 17, and Table 11.4 on page 18 for Small and Large Bank
m

assignments.
om

12.3.2 Program/Erase Suspend and Simultaneous Operation

ec

There is no restriction to implementing a program-suspend or erase-suspend during a simultaneous operation.

R
ot

12.3.3 Common Flash Interface (CFI) and Password Program/Verify and Simultaneous
Operation
N

Simultaneous read/write operation is disabled during the CFI and Password Program/Verify operation, including PPB program/erase
and unlocking a password operation. Only array data can be read in the Large Bank during a simultaneous operation.

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12.4 Writing Commands/Command Sequences

To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the
system must drive WE# and CE# to VIL, and OE# to VIH.
The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the Unlock Bypass mode,
only two write cycles are required to program a word or byte, instead of four. See Sector Erase and Program Suspend Command
on page 42 for details on programming data to the device using both standard and Unlock Bypass command sequences.
An erase operation can erase one sector, multiple sectors, or the entire device. Table 11.1 on page 15 to Table 11.4 on page 18
indicate the address space that each sector occupies. A sector address consists of the address bits required to uniquely select a
sector. See Command Definitions on page 37 for details on erasing a sector or the entire chip, or suspending/resuming the erase
operation.
When in Synchronous read mode configuration, the device is able to perform both asynchronous and synchronous write operations.
CLK and ADV# address latch is supported in synchronous programming mode. During a synchronous write operation, to write a
command or command sequence, (which includes programming data to the device and erasing sectors of memory), the system

n
must drive ADV# and CE# to VIL, and OE# to VIH when providing an address to the device, and drive WE# and CE# to VIL, and

ig
CE# to VIH, when writing commands or data.

es
D
12.4.1 Accelerated Program and Erase Operations
The device offers accelerated program/erase operations through the ACC pin. When the system asserts VHH (12V) on the ACC pin,

ew
the device automatically enters the Unlock Bypass mode. The system may then write the two-cycle Unlock Bypass program
command sequence to do accelerated programming. The device uses the higher voltage on the ACC pin to accelerate the
rN
operation. A sector that is being protected with the WP# pin is protected during accelerated program or Erase.
fo
Note
The ACC pin must not be at VHH during any operation other than accelerated programming, or device damage can result.
d
de

12.4.2 Autoselect Functions

en

If the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read
autoselect codes from the internal register (which is separate from the memory array) on DQ7–DQ0. Standard read cycle timings
m

apply in this mode. See Autoselect Mode on page 22 and Autoselect Command on page 38 for more information.
om

12.5 Automatic Sleep Mode (ASM)

ec

The automatic sleep mode minimizes Flash device energy consumption. While in asynchronous mode, the device automatically
R

enables this mode when addresses remain stable for tACC + 60 ns. The automatic sleep mode is independent of the CE#, WE# and
OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output
ot

data is latched and always available to the system. While in synchronous mode, the device automatically enables this mode when
N

either the first active CLK level is greater than tACC or the CLK runs slower than 5 MHz. Note that a new burst operation is required
to provide new data.
ICC8 in DC Characteristics on page 57 represents the automatic sleep mode current specification.

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12.5.1 Standby Mode

When the system is not responding or writing to the device, it can place the device in the standby mode. In this mode, current
consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input.
The device enters the CMOS standby mode when the CE# and RESET# inputs are both held at Vcc 0.2 V. The device requires
standard access time (tCE) for read access, before it is ready to read data.
If the device is deselected during erasure or programming, the device draws active current until the operation is completed.
ICC5 in DC Characteristics on page 57 represents the standby current specification.
Caution: entering the standby mode via the RESET# pin also resets the device to the read mode and floats the data I/O pins.
Furthermore, entering ICC7 during a program or erase operation leaves erroneous data in the address locations being operated on at
the time of the RESET# pulse. These locations require updating after the device resumes standard operations. See RESET#:
Hardware Reset Pin on page 22 for further discussion of the RESET# pin and its functions.

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12.6 RESET#: Hardware Reset Pin

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The RESET# pin is an active low signal that is used to reset the device under any circumstances. A logic 0 on this pin forces the

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device out of any mode that is currently executing back to the reset state. The RESET# pin may be tied to the system reset circuitry.

D
A system reset would thus also reset the device. To avoid a potential bus contention during a system reset, the device is isolated
from the DQ data bus by tristating the data output pins for the duration of the RESET pulse. All pins are don’t cares during the reset

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operation.
If RESET# is asserted during a program or erase operation, the RY/BY# pin remains low until the reset operation is internally
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complete. This action requires between 1 µs and 7µs for either Chip Erase or Sector Erase. The RY/BY# pin can be used to
determine when the reset operation is complete. Otherwise, allow for the maximum reset time of 11 µs. If RESET# is asserted when
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a program or erase operation is not executing (RY/BY# = 1), the reset operation completes within 500 ns. The Simultaneous Read/
Write feature of this device allows the user to read a bank after 500 ns if the bank was in the read/reset mode at the time RESET#
d

was asserted. If one of the banks was in the middle of either a program or erase operation when RESET# was asserted, the user
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must wait 11 µs before accessing that bank.

en

Asserting RESET# during a program or erase operation leaves erroneous data stored in the address locations being operated on at
the time of device reset. These locations need updating after the reset operation is complete. See Figure 24.6 on page 65 for timing
m

specifications.
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Asserting RESET# active during VCC and VIO power up is required to guarantee proper device initialization until VCC and VIO
reaches steady state voltages.
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12.7 Output Disable Mode

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See Table 12.1 on page 19 Device Bus Operation for OE# Operation in Output Disable Mode.
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12.8 Autoselect Mode

The autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes
output on DQ7–DQ0. This mode is primarily intended for programming equipment to automatically match a device to be
programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system
through the command register.
When using programming equipment, the autoselect mode requires VID on address pin A9. Address pins A6, A1, and A0 must be as
shown in Table 11.2 on page 16 (top boot devices) or Table 11.3 on page 17 (bottom boot devices). In addition, when verifying
sector protection, the sector address must appear on the appropriate highest order address bits (see Table 11.1 on page 15 through
Table 11.4 on page 18). Table 12.3 on page 23 shows the remaining address bits that are don’t care. When all necessary bits are
set as required, the programming equipment may then read the corresponding identifier code on DQ7–DQ0.
To access the autoselect codes in-system, the host system can issue the autoselect command via the command. This method does
not require VID. See Command Definitions on page 37 for details on using the autoselect mode.

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Table 12.3 S29CD-G Flash Family Autoselect Codes (High Voltage Method)
A19 A5 DQ7
Description CE# OE# WE# to A10 A9 A8 A7 A6 to A3 A2 A1 A0 to
A11 A4 DQ0
Manufacturer ID: Spansion L L H X X VID X X L X X X L L 0001h
Read Cycle 1 L L H X X VID X L L X L L L H 007Eh
Autoselect Device Code

Read Cycle 2 VID 0036h (16Mb)

L L H X X X L L L H H H L
0009h (32Mb)
0000h
Ordering Option 00
Read Cycle 3 L L H X X VID X L L L H H H H
0001h
Ordering Option 01
0000h (unprotected)
PPB Protection Status L L H SA X VID X L L L L L H L
0001h (protected)

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ig
Legend
L = Logic Low = VIL

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H = Logic High = VIH
SA = Sector Address

D
X = Don’t care

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Note
The autoselect codes can also be accessed in-system via command sequences. See Table 15.1 on page 43 and Table 15. 3 on page 50.
rN
12.9 Asynchronous Read Operation (Non-Burst)
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The device has two control functions which must be satisfied in order to obtain data at the outputs. CE# is the power control and is
used for device selection. OE# is the output control and is used to gate data to the output pins if the device is selected. The device is
d

powered-up in an asynchronous read mode. In the asynchronous mode the device has two control functions which must be satisfied
de

in order to obtain data at the outputs. CE# is the power control and is used for device selection. OE# is the output control and is used
en

to gate data to the output pins if the device is selected.

Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable access time (tCE) is the
m

delay from the stable addresses and stable CE# to valid data at the output pins. The output enable access time is the delay from the
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falling edge of OE# to valid data at the output pins (assuming the addresses are stable for at least tACC–tOE time).
ec

Figure 12.1 Asynchronous Read Operation

R

CE#
ot

CLK
N

ADV#

Addresses Address 0 Address 1 Address 2 Address 3

Data D0 D1 D2 D3 D3

OE#
WE#
VIH

Float Float
IND/WAIT# VOH
Note
Operation is shown for the 32-bit data bus. For the 16-bit data bus, A-1 is required.

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12.10 Synchronous (Burst) Read Operation

The device is capable of performing burst read operations to improve total system data throughput. The 2, 4, and 8 double word
accesses are configurable as linear burst accesses. All burst operations provide wrap around linear burst accesses. Additional
options for all burst modes include initial access delay configurations (2–16 CLKs) Device configuration for burst mode operation is
accomplished by writing the Configuration Register with the desired burst configuration information. Once the Configuration Register
is written to enable burst mode operation, all subsequent reads from the array are returned using the burst mode protocols. Like the
main memory access, the Secured Silicon Sector memory is accessed with the same burst or asynchronous timing as defined in the
Configuration Register. However, the user must recognize burst operations past the 256 byte Secured Silicon boundary returns
invalid data.
Burst read operations occur only to the main flash memory arrays. The Configuration Register and protection bits are treated as
single cycle reads, even when burst mode is enabled. Read operations to these locations results in the data remaining valid while
OE# is at VIL, regardless of the number of CLK cycles applied to the device.

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12.11 Linear Burst Read Operations

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Linear burst read mode reads either 2, 4, or 8 double words (1 double word = 32 bits). (See Table 12.4 for all valid burst output

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sequences). The IND/WAIT# pin transitions active (VIL) during the last transfer of data during a linear burst read before a wrap
around, indicating that the system should initiate another ADV# to start the next burst access. If the system continues to clock the

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device, the next access wraps around to the starting address of the previous burst access. The IND/WAIT# signal remains inactive

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(floating) when not active. See Table 12.4 for a complete 32 data bus interface order.

Table 12.4 32- Bit Linear and Burst Data Order

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Data Transfer Sequence (Independent of the WORD# pin) Output Data Sequence (Initial Access Address)
fo
0-1 (A0 = 0)
Two Linear Data Transfers
1-0 (A0 = 1)
d
de

0-1-2-3 (A0:A-1/A1-A0 = 00)

1-2-3-0 (A0:A-1/A1-A0 = 01)
Four Linear Data Transfers
en

2-3-0-1 (A:A-1/A1-A0 = 10)

3-0-1-2 (A0:A-1/A1-A0 = 11)
m

0-1-2-3-4-5-6-7 (A1:A-1A2-A0 = 000)

om

1-2-3-4-5-6-7-0 (A1:A-1/A2-A0 = 001)

2-3-4-5-6-7-0-1 (A1:A-1/A2-A0 = 010)
ec

3-4-5-6-7-0-1-2 (A1:A-1/A2-A0 = 011)

Eight Linear Data Transfers
4-5-6-7-0-1-2-3 (A1:A-1/A2-A0 = 100)
R

5-6-7-0-1-2-3-4 (A1:A-1/A2-A0 = 101)

ot

6-7-0-1-2-3-4-5 (A1:A-1/A2-A0 = 110)

7-0-1-2-3-4-5-6 (A1:A-1/A2-A0 = 111)
N

12.11.1 CE# Control in Linear Mode

The CE# (Chip Enable) pin enables the device during read mode operations. CE# must meet the required burst read setup times for
burst cycle initiation. If CE# is taken to VIH at any time during the burst linear or burst cycle, the device immediately exits the burst
sequence and floats the DQ bus signal. Restarting a burst cycle is accomplished by taking CE# and ADV# to VIL.

12.11.2 ADV# Control In Linear Mode

The ADV# (Address Valid) pin is used to initiate a linear burst cycle at the clock edge when CE# and ADV# are at VIL and the device
is configured for either linear burst mode operation. A burst access is initiated and the address is latched on the first rising CLK edge
when ADV# is active or upon a rising ADV# edge, whichever occurs first. If the ADV# signal is taken to VIL prior to the end of a linear
burst sequence, the previous address is discarded and subsequent burst transfers are invalid until ADV# transitions to VIH before a
clock edge, which initiates a new burst sequence.

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12.11.3 RESET# Control in Linear Mode

The RESET# pin immediately halts the linear burst access when taken to VIL. The DQ data bus signal float. Additionally, the
Configuration Register contents are reset back to the default condition where the device is placed in asynchronous access mode.

12.11.4 OE# Control in Linear Mode

The OE# (Output Enable) pin is used to enable the linear burst data on the DQ data bus pin. De-asserting the OE# pin to VIH during
a burst operation floats the data bus. However, the device continues to operate internally as if the burst sequence continues until the
linear burst is complete. The OE# pin does not halt the burst sequence, this is accomplished by either taking CE# to VIH or re-issuing
a new ADV# pulse. The DQ bus remains in the float state until OE# is taken to VIL.

12.11.5 IND/WAIT# Operation in Linear Mode

The IND/WAIT#, or End of Burst Indicator signal (when in linear modes), informs the system that the last address of a burst

n
sequence is on the DQ data bus. For example, if a 2-double-word linear burst access is enabled using a 16-bit DQ bus (WORD# =

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VIL), the IND/WAIT# signal transitions active on the second access. If the same scenario is used, the IND/WAIT# signal has the
same delay and setup timing as the DQ pins. Also, the IND/WAIT# signal is controlled by the OE# signal. If OE# is at VIH, the IND/

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WAIT# signal floats and is not driven. If OE# is at VIL, the IND/WAIT# signal is driven at VIH until it transitions to VIL indicating the

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end of burst sequence. The IND/WAIT# signal timing and duration is (See Configuration Register on page 27 for more information).
The following table lists the valid combinations of the Configuration Register bits that impact the IND/WAIT# timing.

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Table 12.5. Valid Configuration Register Bit Definition for IND/WAIT#
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DOC WC CC Definition
0 0 1 IND/WAIT# = VIL for 1-CLK cycle, Active on last transfer, Driven on rising CLD edge
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0 1 1 IND/WAIT# = VIL for 1-CLK cycle, Active on second to last transfer, Driven on rising CLK edge
d
de
en

Figure 12.2 End of Burst Indicator (IND/WAIT#) Timing for Linear 8-Word Burst Operation
m

VIH
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CE# VIL
ec

CLK
R

3 Clock Delay
ot

ADV# Address 1 Latched

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Addresses Address 1 Address 2

Data Invalid D1 D2 D3 D0

OE#

IND/WAIT#
Note
Operation is shown for the 32-bit data bus. Figure shown with 3-CLK initial access delay configuration, linear address, 4-double-word burst, output on rising CLD edge,
data hold for 1-CLK, IND/WAIT# asserted on the last transfer before wrap-around.

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12.11.6 Burst Access Timing Control

In addition to the IND/WAIT# signal control, burst controls exist in the Control Register for initial access delay, delivery of data on the
CLK edge, and the length of time data is held.

12.11.7 Initial Burst Access Delay Control

The device contains options for initial access delay of a burst access. The initial access delay has no effect on asynchronous read
operations.
Burst Initial Access Delay is defined as the number of clock cycles that must elapse from the first valid clock edge after ADV#
assertion (or the rising edge of ADV#) until the first valid CLK edge when the data is valid.
The burst access is initiated and the address is latched on the first rising CLK edge when ADV# is active or upon a rising ADV#
edge, whichever comes first. (Table 12.6 describes the initial access delay configurations.)

Table 12.6.Burst Initial Access Delay

n
ig
Initial Burst Access (CLK cycles)

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CR13 CR12 CR11 CR10 40 MHz (0J), 56 MHz (0M), 66 MHz (0P),
75 MHz (0R, 32 Mb only)

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0 0 0 0 2

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0 0 0 1 3
0 0 1 0 4
0 0 1 1
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0 1 0 0 6
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0 1 0 1 7
0 1 1 0
d

8
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0 1 1 1 9
en
m

Figure 12.3 Initial Burst Delay Control

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1st CLK 2nd CLK 3rd CLK 4th CLK 5th CLK
CLK
ec

ADV#
R

Address 1 Latched

Addresses
ot

Valid Address
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Three CLK Delay

DQ31-DQ03 D0 D1 D2 D3 D4
Four CLK Delay
DQ31-DQ04 D0 D1 D2 D3

Five CLK Delay

DQ31-DQ05 D0 D1 D2

Notes
1. Burst access starts with a rising CLK edge and when ADV# is active.
2. Configurations register 6 is always set to 1 (CR6 = 1). Burst starts and data outputs on the rising CLK edge.
3. CR [13-10] = 1 or three clock cycles
4. CR [13-10] = 2 or four clock cycles
5. CR [13-10] = 3 or five clock cycles

12.11.8 Burst CLK Edge Data Delivery

The device delivers data on the rising of CLK. Bit 6 in the Control Register (CR6) is set to 1, and is the default configuration.

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12.11.9 Burst Data Hold Control

The device is capable of holding data for one CLKs. The default configuration is to hold data for one CLK and is the only valid state.

12.11.10 Asserting RESET# During A Burst Access

If RESET# is asserted low during a burst access, the burst access is immediately terminated and the device defaults back to
asynchronous read mode. See Hardware Reset (RESET#) on page 64 for more information on the RESET# function.

12.12 Configuration Register

The device contains a Configuration Register for configuring read accesses. The Configuration Register is accessed by the
Configuration Register Read and the Configuration Register Write commands. The Configuration Register does not occupy any
addressable memory location, but rather, is accessed by the Configuration Register commands. The Configuration Register is
readable any time, however, writing the Configuration Register is restricted to times when the Embedded Algorithm™ is not active. If

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the user attempts to write the Configuration Register while the Embedded Algorithm™ is active, the write operation is ignored and

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the contents of the Configuration Register remain unchanged.

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The Configuration Register is a 16 bit data field which is accessed by DQ15–DQ0. During a read operation, DQ31–DQ16 returns all
zeroes. Table 12.7 shows the Configuration Register. Also, Configuration Register reads operate the same as Autoselect command

D
reads. When the command is issued, the bank address is latched along with the command. Reads operations to the bank that was

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specified during the Configuration Register read command return Configuration Register contents. Read operations to the other
bank return flash memory data. Either bank address is permitted when writing the Configuration Register read command.
rN
fo
d
de
en
m
om
ec
R
ot
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Table 12.7 Configuration Register Definitions

CR15 CR14 CR13 CR12 CR11 CR10 CR9 CR8
RM ASD IAD3 IAD2 IAD1 IAD0 DOC WC

CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0

BS CC Reserved Reserved Reserved BL2 BL1 BL0

Configuration Register
CR15 = Read Mode (RM)
0 = Synchronous Burst Reads Enabled
1 = Asynchronous Reads Enabled (Default)
CR14 = Reserved for Future Enhancements
0 = ASM enable

n
1 = ASM disable

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CR13–CR10 = Automatic Sleep Mode Disable

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Speed Options 40, 56, and 66 MHz:
0000 = 2 CLK cycle initial burst access delay 0100 = 6 CLK cycle initial burst access delay

D
0001 = 3 CLK cycle initial burst access delay 0101 = 7 CLK cycle initial burst access delay
0010 = 4 CLK cycle initial burst access delay 0110 = 8 CLK cycle initial burst access delay

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0011 = 5 CLK cycle initial burst access delay 0111 = 9 CLK cycle initial burst access delay—Default
CR9 = Data Output Configuration (DOC) rN
0 = Hold Data for 1-CLK cycle—Default
1 = Reserved
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CR8 = IND/WAIT# Configuration (WC)
0 = IND/WAIT# Asserted During Delay—Default
d

1 = IND/WAIT# Asserted One Data Cycle Before Delay

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CR7 = Burst Sequence (BS)

0 = Reserved
en

1 = Linear Burst Order—Default

CR6 = Clock Configuration (CC)
m

0 = Reserved
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1 = Burst Starts and Data Output on Rising Clock Edge—Default

CR5–CR3 = Reserved For Future Enhancements (R)
ec

These bits are reserved for future use. Set these bits to 0.
CR2–CR0 = Burst Length (BL2–BL0)
R

000 = Reserved, burst accesses disabled (asynchronous reads only)

001 = 64 bit (8-byte) Burst Data Transfer - x32 Linear
ot

010 = 128 bit (16-byte) Burst Data Transfer - x32 Linear

011 = 256 bit (32-byte) Burst Data Transfer - x32 Linear (device default)
N

100 = Reserved, burst accesses disabled (asynchronous reads only)

101 = Reserved, burst accesses disabled (asynchronous reads only)
110 = Reserved, burst accesses disabled (asynchronous reads only)

Table 12.8 Configuration Register After Device Reset

CR15 CR14 CR13 CR12 CR11 CR10 CR9 CR8
RM Reserve IAD3 IAD2 IAD1 IAD0 DOC WC
1 0 0 1 1 1 0 0

CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0

BS CC Reserve Reserve Reserve BL2 BL1 BL0
1 1 0 0 0 1 0 0

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12.13 Initial Access Delay Configuration

The frequency configuration informs the device of the number of clocks that must elapse after ADV# is driven active before data is
available. This value is determined by the input clock frequency.

13. Sector Protection

The device features several levels of sector protection, which can disable both the program and erase operations in certain sectors
or sector groups

Sector and Sector Groups

The distinction between sectors and sector groups is fundamental to sector protection. Sector are individual sectors that can be
individually sector protected/unprotected. These are the outermost 4 Kword boot sectors, that is, SA0 to SA7 and SA70 to SA77.
See Table 13.1 on page 31 and Table 11.1 on page 15 to Table 11.4 on page 18.

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Sector groups are a collection of three or four adjacent 32 kword sectors. For example, sector group SG8 is comprised of sector SA8

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to SA10. When any sector in a sector group is protected/unprotected, every sector in that group is protection/unprotected. See
Table 13.1 on page 31 and Table 11.1 on page 15 to Table 11.4 on page 18.

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Persistent Sector Protection
A command sector protection method that replaces the old 12 V controlled protection method.

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Password Sector Protection rN
A highly sophisticated protection method that requires a password before changes to certain sectors or sector groups are permitted.
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WP# Hardware Protection
A write protect pin that can prevent program or erase to the two outermost 8 Kbytes sectors in the 75% bank.
d

All parts default to operate in the Persistent Sector Protection mode. The customer must then choose if the Persistent or Password
de

Protection method is most desirable. There are two one-time programmable non-volatile bits that define which sector protection
en

method is used. If the customer decides to continue using the Persistent Sector Protection method, they must set the Persistent
Sector Protection Mode Locking Bit. This permanently sets the part to operate only using Persistent Sector Protection. If the
m

customer decides to use the password method, they must set the Password Mode Locking Bit. This permanently sets the part to
operate only using password sector protection.
om

It is important to remember that setting either the Persistent Sector Protection Mode Locking Bit or the Password Mode
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Locking Bit permanently selects the protection mode. It is not possible to switch between the two methods once a locking bit is set.
It is important that one mode is explicitly selected when the device is first programmed, rather than relying on the default
R

mode alone. This is so that it is not possible for a system program or virus to later set the Password Mode Locking Bit, which would
cause an unexpected shift from the default Persistent Sector Protection Mode into the Password Protection Mode.
ot

The WP# Hardware Protection feature is always available, independent of the software managed protection method chosen.
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13.1 Persistent Sector Protection

The Persistent Sector Protection method replaces the old 12 V controlled protection method while at the same time enhancing
flexibility by providing three different sector protection states:
 Persistently Locked—A sector is protected and cannot be changed.
 Dynamically Locked—The sector is protected and can be changed by a simple command
 Unlocked—The sector is unprotected and can be changed by a simple command
In order to achieve these states, three types of bits are going to be used:

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13.1.1 Persistent Protection Bit (PPB)

A single Persistent (non-volatile) Protection Bit is assigned to a maximum of four sectors (see the sector address tables for specific
sector protection groupings). All 8 Kbyte boot-block sectors have individual sector Persistent Protection Bits (PPBs) for greater
flexibility. Each PPB is individually modifiable through the PPB Write Command.
Note
If a PPB requires erasure, all of the sector PPBs must first be preprogrammed prior to PPB erasing. All PPBs erase in parallel, unlike programming where individual PPBs
are programmable. It is the responsibility of the user to perform the preprogramming operation. Otherwise, an already erased sector PPBs has the potential of being over-
erased. There is no hardware mechanism to prevent sector PPBs over-erasure.

13.1.2 Persistent Protection Bit Lock (PPB Lock)

A global volatile bit. When set to 1, the PPBs cannot be changed. When cleared (0), the PPBs are changeable. There is only one
PPB Lock bit per device. The PPB Lock is cleared after power-up or hardware reset. There is no command sequence to unlock the
PPB Lock.

n
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13.1.3 Dynamic Protection Bit (DYB)

es
A volatile protection bit is assigned for each sector. After power-up or hardware reset, the contents of all DYBs is 0. Each DYB is
individually modifiable through the DYB Write Command.

D
When the parts are first shipped, the PPBs are cleared, the DYBs are cleared, and PPB Lock is defaulted to power up in the cleared

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state – meaning the PPBs are changeable.
When the device is first powered on the DYBs power up cleared (sectors not protected). The Protection State for each sector is
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determined by the logical OR of the PPB and the DYB related to that sector. For the sectors that have the PPBs cleared, the DYBs
control whether or not the sector is protected or unprotected. By issuing the DYB Write command sequences, the DYBs is set or
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cleared, thus placing each sector in the protected or unprotected state. These are the so-called Dynamic Locked or Unlocked
states. They are called dynamic states because it is very easy to switch back and forth between the protected and unprotected
d
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conditions. This allows software to easily protect sectors against inadvertent changes yet does not prevent the easy removal of
protection when changes are needed. The DYBs maybe set or cleared as often as needed.
en

The PPBs allow for a more static, and difficult to change, level of protection. The PPBs retain state across power cycles because
they are Non-Volatile. Individual PPBs are set with a command but must all be cleared as a group through a complex sequence of
m

program and erasing commands. The PPBs are limited to 100 erase cycles.
om

The PPB Lock bit adds an additional level of protection. Once all PPBs are programmed to the desired settings, the PPB Lock may
be set to 1. Setting the PPB Lock disables all program and erase commands to the Non-Volatile PPBs. In effect, the PPB Lock Bit
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locks the PPBs into the current state. The only way to clear the PPB Lock is to go through a power cycle. System boot code can
determine if any changes to the PPB are needed e.g. to allow new system code to be downloaded. If no changes are needed then
R

the boot code can set the PPB Lock to disable any further changes to the PPBs during system operation.
ot

The WP# write protect pin adds a final level of hardware protection to the two outermost 8 Kbytes sectors in the 75% bank. When
N

this pin is low it is not possible to change the contents of these two sectors.
It is possible to have sectors that have been persistently locked, and sectors that are left in the dynamic state. The sectors in the
dynamic state are all unprotected. If there is a need to protect some of them, a simple DYB Write command sequence is all that is
necessary. The DYB write command for the dynamic sectors switch the DYBs to signify protected and unprotected, respectively. If
there is a need to change the status of the persistently locked sectors, a few more steps are required. First, the PPB Lock bit must
be disabled by either putting the device through a power-cycle, or hardware reset. The PPBs can then be changed to reflect the
desired settings. Setting the PPB lock bit once again, locks the PPBs and the device operates normally again.
Note
To achieve the best protection, it’s recommended to execute the PPB lock bit set command early in the boot code, and protect the boot code by holding WP# = VIL.

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Table 13.1. Sector Protection Schemes

DYB PPB PPB Lock Sector State
0 0 0 Unprotected—PPB and DYB are changeable
0 0 1 Unprotected—PPB not changeable, DYB is changeable
0 1 0
1 0 0 Protected—PPB and DYB are changeable
1 1 0
0 1 1
1 0 1 Protected—PPB not changeable, DYB is changeable
1 1 1

Table 13.1 contains all possible combinations of the DYB, PPB, and PPB lock relating to the status of the sector.

n
In summary, if the PPB is set, and the PPB lock is set, the sector is protected and the protection can not be removed until the next

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power cycle clears the PPB lock. If the PPB is cleared, the sector can be dynamically locked or unlocked. The DYB then controls

es
whether or not the sector is protected or unprotected.
If the user attempts to program or erase a protected sector, the device ignores the command and returns to read mode. A program

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command to a protected sector enables status polling for approximately 1 µs before the device returns to read mode without having

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modified the contents of the protected sector. An erase command to a protected sector enables status polling for approximately 50
µs after which the device returns to read mode without having erased the protected sector.
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The programming of the DYB, PPB, and PPB lock for a given sector can be verified by writing a DYB/PPB/PPB lock verify command
to the device.
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13.2 Persistent Sector Protection Mode Locking Bit

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Like the password mode locking bit, a Persistent Sector Protection mode locking bit exists to guarantee that the device remain in
en

software sector protection. Once set, the Persistent Sector Protection locking bit prevents programming of the password protection
mode locking bit. This guarantees that an unauthorized user could not place the device in password protection mode.
m
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13.3 Password Protection Mode

The Password Sector Protection Mode method allows an even higher level of security than the Persistent Sector Protection Mode.
ec

There are two main differences between the Persistent Sector Protection and the Password Sector Protection Mode:
R

 When the device is first powered on, or comes out of a reset cycle, the PPB Lock bit set to the locked state, rather than cleared
to the unlocked state.
ot

 The only means to clear the PPB Lock bit is by writing a unique 64-bit Password to the device.
N

The Password Sector Protection method is otherwise identical to the Persistent Sector Protection method.
A 64-bit password is the only additional tool utilized in this method.
The password is stored in a one-time programmable (OTP) region of the flash memory. Once the Password Mode Locking Bit is
set, the password is permanently set with no means to read, program, or erase it. The password is used to clear the PPB Lock bit.
The Password Unlock command must be written to the flash, along with a password. The flash device internally compares the given
password with the pre-programmed password. If they match, the PPB Lock bit is cleared, and the PPBs can be altered. If they do not
match, the flash device does nothing. There is a built-in 2 µs delay for each password check. This delay is intended to stop any
efforts to run a program that tries all possible combinations in order to crack the password.

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13.4 Password and Password Mode Locking Bit

In order to select the Password sector protection scheme, the customer must first program the password. One method of choosing a
password would be to correlate it to the unique Electronic Serial Number (ESN) of the particular flash device. Another method could
generate a database where all the passwords are stored, each of which correlates to a serial number on the device. Each ESN is
different for every flash device; therefore each password should be different for every flash device. While programming in the
password region, the customer may perform Password Verify operations.
Once the desired password is programmed in, the customer must then set the Password Mode Locking Bit. This operation achieves
two objectives:
1. It permanently sets the device to operate using the Password Protection Mode. It is not possible to reverse this function.
2. It also disables all further commands to the password region. All program, and read operations are ignored.
Both of these objectives are important, and if not carefully considered, may lead to unrecoverable errors. The user must be sure that
the Password Protection method is desired when setting the Password Mode Locking Bit. More importantly, the user must be sure
that the password is correct when the Password Mode Locking Bit is set. Due to the fact that read operations are disabled, there is

n
ig
no means to verify what the password is afterwards. If the password is lost after setting the Password Mode Locking Bit, there is no
way to clear the PPB Lock bit.

es
The Password Mode Locking Bit, once set, prevents reading the 64-bit password on the DQ bus and further password programming.

D
The Password Mode Locking Bit is not erasable. Once Password Mode Locking Bit is programmed, the Persistent Sector Protection
Locking Bit is disabled from programming, guaranteeing that no changes to the protection scheme are allowed.

ew
13.4.1 64-bit Password
rN
The 64-bit Password is located in its own memory space and is accessible through the use of the Password Program and Verify
fo
commands (see Password Verify Command on page 45). The password function works in conjunction with the Password Mode
Locking Bit, which when set, prevents the Password Verify command from reading the contents of the password on the pins of the
d

device.
de
en

13.5 Write Protect (WP#)

m

The device features a hardware protection option using a write protect pin that prevents programming or erasing, regardless of the
state of the sector’s Persistent or Dynamic Protection Bits. The WP# pin is associated with the two outermost 8Kbytes sectors in the
om

75% bank. The WP# pin has no effect on any other sector. When WP# is taken to VIL, programming and erase operations of the two
outermost 8 Kbytes sectors in the 75% bank are disabled. By taking WP# back to VIH, the two outermost 8 Kbytes sectors are
ec

enabled for program and erase operations, depending upon the status of the individual sector Persistent or Dynamic Protection Bits.
If either of the two outermost sectors Persistent or Dynamic Protection Bits are programmed, program or erase operations are
R

inhibited. If the sector Persistent or Dynamic Protection Bits are both erased, the two sectors are available for programming or
ot

erasing as long as WP# remains at VIH. The user must hold the WP# pin at either VIH or VIL during the entire program or erase
operation of the two outermost sectors in the 75% bank.
N

13.6 Secured Silicon OTP Sector and Simultaneous Operation

The Secured Silicon Sector is 256 Kbytes and is located in the Small Bank. For S29CD016G and S29CD032G devices. Spansion
programs and permanently locks the Secured Silicon sector with Unique device identification. Please contact your sales
representative for the Electronic Marking information.
Since the Secured Silicon is permanent protected by Spansion, during Simultaneous Operation, the Secured Silicon sector cannot
be erased or reprogrammed.

13.7 Persistent Protection Bit Lock

The Persistent Protection Bit (PPB) Lock is a volatile bit that reflects the state of the Password Mode Locking Bit after power-up
reset. If the Password Mode Locking Bit is set, which indicates the device is in Password Protection Mode, the PPB Lock Bit is also
set after a hardware reset (RESET# asserted) or a power-up reset. The ONLY means for clearing the PPB Lock Bit in Password
Protection Mode is to issue the Password Unlock command. Successful execution of the Password Unlock command clears the

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PPB Lock Bit, allowing for sector PPBs modifications. Asserting RESET#, taking the device through a power-on reset, or issuing the
PPB Lock Bit Set command sets the PPB Lock Bit back to a 1.
If the Password Mode Locking Bit is not set, indicating Persistent Sector Protection Mode, the PPB Lock Bit is cleared after power-
up or hardware reset. The PPB Lock Bit is set by issuing the PPB Lock Bit Set command. Once set the only means for clearing the
PPB Lock Bit is by issuing a hardware or power-up reset. The Password Unlock command is ignored in Persistent Sector Protection
Mode.

13.8 Hardware Data Protection

The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent
writes. In addition, the following hardware data protection measures prevent accidental erasure or programming, which might
otherwise be caused by spurious system level signals during VCC power-up and power-down transitions, or from system noise.

13.8.1 Low VCC Write Inhibit

n
ig
When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC power-up and power-down.

es
The command register and all internal erase/program circuits are disabled, and the device resets. Subsequent writes are ignored
until VCC is greater than VLKO. The system must provide the proper signals to the control pins to prevent unintentional writes when

D
VCC is greater than VLKO.

ew
13.8.2 Write Pulse Glitch Protection rN
Noise pulses of less than 5 ns (typical) on OE#, CE#, or WE# do not initiate a write cycle.
fo

13.8.3 Logical Inhibit

d

Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH, or WE# = VIH. To initiate a write cycle, CE# and WE# must be
de

a logical zero (VIL) while OE# is a logical one (VIH).

en

13.8.4 Power-Up Write Inhibit

m

If WE# = CE# = VIL and OE# = VIH during power-up, the device does not accept commands on the rising edge of WE#. The internal
om

state machine is automatically reset to reading array data on power-up.

ec

13.8.5 VCC and VIO Power-up And Power-down Sequencing

R

The device imposes no restrictions on VCC and VIO power-up or power-down sequencing. Asserting RESET# to VIL is required
during the entire VCC and VIO power sequence until the respective supplies reach the operating voltages. Once, VCC and VIO attain
ot

the operating voltages, de-assertion of RESET# to VIH is permitted.

N

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14. Common Flash Memory Interface (CFI)

The Common Flash Interface (CFI) specification outlines device and host system software interrogation handshake, which allows
specific vendor-specified software algorithms to be used for entire families of devices. Software support can then be device-
independent, JEDEC ID-independent, and forward- and backward-compatible for the specified flash device families. Flash vendors
can standardize existing interfaces for long-term compatibility.
This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address 55h in word mode (or
address AAh in byte mode), any time the device is ready to read array data. The system can read CFI information at the addresses
given in Tables 13–16. To terminate reading CFI data, the system must write the reset command.
The system can also write the CFI query command when the device is in the autoselect mode. The device enters the CFI query
mode, and the system can read CFI data at the addresses given in Tables 13–16. The system must write the reset command to
return the device to the autoselect mode.
For further information, please refer to the CFI Specification and CFI Publication 100, available via the World Wide Web at http://
www.spansion.com. Alternatively, contact an AMD representative for copies of these documents.

n
ig
Table 14.1. CFI Query Identification String

es
Addresses Data Description

D
10h 0051h
11h 0052h Query Unique ASCII string QRY

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12h 0059h
13h 0002h
Primary OEM Command Set rN
14h 0000h
15h 0040h
Address for Primary Extended Table
16h 0000h
fo

17h 0000h
Alternate OEM Command Set (00h = none exists)
18h 0000h
d
de

19h 0000h
Address for Alternate OEM Extended Table (00h = none exists)
1Ah 0000h
en
m

Table 14.2. CFI System Interface String

om

Addresses Data Description

ec

VCC Min. (write/erase)

1Bh 0023h
DQ7–DQ4: volts, DQ3–DQ0: 100 millivolt
R

VCC Max. (write/erase)

1Ch 0027h
DQ7–DQ4: volts, DQ3–DQ0: 100 millivolt
ot

1Dh 0000h VPP Min. voltage (00h = no VPP pin present)

N

1Eh 0000h VPP Max. voltage (00h = no VPP pin present)

1Fh 0004h Typical timeout per single word/doubleword program 2N µs
20h 0000h Typical timeout for Min. size buffer program 2N µs (00h = not supported)
21h 0009h Typical timeout per individual block erase 2N ms
22h 0000h Typical timeout for full chip erase 2N ms (00h = not supported)
23h 0005h Max. timeout for word/doubleword program 2N times typical
24h 0000h Max. timeout for buffer write 2N times typical
25h 0007h Max. timeout per individual block erase 2N times typical
26h 0000h Max. timeout for full chip erase 2N times typical (00h = not supported)

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Table14. 3. Device Geometry Definition

Addresses Data Description
27h 0016h Device Size = 2N byte
Flash Device Interface description (for complete description, please refer to CFI publication 100)
0000 = x8-only asynchronous interface
28h 0005h 0001 = x16-only asynchronous interface
29h 0000h 0002 = supports x8 and x16 via BYTE# with asynchronous interface
0003 = x 32-only asynchronous interface
0005 = supports x16 and x32 via WORD# with asynchronous interface
2Ah 0000h Max. number of byte in multi-byte program = 2N
2Bh 0000h (00h = not supported)
2Ch 0003h Number of Erase Block Regions within device
2Dh 0007h
2Eh 0000h Erase Block Region 1 Information
2Fh 0020h (refer to the CFI specification or CFI publication 100)

n
30h 0000h

ig
31h 003Dh*0

es
32h 000h Erase Block Region 2 Information
33h 0000h (refer to the CFI specification or CFI publication 100)
34h 0001h

D
35h 0007h

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36h 0000h Erase Block Region 3 Information
37h 0020h (refer to the CFI specification or CFI publication 100)
38h 0000h rN
39h 0000h
3Ah 0000h Erase Block Region 4 Information
fo
3Bh 0000h (refer to the CFI specification or CFI publication 100)
3Ch 0000h
d

Note
de

* On 16 Mb device, data at address 31h is 1Dh.

en
m
om
ec
R
ot
N

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Table14. 4. CFI Primary Vendor-Specific Extended Query (Sheet 1 of 2)

Addresses Data Description
40h 0050h
41h 0052h Query-unique ASCII string PRI
42h 0049h
43h 0031h Major version number, ASCII (reflects modifications to the silicon)
44h 0033h Minor version number, ASCII (reflects modifications to the CFI table)
Address Sensitive Unlock (DQ1, DQ0)
00 = Required, 01 = Not Required
Silicon Revision Number (DQ5–DQ2
0000 = CS49
45h 0004h
0001 = CS59
0010 = CS99
0011 = CS69
0100 = CS119

n
Erase Suspend (1 byte)

ig
00 = Not Supported
46h 0002h

es
01 = To Read Only
02 = To Read and Write

D
Sector Protect (1 byte)
47h 0001h
00 = Not Supported, X = Number of sectors in per group

ew
Temporary Sector Unprotect
48h 0000h
00h = Not Supported, 01h = Supported
Sector Protect/Unprotect scheme (1 byte)
rN
01 =29F040 mode, 02 = 29F016 mode
03 = 29F400 mode, 04 = 29LV800 mode
fo
49h 0006h
05 = 29BDS640 mode (Software Command Locking)
06 = BDD160 mode (New Sector Protect)
d

07 = 29LV800 + PDL128 (New Sector Protect) mode

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Simultaneous Read/Write (1 byte)

4Ah 0037h
00h = Not Supported, X = Number of sectors in all banks except Bank 1
en

Burst Mode Type

4Bh 0001h
00h = Not Supported, 01h = Supported
m

Page Mode Type

4Ch 0000h
om

00h = Not Supported, 01h = 4 Word Page, 02h = 8 Word Page

ACC (Acceleration) Supply Minimum
4Dh 00B5h
00h = Not Supported (DQ7-DQ4: volt in hex, DQ3-DQ0: 100 mV in BCD)
ec

ACC (Acceleration) Supply Maximum

4Eh 00C5h
00h = Not Supported, (DQ7-DQ4: volt in hex, DQ3-DQ0: 100 mV in BCD)
R

Top/Bottom Boot Sector Flag (1 byte)

ot

00h = Uniform device, no WP# control,

01h = 8 x 8 Kb sectors at top and bottom with WP# control
N

02h = Bottom boot device

4Fh 0001h
03h = Top boot device
04h = Uniform, Bottom WP# Protect
05h = Uniform, Top WP# Protect
If the number of erase block regions = 1, then ignore this field
Program Suspend
50h 0001h 00 = Not Supported
01 = Supported
Write Buffer Size
51h 0000h
2(N+1) word(s)
Bank Organization (1 byte)
57h 0002h 00 = If data at 4Ah is zero
XX = Number of banks
Bank 1 Region Information (1 byte)
58h 0017h
XX = Number of Sectors in Bank 1
Bank 2 Region Information (1 byte)
59h 0037h
XX = Number of Sectors in Bank 2

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Table14. 4. CFI Primary Vendor-Specific Extended Query (Sheet 2 of 2)

Addresses Data Description
Bank 3 Region Information (1 byte)
5Ah 0000h
XX = Number of Sectors in Bank 3
Bank 4 Region Information (1 byte)
5Bh 0000h
XX = Number of Sectors in Bank 4

15. Command Definitions

Writing specific address and data commands or sequences into the command register initiates device operations. Table 15.2
on page 48 and Table 15. 3 on page 50 define the valid register command sequences. Writing incorrect address and data values
or writing them in the improper sequence resets the device to reading array data.
All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE#
or CE#, whichever happens first. See AC Characteristics on page 60 for timing diagrams.

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ig
15.1 Reading Array Data in Non-burst Mode

es
The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device

D
is also ready to read array data after completing an Embedded Program or Embedded Erase algorithm.

ew
After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode. The system can read array data
using the standard read timings, except that if it reads at an address within erase-suspended sectors, the device outputs status data.
rN
After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same
exception. See Sector Erase and Program Suspend Command on page 42 for more information on this mode.
fo
The system must issue the reset command to re-enable the device for reading array data if DQ5 goes high, or while in the autoselect
mode. See PPB Lock Bit Set Command on page 45.
d
de

Asynchronous Read Operation (Non-Burst) on page 23 for more information. See Sector Erase and Program Resume Command
on page 44 for more information on this mode.
en
m

15.2 Reading Array Data in Burst Mode

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The device is capable of very fast Burst mode read operations. The configuration register sets the read configuration, burst order,
frequency configuration, and burst length.
ec

Upon power on, the device defaults to the asynchronous mode. In this mode, CLK, and ADV# are ignored. The device operates like
a conventional Flash device. Data is available tACC/tCE nanoseconds after address becomes stable, CE# become asserted. The
R

device enters the burst mode by enabling synchronous burst reads in the configuration register. The device exits burst mode by
ot

disabling synchronous burst reads in the configuration register. (See Command Definitions on page 37). The RESET# command
does not terminate the Burst mode. System reset (power on reset) terminates the Burst mode.
N

The device has the regular control pins, i.e. Chip Enable (CE#), Write Enable (WE#), and Output Enable (OE#) to control normal
read and write operations. Moreover, three additional control pins were added to allow easy interface with minimal glue logic to a
wide range of microprocessors / microcontrollers for high performance Burst read capability. These additional pins are Address Valid
(ADV#) and Clock (CLK). CE#, OE#, and WE# are asynchronous (relative to CLK). The Burst mode read operation is a synchronous
operation tied to the edge of the clock. The microprocessor / microcontroller supplies only the initial address, all subsequent
addresses are automatically generated by the device with a timing defined by the Configuration Register definition. The Burst read
cycle consists of an address phase and a corresponding data phase.
During the address phase, the Address Valid (ADV#) pin is asserted (taken Low) for one clock period. Together with the edge of the
CLK, the starting burst address is loaded into the internal Burst Address Counter. The internal Burst Address Counter can be
configured to either 2, 4, and 8 double word linear burst, with or without wrap around. See Initial Access Delay Configuration
on page 29.
During the data phase, the first burst data is available after the initial access time delay defined in the Configuration Register. For
subsequent burst data, every rising (or falling) edge of the CLK triggers the output data with the burst output delay and sequence
defined in the Configuration Register.

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Table 15.2 on page 48 and Table 15. 3 on page 50 show all the commands executed by the device. The device automatically
powers up in the read/reset state. It is not necessary to issue a read/reset command after power-up or hardware reset.

15.3 Read/Reset Command

After power-up or hardware reset, the device automatically enter the read state. It is not necessary to issue the reset command after
power-up or hardware reset. Standard microprocessor cycles retrieve array data, however, after power-up, only asynchronous
accesses are permitted since the Configuration Register is at its reset state with burst accesses disabled.
The Reset command is executed when the user needs to exit any of the other user command sequences (such as autoselect,
program, chip erase, etc.) to return to reading array data. There is no latency between executing the Reset command and reading
array data.
The Reset command does not disable the Secured Silicon sector if it is enabled. This function is only accomplished by issuing the
Secured Silicon Sector Exit command.

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ig
15.4 Autoselect Command

es
Flash memories are intended for use in applications where the local CPU alters memory contents. As such, manufacturer and

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device codes must be accessible while the device resides in the target system. PROM programmers typically access the signature
codes by raising A9 to VID. However, multiplexing high voltage onto the address lines is not generally desired system design

ew
practice.
The device contains an Autoselect Command operation to supplement traditional PROM programming methodology. The operation
rN
is initiated by writing the Autoselect command sequence into the command register. The bank address (BA) is latched during the
autoselect command sequence write operation to distinguish which bank the Autoselect command references. Reading the other
fo
bank after the Autoselect command is written results in reading array data from the other bank and the specified address. Following
the command write, a read cycle from address (BA)XX00h retrieves the manufacturer code of (BA)XX01h. Three sequential read
d

cycles at addresses (BA) XX01h, (BA) XX0Eh, and (BA) XX0Fh read the three-byte device ID (see Table 15.2 on page 48).
de

(The Autoselect Command requires the user to execute the Read/Reset command to return the device back to reading the array
en

contents.)
m

15.5 Program Command Sequence

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Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed
ec

by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program
algorithm. The system is not required to provide further controls or timings. The device automatically generates the program pulses
R

and verifies the programmed cell margin. Table 15.2 on page 48 and Table 15. 3 on page 50 show the address and data
requirements for the program command sequence.
ot

During the Embedded Program algorithm, the system can determine the status of the program operation by using DQ7, DQ6, or RY/
N

BY#. (See Write Operation Status on page 51 for information on these status bits.) When the Embedded Program algorithm is
complete, the device returns to reading array data and addresses are no longer latched. Note that an address change is required to
begin read valid array data.
Except for Program Suspend, any commands written to the device during the Embedded Program Algorithm are ignored. Note that
a hardware reset immediately terminates the programming operation. The command sequence should be reinitiated once that bank
returns to reading array data, to ensure data integrity.
Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from a 0 back to a 1.
Attempting to do so may halt the operation and set DQ5 to 1, or cause the Data# Polling algorithm to indicate the operation was
successful. However, a succeeding read shows that the data is still 0. Only erase operations can convert a 0 to a 1.

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15.6 Accelerated Program Command

The Accelerated Chip Program mode is designed to improve the Word or Double Word programming speed. Improving the
programming speed is accomplished by using the ACC pin to supply both the wordline voltage and the bitline current instead of
using the VPP pump and drain pump, which is limited to 2.5 mA. Because the external ACC pin is capable of supplying significantly
large amounts of current compared to the drain pump, all 32 bits are available for programming with a single programming pulse.
This is an enormous improvement over the standard 5-bit programming. If the user is able to supply an external power supply and
connect it to the ACC pin, significant time savings are realized.
In order to enter the Accelerated Program mode, the ACC pin must first be taken to VHH (12 V ± 0.5 V) and followed by the one-cycle
command with the program address and data to follow. The Accelerated Chip Program command is only executed when the device
is in Unlock Bypass mode and during normal read/reset operating mode.
In this mode, the write protection function is bypassed unless the PPB Lock Bit = 1.
The Accelerated Program command is not permitted if the Secured Silicon sector is enabled.

n
ig
15.7 Unlock Bypass Command Sequence

es
The unlock bypass feature allows the system to program words to the device faster than using the standard program command
sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle

D
containing the unlock bypass command, 20h. The device then enters the unlock bypass mode. A two-cycle unlock bypass program

ew
command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass
program command, A0h; the second cycle contains the program address and data. Additional data is programmed in the same
rN
manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in
faster total programming time. Table 14. 4 on page 36 and Table 15.2 on page 48 show the requirements for the command
sequence.
fo

During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are valid. To exit the unlock
d

bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. The first cycle must contain the data
de

90h; the second cycle the data 00h. Addresses are don’t care for both cycles. The device then returns to reading array data.
en

Table 15.1 on page 40 illustrates the algorithm for the program operation. See Erase/Program Operations on page 66 for
parameters, and to Figure 24.8 on page 67 and Figure 24.9 on page 67 for timing diagrams.
m
om
ec
R
ot
N

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Figure 15.1 Program Operation

START

Write Program
Command Sequence

Data Poll
from System
Embedded
Program
algorithm
in progress

n
Verify Data?
No

ig
es
Yes

D
No
Increment Address Last Address?

ew
rN Yes

Programming
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Completed
d

Note
See Table 15.2 on page 48 and Table 15. 3 on page 50 for program command sequence.
de
en

15.7.1 Unlock Bypass Entry Command

m

The Unlock Bypass command, once issued, is used to bypass the unlock sequence for program, chip erase, and CFI commands.
This feature permits slow PROM programmers to significantly improve programming/erase throughput since the command
om

sequence often requires microseconds to execute a single write operation. Therefore, once the Unlock Bypass command is issued,
only the two-cycle program and erase bypass commands are required. The Unlock Bypass Command is ignored if the Secured
ec

Silicon sector is enabled. To return back to normal operation, the Unlock Bypass Reset Command must be issued.
R

The following four sections describe the commands that may be executed within the unlock bypass mode.
ot

15.7.2 Unlock Bypass Program Command

N

The Unlock Bypass Program command is a two-cycle command that consists of the actual program command (A0h) and the
program address/data combination. This command does not require the two-cycle unlock sequence since the Unlock Bypass
command was previously issued. As with the standard program command, multiple Unlock Bypass Program commands can be
issued once the Unlock Bypass command is issued.
To return back to standard read operations, the Unlock Bypass Reset command must be issued.
The Unlock Bypass Program Command is ignored if the Secured Silicon sector is enabled.

15.7.3 Unlock Bypass Chip Erase Command

The Unlock Bypass Chip Erase command is a 2-cycle command that consists of the erase setup command (80h) and the actual chip
erase command (10h). This command does not require the two-cycle unlock sequence since the Unlock Bypass command was
previously issued. Unlike the standard erase command, there is no Unlock Bypass Erase Suspend or Erase Resume commands.
To return back to standard read operations, the Unlock Bypass Reset command must be issued.
The Unlock Bypass Program Command is ignored if the Secured Silicon sector is enabled.

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15.7.4 Unlock Bypass CFI Command

The Unlock Bypass CFI command is available for PROM programmers and target systems to read the CFI codes while in Unlock
Bypass mode. See Common Flash Interface (CFI) Command on page 44 for specific CFI codes.
To return back to standard read operations, the Unlock Bypass Reset command must be issued.
The Unlock Bypass Program Command is ignored if the Secured Silicon sector is enabled.

15.7.5 Unlock Bypass Reset Command

The Unlock Bypass Reset command places the device in standard read/reset operating mode. Once executed, normal read
operations and user command sequences are available for execution.
The Unlock Bypass Program Command is ignored if the Secured Silicon sector is enabled.

n
15.8 Chip Erase Command

ig
The Chip Erase command is used to erase the entire flash memory contents of the chip by issuing a single command. Chip erase is

es
a six-bus cycle operation. There are two unlock write cycles, followed by writing the erase set-up command. Two more unlock write
cycles are followed by the chip erase command. Chip erase does not erase protected sectors.

D
The chip erase operation initiates the Embedded Erase algorithm, which automatically preprograms and verifies the entire memory

ew
to an all zero pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations.
Note that a hardware reset immediately terminates the programming operation. The command sequence should be reinitiated once
rN
that bank returns to reading array data, to ensure data integrity.
The Embedded Erase algorithm erase begins on the rising edge of the last WE# or CE# pulse (whichever occurs first) in the
fo

command sequence. The status of the erase operation is determined three ways:
d

 Data# polling of the DQ7 pin (See DQ7: Data# Polling on page 51)
de

 Checking the status of the toggle bit DQ6 (See DQ6: Toggle Bit I on page 53)
en

 Checking the status of the RY/BY# pin (See RY/BY#: Ready/Busy# on page 51)
m

Once erasure begins, only the Erase Suspend command is valid. All other commands are ignored.
om

When the Embedded Erase algorithm is complete, the device returns to reading array data, and addresses are no longer latched.
Note that an address change is required to begin read valid array data.
ec

Figure 15.2 on page 43 illustrates the Embedded Erase Algorithm. See Erase/Program Operations on page 66 for parameters, and
Figure 24.8 on page 67 and Figure 24.9 on page 67 for timing diagrams.
R
ot

15.9 Sector Erase Command

N

The Sector Erase command is used to erase individual sectors or the entire flash memory contents. Sector erase is a six-bus cycle
operation. There are two unlock write cycles, followed by writing the erase set-up command. Two more unlock write cycles are then
followed by the erase command (30h). The sector address (any address location within the desired sector) is latched on the falling
edge of WE# or CE# (whichever occurs last) while the command (30h) is latched on the rising edge of WE# or CE# (whichever
occurs first).
Specifying multiple sectors for erase is accomplished by writing the six bus cycle operation, as described above, and then following
it by additional writes of only the last cycle of the Sector Erase command to addresses or other sectors to be erased. The time
between Sector Erase command writes must be less than 80 µs, otherwise the command is rejected. It is recommended that
processor interrupts be disabled during this time to guarantee this critical timing condition. The interrupts can be re-enabled after the
last Sector Erase command is written. A time-out of 80 µs from the rising edge of the last WE# (or CE#) initiates the execution of the
Sector Erase command(s). If another falling edge of the WE# (or CE#) occurs within the 80 µs time-out window, the timer is reset.
Once the 80 µs window times out and erasure begins, only the Erase Suspend command is recognized (See Sector Erase and
Program Suspend Command on page 42 and Sector Erase and Program Resume Command on page 44). If that occurs, the sector
erase command sequence should be reinitiated once that bank returns to reading array data, to ensure data integrity. Loading the
sector erase registers may be done in any sequence and with any number of sectors.

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Sector erase does not require the user to program the device prior to erase. The device automatically preprograms all memory
locations, within sectors to be erased, prior to electrical erase. When erasing a sector or sectors, the remaining unselected sectors
or the write protected sectors are unaffected. The system is not required to provide any controls or timings during sector erase
operations. The Erase Suspend and Erase Resume commands may be written as often as required during a sector erase operation.
Automatic sector erase operations begin on the rising edge of the WE# or CE# pulse of the last sector erase command issued, and
once the 80 µs time-out window expires. The status of the sector erase operation is determined three ways:
 Data# polling of the DQ7 pin
 Checking the status of the toggle bit DQ6
 Checking the status of the RY/BY# pin
Further status of device activity during the sector erase operation is determined using toggle bit DQ2 (See DQ2: Toggle Bit II
on page 53).
When the Embedded Erase algorithm is complete, the device returns to reading array data, and addresses are no longer latched.

n
Note that an address change is required to begin read valid array data.

ig
Figure 15.2 on page 43 illustrates the Embedded™ Erase Algorithm, using a typical command sequence and bus operation. See

es
Erase/Program Operations on page 66 for parameters, and to Figure 24.8 on page 67 and Figure 24.9 on page 67 for timing
diagrams.

D
ew
15.10 Sector Erase and Program Suspend Command rN
The Sector Erase and Program Suspend command allows the user to interrupt a Sector Erase or Program operation and perform
data read or programs in a sector that is not being erased or to the sector where a programming operation was initiated. This
fo
command is applicable only during the Sector Erase and Programming operation, which includes the time-out period for Sector
Erase.
d
de

15.11 Sector Erase and Program Suspend Operation Mechanics

en

The Sector Erase and Program Suspend command is ignored if written during the execution of the Chip Erase operation or
Embedded Program Algorithm (but resets the chip if written improperly during the command sequences). Writing the Sector Erase
m

and Program command during the Sector Erase time-out results in immediate termination of the time-out period and suspension of
om

the erase operation. Once in Erase Suspend, the device is available for reading (note that in the
ec
R
ot
N

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Figure 15.2 Erase Operation

START

Write Erase
Command Sequence

Data Poll
from System
Embedded
Erase
algorithm
in progress

n
No
Data = FFh?

ig
es
Yes

D
Erasure Completed

ew
Notes rN
1. See Table 15.2 on page 48 and Table 15. 3 on page 50 for erase command sequence.
2. See DQ3: Sector Erase Timer on page 54 for more information.
fo

Erase Suspend mode, the Reset command is not required for read operations and is ignored) or program operations in sectors not
d

being erased. Any other command written during the Erase Suspend mode is ignored, except for the Sector Erase and Program
de

Resume command. Writing the Erase and Program Resume command resumes the sector erase operation. The bank address of
the erase suspended bank is required when writing this command
en

If the Sector Erase and Program Suspend command is written during a programming operation, the device suspends programming
m

operations and allows only read operations in sectors not selected for programming. Further nesting of either erase or programming
om

operations is not permitted. Table 15.1 summarizes permissible operations during Erase and Program Suspend. (A busy sector is
one that is selected for programming or erasure.):
ec

Table 15.1 Allowed Operations During Erase/Program Suspend

R

Sector Program Suspend Erase Suspend

ot

Busy Sector Program Resume Erase Resume

N

Non-busy sectors Read Only Read or Program

When the Sector Erase and Program Suspend command is written during a Sector Erase operation, the chip takes between 0.1 µs
and 20 µs to actually suspend the operation and go into the erase suspended read mode (pseudo-read mode), at which time the
user can read or program from a sector that is not erase suspended. Reading data in this mode is the same as reading from the
standard read mode, except that the data must be read from sectors that were not erase suspended.
Polling DQ6 on two immediately consecutive reads from a given address provides the system with the ability to determine if the
device is in Erase or Program Suspend. Before the device enters Erase or Program Suspend, the DQ6 pin toggles between two
immediately consecutive reads from the same address. After the device enters Erase suspend, DQ6 stops toggling between two
immediately consecutive reads to the same address. During the Sector Erase operation and also in Erase suspend mode, two
immediately consecutive readings from the erase-suspended sector causes DQ2 to toggle. DQ2 does not toggle if reading from a
non-busy (non-erasing) sector (stored data is read). No bits are toggled during program suspend mode. Software must keep track of
the fact that the device is in a suspended mode.
After entering the erase-suspend-read mode, the system may read or program within any non-suspended sector:
 A read operation from the erase-suspended bank returns polling data during the first 8 µs after the erase suspend command is
issued; read operations thereafter return array data. Read operations from the other bank return array data with no latency.

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 A program operation while in the erase suspend mode is the same as programming in the regular program mode, except that the
data must be programmed to a sector that is not erase suspended. Write operation status is obtained in the same manner as a
normal program operation.

15.12 Sector Erase and Program Resume Command

The Sector Erase and Program Resume command (30h) resumes a Sector Erase or Program operation that was suspended. Any
further writes of the Sector Erase and Program Resume command ignored. However, another Sector Erase and Program Suspend
command can be written after the device resumes sector erase operations. Note that until a suspended program or erase operation
resumes, the contents of that sector are unknown.
The Sector Erase and Program Resume Command is ignored if the Secured Silicon sector is enabled.

15.13 Configuration Register Read Command

n
The Configuration Register Read command is used to verify the contents of the Configuration Register. Execution of this command

ig
is only allowed while in user mode and is not available during Unlock Bypass mode or during Security mode. The Configuration

es
Register Read command is preceded by the standard two-cycle unlock sequence, followed by the Configuration Register Read
command (C6h), and finally followed by performing a read operation to the bank address specified when the C6h command was

D
written. Reading the other bank results in reading the flash memory contents. The contents of the Configuration Register are place

ew
on DQ15–DQ0. Contents of DQ31–DQ16 are XXXXh and should be ignored. The user should execute the Read/Reset command to
place the device back in standard user operation after executing the Configuration Register Read command.
rN
The Configuration Register Read Command is fully operational if the Secured Silicon sector is enabled.
fo

15.14 Configuration Register Write Command

d

The Configuration Register Write command is used to modify the contents of the Configuration Register. Execution of this command
de

is only allowed while in user mode and is not available during Unlock Bypass mode or during Security mode. The Configuration
Register Write command is preceded by the standard two-cycle unlock sequence, followed by the Configuration Register Write
en

command (D0h), and finally followed by writing the contents of the Configuration Register to any address. The contents of the
Configuration Register are placed on DQ31–DQ0. The contents of DQ31–DQ16 are XXXXh and are ignored. Writing the
m

Configuration Register while an Embedded Algorithm™ or Erase Suspend modes are executing results in the contents of the
om

Configuration Register not being updated.

The Configuration Register Read Command is fully operational if the Secured Silicon sector is enabled.
ec
R

15.15 Common Flash Interface (CFI) Command

ot

The Common Flash Interface (CFI) command provides device size, geometry, and capability information directly to the users
N

system. Flash devices that support CFI, have a Query Command that returns information about the device to the system. The Query
structure contents are read at the specific address locations following a single system write cycle where:
 A 98h query command code is written to 55h address location within the device’s address space
 The device is initially in any valid read state, such as Read Array or Read ID Data
Other device statistics may exist within a long sequence of commands or data input; such sequences must first be completed or
terminated before writing of the 98H Query command, otherwise invalid Query data structure output may result.
Note that for data bus bits greater than DQ7 (DQ31–DQ8), the valid Query access code contains all zeroes (0s) in the upper DQ bus
locations. Thus, the 16-bit Query command code is 0098h and the 32-bit Query command code is 00000098h.
To terminate the CFI operation, it is necessary to execute the Read/Reset command.
The CFI command is not permitted if the Secured Silicon sector is enabled and Simultaneous Read/Write operation is disabled once
the command is entered.
See Common Flash Interface (CFI) Command on page 44 for the specific CFI command codes.

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15.16 Password Program Command

The Password Program Command permits programming the password that is used as part of the hardware protection scheme. The
actual password is 64-bits long. Depending upon the state of the WORD# pin, multiple Password Program Commands are required.
For a x32 bit data bus, 2 Password Program commands are required. The user must enter the unlock cycle, password program
command (38h) and the program address/data for each portion of the password when programming. There are no provisions for
entering the 2-cycle unlock cycle, the password program command, and all the password data. There is no special addressing order
required for programming the password. Also, when the password is undergoing programming, Simultaneous Read/Write operation
is disabled. Read operations to any memory location returns the programming status. Once programming is complete, the user must
issue a Read/Reset command to return the device to normal operation. Once the Password is written and verified, the Password
Mode Locking Bit must be set in order to prevent verification. The Password Program Command is only capable of programming 0s.
Programming a 1 after a cell is programmed as a 0 results in a time-out by the Embedded Program Algorithm™ with the cell
remaining as a 0. The password is all F’s when shipped from the factory. All 64-bit password combinations are valid as a password.
Password Programming is permitted if the Secured Silicon sector is enabled.

n
ig
15.17 Password Verify Command

es
The Password Verify Command is used to verify the Password. The Password is verifiable only when the Password Mode Locking
Bit is not programmed. If the Password Mode Locking Bit is programmed and the user attempts to verify the Password, the device

D
always drives all F’s onto the DQ data bus.

ew
The Password Verify command is permitted if the Secured Silicon sector is enabled. Also, Simultaneous Read/Write operation is
disabled when the Password Verify command is executed. Only the password is returned regardless of the bank address. The lower
rN
two address bits (A0:A-1) are valid during the Password Verify. Writing the Read/Reset command returns the device back to normal
operation.
fo
d

15.18 Password Protection Mode Locking Bit Program Command

de

The Password Protection Mode Locking Bit Program Command programs the Password Protection Mode Locking Bit, which
en

prevents further verifies or updates to the Password. Once programmed, the Password Protection Mode Locking Bit cannot be
erased! If the Password Protection Mode Locking Bit is verified as program without margin, the Password Protection Mode Locking
m

Bit Program command can be executed to improve the program margin. Once the Password Protection Mode Locking Bit is
programmed, the Persistent Sector Protection Locking Bit program circuitry is disabled, thereby forcing the device to remain in the
om

Password Protection mode. Exiting the Mode Locking Bit Program command is accomplished by writing the Read/Reset command.
ec

The Password Protection Mode Locking Bit Program command is permitted if the Secured Silicon sector is enabled.
R

15.19 Persistent Sector Protection Mode Locking Bit Program Command

ot

The Persistent Sector Protection Mode Locking Bit Program Command programs the Persistent Sector Protection Mode Locking Bit,
N

which prevents the Password Mode Locking Bit from ever being programmed. If the Persistent Sector Protection Mode Locking Bit is
verified as programmed without margin, the Persistent Sector Protection Mode Locking Bit Program Command should be reissued
to improve program margin. By disabling the program circuitry of the Password Mode Locking Bit, the device is forced to remain in
the Persistent Sector Protection mode of operation, once this bit is set. Exiting the Persistent Protection Mode Locking Bit Program
command is accomplished by writing the Read/Reset command.
The Persistent Sector Protection Mode Locking Bit Program command is permitted if the Secured Silicon sector is enabled.

15.20 PPB Lock Bit Set Command

The PPB Lock Bit Set command is used to set the PPB Lock bit if it is cleared either at reset or if the Password Unlock command
was successfully executed. There is no PPB Lock Bit Clear command. Once the PPB Lock Bit is set, it cannot be cleared unless the
device is taken through a power-on clear or the Password Unlock command is executed. Upon setting the PPB Lock Bit, the PPBs
are latched into the DYBs. If the Password Mode Locking Bit is set, the PPB Lock Bit status is reflected as set, even after a power-
on reset cycle. Exiting the PPB Lock Bit Set command is accomplished by writing the Read/Reset command.
The PPB Lock Bit Set command is permitted if the Secured Silicon sector is enabled.

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15.21 DYB Write Command

The DYB Write command is used to set or clear a DYB for a given sector. The high order address bits (A19–A11) are issued at the
same time as the code 01h or 00h on DQ7-DQ0. All other DQ data bus pins are ignored during the data write cycle. The DYBs are
modifiable at any time, regardless of the state of the PPB or PPB Lock Bit. The DYBs are cleared at power-up or hardware reset.
Exiting the DYB Write command is accomplished by writing the Read/Reset command.
The DYB Write command is permitted if the Secured Silicon sector is enabled.

15.22 Password Unlock Command

The Password Unlock command is used to clear the PPB Lock Bit so that the PPBs can be unlocked for modification, thereby
allowing the PPBs to become accessible for modification. The exact password must be entered in order for the unlocking function to
occur. This command cannot be issued any faster than 2 µs at a time to prevent a hacker from running through the all 64-bit
combinations in an attempt to correctly match a password. If the command is issued before the 2 µs execution window for each
portion of the unlock, the command is ignored.

n
ig
The Password Unlock function is accomplished by writing Password Unlock command and data to the device to perform the clearing

es
of the PPB Lock Bit. The password is 64 bits long, so the user must write the Password Unlock command 2 times for a x32 bit data
bus. A0 is used to determine whether the 32 bit data quantity is used to match the upper 32 bits or lower 32 bits. Writing the

D
Password Unlock command is address order specific. In other words, for the x32 data bus configuration, the lower 32 bits of the
password are written first and then the upper 32 bits of the password are written. Writing out of sequence results in the Password

ew
Unlock not returning a match with the password and the PPB Lock Bit remains set.
rN
Once the Password Unlock command is entered, the RY/BY# pin goes LOW indicating that the device is busy. Also, reading the
small bank (25% bank) results in the DQ6 pin toggling, indicating that the Password Unlock function is in progress. Reading the
large bank (75% bank) returns actual array data. Approximately 1uSec is required for each portion of the unlock. Once the first
fo

portion of the password unlock completes (RY/BY# is not driven and DQ6 does not toggle when read), the Password Unlock
d

command is issued again, only this time with the next part of the password. The second Password Unlock command is the final
de

command before the PPB Lock Bit is cleared (assuming a valid password). As with the first Password Unlock command, the RY/BY#
signal goes LOW and reading the device results in the DQ6 pin toggling on successive read operations until complete. It is the
en

responsibility of the microprocessor to keep track of the number of Password Unlock commands (2 for x32 bus), the order, and when
to read the PPB Lock bit to confirm successful password unlock
m

The Password Unlock command is permitted if the Secured Silicon sector is enabled.
om

15.23 PPB Program Command

ec

The PPB Program command is used to program, or set, a given PPB. Each PPB is individually programmed (but is bulk erased with
R

the other PPBs). The specific sector address (A19–A11) are written at the same time as the program command 60h with A6 = 0. If
ot

the PPB Lock Bit is set and the corresponding PPB is set for the sector, the PPB Program command does not execute and the
command times-out without programming the PPB.
N

The host system must determine whether a PPB is fully programmed by noting the status of DQ0 in the sixth cycle of the PPB
Program command. If DQ0 = 0, the entire six-cycle PPB Program command sequence must be reissued until DQ0 = 1.

15.24 All PPB Erase Command

The All PPB Erase command is used to erase all PPBs in bulk. There is no means for individually erasing a specific PPB. Unlike the
PPB program, no specific sector address is required. However, when the PPB erase command is written (60h) and A6 = 1, all Sector
PPBs are erased in parallel. If the PPB Lock Bit is set the ALL PPB Erase command does not execute and the command times-out
without erasing the PPBs. The host system must determine whether all PPB was fully erased by noting the status of DQ0 in the sixth
cycle of the All PPB Erase command. If DQ0 = 1, the entire six-cycle All PPB Erase command sequence must be reissued until DQ0
= 1.
It is the responsibility of the user to preprogram all PPBs prior to issuing the All PPB Erase command. If the user attempts to erase a
cleared PPB, over-erasure may occur making it difficult to program the PPB at a later time. Also note that the total number of PPB
program/erase cycles is limited to 100 cycles. Cycling the PPBs beyond 100 cycles is not guaranteed.
The All PPB Erase command is permitted if the Secured Silicon sector is enabled.

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15.25 DYB Write

The DYB Write command is used for setting the DYB, which is a volatile bit that is cleared at reset. There is one DYB per sector. If
the PPB is set, the sector is protected regardless of the value of the DYB. If the PPB is cleared, setting the DYB to a 1 protects the
sector from programs or erases. Since this is a volatile bit, removing power or resetting the device clears the DYBs. The bank
address is latched when the command is written.
The DYB Write command is permitted if the Secured Silicon sector is enabled.

15.26 PPB Lock Bit Set

The PPB Lock Bit set command is used for setting the DYB, which is a volatile bit that is cleared at reset. There is one DYB per
sector. If the PPB is set, the sector is protected regardless of the value of the DYB. If the PPB is cleared, setting the DYB to a 1
protects the sector from programs or erases. Since this is a volatile bit, removing power or resetting the device clears the DYBs. The
bank address is latched when the command is written.

n
The PPB Lock command is permitted if the Secured Silicon sector is enabled.

ig
es
15.27 DYB Status

D
The programming of the DYB for a given sector can be verified by writing a DYB status verify command to the device.

ew
15.28 PPB Status rN
The programming of the PPB for a given sector can be verified by writing a PPB status verify command to the device.
fo

15.29 PPB Lock Bit Status

d
de

The programming of the PPB Lock Bit for a given sector can be verified by writing a PPB Lock Bit status verify command to the
device.
en
m

15.30 Non-volatile Protection Bit Program And Erase Flow

om

The device uses a standard command sequence for programming or erasing the Secured Silicon Sector Protection, Password
Locking, Persistent Sector Protection Mode Locking, or Persistent Protection Bits. Unlike devices that have the Single High Voltage
ec

Sector Unprotect/Protect feature, the device has the standard two-cycle unlock followed by 60h, which places the device into non-
volatile bit program or erase mode. Once the mode is entered, the specific non-volatile bit status is read on DQ0. Figure 15.1
R

on page 40 shows a typical flow for programming the non-volatile bit and Figure 15.2 on page 43 shows a typical flow for erasing the
ot

non-volatile bits. The Secured Silicon Sector Protection, Password Locking, Persistent Sector Protection Mode Locking bits are not
erasable after they are programmed. However, the PPBs are both erasable and programmable (depending upon device security).
N

Unlike Single High Voltage Sector Protect/Unprotect, the A6 pin no longer functions as the program/erase selector nor the program/
erase margin enable. Instead, this function is accomplished by issuing the specific command for either program (68h) or erase (60h).
In asynchronous mode, the DQ6 toggle bit indicates whether the program or erase sequence is active. (In synchronous mode, ADV#
indicates the status.) If the DQ6 toggle bit toggles with either OE# or CE#, the non-volatile bit program or erase operation is in
progress. When DQ6 stops toggling, the value of the non-volatile bit is available on DQ0.

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Table 15.2 Memory Array Command Definitions

Bus Cycles (Notes 1–4)

Cycles
Command (Notes) First Second Third Fourth Fifth Sixth
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read (5) 1 RA RD
Reset (6) 1 XXX F0
Manufacturer ID 4 555 AA 2AA 55 555 90 BA+X00 01
09 for
Autoselect 32 Mb
(7) Device ID (11) 6 555 AA 2AA 55 555 90 BA+X01 7E BA+X0E 36 or BA+X0F 00/01
08 for
16 Mb
Program 4 555 AA 2AA 55 555 A0 PA PD
Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10

n
Sector Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 SA 30

ig
Program/Erase Suspend (12) 1 BA B0

es
Program/Erase Resume (13) 1 BA 30

D
CFI Query (14, 15) 1 55 98
Accelerated Program (16) 2 XX A0 PA PD

ew
Configuration Register Verify (15) 3 555 AA 2AA 55 BA+555 C6 BA+XX RD
Configuration Register Write (17) 4 555 AA 2AA 55 555 rN D0 XX WD
Unlock Bypass Entry (18) 3 555 AA 2AA 55 555 20
Unlock Bypass Program (18) 2 XX A0 PA PD
fo
Unlock Bypass Erase (18) 2 XX 80 XX 10
Unlock Bypass CFI (14, 18) 1 XX 98
d
de

Unlock Bypass Reset (18) 2 XX 90 XX 00

Legend
en

BA = Bank Address. The set of addresses that comprise a bank. The system may write any address within a bank to identify that bank for a
command.
m

PA = Program Address (Amax–A0). Addresses latch on the falling edge of the WE# or CE# pulse, whichever happens later.
PD = Program Data (DQmax–DQ0) written to location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens first.
om

RA = Read Address (Amax–A0).

RD = Read Data. Data DQmax–DQ0 at address location RA.
ec

SA = Sector Address. The set of addresses that comprise a sector. The system may write any address within a sector to identify that sector for a
command.
R

WD = Write Data. See Configuration Register on page 27 definition for specific write data. Data latched on rising edge of WE#.
X = Don’t care
ot

Notes
1. See Table 12.1 on page 19 for description of bus operations.
N

2. All values are in hexadecimal.

3. Shaded cells in table denote read cycles. All other cycles are write operations.
4. During unlock cycles, (lower address bits are 555 or 2AAh as shown in table) address bits higher than A11 (except where BA is required) and
data bits higher than DQ7 are don’t cares.
5. No unlock or command cycles required when bank is reading array data.
6. The Reset command is required to return to the read mode (or to the erase-suspend-read mode if previously in Erase Suspend) when a bank
is in the autoselect mode, or if DQ5 goes high (while the bank is providing status information).
7. The fourth cycle of the autoselect command sequence is a read cycle. The system must provide the bank address to obtain the manufacturer
ID or device ID information. See Autoselect Command on page 38 for more information.
8. This command cannot be executed until The Unlock Bypass command must be executed before writing this command sequence. The Unlock
Bypass Reset command must be executed to return to normal operation.
9. This command is ignored during any embedded program, erase or suspended operation.
10. Valid read operations include asynchronous and burst read mode operations.
11. The device ID must be read across the fourth, fifth, and sixth cycles. 00h in the sixth cycle indicates ordering option 00, 01h indicates ordering
option 01.
12. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Program/Erase Suspend mode. The
Program/Erase Suspend command is valid only during a sector erase operation, and requires the bank address.
13. The Program/Erase Resume command is valid only during the Erase Suspend mode, and requires the bank address.

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14. Command is valid when device is ready to read array data or when device is in autoselect mode.
15. Asynchronous read operations.
16. ACC must be at VID during the entire operation of this command.
17. Command is ignored during any Embedded Program, Embedded Erase, or Suspend operation.
18. The Unlock Bypass Entry command is required prior to any Unlock Bypass operation. The Unlock Bypass Reset command is required to return
to the read mode.

n
ig
es
D
ew
rN
fo
d
de
en
m
om
ec
R
ot
N

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Table15. 3. Sector Protection Command Definitions

Bus Cycles (Notes 1 – 4)

Cycles
Command (Notes) First Second Third Fourth Fifth Sixth
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Reset 1 XXX F0
Secured Silicon Sector Entry 3 555 AA 2AA 55 555 88
Secured Silicon Sector Exit 4 555 AA 2AA 55 555 90 XX 00
Secured Silicon Protection Bit
6 555 AA 2AA 55 555 60 OW RD(0)
Status
Password Program (5, 7, 8) 4 555 AA 2AA 55 555 38 PWA[0-1] PWD[0-1]
Password Verify 4 555 AA 2AA 55 555 C8 PWA[0-1] PWD[0-1]
Password Unlock (7, 8) 5 555 AA 2AA 55 555 28 PWA[0-1] PWD[0-1]
PPB Program (5, 6) 6 555 AA 2AA 55 555 60 SG+WP 68 SG+WP 48 SG+WP RD(0)

n
All PPB Erase (5, 9, 10) 6 555 AA 2AA 55 555 60 WP 60 WP 40 WP RD(0)

ig
PPB Status (11, 12) 4 555 AA 2AA 55 BA+555 90 SA+X02 00/01

es
PPB Lock Bit Set 3 555 AA 2AA 55 555 78
PPB Lock Bit Status 4 555 AA 2AA 55 BA+555 58 SA RD(1)

D
DYB Write (7) 4 555 AA 2AA 55 555 48 SA X1

ew
DYB Erase (7) 4 555 AA 2AA 55 555 48 SA X0
DYB Status (12) 4 555 AA 2AA 55 BA+555 58 SA RD(0)
PPMLB Program (5, 8) 6 555 AA 2AA 55 555
rN
60 PL 68 PL 48 PL RD(0)
PPMLB Status (5) 6 555 AA 2AA 55 555 60 PL RD(0)
fo
SPMLB Program (5, 8) 6 555 AA 2AA 55 555 60 SL 68 SL 48 SL RD(0)
SPMLB Status (5) 6 555 AA 2AA 55 555 60 SL RD(0)
d

Legend
de

DYB = Dynamic Protection Bit

OW = Address (A5–A0) is (011X10).
en

PPB = Persistent Protection Bit

PWA = Password Address. A0 selects between the low and high 32-bit portions of the 64-bit Password
m

PWD = Password Data. Must be written over two cycles.

om

PL = Password Protection Mode Lock Address (A5–A0) is (001X10)

RD(0) = Read Data DQ0 protection indicator bit. If protected, DQ0= 1, if unprotected, DQ0 = 0.
RD(1) = Read Data DQ1 protection indicator bit. If protected, DQ1 = 1, if unprotected, DQ1 = 0.
ec

SA = Sector Address. The set of addresses that comprise a sector. The system may write any address within a sector to identify that sector for a
command.
R

SG = Sector Group Address

BA = Bank Address. The set of addresses that comprise a bank. The system may write any address within a bank to identify that bank for a
ot

command.
N

SL = Persistent Protection Mode Lock Address (A5–A0) is (010X10)

WP = PPB Address (A5–A0) is (111010)
X = Don’t care
PPMLB = Password Protection Mode Locking Bit
SPMLB = Persistent Protection Mode Locking Bit
Notes
1. See Table 12.1 on page 19 for description of bus operations.
2. All values are in hexadecimal.
3. Shaded cells in table denote read cycles. All other cycles are write operations.
4. During unlock cycles, (lower address bits are 555 or 2AAh as shown in table) address bits higher than A11 (except where BA is required) and
data bits higher than DQ7 are don’t cares.
5. The reset command returns the device to reading the array.
6. The fourth cycle programs the addressed locking bit. The fifth and sixth cycles are used to validate whether the bit is fully programmed. If DQ0
(in the sixth cycle) reads 0, the program command must be issued and verified again.
7. Data is latched on the rising edge of WE#.
8. The entire four bus-cycle sequence must be entered for each portion of the password.
9. The fourth cycle erases all PPBs. The fifth and sixth cycles are used to validate whether the bits were fully erased. If DQ0 (in the sixth cycle)
reads 1, the erase command must be issued and verified again.
10. Before issuing the erase command, all PPBs should be programmed in order to prevent over-erasure of PPBs.

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11. In the fourth cycle, 00h indicates PPB set; 01h indicates PPB not set.
12. The status of additional PPBs and DYBs may be read (following the fourth cycle) without reissuing the entire command sequence.

16. Write Operation Status

The device provides several bits to determine the status of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7, and RY/BY#. Table 16.1
on page 55 and the following subsections describe the functions of these bits. DQ7, RY/BY#, and DQ6 each offer a method for
determining whether a program or erase operation is complete or in progress. These three bits are discussed first.

16.1 DQ7: Data# Polling

The device features a Data# polling flag as a method to indicate to the host system whether the embedded algorithms are in
progress or are complete. During the Embedded Program Algorithm, an attempt to read the bank in which programming was
initiated produces the complement of the data last written to DQ7. Upon completion of the Embedded Program Algorithm, an attempt
to read the device produces the true last data written to DQ7. Note that DATA# polling returns invalid data for the address being

n
programmed or erased.

ig
For example, the data read for an address programmed as 0000 0000 1000 0000b, returns XXXX XXXX 0XXX XXXXb during an

es
Embedded Program operation. Once the Embedded Program Algorithm is complete, the true data is read back on DQ7. Note that at

D
the instant when DQ7 switches to true data, the other bits may not yet be true. However, they are all true data on the next read from
the device. Please note that Data# polling may give misleading status when an attempt is made to write to a protected sector.

ew
For chip erase, the Data# polling flag is valid after the rising edge of the sixth WE# pulse in the six write pulse sequence. For sector
erase, the Data# polling is valid after the last rising edge of the sector erase WE# pulse. Data# polling must be performed at sector
rN
addresses within any of the sectors being erased and not a sector that is a protected sector. Otherwise, the status may not be valid.
DQ7 = 0 during an Embedded Erase Algorithm (chip erase or sector erase operation), but returns a 1 after the operation completes
fo
because it drops back into read mode.
d

In asynchronous mode, just prior to the completion of the Embedded Algorithm operations, DQ7 may change asynchronously while
de

OE# is asserted low. (In synchronous mode, ADV# exhibits this behavior.) The status information may be invalid during the instance
of transition from status information to array (memory) data. An extra validity check is therefore specified in the data polling
en

algorithm. The valid array data on DQ31–DQ0 is available for reading on the next successive read attempt.
The Data# polling feature is only active during the Embedded Programming Algorithm, Embedded Erase Algorithm, Erase Suspend,
m

Erase Suspend-Program mode, or sector erase time-out.

om

If the user attempts to write to a protected sector, Data# polling is activated for about 1 µs: the device then returns to read mode, with
the data from the protected sector unchanged. If the user attempts to erase a protected sector, Toggle Bit (DQ6) is activated for
ec

about 150 µs; the device then returns to read mode, without having erased the protected sector.
R

Table 16.1 on page 55 shows the outputs for Data# Polling on DQ7. Figure 16.1 on page 52 shows the Data# Polling algorithm.
Figure 24.10 on page 68 shows the timing diagram for synchronous status DQ7 data polling.
ot
N

16.2 RY/BY#: Ready/Busy#

The device provides a RY/BY# open drain output pin as a way to indicate to the host system that the Embedded Algorithms are
either in progress or completed. If the output is low, the device is busy with either a program, erase, or reset operation. If the output
is floating, the device is ready to accept any read/write or erase operation. When the RY/BY# pin is low, the device does not accept
any additional program or erase commands with the exception of the Erase suspend command. If the device enters Erase Suspend
mode, the RY/BY# output is floating. For programming, the RY/BY# is valid (RY/BY# = 0) after the rising edge of the fourth WE#
pulse in the four write pulse sequence. For chip erase, the RY/BY# is valid after the rising edge of the sixth WE# pulse in the six write
pulse sequence. For sector erase, the RY/BY# is also valid after the rising edge of the sixth WE# pulse.

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Figure 16.1 Data# Polling Algorithm

START

Read DQ7–DQ0
Addr = VA

Yes
DQ7 = Data?

No

n
ig
No DQ5 = 1?

es
D
Yes

ew
Read DQ7–DQ0 rN
Addr = VA
fo

Yes
d

DQ7 = Data?
de
en

No
m

FAIL PASS
om

Notes
1. VA = Valid address for programming. During a sector erase operation, a valid address is an address within any sector selected for erasure. During chip erase, a valid
ec

address is any non-protected sector address.

2. DQ7 should be rechecked even if DQ5 = 1 because DQ7 may change simultaneously with DQ5
R
ot

If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a 0 (busy) until the internal reset operation is
complete, which requires a time of tREADY (during Embedded Algorithms). The system can thus monitor RY/BY# to determine
N

whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin is
floating), the reset operation is completed in a time of tREADY (not during Embedded Algorithms). The system can read data tRH after
the RESET# pin returns to VIH.
Since the RY/BY# pin is an open-drain output, several RY/BY# pins can be tied together in parallel with a pull-up resistor to VCC. An
external pull-up resistor is required to take RY/BY# to a VIH level since the output is an open drain.
Table 16.1 on page 55 shows the outputs for RY/BY#. Figure 24.2 on page 61, Figure 24.6 on page 65, and Figure 24.8 on page 67
show RY/BY# for read, reset, program, and erase operations, respectively.

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16.3 DQ6: Toggle Bit I

Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device
entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE# pulse
in the command sequence (prior to the program or erase operation), and during the sector erase time-out.
During an Embedded Program or Erase algorithm operation, two immediately consecutive read cycles to any address cause DQ6 to
toggle. When the operation is complete, DQ6 stops toggling. For asynchronous mode, either OE# or CE# can be used to control the
read cycles. For synchronous mode, the rising edge of ADV# is used or the rising edge of clock while ADV# is Low.
After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately 100 µs,
then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected
sectors, and ignores the selected sectors that are protected.
The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase-suspended. When the
device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase
Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erase-

n
suspended. Alternatively, the system can use DQ7 (See DQ7: Data# Polling on page 51).

ig
If a program address falls within a protected sector, DQ6 toggles for approximately 1 µs after the program command sequence is

es
written, then returns to reading array data.

D
DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program algorithm is complete.

ew
Table 16.1 on page 55 shows the outputs for Toggle Bit I on DQ6. Figure 16.2 on page 54 shows the toggle bit algorithm in flowchart
form, and Reading Toggle Bits DQ6/DQ2 on page 53 explains the algorithm. Figure 24.11 on page 68 shows the toggle bit timing
rN
diagrams. Figure 24.12 on page 69 shows the differences between DQ2 and DQ6 in graphical form. Also see DQ2: Toggle Bit II
on page 53. Figure 24.11 on page 68 shows the timing diagram for synchronous toggle bit status.
fo

16.4 DQ2: Toggle Bit II

d
de

The Toggle Bit II on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the Embedded
Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE#
en

pulse in the command sequence.

m

DQ2 toggles when the system performs two immediately consecutive reads at addresses within those sectors that were selected for
erasure. (For asynchronous mode, either OE# or CE# can be used to control the read cycles. For synchronous mode, ADV# is
om

used.) But DQ2 cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates
whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus,
ec

both status bits are required for sector and mode information. Refer to Table 16.1 on page 55 to compare outputs for DQ2 and DQ6.
R

Toggle bit algorithm in is shown in Figure 16.2 on page 54 in flowchart form, and the algorithm is explained in Reading Toggle Bits
DQ6/DQ2 on page 53. Also see DQ6: Toggle Bit I on page 53. Figure 24.11 on page 68 shows the toggle bit timing diagram.
ot

Figure 24.12 on page 69 shows the differences between DQ2 and DQ6 in graphical form. Figure 24.13 on page 69 shows the timing
N

diagram for synchronous DQ2 toggle bit status.

16.5 Reading Toggle Bits DQ6/DQ2

Refer to Figure 24.11 on page 68 for the following discussion. Whenever the system initially begins reading toggle bit status, it must
perform two immediately consecutive reads of DQ7–DQ0 to determine whether a toggle bit is toggling. Typically, the system would
note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the
toggle bit with the first. If the toggle bit is not toggling, the device completed the program or erase operation. The system can read
array data on DQ7–DQ0 on the following read cycle.
However, if after the initial two immediately consecutive read cycles, the system determines that the toggle bit is still toggling, the
system also should note whether the value of DQ5 is high (See DQ5: Exceeded Timing Limits on page 54). If it is, the system should
then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the
toggle bit is no longer toggling, the device successfully completed the program or erase operation. If it is still toggling, the device did
not complete the operation successfully, and the system must write the reset command to return to reading array data.
The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system
may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous

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paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the
algorithm when it returns to determine the status of the operation (top of Figure 16.2).

Figure 16.2 Toggle Bit Algorithm

START

Read Byte
(DQ0-DQ7)
Address = VA
(Note 1)
Read Byte
(DQ0-DQ7)
Address = VA

n
ig
No

es
DQ6 = Toggle?

D
Yes

ew
No
DQ5 = 1? rN
Yes
fo
d

Read Byte Twice

(DQ 0-DQ7)
de

Adrdess = VA
(Notes 1, 2)
en

No
m

DQ6 = Toggle?
om

Yes
ec

FAIL PASS
R

Notes
ot

1. Read toggle bit with two immediately consecutive reads to determine whether or not it is toggling.
N

2. Recheck toggle bit because it may stop toggling as DQ5 changes to 1.

16.6 DQ5: Exceeded Timing Limits

DQ5 indicates whether the program or erase time exceeded a specified internal pulse count limit. Under these conditions DQ5
produces a 1. This is a failure condition that indicates the program or erase cycle was not successfully completed.
The DQ5 failure condition may appear if the system tries to program a 1 to a location that is previously programmed to 0. Only an
erase operation can change a 0 back to a 1. Under this condition, the device halts the operation, and when the operation exceeds
the timing limits, DQ5 produces a 1.
Under both these conditions, the system must issue the reset command to return the device to reading array data.

16.7 DQ3: Sector Erase Timer

After writing a sector erase command sequence, the system may read DQ3 to determine whether or not an erase operation started.
(The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out
also applies after each additional sector erase command. When the time-out is complete, DQ3 switches from 0 to 1. The system

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may ignore DQ3 if the system can guarantee that the time between additional sector erase commands is always less than 50 µs.
Also see Sector Erase Command on page 41.
After the sector erase command sequence is written, the system should read the status on DQ7 (Data# Polling) or DQ6 (Toggle Bit
I) to ensure the device accepted the command sequence, and then read DQ3. If DQ3 is 1, the internally controlled erase cycle
started; all further commands (other than Erase Suspend) are ignored until the erase operation is complete. If DQ3 is 0, the device
accepts additional sector erase commands. To ensure the command is accepted, the system software should check the status of
DQ3 prior to and following each subsequent sector erase command. If DQ3 is high on the second status check, the last command
might not have been accepted. Table 16.1 shows the outputs for DQ3.

Table 16.1 Write Operation Status

DQ7 DQ5 DQ2
Operation DQ6 DQ3 RY/BY#
(Note 2) (Note 1) (Note 2)
Standard Embedded Program Algorithm DQ7# Toggle 0 N/A No toggle 0
Mode Embedded Erase Algorithm 0 Toggle 0 1 Toggle 0

n
Reading within Erase

ig
1 No toggle 0 N/A Toggle 1
Suspended Sector
Erase

es
Suspend Reading within Non-Erase
Data Data Data Data Data 1
Mode Suspended Sector

D
Erase-Suspend-Program DQ7# Toggle 0 N/A N/A 0

ew
Notes
1. DQ5 switches to 1 when an Embedded Program or Embedded Erase operation exceeds the maximum timing limits. See DQ5: Exceeded Timing Limits on page 54 for
more information. rN
2. DQ7 and DQ2 require a valid address when reading status information. See DQ7: Data# Polling on page 51 and DQ2: Toggle Bit II on page 53 for further details.
fo

17. Absolute Maximum Ratings

d
de

Storage Temperature, Plastic Packages –65°C to +150°C

en

Ambient Temperature with Power Applied –65°C to +145°C

VCC, VIO (Notes 1, 5) -0.5 V to + 3.0V (16Mb), -0.5V to + 2.75V (32Mb)
m

ACC, A9, OE#, and RESET# (Note 2) –0.5 V to +13.0 V

om

Address, Data, Control Signals

Except CLK (Notes 1, 6) -0.5V to 3.6V (16 Mb), –0.5 V to 2.75 V (32 Mb)
ec

All other pins (Notes 1, 6) -0.5V to 3.6V (16 Mb),–0.5 V to 2.75 V (32 Mb)
Output Short Circuit Current (Note 3) 200 mA
R

Notes
ot

1. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, input at I/O pins may overshoot VSS to -2.0V for periods of up to 20 ns. See Figure 17.2
on page 56. Maximum DC voltage on output and I/O pins is 3.6V (16Mb), 2.75V (32Mb). During voltage transitions output pins may overshoot to VCC + 2.0V for periods
N

up to 20 ns. See Figure 17.2 on page 56.

2. Minimum DC input voltage on pins ACC, A9, OE#, and RESET# is -0.5 V. During voltage transitions, A9, OE#, and RESET# may overshoot VSS to -2.0V for periods of
up to 20 ns. See Figure 17.1 on page 56. Maximum DC input voltage on pin A9 and OE# is +13.0 V which may overshoot to 14.0 V for periods up to 20 ns.
3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second.
4. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum
rating conditions for extended periods may affect device reliability.
5. Parameter describes VIO power supply.
6. Parameter describes I/O pin voltage tolerances.

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Figure 17.1 Maximum Negative Overshoot Waveform

20 ns 20 ns

+0.8 V

–0.5 V

–2.0 V

20 ns

Figure 17.2 Maximum Positive Overshoot Waveform

20 ns

n
ig
V CC +2.0 V

es
D
V CC +0.5 V

ew
2.0 V

20 ns rN 20 ns
fo
18. Operating Ranges
d

Industrial (I) Devices

de

Ambient Temperature (TA) –40°C to +85°C

en

Extended (E) Devices

m

Ambient Temperature (TA) –40°C to +125°C

om

VCC Supply Voltages

VCC for 2.6 V regulated voltage range2.50 V to 2.75 V
ec

VIO Supply Voltages

R

VIO 1.65 V to 3.6 V (16 Mb), 1.65 V to 2.75 V (32 Mb)

ot

Note
N

Operating ranges define those limits between which the functionality of the device is guaranteed.

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19. DC Characteristics

19.1 CMOS Compatible

Parameter Description Test Conditions Min Typ Max Unit
ILI Input Load Current VIN = VSS to VIO, VIO = VIO max 1.0
ILIWP WP# Input Load Current VIN = VSS to VIO, VIO = VIO max –25
µA
ILIT A9, ACC Input Load Current VCC = VCCmax; A9 = 12.5 V 35
ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC max 1.0

CE# = VIL, 56 MHz 8 Double

ICCB VCC Active Burst Read Current (1) 70 90
OE# = VIL 66, 75 MHz Word

VCC Active Asynchronous

ICC1 CE# = VIL, OE# = VIL 1 MHz 10 mA

n
Read Current (1)

ig
ICC3 VCC Active Program Current (2, 4) CE# = VIL, OE# = VIH, ACC = VIH 40 50

es
ICC4 VCC Active Erase Current (2, 4) CE# = VIL, OE# = VIH, ACC = VIH 20 50
ICC5 VCC Standby Current (CMOS) VCC= VCC max, CE# = VCC  0.3 V 60 µA

D
VCC Active Current
ICC6 CE# = VIL, OE# = VIL 30 90 mA

ew
(Read While Write)
ICC7 VCC Reset Current () RESET# = VIL 60 µA
ICC8 Automatic Sleep Mode Current
rN
VIH = VCC 0.3 V, VIL = VSS 0.3 V 60 µA
IACC VACC Acceleration Current ACC = VHH 20 mA
fo
VIL Input Low Voltage –0.5 0.3 x VIO
VIH Input High Voltage 0.7 x VIO VCC
d
de

VILCLK CLK Input Low Voltage –0.2 0.3 x VIO

V
VIHCLK CLK Input High Voltage 0.7 x VCC 2.75
en

VID Voltage for Autoselect VCC = 2.5 V 11.5 12.5

VOL Output Low Voltage IOL = 4.0 mA, VCC = VCC min 0.45
m

IOLRB RY/BY#, Output Low Current VOL = 0.4 V 8 mA

om

VHH Accelerated (ACC pin) High Voltage IOH = –2.0 mA, VCC = VCC min 0.85 x VCC
VOH Output High Voltage IOH = –100 µA, VCC = VCC min VIO –0.1 V
ec

VLKO Low VCC Lock-Out Voltage (3) 1.6 2.0

R

Notes
1. The ICC current listed includes both the DC operating current and the frequency dependent component.
ot

2. ICC active while Embedded Erase or Embedded Program is in progress.

N

3. Not 100% tested.

4. Maximum ICC specifications are tested with VCC = VCCmax.

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19.2 Zero Power Flash

Figure 19.1 ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents)

Supply Current in mA

n
1

ig
es
0

D
0 500 1000 1500 2000 2500 3000 3500 4000

Time in ns

ew
Note rN
Addresses are switching at 1 MHz
fo
Figure 19.2 Typical ICC1 vs. Frequency
d

5
de
en

2.7 V
Supply Current in mA

4
m
om

3
ec
R

2
ot
N

0
1 2 3 4 5

Frequency in MHz

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20. Test Conditions

Figure 20.1 Test Setup

Device
Under
Test

CL

Note
Diodes are IN3064 or equivalent.

n
ig
21. Test Specifications

es
Table 21.1 Test Specifications

D
Test Condition 40 MHz, 56 MHz 66 MHz, 75MHz Unit

ew
Output Load 1 TTL gate
Output Load Capacitance, CL (including jig capacitance) 30
rN 100 pF
Input Rise and Fall Times 5 ns
fo
Input Pulse Levels 0.0 V – VIO
Input timing measurement reference levels VIO/2 V
d

Output timing measurement reference levels VIO/2

de
en

22. Key to Switching Waveforms

m

Table 1:
om

Waveform Inputs Outputs

ec

Steady
R

Changing from H to L
ot
N

Changing from L to H

Don’t Care, Any Change Permitted Changing, State Unknown

Does Not Apply Center Line is High Impedance State (High Z)

23. Switching Waveforms

Figure 23.1 Input Waveforms and Measurement Levels
VIO
Input VIO/2 V Measurement Level VIO/2 V Output
VSS

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24. AC Characteristics

24.1 VCC and VIO Power-up

Parameter Description Test Setup Speed Unit
tVCS VCC Setup Time
tVIOS VIO Setup Time Min 50 µs
tRSTH RESET# Low Hold Time

Figure 24.1 VCC and VIO Power-up Diagram

n
ig
tVCS

es
D
VCC

ew
tVIOS
rN
fo
VIOP
d

tRSTH
de
en

RESET#
m

24.2 Asynchronous Read Operations

om

Parameter Speed Options

ec

Description Test Setup 75 MHz, 66 MHz, 56 MHz, 40 MHz, Unit

JEDEC Std.
0R 0P 0M OJ
R

tAVAV tRC Read Cycle Time (Note 1) Min 48 54 64 67

ot

CE# = VIL
tAVQV tACC Address to Output Delay Max 48 54 64 67
N

OE# = VIL
tELQV tCE Chip Enable to Output Delay OE# = VIL Max 52 58 69 71
tGLQV tOE Output Enable to Output Delay Max 20 28
Chip Enable to Output High Z
tEHQZ tDF Max 10
(Note 1)
ns
Min 2
tGHQZ tDF Output Enable to Output High Z (Note 1)
Max 10
Read Min 0
Output Enable Hold Time
tOEH Toggle and Data#
(Note 1) Min 10
Polling
Output Hold Time From Addresses, CE# or OE#,
tAXQX tOH Min 2
Whichever Occurs First (Note 1)

Notes
1. Not 100% tested.
2. See Figure 20.1 on page 59 and Table 21.1 on page 59 for test specifications

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Figure 24.2 Conventional Read Operations Timings

tRC

Addresses Addresses Stable

tACC
CE#

tDF
tOE
OE#
tOEH

WE# tCE
tOH
High Z High Z
Outputs Output Valid

n
ig
RESET#

es
RY/BY#

D
0V

ew
rN
fo
d
de
en
m
om
ec
R
ot
N

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24.3 Burst Mode Read for 32 Mb & 16 Mb

Parameter Speed Options
Description 75 MHz, 0R 66 MHz, 56 MHz, 40 MHz, Unit
JEDEC Std.
32 MHz 0P 0M OJ
9 FBGA 10 FBGA
tBACC Burst Access Time Valid Clock to Output Delay Max 7.5 FBGA 17
9.5 PQFP 10 PQFP
tADVCS ADV# Setup Time to Rising Edge of CLK Min 5.75 6
tADVCH ADV# Hold Time from Rising Edge of CLK Min 1.5 2
tADVP ADV# Pulse Width (32Mb, 75MHz) Min 12 13 15 22
tDVCH Valid Data Hold from CLK (See Note) Min 2 3
9 FBGA 10 FBGA
tDIND CLK to Valid IND/WAIT# Max 7.5 FBGA 17
9.5 PQFP 10 PQFP
tINDH IND/WAIT# Hold from CLK Min 2 3

n
ig
tIACC CLK to Valid Data Out, Initial Burst Access Max 48 54 64 67
Min 13. 15 18 25

es
tCLK CLK Period
Max 60

D
tCLKR CLK Rise Time Max 3

ew
tCLKF CLK Fall Time Max 3
ns
tCKL CLK Low Time Min 2 2.5 3
tCLKH CLK to High Time Min 2
rN 2.5 3
tCES CE# Setup Time to Clock Min 6
fo
16 Mb =3
tCH CE# Hold Time Min
32 Mb = 8
d

tACS Address Setup Time to CLK Min 6

de

Address Hold Time from ADV# Rising

tACH Min 5
en

Edge of CLK while ADV# is Low

tOE Output Enable to Output Valid Max 20 28
m

Min 2 2 3 3
tDF tOEZ Output Enable to Output High Z (See Note)
om

Max 7.5 10 15 17
tEHQZ tCEZ Chip Enable to Output High Z (See Note) Max 7.5 10 15 17
ec

tWADVH WE hold time after ADV falling edge Min 0

tWCKS WE rising edge setup time to clock rising edge Min 5
R

Note
ot

Not 100% tested.

N

Document Number: 002-01299 Rev. *B Page 62 of 78

 S29CD032G
S29CD016G

Figure 24.3 Burst Mode Read

tCES tCEZ
CE#

CLK
tADVCS
ADV#
tADVCH
tACS
Addresses Aa
tDVCH tBACC
tACH
Data
tIACC Da Da + 1 Da + 2 Da + 3 Da + 31

n
ig
tOE tOEZ
OE#*

es
D
IND#

ew
rN
Figure 24.4 Asynchronous Command Write Timing
fo

CLK
d
de

ADV#
en

CE#
m

tCS tCH
om

Addresses Stable Address

tWC
ec

Data Valid Data

R

tAS tAH
tDS tDH
ot

WE# tOEH
N

OE#
tWPH

IND/WAIT#

Note
All commands have the same number of cycles in both asynchronous and synchronous modes, including the READ/RESET command. Only a single array access occurs
after the F0h command is entered. All subsequent accesses are burst mode when the burst mode option is enabled in the Configuration Register.

Document Number: 002-01299 Rev. *B Page 63 of 78

 S29CD032G
S29CD016G

Figure 24.5 Synchronous Command Write/Read Timing

CE#
tCES

CLK
tADVCS
tADVP
ADV#
ttACS
AS tACH tACS tACH
Addresses Valid Address Valid Address
tWC tEHQZ
tADVCH

Data Data In Data Out

n
ig
tDF
tWADVH tWCKS
tOE

es
OE# tDH
tDS

D
tWP
WE#

ew
10 ns

IND/WAIT#
rN
Note
All commands have the same number of cycles in both asynchronous and synchronous modes, including the READ/RESET command. Only a single array access occurs
fo
after the F0h command is entered. All subsequent accesses are burst mode when the burst mode option is enabled in the Configuration Register.
d
de

24.4 Hardware Reset (RESET#)

en

Parameter Test All Speed

Description Unit
m

JEDEC Std. Setup Options

om

RESET# Pin Low (During Embedded Algorithms)

tREADY Max 11 µs
to Read or Write (See Note)
RESET# Pin Low (NOT During Embedded Algorithms)
ec

tREADY Max 500 ns

to Read or Write (See Note)
tRP RESET# Pulse Width Min 500 ns
R

tRH RESET# High Time Before Read (See Note) Min 50 ns

ot

tRPD RESET# Low to Standby Mode Min 20 µs

N

tRB RY/BY# Recovery Time Min 0 ns

Note
Not 100% tested.

Document Number: 002-01299 Rev. *B Page 64 of 78

 S29CD032G
S29CD016G

Figure 24.6 RESET# Timings

RY/BY#

CE#, OE#
tRH

RESET#

tRP
tReady

Reset Timing to Bank NOT Executing Embedded Algorithm

n
Reset Timing to Bank Executing Embedded Algorithm

ig
es
tReady
RY/BY#

D
tRB

ew
CE#, OE# rN
fo
RESET#
d

tRP
de
en

Figure 24.7 WP# Timing

m
om

Data Program/Erase Command

ec

tDS tDH

WE# tWP
R

tWPWS
ot

WP# Valid WP#

N

tCH tWPRH
RY/BY#

Document Number: 002-01299 Rev. *B Page 65 of 78

 S29CD032G
S29CD016G

24.5 Erase/Program Operations

Parameter
Description All Speed Options Unit
JEDEC Std.
tAVAV tWC Write Cycle Time (Note 1) Min 60
tAVWL tAS Address Setup Time Min 0
tWLAX tAH Address Hold Time Min 25
tDVWH tDS Data Setup to WE# Rising Edge Min 18
tWHDX tDH Data Hold from WE# Rising Edge Min 2
Read Recovery Time Before Write ns
tGHWL tGHWL Min 0
(OE# High to WE# Low)
tELWL tCS CE# Setup Time Min 0
tWHEH tCH CE# Hold Time Min 2

n
tWLWH tWP WE# Width Min 25

ig
tWHWL tWPH Write Pulse Width High Min 30

es
tWHWH1 tWHWH1 Programming Operation (Note 2) Double-Word Typ 18 µs

D
tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 1.0 sec.
tVCS VCC Setup Time (Note 1) Min 50 µs

ew
tRB Recovery Time from RY/BY# Min 0
tBUSY RY/BY# Delay After WE# Rising Edge rN Max 90
ns
tWPWS WP# Setup to WE# Rising Edge with Command Min 20
fo
tWPRH WP# Hold after RY/BY# Rising Edge Min 2

Notes
d

1. Not 100% tested.

de

2. See Command Definitions on page 37 for more information.

en
m

Program Command Sequence (last two cycles) Read Status Data (last two cycles)
tWC tAS
om

Addresses 555h PA PA PA
tAH
ec

CE#
R

tCH
ot

OE#
N

tWP tWHWH1

WE#
tWPH
tCS
tDS
tDH

Data A0h PD Statu DOUT

tBUSY tRB

RY/BY#

VCC
tVCS
Note
PA = program address, PD = program data, DOUT is the true data at the program address.

Document Number: 002-01299 Rev. *B Page 66 of 78

 S29CD032G
S29CD016G

Figure 24.8 Chip/Sector Erase Operation Timings

Erase Command Sequence (last two cycles) Read Status Data

tWC tAS
Addresses 2AAh SA VA VA
555h for chip erase
tAH
CE#

OE# tCH

tWP
WE#
tWPH tWHWH2
tCS

n
tDS

ig
tDH

es
In
Data 55h 30h Progress Complete

D
10 for Chip Erase

tBUSY tRB

ew
RY/BY# rN
tVCS
VCC
fo
d

Note
de

SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see Write Operation Status on page 51).
en
m

Figure 24.9 Back-to-Back Cycle Timings

om

tWC tRC tWC tWC

ec

Addresses Valid PA Valid RA Valid PA Valid PA

tAH
R

tACC tCPH
tCE
ot

CE#
tCP
N

tOE
OE#

tOEH tGHWL
tWP tWPH

WE#
tDF
tWPH tDS
tDH tOH
Valid Valid Valid Valid
Data
In Out In In

tSR/W
WE# Controlled Write Cycle Read Cycle CE# Controlled Write Cycles

Document Number: 002-01299 Rev. *B Page 67 of 78

 S29CD032G
S29CD016G

Figure 24.10 Data# Polling Timings (During Embedded Algorithms)

tWC
tRC
Addresses VA VA VA
tACC
tCE
CE#

tCH
tOE
OE#
tOEH tDF
WE#
tOH
High Z
DQ7 Complement Complement True Valid Data

n
ig
High Z
Data Status Data Status Data True Valid Data

es
tBUSY

D
RY/BY#

ew
Note
VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.
rN
fo

Figure 24.11 Toggle Bit Timings (During Embedded Algorithms)

d

tRC
de

Addresses VA VA VA VA
en

tACC
tCE
m

CE#
om

tCH
tOE
OE#
ec

tOEH tDF
WE#
R

tOH
High Z
ot

DQ6/DQ2 Valid Status Valid Status Valid Status Valid Data

(first read) (second read) (stops toggling)
N

tBUSY

RY/BY#

Note
VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle.

Document Number: 002-01299 Rev. *B Page 68 of 78

 S29CD032G
S29CD016G

Figure 24.12 DQ2 vs. DQ6 for Erase/Erase Suspend Operations

Enter Embedded Erase Enter Erase Erase
Erasing Suspend Suspend Program Resume
WE#
Erase Erase Suspend Erase Suspend Erase Suspend Erase Erase
Read Program Read Complete

DQ6

DQ2

Note
The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an erase-suspended sector.

Figure 24.13 Synchronous Data Polling Timing/Toggle Bit Timings

n
ig
CE#

es
CLK

D
ew
AVD#

Addresses VA
rN VA
fo

OE#
d

tOE tOE
de

Data Status Data Status Data

en

RDY
m

Notes
om

1. The timings are similar to synchronous read timings and asynchronous data polling Timings/Toggle bit Timing.
2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete, the toggle bits stop toggling.
ec

3. RDY is active with data (A18 = 0 in the Configuration Register). When A18 = 1 in the Configuration Register, RDY is active one clock cycle before data.
4. Data polling requires burst access time delay.
R
ot
N

Document Number: 002-01299 Rev. *B Page 69 of 78

 S29CD032G
S29CD016G

Figure 24.14 Sector Protect/Unprotect Timing Diagram

VIH
RESET#

SA, A6,
Valid* Valid* Valid*
A1, A0
Sector Protect/Unprotect Verify

Data 60h 60h/68h** 40h/48h*** Status

Sector Protect: 150 µs

1 µs Sector Unprotect: 15 ms

CE#

n
ig
WE#

es
D
OE#

ew
Note
* Valid address for sector protect: A[7:0] = 3Ah. Valid address for sector unprotect: A[7:0] = 3Ah.
** Command for sector protect is 68h. Command for sector unprotect is 60h.
*** Command for sector protect verify is 48h. Command for sector unprotect verify is 40h.
rN
fo

24.6 Alternate CE# Controlled Erase/Program Operations

d
de

Parameter All Speed

Description Unit
Options
en

JEDEC Std.
tAVAV tWC Write Cycle Time (Note 1) Min 65
m

tAVEL tAS Address Setup Time Min 0

om

tELAX tAH Address Hold Time Min 45

tDVEH tDS Data Setup Time Min 35
ec

tEHDX tDH Data Hold Time Min 2

tOES Output Enable Setup Time Min
R

ns
tGHEL tGHEL Read Recovery Time Before Write (OE# High to WE# Low) Min
ot

0
tWLEL tWS WE# Setup Time Min
N

tEHWH tWH WE# Hold Time Min

tWP WE# Width Min 32
tELEH tCP CE# Pulse Width Min 16
tEHEL tCPH CE# Pulse Width High Min 30
tWHWsH1 tWHWH1 Programming Operation (Note 2) Double-Word Typ 18 µs
tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 1 sec.

Notes
1. Not 100% tested.
2. See Command Definitions on page 37 for more information.

Document Number: 002-01299 Rev. *B Page 70 of 78

 S29CD032G
S29CD016G

Figure 24.15 Alternate CE# Controlled Write Operation Timings

555 for program PA for program
2AA for erase SA for sector erase
555 for chip erase
Data# Polling

Addresses PA
tWC tAS
tAH
tWH tWPH
tWP
WE#
tGHEL
OE#
tWHWH1 or 2

n
tCP

ig
CE#

es
tWS tCPH
tBUSY

D
tDS
tDH

ew
DQ7# DOUT
Data
tRH A0 for program
rN
PD for program
55 for erase 30 for sector erase
10 for chip erase
fo

RESET#
d
de

RY/BY#
en

Notes
m

1. PA = program address, PD = program data, DQ7# = complement of the data written to the device, DOUT = data written to the device.
om

2. Figure indicates the last two bus cycles of the command sequence.
ec

25. Erase and Programming Performance

R

Typ Max
Parameter Unit Comments
ot

(Note 1) (Note 2)
N

Sector Erase Time 1.0 5 s

Excludes 00h programming prior to erasure
16 Mb = 46 16 Mb = 230
Chip Erase Time s (Note 4)
32 Mb = 78 32 Mb = 460
Double Word Program Time 18 250 µs
Accelerated Double Word Program Time 8 130 µs
16 Mb = 5 16 Mb = 50
Accelerated Chip Program Time s Excludes system level overhead (Note 5)
32 Mb = 10 32 Mb = 100
16 Mb = 12 16 Mb = 120
Chip Program Time (Note 3) x32 s
32 Mb = 24 32 Mb = 240

Notes
1. Typical program and erase times assume the following conditions: 25C, 2.5 V VCC, 100K cycles. Additionally, programming typicals assume checkerboard pattern.
2. Under worst case conditions of 145°C, VCC = 2.5 V, 1M cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 15.2 on page 48 and Table 15. 3
on page 50 for further information on command definitions.
6. PPBs have a program/erase cycle endurance of 100 cycles.

Document Number: 002-01299 Rev. *B Page 71 of 78

 S29CD032G
S29CD016G

26. Latchup Characteristics

Description Min Max
Input voltage with respect to VSS on all pins except I/O pins (including A9, ACC, and WP#) –1.0 V 12.5 V
Input voltage with respect to VSS on all I/O pins –1.0 V VCC + 1.0 V
VCC Current –100 mA +100 mA

Note
Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time.

27. PQFP and Fortified BGA Pin Capacitance

Parameter Symbol Parameter Description Test Setup Typ Max Unit
CIN Input Capacitance VIN = 0 6 7.5 pF

n
ig
COUT Output Capacitance VOUT = 0 8.5 12 pF

es
CIN2 Control Pin Capacitance VIN = 0 7.5 9 pF

Notes

D
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz.

ew
rN
fo
d
de
en
m
om
ec
R
ot
N

Document Number: 002-01299 Rev. *B Page 72 of 78

 S29CD032G
S29CD016G

28. Document History Page

Document Title:S29CD032G, S29CD016G 32 Mbit (1M x 32-Bit), 16 Mbit (512K x 32-Bit), 2.5 V, Burst, Dual Boot Flash
Document Number: 002-01299
Orig. of Submission
Rev. ECN No. Description of Change
Change Date
** - RYSU 03/22/2004 Spansion Publication Number: S29CD-G_00
A1:Performance Characteristics
Burst Mode Read: changed to 66-MHz.
Ordering Information
Changed device number/description call out to show the two 16-Mbit
configurations.
Table 12 and Table 13

n
ig
Corrected which sectors report to which bank.
Asynchronous Read Operations Table

es
Removed the OR Speed option.

D
** - RYSU 05/24/2004 A2:“Spansion” logo
Replaces AMD in bullet seven, first column.

ew
Fujitsu MBM29LV and MBM129F
rN
Added to bullet ten, first column.
Ultra Low Power Consumption Bullet
fo
“capable of...” deleted from first bullet, second column.
Block diagram
d

Reset# moved, RY/BY added.

de

Simultaneous Read/Write Circuit Block Diagram

RY/BY added; Bank 1 added; Bank 0 added.
en

Pin Configuration
m

“A pull-up resistor of 10k...” added to RY/BY#.

Ordering Information
om

Additional ordering options updated to “protects sectors 44 and 45”.

Device Number/Description
ec

Bit description altered.

R

Simultaneous Read/Write Operation With Zero Latency

Table 3 and 4 Bank # change.
ot

Auto Select Mode

N

Table 5: Manufacturer ID Row updated (A3, A2).

Table 5: DQ7 to DQ0 Column updated.
Linear Burst Read Operations
Table 6: “(x16)” removed from header row.
IND/Wait# Operation in Linear Mode
Figure 2 - “Address 2” removed.
Initial Burst Access Delay Control
Figure 3 - Valid Address line changed.
Notes - Clock cycles updated.
Configuration Register
Table 9: CR14 reserve bit assigned ASD.
Table 9: Speed options changed.
Table 10: CR14 reserve changed to ASD.
Table12. Sector Addresses for Ordering Option 00
Bank changed to 0.
Bank changed to 1.

Document Number: 002-01299 Rev. *B Page 73 of 78

 S29CD032G
S29CD016G

Document Title:S29CD032G, S29CD016G 32 Mbit (1M x 32-Bit), 16 Mbit (512K x 32-Bit), 2.5 V, Burst, Dual Boot Flash
Document Number: 002-01299
Orig. of Submission
Rev. ECN No. Description of Change
Change Date
** - RYSU 05/24/2004 Table 13. Sector Addresses for Ordering Option 01
Bank changed to 0.
Bank changed to 1.
Table 16. Device Geometry Definition
0005 = supports x16 and x32 via WORD#...” Removed.
Unlock Bypass Command Sequence
Table “18” replaced with “19” in text.
Table 19. Memory Array Command Definitions (x32 Mode)

n
Autoselect (7) - Device ID (11); Fifth/Data changed to “36”.

ig
Table 20. Sector Protection Command Definitions (x32 Mode)

es
PBB Status (11,12) Third/Addr changed to “SG”. PPB Lock Bit Status;
Third/Addr “BA” removed. DYB Status;

D
Third/Addr changed to “SA”.

ew
Absolute Maximum Ratings
Address, Data... changed to 3.6v.
rN
Table 22 CMOS Compatible
Input High Voltage Max changed to 3.6. RY/BY#, OUtput Low Current Min
fo
removed, Max added (8).
Table 23. Test Specifications
d

Test conditions changed to OJ,OM,OP.

de

AC Characteristics
en

Figure 14 updated RESET#.

Table number 24. Asynchronous Read Operations
m

OM speed options; Output Enable to Output Delay “20” added.

om

Table 26. Hardware Reset

Last row deleted.
ec

Erase/Program Operations
TWADVH row added. TWCKS row added.
R

Table 27. Alternate CE# Controlled Erase/Program Operations

ot

TWPH row added, TWADVH row added, TWCKS row added.

Physical Dimensions
N

Latchup characteristics deleted.

Pin Description
“WAIT# Provides data valid feedback only when the burst length is set to
continuous.” Removed from
document.

Document Number: 002-01299 Rev. *B Page 74 of 78

 S29CD032G
S29CD016G

Document Title:S29CD032G, S29CD016G 32 Mbit (1M x 32-Bit), 16 Mbit (512K x 32-Bit), 2.5 V, Burst, Dual Boot Flash
Document Number: 002-01299
Orig. of Submission
Rev. ECN No. Description of Change
Change Date
** - RYSU 05/26/2004 A3:Block Diagram on page 6
Moved RESET# to point to the State Control/Command Register.
Figure 2, on page 22
Updated note added “Double-Word” to figure title.
Table 9, “Configuration Register Definitions,” on page 24
Added “CR14 = Automatic Sleep Mode...” configurations.
Table 1, “Sector Addresses for Ordering Option 00,” on page 33
Re-inserted previously missing data.

n
Removed “Note 1” from Sector SA1.

ig
Added “Note 3” to Sector SA44 and SA45.

es
Moved Sectors SA15 - SA30 to Bank 1.
Table on page 35

D
Added “Note 3” to Sector SA45.

ew
** - RYSU 11/05/2004 Global
Added reference links
rN
Added Colophon
Updated Trademark
fo
Product Selector Guide
Removed note from Product Selector Guide table
d
de

Block Diagram
Changed text on Input/Output buffers to show DQ0 to DQ31
en

Pin Configuration
Changed text in ACC description
m

Accelerated Program and Erase Operations

om

Changed text in this paragraph

Table 5
ec

Change Address text column.

SecSi Sector Entry Command
R

Changed address text in this paragraph

ot

Figure 18
Changed time spec call out from 10 ns to tWADVH2
N

Table 27
Added new row for tWADVH2

Document Number: 002-01299 Rev. *B Page 75 of 78

 S29CD032G
S29CD016G

Document Title:S29CD032G, S29CD016G 32 Mbit (1M x 32-Bit), 16 Mbit (512K x 32-Bit), 2.5 V, Burst, Dual Boot Flash
Document Number: 002-01299
Orig. of Submission
Rev. ECN No. Description of Change
Change Date
** - RYSU 07/18/2005 Family Data Sheet Revision History
A:Global
Merged S29CD016G and S29CD032G data sheets into one family CD-G
data sheet
Changed data sheet status to “Preliminary Information”
Added in 75MHz parameters
Ordering Information
Model numbers (character 15th & 16th) changed to reflect mask revision,

n
autoselect code and top/bottom

ig
boot

es
Added GT Grade under Temperature Range and Quality Grade
Added note to “Refer to the KGD Data Sheet supplement for die/wafer

D
sales”

ew
Product Selector Guide
Changed Min. Initial clock Delay values
rN
Memory Map and Sector Protect Groups
Modified Notes 1 & 3
fo
Add in Note 4
Simultaneous Read/Write Operation
d

Removed Table 2: Bank Assignment for Boot Bank Sector Device

de

Removed Table 3: Ordering Option 00

en

Removed Table 4: Ordering Option 01

Secured Silicon Sector
m

Added in Electronic Marking

om

Common Flash Memory Interface

Updated web site to reflect Spansion.com
ec

Changed address 28h from 0003h to 0005h

Command Definitions
R

Remove Secured Silicon Protection Bit Program command

Absolute Maximum Ratings
ot

Changed Overshoot/Undershoot to be ± 0.7V from ± 2.0V

N

Changed Address, Data, Control Signals to -0.5V to 3V for 16Mb

Operating Ranges
Changed VIO to 1.65V to 3.6V
Burst Mode Read for 32Mb & 16 Mb
Changed tADVCS = 5.75ns for 75MHz
Changed tADVCH to be 2ns for 66MHz, 56MHz, 40 MHz
Changed tIACC values
Rounded tCLK values
Changed tCR to tCLKR
Changed tCF to tCLKF
Changed tCL to tCLKL
Changed tCH to tCLKH and changed values
Removed tDS, tDH, tAS, tAH, tCS
Added tWADVH, tWCKS

Document Number: 002-01299 Rev. *B Page 76 of 78

 S29CD032G
S29CD016G

Document Title:S29CD032G, S29CD016G 32 Mbit (1M x 32-Bit), 16 Mbit (512K x 32-Bit), 2.5 V, Burst, Dual Boot Flash
Document Number: 002-01299
Orig. of Submission
Rev. ECN No. Description of Change
Change Date
** - RYSU 07/18/2005 Erase/Program Operations
Removed tWCKS
Alternative CE# Controlled Erase/Program Operations
Added tWADVH
Added tWCKS
** - RYSU 11/14/2005 B0:Absolute Maximum Ratings
Changed under/overshoot to ± 2.0V
Changed Vcc, VIO values

n
Changed Address, Data, Control Signal values

ig
Note 5 & 6

es
Revision History
Added in previous revision histories.

D
Erase/Program Operations

ew
Added Note 1 to tWC and tVCS
Global rN
Changed SecSi to Secured Silicon.
** - RYSU 03/03/2009 B1:Global
fo
Added obsolescence information
*A 5051861 RYSU 01/05/2016 Updated to Cypress template
d
de

*B 5074560 RYSU 01/14/2016 Removed "Preliminary" from the datasheet header

Removed the Spansion Revision History
en
m
om
ec
R
ot
N

Document Number: 002-01299 Rev. *B Page 77 of 78

 S29CD032G
S29CD016G
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.

Products PSoC® Solutions

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PSoC ....................................................cypress.com/go/psoc
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Touch Sensing .................................... cypress.com/go/touch

n
USB Controllers....................................cypress.com/go/USB

ig
Wireless/RF .................................... cypress.com/go/wireless

es
D
ew
rN
fo
d
de
en
m
om
ec
R
ot
N

© Cypress Semiconductor Corporation, 2004-2016. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Document Number: 002-01299 Rev.*B Revised January 14, 2016 Page 78 of 78

® ® ® ®
Cypress , Spansion , MirrorBit , MirrorBit Eclipse™, ORNAND™, EcoRAM™, HyperBus™, HyperFlash™, and combinations thereof, are trademarks and registered trademarks of Cypress
Semiconductor Corp. All products and company names mentioned in this document may be the trademarks of their respective holders.