This article has been accepted for publication in a future issue of this journal, but has not been

fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TIA.2019.2919266, IEEE
Transactions on Industry Applications
1

Efficiency and Conducted EMI evaluation of a single-phase power factor correction

boost converter using state-of-the-art SiC MOSFET and SiC diode

Subhadra Tiwari1 , Supratim Basu2 , Tore Undeland1 , and Ole-Morten Midtgård1

1
Norwegian University of Science and Technology, Trondheim, Norway, [email protected]
2
Bose Research PVT. Ltd, Bangalore, India, [email protected]

Abstract—SiC-based diodes and MOSFETs switch extremely with these standards, an active power factor correction (PFC)
quickly with low conduction losses. Thus, from the perspective circuit must be used [2], [3]. However, this solution leads to an
of efficiency, such devices are ideal for a continuous conduction increased pollution within the 20 kHz to 1 GHz range because
mode (CCM) boost power factor correction (PFC) converter.
However, the circuit parasitic becomes alive while switching with it involves a power electronic converter [9]. Therefore, this
high dv/dt and di/dt values, which necessitates the need for EMC active PFC must also satisfy the standard for a high-frequency
compliance measurements. Employing the best available low-loss range; i.e., conducted (150 kHz to 30 MHz) and radiated (30
SiC MOSFET and SiC diode, in this study, a 1 kW PFC boost MHz to 1 GHz) noises must meet the IEC CISPR 16-1-2
converter prototype was designed, developed, and evaluated with regulation [10].
the objective of quantifying the efficiency and electromagnetic
compatibility signature. The efficiency is evaluated through Aside from meeting the mandatory line harmonic require-
two approaches, namely, a circuit simulation and a laboratory ments, as mentioned above, AC-DC power converters also
measurement. With the first approach, the switching losses are require satisfying efficiency-related needs, which are enforced
obtained using a widely accepted double-pulse test methodology, owing to economic and environmental concerns by various
and the conduction losses are taken from the data sheet, whereas programs and organizations, such as the 80 PLUS incentive
with the second approach, the current and voltage are recorded at
the input and output of the PFC converter using power analyzer. program [11], the U.S. Environmental Protection Agency’s
The electromagnetic interference (EMI) is monitored using LISN (EPA) Energy Star [12], and the Climate Saver Computing
and EMC analyzer. To maximize the efficiency, a fast, clean Initiative (CSCI) [13]. As an example, the 80 PLUS certifica-
switching of the SiC is necessary. Utilizing a low-parasitic printed tion requires an efficiency of ≥ 80% at 20%, 50%, and 100%
circuit board design approach and switching the selected low- of the rated load [11].
loss SiC devices with a 0 Ω external gate drive resistance, this
PFC boost yields a peak efficiency of 97.2% at full rated power Comprehensive research into an electromagnetic interfer-
when switched at 250 kHz. Furthermore, the EMI noise was ence (EMI) analysis has been carried out [14]–[20]. In [14],
measured at 66 and 250 kHz. It was found that the same EMI two separate heat sinks are proposed to achieve a better EMC
filter size satisfies the CISPR 11 Class B conducted EMI limit at performance of SiC JFET-based motor drives. Oswald et al.
both switching frequencies with a noise of approximately 10 dB [15] compared the spectra of SiC MOSFET/SiC, SiC MOS-
higher at 250 kHz. As the main contribution of the present study,
the best case efficiency and worst case EMI are evaluated in this FET/Si, and Si IGBT/Si diodes based on switching waveforms
study. obtained from a double-pulse tester, which revealed that SiC
MOSFETs generate higher EMI noise than Si IGBTs within
Index Terms—AC-DC power converters, circuit simulation,
electromagnetic interference, energy efficiency, power MOSFET, a frequency range of 2–50 MHz. Furthermore, the reverse-
printed circuit board layout, Schottky diodes, silicon carbide, recovery effect of silicon carbide (SiC) versus silicon (Si)
switching loss, wide-bandgap semiconductors. diodes was studied in [16], in which it was concluded that
parasitic oscillation during switching transients magnifies the
EMI noise within the corresponding ringing frequency range
I. I NTRODUCTION
in the spectra. In addition, the CM choke sizing for 20 kHz
Rectifiers for AC-DC conversion are widely used in many versus 200 kHz drives [17], the suppression of EMI using
applications, such as switched-mode power supplies (SMPSs), random modulation techniques [18], and optimal EMI filter
pulse width modulated (PWM) motor drives, and uninterrupted designs [19], [20] have been reported.
power supplies (UPSs), which result in non-sinusoidal input To minimize the conduction loss of the diode bridge, various
currents with large harmonic components leading to a poor PFC topologies, such as a boost bridgeless PFC, totem-pole
power factor [1]–[3]. This eventually entails myriad problems, bridgeless PFC, and numerous control strategies have been
for instance, interference with the communication circuits proposed and analyzed [21]–[27]. Since the commercialization
and other equipment; losses and heating of the capacitors, of an SiC Schottky barrier diode (SBD) in 2001, many authors
motors, and transformers; and an accelerated ageing of their have compared the efficiency gain brought about by SiC
insulation [4]–[6]. To improve the power quality, line harmonic SBD over a Si ultra-fast boost diode, primarily focusing on
regulations, namely, EN 61000-3-2 [7] and IEEE Std. 519- minimizing the reverse-recovery loss associated with it [28]–
2014 [8], are established. As an example, for the bus voltage of [34]. A Si super junction MOSFET and SiC SBD were
≤ 1 kV at the point of common coupling (PCC), the IEEE Std. long considered ideal solid-state devices [35]–[39] until the
519-2014 recommends that the individual and total harmonic commercialization of an SiC MOSFET in 2010. For this
distortion be ≤ 5% and ≤ 8%, respectively [8]. To comply application, many publications have reported the use of an

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SiC SBD and SiC MOSFET [40]–[46]. As the best example, Input current 400 V
during MOSFET iL LB id Diode 2.5 A
a 1 kW SiC-based PFC was reported, which resulted in an
efficiency of 97% when switched at 100 kHz [42]. However, turn-on
in this study, a 1 kW SiC-based PFC converter is designed, is ic
vs

EMI Filter
developed, and evaluated using the best available low-loss SiC 85 – 265 V MOSFET
Cout Load
MOSFET and SiC diode. With the goal of fully exploiting a PWM
high switching speed and low-loss capability of SiC devices, a
Rout
low inductive and capacitive printed circuit board (PCB), along ids
with an external gate drive resistance of 0 Ω, is employed.
Initially, through low-inductive measurement connections, a Boost stage
MOSFET turn-on
clean, fast switching of the chosen state-of-the-art SiC devices current Diode reverse
is accomplished. An efficiency of 97.2% is demonstrated when recovery current
switched at 250 kHz. Moreover, EMC compliance was investi-
gated for two different switching frequencies, namely, 66 and
250 kHz, the results of which revealed that the same filter Fig. 1. Schematic diagram of an active PFC boost converter, illustrating the
current paths for the MOSFET and diode in a CCM operation. During the
size satisfies the CISPR Class B conducted EMI regulations boost diode turn-off and boost MOSFET turn-on, the reverse-recovery current
with excellent margins. Overall, to minimize the EMI at the in the diode not only contributes to the switching loss in itself but also to
source, a clean switching approach of an SiC is required; to the turn-on switching loss in the MOSFET, which demands larger die devices
to meet the efficiency and thermal specifications when using a diode with a
obtain the highest efficiency, a clean, fast switching of an SiC large recovery charge.
is indispensable; and to evaluate the converter EMI, a fast
and high-frequency switching of SiC is the most interesting
condition (the EMI is significantly aggravated using fast- simulation in MATLAB. Alternatively, the simulated value of
and high-frequency switching). In the present study, a PFC LB is assured through an analytical expression given in (1)
rectifier was evaluated under such conditions, thus extending [see Appendix]. The output capacitor (Cout ) was designed
the research in this regard. to handle the double-line frequency ripple voltage (∆vout
The remainder of this paper is organized as follows. A = 10 Vpp ) and meet the hold-up time requirement (thold =
description of the converter and its specifications are presented 16.6 ms at the minimum output voltage, vout,min = 350 V).
in Section II. The hardware setup for a double-pulse test (DPT) Both the simulation and analytical approaches are used to
and circuit simulation is then described in Section III, which guarantee the designed size. See the analytical expression
covers the loss measurement using the DPT methodology with used for Cout in (2) [Appendix]. Furthermore, the switching
high-bandwidth measurement equipment and low-inductance frequency was detected by the maximum possible value that a
connections. In addition, a converter loss breakdown is shown commercially available analog controller IC could offer. The
in this section. Section IV focuses on the circuit design controller IC, UCC28180, could operate in CCM mode with
considerations for the clean switching of SiC devices through user programmable switching frequency of 250 kHz.
the design and measurement of a conventional PFC converter Table II shows the part number and specifications of the
prototype. The experiment results are presented in Section V. components, particularly chosen with the goal of maximiz-
Finally, Section VI highlights the major conclusions of the ing the efficiency in a prototype PFC converter. The bridge
present study. diodes are based on Si technology, with the lowest VF of
the commercially available devices. Using an off-the-shelf
II. C ONVERTER DESCRIPTION AND SPECIFICATIONS single sendust core [47] with 85 turns of the copper wire,
a boost inductor is produced that provides an inductance of
A conventional or classical PFC circuit consists of an input approximately 424 µH at zero bias and a DC resistance (DCR)
EMI filter, diode bridge, and boost converter, as shown in
Fig. 1. The primary objective of this circuit is the active
shaping of the input current (is ), allowing it to be in phase TABLE I
with the input AC voltage (vs ), thus minimizing the harmonic S PECIFICATIONS OF PFC BOOST CONVERTER .
distortion. The current paths when the PFC operates in a
Parameters Specifications
continuous conduction mode (CCM) are also illustrated in
Input voltage (vs,min )–(vs,max ) 85–265 V
Fig. 1, which shows that the reverse current resulting from
Line frequency (fline ) 50/60 Hz
parasitic capacitance within the diode contributes to the turn-
Output voltage (vout ) 400 V
on switching loss in the MOSFET apart from the switching
Output power (Pout ) 1 kW
loss in itself.
Switching frequency (fsw ) 250 kHz
Table I shows the specifications of the converter. The
Boost inductor current (∆iL ) 30% @85 V, 1 kW, 250 kHz
input voltage (vs ) has a range (vs,min –vs,max ) of 85–265 V.
Output voltage ripple (∆vout ) 10 Vpp
The line frequency (fline ) is 50/60 Hz, the output voltage
Hold-up time (thold ) 16.6 ms @ vout,min = 350 V
(vout ) is 400 V, and the output power (Pout ) is 1 kW. The
EMI standards CISPR 11 Class B
boost inductor (LB ) is specified such that the ripple current
(∆iL ) is 30% at a low-line voltage (85 V) through a circuit Efficiency regulations 80 PLUS

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Voltage probes
Oscilloscope, 1 GHz 500 MHz &1 GHz

Double-pulse generator Vgs

Current shunt
Vds 1 GHz
I ds
Shunt
Probe-tip adapters
Low-voltage DC power supply Voltage probes
Current probe, 120 MHz

2 single winding inductors in series, 1 pF Ferrite core transformer

(a) Hardware setup. (b) Measurement arrangements.
Fig. 2. Laboratory setup showing the arrangement for current and voltage measurements of the DUT. Double-pulses are generated using a function generator.
The DUT current is measured using a high-bandwidth, low-inductive-current shunt. The voltage is measured using a high-bandwidth single-ended probe,
mounted to the PCB using a probe-tip adaptor for a reduction of the ground-lead inductance.

TABLE II A. Hardware setup and measurement considerations

C HOSEN COMPONENTS WITH THEIR PART NUMBERS AND SPECIFICATIONS .
T HE ON - STATE PARAMETERS ASSOCIATED WITH THE DIODE , VF O AND An image of the laboratory setup used for DPT measure-
Rd , AND MOSFET, RDS,on , ARE TAKEN AT 125 ◦ C [48], [49]. ments of the chosen devices is shown in Fig. 2. To maximize
the high performance achieved by an SiC device, some of
Components Part number Specification
the design techniques implemented in this DPT setup are as
Bridge diode GSIB2580 VF O = 0.98 V, Rd = 22 mΩ
follows. First, slits are made in the PCB between the gate,
LB CS330060 sendust, DCR = 80 mΩ
drain, and source to avoid a coupling capacitance. Second, gate
MOSFET C3M0065090D RDS,on = 82 mΩ
and drain traces are routed either perpendicular or anti-parallel
Boost diode SCS220AE2 VF O = 0.8 V, Rd = 34 mΩ to each other to avoid inserting an external stray capacitance
Cout B43508A5567M062 ESR = 220 mΩ @100 Hz through the PCB. Third, a transmission-line like structure in
which the negative trace runs just below the positive trace
is employed in the PCB design to reduce the stray magnetic
of 80 mΩ. A single-layer winding approach with multiple flux and EMI that occurs from leakage or stray inductance.
parallel wires is used for reducing the AC losses. The boost Furthermore, the positive and negative planes are designed as
MOSFET and diode are based on SiC and chosen based on polygon fills whenever possible in the PCB layout because
state-of-the-art low-loss devices. An effective series resistance this technique increases the size of the area. Moreover, the
(ESR) of Cout is 220 mΩ. The on-state parameters associated main power trace and switching device are placed on the
with the diode, namely, the forward voltage drop (VF O ) and bottom layer; simultaneously, the gate driver parts and the
on-state resistance (Rd ), and with the MOSFET, namely, on- signal traces are placed on the top side of the PCB board. This
state resistance (RDS,on ), are taken at 125 ◦ C, whereas those arrangement minimizes the impact of high dv/dt and di/dt
related to the inductor and capacitor are provided for 25 ◦ C noises from the switching node to the gate side. In addition,
in Table II, which are the inputs for the loss calculation of the small film capacitors (5–10 nF), as indicated in Fig. 3, are
converter. placed close to the SiC devices to provide a low impedance
path to the fast switching signals, and the gate driver is kept as
close as possible to the SiC MOSFET. In a previous study, the
III. H ARDWARE SETUP FOR DOUBLE - PULSE TEST OF S I C authors used an Ansys Q3D extractor (3D FEM simulations) to
DEVICES AND CONVERTER LOSS BREAKDOWN evaluate a similar low-parasitic busbar layout for SiC modules
[50], the knowledge of which is implemented herein.
In this section, a hardware setup designed for the clean Fig. 2 (b) shows a detailed view of low-inductive connec-
switching of an SiC MOSFET and diode is discussed. Fur- tions used for the measurements, in which a PCB probe-
thermore, the connections of the measurement probes in the tip adapter is used to minimize the ground-lead inductance
PCB are illustrated, which is crucial for accurately tracking associated with the return probe of a typical voltage probe.
the fast rising and falling transients. The switching energy A high bandwidth voltage (P5100A, 500 MHz) and current
loss is then quantified through DPT measurements. Finally, a probes (coaxial shunt, SDN-25, 1 GHz), together with a high-
circuit simulation for evaluating the converter loss breakdown bandwidth oscilloscope (DPO5104B, 1 GHz), are used for
is presented. capturing the fast rising and falling transients of an SiC MOS-

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5 nH 5 nH

10 nF 5 nF T1 5 nF 10 nF
D1 Rg ,ext 300
Cdclink Gate Cdclink
Driver 250
IL IL

Energy loss [ J]
200
DUT C1 400 V C1 400 V
Rg ,ext DUT Vsd 150
Gate Vds I sd 100
Driver
I ds Shunt 50
Shunt 2 nH
2 nH 0
0 5 10 15 20 25
Series inductors
Load current [A]
(a) DPT circuit for MOSFET. (b) DPT circuit for diode. (c) Switching energy loss of SiC MOSFET.
Fig. 3. An inductive load circuit for a hard switching test of the (a) SiC MOSFET and (b) SiC Schottky diode. Double-pulses are applied to the device under
test (DUT) in (a); in contrast, they are applied to the control device (upper transistor T1) in (b). An external gate resistor (Rg,ext ) is used to regulate the
dv/dt and di/dt of the DUT. (c) Switching energy loss versus load current of the chosen SiC MOSFET at a VDC of 400 V and a Tj of 125 ◦ C.

FET and SiC diode. Note that the shunt introduces a parasitic
inductance of 2 nH into the circuit. After compensating for the Turn-on Parasitic
probe delays, the recorded switching waveforms are multiplied Vds oscillation
and integrated over the defined switching time to compute the ≈ 25 MHz
associated energy loss. 60 V/ns
74 V/ns
1.5 A/ns
B. Switching loss measurement using DPT methodology
Vgs− L
The dynamic performance of an SiC MOSFET was assessed
using DPT methodology, in which two pulses were sent to 3 A/ns Turn-off
the device under test (DUT) in a clamped inductive load I ds
circuit, as shown in Fig. 3 a). Double-pulses were generated 100 ns/div
using a function generator. By regulating the width of the first
pulse and the DC-link voltage, the desired load current was
(a) Turn-on and turn-off switching transients of SiC MOSFET.
achieved. Only two pulses were applied to the DUT each time;
consequently, the DUT junction temperature increase from the
switching loss was negligible. Fig. 3 (b) shows a schematic Vsd
diagram of the DPT measurements of the SiC diode. Here, the 20.0 V/ns
double-pulses are fed to the upper transistor. The measured
turn-on, turn-off, and total switching energy losses, namely,
I sd
Eon , Eof f , and Etot , respectively, at a junction temperature, 1.5 A/ns
Tj , of 125 ◦ C are shown in Fig. 3 (c). To monitor the junction
temperature, a small hole was made in the heat sink where the Vgs− H
device was mounted. This hole was made as close to the chip
as possible to estimate the junction temperature. Moreover,
such measurements were taken for a temperature range of Turn-off Turn-on 100 ns/div
25–150 ◦ C, and it was found that the influence on the losses
was extremely trivial. Thus, it was concluded that the method (b) Turn-on and turn-off switching transients of SiC diode.
used for the temperature measurements is sufficient for this Fig. 4. Sample of switching events of SiC MOSFET and SiC diode at a
case. A sample of the switching events for the chosen SiC DC-link voltage of 400 V and a load current of 20 A with an external gate
resistance of 0 Ω. Clearly, the overshoot and oscillations are slight in the
MOSFET and SiC diode are depicted in Fig. 4 at a Rg,ext of switching signals, indicating that the stray inductances of the switching and
0 Ω. These devices switch extremely quickly with very little gate loops are fairly low. Voltage probes are connected (using a PCB probe-
ringing, substantiating the low inductive design described in tip adapter) directly across the drain-source and gate-source terminals while
measuring the associated voltages. The highest achievable dv/dt during a
Section III-A. Here, dv/dt within the range of 60–75 V/ns turn-off is 60 and 20 V/ns for an SiC MOSFET and SiC diode, respectively.
and di/dt within the range of 1.5–3 A/ns are achieved at a Likewise, the highest achievable di/dt is 3 A/ns during a turn-on of an SiC
DC-link voltage of 400 V and a load current of 20 A. As can MOSFET and 1.5 A/ns during turn-off of an SiC diode. A parasitic oscillation
of approximately 25 MHz was observed during these transients.
be seen, a parasitic oscillation of 25 MHz is observed during
the switching transients.

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C. PFC converter loss evaluation using circuit simulation

1
0.5 Using MATLAB Simulink, the total converter loss is sim-
0 ulated, the inputs for which are the switching losses obtained
0.19598 0.19599 0.196
from the laboratory measurement and the conduction losses
20
19.5 from the data sheet. These data are used as look-up tables or
19 polynomial functions based on a curve fitting. To compute the
0.19598 0.19599 0.196
losses associated with the rectifier bridge, the on-state loss of
20 the Si diodes, the output capacitor ESR, and the boost inductor
10
0 copper loss are used as input into the simulation model. As a
0.19598 0.19599 0.196
cross-check, conduction losses are calculated using the simple
20 analytical expressions provided in the Appendix in (3), and
10
0 are found to be in accordance with the simulations. Regarding
0.19598 0.19599 0.196
the switching loss, the look-up table method implemented in
20 this study calculates the switching power loss by counting the
10
0 number of switching events during the fundamental cycle of
0.19598 0.19599 0.196 the input.
400 Fig. 5 (a), (b) illustrates the simulated waveforms of the
200
0 PFC converter, such as the PWM input into the MOSFET,
0.19598 0.19599 0.196 the current through the boost inductor (iL ), the switching
50 current in the boost MOSFET (ids ), the switching current
in the boost diode (id ), the instantaneous power loss of the
0
0 0.04 0.08 0.12 0.16 0.2 MOSFET (pinst ), and the average power loss of the MOSFET
time [s] (pavg ) with a filter of 0.01 s (1/60, with 60 Hz being the funda-
mental frequency). The sample plots are given for a switching
(a) A sample with a 85 V line input.
frequency of 250 kHz. Apparently, when the MOSFET is in
an on-state, iL increases, and when the MOSFET is in an off-
1
0.5
state (namely, when the diode conducts), iL decreases. At a
0 low input voltage (85 V), the diode has a shorter duty cycle
0.19598 0.19599 0.196
than the MOSFET, whereas the opposite holds true at a high
7 input voltage, which is why the diode with a low VF is desired
6.5
6 for achieving a low loss, particularly at a low line voltage. The
0.19598 0.19599 0.196 last signal in the sub-plot is the average power loss over the
10 SiC MOSFET, which includes the conduction and switching
5
0 loss. Note that this particular sub-plot has a different time
0.19598 0.19599 0.196 range (0–0.2 s) than the other sub-plots, which has deliberately
10 been chosen to observe the average power loss characteristics
5
0
of the SiC MOSFET over a longer time frame.
0.19598 0.19599 0.196 The detailed conduction loss breakdown for different line
10 inputs, namely, 85, 115, and 230 V, is shown in Fig. 6, and the
5
0
0.19598 0.19599 0.196
100 35
50 30
Conduction loss [W]

0
0.19598 0.19599 0.196 25
20 20
10
15
0
0 0.04 0.08 0.12 0.16 0.2 10
time [s]
5
(b) A sample with a 230 V line input.
0
Fig. 5. Sample plots at different locations in the circuit (Fig. 1) at two different
er

ET

e
r

r
o

to
d
ifi

ct

io

values of vs , namely, 85 and 230 V, when switched at a fsw of 250 kHz.

i
SF

ac
du
ct

p
O
Re

In

At a low input voltage (85 V), the diode has a shorter duty cycle than the
Ca
M

MOSFET compared to that at a high input voltage, and thus a diode with a
low VF is desired for achieving a low loss, particularly at 85 V. In a 1 kW Fig. 6. Illustration of conduction loss breakdown at different input voltages,
PFC boost converter, the total MOSFET loss reaches approximately 40 W namely, 85, 115, and 230 V, at a 100% output power. The bridge rectifier has
at 85 V and 9 W at 230 V when switched at 250 kHz. It should be noted the largest part of the conduction losses compared to the other components
that the time scale of the last sub-plot differs (0–0.2 s) compared to those of in the circuit. Simultaneously, the conduction losses are more pronounced at
the other sub-plots, and thus the pattern of pavg can be seen over the full lower line voltages compared to those at higher line voltages.
simulation time.

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switching losses of the boost diode and MOSFET at these line and PFC controller are included. A full schematic diagram of
inputs are shown in Fig. 7. For the same output power (1 kW), the prototype is shown in Fig. 16 in the Appendix, and a
higher losses are incurred at a low line voltage compared to complete component layout along with PCB routing is shown
a high voltage, the primary reason for which is the higher in Fig. 17.
current at the low line compared to that at the high line. With the objective of reducing the oscillations in the switch-
ing transients, the electric and magnetic field generations
35
are minimized for controlling the generation of the EMI at
the source. High-voltage switching traces are kept as small
30 as possible to minimize the electric fields. The heat sink
Switching loss [W]

25 is connected to the return such that it does not act as a

20 voltage-driven antenna. The gate drive track inductance is
minimized. The switching current conductors are balanced
15
and run opposite to each other to minimize stray inductance.
10 Guard rings are used for the current sense signals. A ground
5 plane was used for the control circuits. In addition, decoupling
capacitors are used as closely as possible to the switching
0
0 50 100 150 200 250 nodes. An image of the implemented hardware prototype with
Frequency [kHz] two different side views delineating the placement of different
components is provided in Fig. 9.
Fig. 7. Illustration of switching loss breakdown at different input voltages,
namely, 85, 115, and 230 V, at a 100% output power. The switching losses
imposed by the SiC MOSFET are larger compared to those imposed by the
SiC diode. Of special note is that the switching losses of the SiC diode are Boost inductor
independent of the load current, hence giving the same results at different
line voltages, but the losses increase with the increase in voltage in the SiC Bridge
Output
MOSFET under similar circumstances. rectifier
Gate capacitor
drivers and
control
100 circuits

80
Loss [W]

60
EMI input
40
SiC MOSFET filter
20 and SiC diode

0
0 200 400 600 800 1000
(a) Illustration of component placement in PFC rectifier.
Output power [W]

Fig. 8. Plots illustrating the conduction loss (Pcond ), switching loss (Psw ),
and total loss (Ptot ) at 250 kHz. Clearly, Pcond is lower throughout the entire Output
load for a vs of 230 V, whereas the opposite is true for a vs of 85 V. Heat sink capacitor

The capacitive charge is low for the SiC diode and almost
independent of di/dt, the forward current, and the temper-
Boost
ature. Hence, the switching loss of the SiC Schottky diode inductor
is taken as a constant for a given output voltage of 400 V.
Fig. 8 illustrates the total conduction, total switching, and
their summation, Pcond , Psw , and Ptot , respectively, over the
entire load range at 250 kHz for two different line voltages.
As shown, Pcond is lower over the entire load range for a vs EMI input
of 230 V, whereas the opposite is true for a vs of 85 V. filter

IV. C IRCUIT DESIGN AND LAYOUT CONSIDERATIONS IN A

PROTOTYPE PFC CONVERTER
This section describes the circuit design and layout consid-
erations in a PFC rectifier prototype for achieving the clean (b) Illustration of components along with heat sink.
switching of an SiC MOSFET and SiC diode. In addition, brief Fig. 9. Photographs of the prototype PFC converter with two different side
descriptions of the input EMI filter, boost inductor, gate driver, views showing the placement of different components.

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TABLE III
EMI FILTER SPECIFICATIONS .

L3-A CY 1 –CY 4 , CM capacitances, Ceramic, Class X1/Y2

attenuates Bridge rectifier 4 × 4n7F, P10 mm
DM EMI CX3 L1−A , L2−A , CM chokes, EPCOS-TDK, R25 Ring core
CY4
CY3 T38 material, 19 turns per coil, wire diameter 1.219 mm
Two
stage 2 × 3.6 mH ± 25% @ 1 kHz
4 × 4n7 F
EMI L3−A , DM chokes, Micrometal, T106-26 core, 36 turns
filter L1-A – L2-A CY2 wire diameter 1.422 mm, 1 × 120 µH ± 10% @ 1 kHz
CX2
attenuates CX1 –CX3 , DM capacitances, MKR, EPCOS, × 2 Class
CM EMI CY1
CX1 3 × 1µF, 305 V, P22.5 mm

Fig. 10. Schematic diagram showing the two-stage EMI filter, the first stage
consisting of inductors, L1−A and L2−A , attenuating the CM EMI, and the
second stage with L3−A attenuating DM EMI. Capacitances CY 1 –CY 4 (nF
range) primarily serve as a CM filter; and CX1 –CX3 (µF range), as a DM
filter.

A two-stage EMI filter, as shown in Fig. 10, was designed

and implemented. The first stage consisting of the inductance,
L1−A , L2−A , and the capacitances, CY 1 –CY 4 , attenuates a (a) fsw = 66 kHz. (b) fsw = 250 kHz.
common-mode (CM) EMI. The second stage incorporating the Fig. 11. Switching at 66 kHz requires 2× stacked sendust core, CS358060,
inductance, L3−A , and capacitances, CX1 –CX3 , attenuates a with 70 turns giving 565 µH, whereas at 250 kHz, only a 1× stacked sendust
core, CS330060, is sufficient, leading to a dramatic reduction in the size of
differential-mode (DM) EMI. Table III shows the designed the inductor.
EMI filter components for the prototype. The procedure fol-
lowed in the design of the CM and DM filter is enumerated
below. switching frequency was possible without compromising the
1) Because the switching transients are the sources of the efficiency and achieving a dramatic size and cost reduction
EMI, the measured DPT waveforms (time domain) are of the PFC boost inductor. A photograph showing the size
taken as an input to plot the corresponding frequency difference in an inductor when switched at 66 kHz versus
domain equivalent to a Fourier transform in MATLAB. 250 kHz is provided in Fig. 11. The SiC MOSFET was driven
This measured original noise is compared with the CISPR by a +2.5/-5 A driver that can generate an approximately +18/-
limits. Selecting the filter topology, as shown in Fig. 10, 5 V drive voltage.
the corner frequency is calculated such that the attenua-
tion satisfies the limit with an extra 6 dB safety margin. V. M EASUREMENT RESULTS
2) First, the CM capacitances, CY 1 –CY 4 , are limited based In this section, the efficiency and EMI evaluation of the
on regulations indicating that the current-to-ground must prototype PFC converter are presented. The higher the ripple
not exceed 3 mA at 50/60 Hz. Accordingly, CM induc- current in the boost inductance, the higher the AC losses
tances are calculated using the resonance principle at the in it. As a consequence, higher is the EMI because of the
computed corner frequency. Then, the CM filter is tested potential higher radiations of magnetic field. In this work, the
in the MATLAB Simulink model of the PFC converter SiC devices are switched with 0 Ω gate resistance together
to check the defined 3 mA leakage current limit. with the low parasitic design approach (the highest possible
3) Because the leakage inductance of the CM choke, as well dv/dt and di/dt) with the aim of maximizing the efficiency
as the boost inductance of the PFC stage, help minimize and measuring the worst case EMI. However, slowing the
the DM noise, a fairly low DM inductance is selected, SiC MOSFETs would potentially minimize EMI noises with
namely, 1–4% of the CM inductance. Again, using the the penalty of higher switching losses. Fig. 12 (a) shows the
resonance equation, the CM capacitance is computed. measured ac mains voltage and current. Clearly, is shapes vs as
4) The designed filter was simulated in LTSpice employing expected. Fig. 12 (b) shows the MOSFET drain-source voltage
realistic spice models of the circuit components, including and inductor current when switched at approximately 250 kHz.
SiC MOSFET, SiC diode, and EMI filters to check the The discontinuity at zero-crossing of is is clearly seen because
EMC compliance before building the EMI filter in a the dead-time comprises a major part with fsw of 250 kHz
laboratory. compared with fsw of 66 kHz. Fig. 13 (a) and (b) show the
A PFC controller UCC28180D from Texas Instruments is drain- and gate-source voltages during the turn-off and turn-on
used with the switching frequency set to 250 kHz. Given the transients, respectively, illustrating the clean switching of an
high switching speed capabilities of SiC devices, a higher SiC MOSFET.

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98
vs 97
96
95
94
93
is 92
91
90
89
88

(a) Measured ac mains voltage, vs , and current, is . 0 200 400 600 800 1000

vds Fig. 14. Illustration of the simulated and measured efficiency of the PFC
rectifier as a function of the output power, indicating that the converter
achieves an efficiency of above 97% for a rated load of > 60% with a peak
efficiency of 97.2%. The measurements were taken using a prototype converter
with a Yokogawa WT3000 power analyzer.

iL
A. Efficiency evaluation
The simulated efficiency of the rectifier as a function of the
output power for vs = 230 V is shown in Fig. 14, together with
(b) MOSFET drain-source voltage, vds , and inductor current, iL . the measurement results taken using a Yokogawa WT3000
Fig. 12. Oscilloscope graphs at a switching frequency of roughly 250 kHz. power analyzer. As can be seen, the simulated results of the
(a) Illustration of is shaping vs . (b) With fsw of 250 kHz, boost inductor converter follow a similar pattern as the measured efficiency
current, ∆iL , is 0.7 A, while it was 1.5 A with fsw of 66 kHz. Influence of over a wide range of output power, and the discrepancy
dead-time is seen as the discontinuity at zero-crossing of is .
between the two is primarily due to two reasons. First, the
simulated case does not consider the core losses in the boost
vds inductor or the input EMI filter losses, whereas the measured
case includes the overall losses in the PFC rectifier. Second, to
measure such a high efficiency, an error introduced when using
a power analyzer is also critical. Nonetheless, the converter
achieves an efficiency of above 97% for > 60% of the rated
vgs load with a peak efficiency of 97.2%, and is well above the
80 PLUS efficiency required over the entire load range.

B. EMI evaluation
(a) Measured vds and vgs during turn-off.
A standard line impedance stabilizing network (LISN) and
an EMC analyzer (Agilent E7401A) were used for measur-
vds ing the EMI. Fig. 15 shows the measured conducted EMI
emission (within the frequency range of 150 kHz–30 MHz)
of the prototype PFC rectifier at an input voltage of 230 V
and an output power of 1 kW at two different switching
frequencies, 66 and 250 kHz. Compared to 66 kHz switching,
vgs at 250 kHz, the EMI noise shifts toward the right slightly,
and then increases by approximately 10 dB (23-13 = 10 dB)
over the entire spectra applied, given the same EMI filter size.
Alternatively, it can be stated that, as the switching frequency
increases, the filter size increases if the same noise level needs
(b) Measured vds and vgs during turn-on.
to be maintained. In Section III-B, it was stated that the
Fig. 13. Measured drain-source voltage, vds , and gate-source voltage, vgs , DPT-measured parasitic oscillations (labelled in Fig. 4) are
illustrating the clean switching of an SiC MOSFET. The gate oscillations
are within the region where the device is beginning to partly turn on and within the range of 25 MHz. Interestingly, the EMI noises in
transiting through the Miller plateau. This initial ringing is due to the input the corresponding frequency range are augmented, which is
gate capacitance and the circuit parasitic inductance. Thereafter, the change clearly shown in Fig. 15. This was also corroborated through
in drain current is minor, resulting in insignificant ringing in vds during a
turn on. a simulation conducted in LTSpice by varying the switching
loop inductance and observing the noise within the frequency
domain plot.

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100 • Clean switching of the state-of-the-art SiC devices was

@ 66 kHz CISPR 11 Class B QP Limit
illustrated to substantiate the design of a low-parasitic
80 Avg Limit
layout.
Noise [dB V]

60
≈ 23 dB Thus, with a proper design and circuit layout, the clean
40 switching of SiC devices can be achieved without sacrificing
20
their high-speed switching potential, leading to negligible
switching losses in these devices and an improved EMI signa-
0 Parasitic oscillation ture. Furthermore, a reduction in the switching speed can also
amplifies noise
-20 be utilized to optimize the circuit design, such as increasing
150 k 1M 10 M 30 M
the efficiency and reducing the cooling requirements, and by
Frequency [Hz]
increasing the switching frequency, the size of the magnetic
(a) Conducted EMI at a switching frequency of 66 kHz.
components can be minimized.
100
@ 250 kHz CISPR 11 Class B QP Limit VII. A PPENDIX
80 Avg Limit
Equations for passive component sizing
Noise [dB V]

60 √
≈ 13 dB
!
2
1 vs,min 2 · vs,min 1
40 LB = · · 1− · (1)
∆iL Pout vout fsw
20

0 shift Parasitic oscillation 2 · Pout · thold Pout

amplifies noise Cout = 2 2 ,= (2)
-20 vs,min − vout,min 2 · π · fline · ∆vout · vout
150 k 1M 10 M 30 M
Frequency [Hz] The higher value of Cd is considered to be the output capacitor
(b) Conducted EMI at a switching frequency of 250 kHz. size for the design.
Fig. 15. Conducted maximum peak and average EMI noise emissions of the Equations for conduction loss calculation
prototype PFC rectifier at an input voltage of 230 V and an output power 2
of 1 kW at two different switching frequencies, namely, 66 and 250 kHz. Pcond (rectif ier) = 2 × (IL,rms × Rd + IL,avg × VF O )
All measurements are below the quasi peak (QP) and average (Avg) limits, 2
Pcond (inductor) = IL,rms × DCR
and thus meet the CISPR 11 regulation for Class B equipment. Compared to
2
66 kHz, a 250 kHz switching incurs a higher noise provided an identical EMI Pcond (capacitor) = Ic,rms × ESR
filter. 2
Pcond (M OSF ET ) = Ids,rms × RDS,on
2
Pcond (diode) = Id,rms × Rd + Id,avg × VF O
VI. C ONCLUSION
(3)
The main conclusions from this work are described below.
where, IL,rms , IL,avg , Id,rms , Id,avg , Ids,rms and Ic,rms
• Employing low-loss SiC power devices in the boost
are the currents through rectifier, boost diode, MOSFET and
stage, the efficiency was evaluated in a classic boost PFC
output capacitor. Diodes have average (avg) and RMS values.
topology, the results of which revealed that the major
converter loss is comprised of a diode rectifier part, which
is particularly pronounced at a low-line as compared to
a high-line voltage. ACKNOWLEDGMENT
• A comparison between the efficiencies evaluated using The authors would like to thank The Research Council of
a simple look-up table input from a double-pulse test Norway and the industry partners, namely, EFD Induction,
follows the pattern measured using a power analyzer Siemens, Eltek, Statkraft, Norwegian Electric Systems, and
meeting the 80 PLUS efficiency regulation over the entire Vacon, who sponsored this project.
load range with an excellent margin.
• The conducted EMI in the prototype converter was found R EFERENCES
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0093-9994 (c) 2019 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TIA.2019.2919266, IEEE
Transactions on Industry Applications
10

Bypass diode
SiC diode
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Bridge Output
Gate driver Z1 and Z2 provides gate capacitor
rectifier overvoltage protection

SiC Provides
MOSFET inrush current
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PFC
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Fig. 16. A complete schematic diagram of the PFC rectifier prototype board.

Driver and
PFC controller
control circuits
UCC28180D

Ground Output
Boost
plane capacitor
inductor

Gate
driver IC
UCC275
High voltage
38DBV
switching
track

Balanced
switching
conductors
Gate drive
track

Two stage
EMI filter

Fig. 17. A complete component layout and routing of the PFC rectifier prototype board (two-layer board).

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