TEA1716T

Resonant power supply control IC with PFC

Rev. 1 — 27 January 2012 Objective data sheet

1. General description
The TEA1716 integrates a Power Factor Corrector (PFC) controller and a controller for a
Half-Bridge resonant Converter (HBC) in a multi-chip IC. It provides the drive function for
the discrete MOSFET in an up-converter and for the two discrete power MOSFETs in a
resonant half-bridge configuration.

The efficient operation of the PFC is achieved by implementing functions such as

quasi-resonant operation at high-power levels and quasi-resonant operation with valley
skipping at lower power levels. OverCurrent Protection (OCP), OverVoltage Protection
(OVP), and demagnetization sensing ensure safe operation under all conditions.

The HBC module is a high-voltage controller for a zero-voltage switching LLC resonant
converter. It contains a high-voltage level shift circuit and several protection circuits
including OCP, open-loop protection, capacitive mode protection and a general purpose
latched protection input.

The high-voltage chip is fabricated using a proprietary high-voltage Bipolar-CMOS-DMOS

power logic process that enables efficient direct start-up from the rectified universal mains
voltage. The low-voltage Silicon-On-Insulator (SOI) chip is used for accurate, high-speed
protection functions and control.

The topology of a PFC circuit and a resonant converter controlled by the TEA1716 is very
flexible. It enables the device to be used in a broad range of applications with a wide
mains voltage range. Combining PFC and HBC controllers in a single IC makes the
TEA1716 ideal for controlling power supplies in LCD and plasma televisions.

Highly efficient and reliable power supplies providing from 90 W to 500 W can be
designed easily using the TEA1716, with a minimum of external components.

The integrated burst mode and power management functionality of TEA1716 enable
resonant applications that meet the Energy Using Product Directive (EuP) lot 6 (< 0.5 W in
standby mode).
NXP Semiconductors TEA1716T
Resonant power supply control IC with PFC

2. Features and benefits

2.1 General features

 Integrated PFC and HBC controllers
 Universal mains supply operation (70 V to 276 V (AC))
 High level of integration resulting in a low external component count and a cost
effective design
 Integrated burst mode sensing
 Compliant with Energy Using Product Directive (EuP) lot 6
 Enable input (enable only PFC or both PFC and HBC controllers)
 On-chip high-voltage start-up source
 Stand-alone operation or IC supplied from external DC source

2.2 PFC controller features

 Boundary mode operation with on-time control
 Valley/zero voltage switching for minimum switching losses
 Frequency limiting to reduce switching losses
 Accurate boost voltage regulation
 Burst mode switching with soft start and soft stop

2.3 HBC controller features

 Integrated high-voltage level shifter
 Adjustable minimum and maximum frequency
 Maximum 500 kHz half-bridge switching frequency
 Adaptive non-overlap time
 Burst mode switching

2.4 Protection features

 Safe restart mode for system fault conditions
 General latched protection input for output overvoltage protection or external
temperature protection
 Protection timer for time-out and restart
 Overtemperature protection
 Soft (re)start for both controllers
 Undervoltage protection for mains (brownout), boost, IC supply
 Overcurrent regulation and protection for both controllers
 Accurate overvoltage protection for boost voltage
 Capacitive mode protection for HBC controller

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Objective data sheet Rev. 1 — 27 January 2012 2 of 46

NXP Semiconductors TEA1716T
Resonant power supply control IC with PFC

3. Applications
 LCD television
 Plasma television
 Notebook adapter
 Desktop and all-in-one PCs

4. Ordering information
Table 1. Ordering information
Type number Package
Name Description Version
TEA1716T SO24 plastic small outline package; 24 leads; body width 7.5 mm SOT137-1

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Objective data sheet Rev. 1 — 27 January 2012 3 of 46

NXP Semiconductors TEA1716T
Resonant power supply control IC with PFC

5. Block diagram

SNSBOOST SUPHV SUPIC SUPREG

2 24 12 6 9
SNSMAINS
14
+1.15 V SUPHS
MAINS RESET,
UNDERVOLTAGE High-side driver
+10.9 V
SENSING SERIES
AND CLAMP STABILIZER AND LEVEL 13
GATEHS
SUPREG SENSING SHIFTER
+10.3 V

MAINS 15
HB
COMPENSATION HV START-UP SUPPLY SWITCH Low-side driver
SOURCE CONTROL CONTROL SUPREG
10
ON-TIMER GATELS
OFF-TIME LIMIT
FREQUENCY LIMIT ADAPTIVE
HV START-UP INTERNAL 8
NON-OVERLAP PGND
SELECTION SUPPLIES
+20 V SENSING
Error
amplifier
and clamp BOOST
1 +2.5 V COMPENSATION
COMPPFC SUPIC
+22/17 V CAPACITIVE
START AND
MODE
PFC driver +15 V UNDERVOLTAGE
SENSING
SUPREG SUPPLY MODULE SENSING
17
7 PFC SNSCURHBC
GATEPFC
CONTROL

PGND +0.5 V OVERCURRENT +1.75 V OVERCURRENT

3 BOOST REGULATION PROTECTION
SNSAUXPFC OVERVOLTAGE -0.5 V SENSING -1.75 V SENSING
+2.63 V SENSING
-0.1 V DEMAGNETIZING
SENSING
OUTPUT OUTPUT
+2.3 V BOOST +2.3 V PRESENT +3.5 V OVERVOLTAGE
UNDERVOLTAGE SENSING SENSING
+1.6 V SENSING
VALLEY
SENSING 5
SNSOUT
4 20
SNSCURPFC BOOST
BOOST SHORT SNSBURST
CHARGED BURST BURST
SENSING
SENSING 2.5 V +0.4 V STOP SENSING 3.5 V
+0.45 V SOFT START
CONTROL
PFC CONTROLLER

+0.5 V OVERCURRENT
SOFT START 21
SENSING +3.0 V SNSFB
RESET HBC CONTROLLER

6.4 V
OPEN-LOOP FEEDBACK
8.2 V
PROTECTION FREQUENCY SENSING INPUT
23 4.1 V
RCPROT AND RESTART CONTROL
TIMER

OVER- +8.0 V TWO SPEED +

POLARITY
TEMPERATURE SOFT START
+5.6 V INVERSION
SENSING SWEEP +8.0 V I-V
+3.2 V AND CLAMP
V-I HIGH
+2 V FREQUENCY
ENABLE CONTROLLED
+1.83 V SENSING
SENSING OSCILLATOR
+1 V
PFC/HBC Rfmax
TEA1716T
18 22 19

SGND SSHBC/EN CFMIN aaa--000764

Fig 1. Block diagram of TEA1716

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NXP Semiconductors TEA1716T
Resonant power supply control IC with PFC

6. Pinning information

6.1 Pinning

COMPPFC 1 24 SNSBOOST
SNSMAINS 2 23 RCPROT
SNSAUXPFC 3 22 SSHBC/EN
SNSCURPFC 4 21 SNSFB
SNSOUT 5 20 SNSBURST
SUPIC 6 19 CFMIN
TEA1716T
GATEPFC 7 18 SGND
PGND 8 17 SNSCURHBC
SUPREG 9 16 n.c.
GATELS 10 15 HB
n.c. 11 14 SUPHS
SUPHV 12 13 GATEHS

aaa-000765

Fig 2. Pin configuration

6.2 Pin description

Table 2. Pin description
Symbol Pin Description
COMPPFC 1 frequency compensation for PFC controller; externally connected to filter
SNSMAINS 2 sense input for mains voltage; externally connected to resistive divided
mains voltage
SNSAUXPFC 3 sense input for PFC demagnetization timing; externally connected to
auxiliary winding of PFC
SNSCURPFC 4 sense input for momentary current and soft start of the PFC controller;
externally connected to current sense resistor and soft start filter
SNSOUT 5 sense input for monitoring the output voltage of the HBC; externally
connected to the auxiliary winding
SUPIC 6 low-voltage supply for SUPIC input; output of internal HV start-up source;
externally connected to auxiliary winding of HBC or to external DC supply
GATEPFC 7 gate driver output for PFC MOSFET
PGND 8 power ground; reference (ground) for HBC low-side and PFC driver
SUPREG 9 regulated SUPREG IC supply; output from internal regulator; input for
drivers; externally connected to SUPREG buffer capacitor
GATELS 10 gate driver output for low-side MOSFET of HBC
n.c. 11 not connected; high-voltage spacer.
SUPHV 12 high-voltage supply input for internal HV start-up source; externally
connected to boost voltage
GATEHS 13 gate driver output for high-side MOSFET of HBC
SUPHS 14 high-side driver supply input; externally connected to bootstrap capacitor
(CSUPHS)

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NXP Semiconductors TEA1716T
Resonant power supply control IC with PFC

Table 2. Pin description …continued

Symbol Pin Description
HB 15 reference for high-side driver; input for half-bridge slope detection;
externally connected to half-bridge node HB between HBC MOSFETs (see
Figure 17)
n.c. 16 not connected; high-voltage spacer
SNSCURHBC 17 sense input for momentary HBC current; externally connected to resonant
current sense resistor
SGND 18 signal ground; reference (ground) for IC.
CFMIN 19 minimum frequency setting for HBC; externally connected to capacitor
SNSBURST 20 sense input for burst stop activation; externally connected to resistive
divided SNSFB voltage
SNSFB 21 sense input for output voltage regulation feedback; externally connected to
optocoupler and pull-up resistor
SSHBC/EN 22 combined soft start timing of HBC and IC enable input; enabling of PFC or
PFC and HBC controllers; externally connected to soft start capacitor and
enable pull-down signal
RCPROT 23 protection timer setting for time-out and restart; externally connected to
resistor and capacitor
SNSBOOST 24 sense input for boost voltage; externally connected to resistive divided
boost voltage

7. Functional description

7.1 Overview of IC modules

The functionality of the TEA1716 can be grouped as follows:

• Supply module:
Supply management for the IC; includes the restart and (latched) shut-down states
• Protection and restart timer:
Externally adjustable timer used for delayed protection and restart timing
• Enable input:
Control input for enabling and disabling the controllers; very low current consumption
when disabled
• PFC controller:
Controls and protects the power factor converter; generates a 400 V (DC) boost
voltage from the rectified AC mains input with a high-power factor
• HBC controller:
Controls and protects the resonant converter; generates a regulated (mains isolated)
output voltage from the 400 V (DC) boost voltage

Figure 1 shows the block diagram of the TEA1716. A typical application is illustrated in
Figure 17.

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NXP Semiconductors TEA1716T
Resonant power supply control IC with PFC

7.2 Power supply

The TEA1716 contains several supply-related pins.

7.2.1 Low-voltage supply input (pin SUPIC)

The SUPIC pin is the main low-voltage supply input to the IC. All internal circuits (other
than the high-voltage circuit) are directly or indirectly (via SUPREG) supplied from this pin.
SUPIC is connected externally to a buffer capacitor CSUPIC. This buffer capacitor can be
charged in several ways:

• from the internal high voltage start-up source

• from the auxiliary winding of the HBC transformer
• from the capacitive supply of the switching half-bridge node
• from an external DC supply, for example, a standby supply

The IC starts operating when the voltage on SUPIC reaches the start level, if the voltage
on SUPREG has also reached the start level. The start level depends on the condition of
the SUPHV pin:

• High voltage present on SUPHV, VSUPHV > Vdet(SUPHV).

This is the case with a stand-alone application where CSUPIC is initially charged from
the HV start-up source. The start level is Vstart(hvd)(SUPIC) (20 V typical). The wide
difference between the start and stop (Vuvp(SUPIC)) levels allows energy to be stored in
the SUPIC buffer capacitor. This energy is used to supply the IC until the output
voltage has stabilized.
• Not connected or no voltage present at SUPHV, VSUPHV < Vdet(SUPHV).
This is the case when the TEA1716 is supplied from an external DC source. The start
level is Vstart(nohvd)(SUPIC) (15 V typical). The IC is supplied from the DC supply during
start-up. To minimize power dissipation, the DC supply to pin SUPIC must be above,
but close to, Vuvp(SUPIC) (13 V typical).

The IC stops operating when VSUPIC drops below Vuvp(SUPIC). This is the SUPIC
UnderVoltage Protection (UVP) voltage (UVP-SUPIC; see Section 7.9). The PFC
controller stops switching immediately, but the HBC controller continues operating until
the low-side MOSFET becomes active.

The current consumption depends on the state of the IC. The TEA1716 operating states
are described in Section 7.3.

• Disabled IC state
When the IC is disabled via the SSHBC/EN pin, the current consumption is very low
(Idism(SUPIC)).
• SUPIC charge, SUPREG charge, Thermal hold, Restart and Protection shut-down
states
Only a small section of the IC is active while CSUPIC and CSUPREG are charging during
a restart sequence before start-up or during shutdown after a protection function has
been activated. The PFC and HBC controllers are disabled. Current consumption is
limited to Iprotm(SUPIC).

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NXP Semiconductors TEA1716T
Resonant power supply control IC with PFC

• Boost charge state

The PFC controller is switching; the HBC controller is off. The current from the
high-voltage start-up source is large enough to supply SUPIC
(current consumption < Ich(nom)(SUPIC)).
• Operational supply state
Both the PFC and HBC controllers are switching. Current consumption is Ioper(SUPIC).
When the HBC controller is enabled, the switching frequency is high initially and the
current consumption of the HBC MOSFET drivers is dominant. The stored energy in
CSUPIC supplies the initial SUPIC current before the SUPIC supply source takes over.
• Burst stop mode
Only a small section of the IC is active while CSUPREG is kept charged and the sensing
of the SNSBURST input is active. The PFC and HBC controllers are stopped. Current
consumption is limited to Iburstm(SUPIC).

Pin SUPIC has a low short-circuit detection voltage (Vscp(SUPIC); 0.65 V typical). The
current dissipated in the HV start-up source is limited while VSUPIC < Vscp(SUPIC)
(see Section 7.2.4).

7.2.2 Regulated supply (pin SUPREG)

The voltage range on pin SUPIC exceeds that of the gate voltages of the external
MOSFETs. For this reason, the TEA1716 contains an integrated series stabilizer. The
series stabilizer creates an accurate regulated voltage (Vreg(SUPREG); 11.3 V typical) at the
buffer capacitor CSUPREG. This stabilized voltage is used to:

• supply the internal PFC driver

• supply the internal low-side HBC driver
• supply the internal high-side driver via external components
• as a reference voltage for optional external circuits

The SUPREG series stabilizer is enabled after CSUPIC has been fully charged. This
ensures that any optional external circuitry connected to SUPREG does not dissipate any
of the start-up current.

The voltage on SUPREG must reach Vstart(SUPREG) (and the voltage on SUPIC must reach
the start level) before the IC starts operating to ensure that the external MOSFETs receive
sufficient gate drive current.

SUPREG is provided with undervoltage protection (UVP-SUPREG; see Section 7.9).

When VSUPREG falls below Vuvp(SUPREG) (10 V typical), two events are triggered:

• The IC stops operating to prevent unreliable switching because the gate driver voltage
is too low. The PFC controller stops switching immediately, but the HBC controller
continues until the low-side stroke is active.
• The maximum current from the internal SUPREG series stabilizer is reduced to
Ich(red)(SUPREG) (5.4 mA typical). This reduces the dissipation in the series stabilizer in
the event of an overload at SUPREG while SUPIC is supplied from an external DC
source.

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NXP Semiconductors TEA1716T
Resonant power supply control IC with PFC

7.2.3 High-side driver floating supply (pin SUPHS)

The high-side driver is supplied by an external bootstrap buffer capacitor, CSUPHS. The
bootstrap capacitor is connected between the high-side reference pin HB and the
high-side driver supply input pin SUPHS. CSUPHS is charged from pin SUPREG via an
external diode DSUPHS. The voltage drop between SUPREG and SUPHS can be
minimized by carefully selecting the appropriate diode, especially when using large
MOSFETs and high switching frequencies.

7.2.4 High-voltage supply input (pin SUPHV)

In a stand-alone power supply application, this pin is connected to the boost voltage. The
HV start-up source (which delivers a constant current from SUPHV to SUPIC) charges
CSUPIC and CSUPREG using this pin.

Short-circuit protection on pin SUPIC (SCP-SUPIC; see Section 7.9) limits the dissipation
in the HV start-up source when SUPIC is shorted to ground. It limits the current on
SUPHV (to Ired(SUPHV)) as long as the voltage on SUPIC is below Vscp(SUPIC).

Under normal operating conditions, the voltage on pin SUPIC exceeds Vscp(SUPIC) very
quickly after start-up and the HV start-up source switches to the nominal current
Inom(SUPHV).

During start-up and restart, the HV start-up source charges CSUPIC and regulates the
voltage on SUPIC by hysteretic control. So the start level has a small degree of hysteresis
Vstart(hys)(SUPIC). The HV start-up source switches off when VSUPIC exceeds the start level
Vstart(hvd)(SUPIC). Current consumption through pin SUPHV is low (Itko(SUPHV)).

Once start-up is complete and the HBC controller is operating, SUPIC can be supplied
from the auxiliary winding of the HBC transformer. In this operational state, the HV
start-up source is disabled.

7.3 Flow diagram

The operation of the TEA1716 can be divided into a number of states - see Figure 3. The
abbreviations used in Figure 3 are explained In Table 8.

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NXP Semiconductors TEA1716T
Resonant power supply control IC with PFC

START
UVP supplies = yes

NO SUPPLY

-All off
enable PFC = no UVP supplies = no

DISABLED lC

-Only "Enable lC" detection active

Explanation flow diagram symbols Enable PFC = yes

STATE NAME THERMAL HOLD

-action 1 -Minimum functionality active

-action 2 OTP = no
-...
Disabled items are not mentioned
exit condition 1 exit condition 2 SUPIC CHARGE
reached reached
-HV start-up source on
UVP SUPIC = no OTP = yes

exit condition

next state can be entered SUPREG CHARGE

from any state when exit
condition is true -HV start-up source on
-Series stabilizer on
UVP SUPREG = no UVP SUPIC= yes OTP = yes

BOOST CHARGE

-HV start-up source on

-Series stabilizer on
*1Protection timer is activated by:
-PFC on
-UVP output
-OLP HBC
UVP boost = no and
-OCR HBC SCP boost = yes UVP SUPREG = yes UVP SUPIC = yes OTP = yes
Enable lC = yes
-HFP

OPERATIONAL SUPPLY

-Series stabilizer on
-PFC on
-HBC on

Protection timer UVP boost = yes

SCP boost = yes OVP output = yes Burst stop = yes UVP SUPREG = yes UVP SUPIC = yes OTP = yes
passed *1 or Enable IC = no

RESTART PROTECTION SHUTDOWN

-HV start-up source on

-Restart timer on Mains reset = yes

Restart time passed

BURST STOP

-Series stabilizer on

UVP SUPREG = yes UVP SUPIC = yes OTP = yes Burst stop = no

aaa-000766

Fig 3. Flow diagram of the TEA1716

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Resonant power supply control IC with PFC

Table 3. Operating states

State Description
No supply Supply voltages on SUPIC and SUPHV are too low to provide any functionality. Undervoltage
protection (UVP-supplies; see Section 7.9) is active when VSUPHV < Vrst(SUPHV) and
VSUPIC < Vrst(SUPIC). The IC is reset.
Disabled IC IC is disabled because pin SSHBC/EN is LOW.
Thermal hold Activated as long as OTP is active. IC is not operating. PFC and HBC controllers are disabled
and CSUPIC and CSUPREG are not charged.
SUPIC charge HV start-up source charges IC supply capacitor (CSUPIC). CSUPREG is not charged.
SUPREG charge Series regulator charges stabilized supply capacitor (CSUPREG).
Boost charge Operational PFC builds up boost voltage.
Operational supply Output voltage is generated. Both PFC and HBC controllers are fully operational.
Burst stop Power-saving state for burst mode operation. PFC and HBC controllers are disabled and CSUPIC
is not charged. CSUPREG is charged.
Restart Activated when a protection function is triggered. Restart timer is activated. During this time,
PFC and HBC controllers are disabled and CSUPREG is not charged. CSUPIC is charged.
Protection shut-down Activated when a protection function is triggered. IC is not operational. PFC and HBC controllers
are disabled and CSUPIC and CSUPREG are not charged.

7.4 Enable input (pin SSHBC/EN)

The power supply application can be completely disabled by pulling pin SSHBC/EN LOW.

Figure 4 illustrates the internal functionality. When a voltage is present on pin SUPHV or
on pin SUPIC, a current Ipu(EN) (42 A typical) flows out of SSHBC/EN. If the pin is not
pulled-down, this current lifts the voltage up to Vpu(EN) (3 V typical). Since this voltage is
above both Ven(PFC)(EN) (1.2 V typical) and Ven(IC)(EN) (2.2 V typical), the IC is completely
enabled.

The IC can be completely disabled by pulling the voltage on SSHBC/EN down below both
Ven(PFC)(EN) and Ven(IC)(EN) via an optocoupler driven from the secondary side of the HBC
transformer (see Figure 4). The PFC controller stops switching immediately, but the HBC
controller continues switching until the low-side stroke is active. It is also possible to
control the voltage on SSHBC/EN from another circuit on the secondary side via a diode.
The external pull-down current must be larger than the internal soft start charge current
Iss(hf)(SSHBC).

If the voltage on SSHBC/EN is pulled down below Ven(IC)(EN), but not below Ven(PFC)(EN),
only the HBC is disabled. This feature can be useful when another power converter is
connected to the boost voltage of the PFC.

The low-side power switch of the HBC is on when the HBC is disabled via the SSHBC/EN
pin.

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NXP Semiconductors TEA1716T
Resonant power supply control IC with PFC

Enable detection
lpu(EN)

Vpu(EN)
Enable supply
signal (0 to > 2 V)
SSHBC/EN

Disable supply Ven(IC)(EN)

EnableIc
Css(HBC)

Ven(PFC)(EN)
EnableIcPfc

To soft start
circuit TEA1716

aaa-000769

Fig 4. Circuit configuration around pin SSHBC/EN

7.5 IC protection

7.5.1 IC restart and shut-down

In addition to the protection functions that influence the operation of the PFC and HBC
controllers, a number of protection functions are provided that disable both controllers.
See the protection overview in Section 7.9 for details on which protections trigger a restart
or a protection shut-down.

• Restart
When the TEA1716 enters the Restart state, the PFC and HBC controllers are
switched off. After a period, defined by the Restart timer, the IC automatically restarts
following the normal start-up cycle.
• Protection shut-down
When the TEA1716 enters the Protection shut-down state, the PFC and HBC
controllers are switched off. The Protection shut-down state is latched, so the IC does
not start up again automatically. It can be restarted by resetting the Protection
shut-down state in one of the following ways:
– by lowering VSUPIC and VSUPHV below their respective reset levels, Vrst(SUPIC) and
Vrst(SUPHV)
– via a fast shut-down reset (see Section 7.5.3).
– via the enable pin (see Section 7.4)
• Thermal hold
In the Thermal hold state, the PFC and HBC controllers are switched off. The Thermal
hold state remains active until the IC junction temperature drops to about 10 C below
Totp (see Section 7.5.6).

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NXP Semiconductors TEA1716T
Resonant power supply control IC with PFC

7.5.2 Protection and restart timer

The TEA1716 contains a programmable timer which can be used for timing several
protection functions. The timer can be used in two ways - as a protection timer and as a
restart timer. The timing of the timers can be set independently via an external resistor
Rprot and capacitor Cprot connected to pin RCPROT.

7.5.2.1 Protection timer

Certain error conditions can be allowed to persist for a time before protective action is
required. The protection timer defines the protection period - how long the error is allowed
to persist before the protection function is triggered. The protection functions that use the
protection timer can be found in the protection overview in Section 7.9.

short long repetative

error error error
present
Error
none

Ich(slow)(RCPROT)
IRCPROT 0

Vu(RCPROT)

VRCPROT

passed
Protection time
t
014aaa853

Fig 5. Operation of the protection timer

Figure 5 shows the operation of the protection timer. When an error condition occurs, a
fixed current Ich(slow)(RCPROT) (100 A typical) flows out of the RCPROT pin and charges
Cprot. Rprot causes the voltage to rise exponentially. The protection time has elapsed when
the voltage on RCPROT reaches the upper switching level Vu(RCPROT) (4 V typical). At this
instant, the appropriate protective action is taken and Cprot is discharged.

If the error condition is removed before the voltage on RCPROT reaches Vu(RCPROT), Cprot
is discharged via Rprot and no action is taken.

The voltage on RCPROT can be raised above Vu(RCPROT) by an external circuit to force a
restart.

7.5.2.2 Restart timer

Certain error conditions require that the IC is disabled, particularly when the error
condition can cause components to overheat. In such cases, the IC must be disabled to
allow the power supply to cool down, before restarting automatically. The restart timer
determines the restart time. The restart timer is active in the Restart state. The protection
functions that trigger a restart can be found in the protection overview in Section 7.9.

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NXP Semiconductors TEA1716T
Resonant power supply control IC with PFC

yes
Restart request
no

Vu(RCPROT)

VRCPROT

Vl(RCPROT)
0

passed
Restart time
t
014aaa854

Fig 6. Operation of the restart timer

Figure 6 shows the operation of the restart timer. Normally Cprot is discharged to 0 V.
When a restart is requested, Cprot is quickly charged to the upper switching level
Vu(RCPROT). Then the RCPROT pin becomes high ohmic and Cprot discharges through
Rprot. The restart time has elapsed when VRCPROT reaches the lower switching level
Vl(RCPROT) (0.5 V typical). The IC then restarts and Cprot is discharged.

7.5.3 Fast shutdown reset (pin SNSMAINS)

The latched Protection shut-down state is reset when VSUPIC and VSUPHV drop below their
respective reset levels, Vrst(SUPIC) and Vrst(SUPHV). Typically, the PFC boost capacitor,
Cboost, requires a discharge before VSUPIC and VSUPHV drop below their reset levels, which
can take a long time.

Fast shut-down reset facilitates a faster reset. When the mains supply is interrupted, the
voltage on pin SNSMAINS drops. When VSNSMAINS falls below Vrst(SNSMAINS) and then
rises again by a hysteresis value, the IC leaves the Protection shut-down state. The boost
capacitor Cboost does not have to be discharged to initiate a new start-up.

The Protection shut-down state can also be ended by pulling down the enable input (pin
SSHBC/EN).

7.5.4 Output overvoltage protection, OVP-output (pin SNSOUT)

The TEA1716 outputs are provided with overvoltage protection (OVP-output; see
Section 7.9). The output voltage can be measured via the auxiliary winding of the
resonant transformer. This voltage can be sensed at the SNSOUT pin via an external
rectifier and resistive divider. An overvoltage is detected when the SNSOUT voltage
exceeds Vovp(SNSOUT) (3.5 V typical). Once an overvoltage has been detected, the
TEA1716 enters the Protection shut-down state.

Additional external protection circuits, such as an external overtemperature protection

circuit, can be connected to this pin. Connect them to pin SNSOUT via a diode so that the
error condition triggers an OVP event.

7.5.5 Output failed start protection, FSP-output (pin SNSOUT)

The TEA1716 outputs are provided with failed start protection (FSP output;
see Section 7.9). During start-up, the output voltage is below Vfsp(SNSOUT) for a time. This
is not an error condition if does not last longer than expected. For this reason, the
protection timer is started when VSNSOUT is below Vfsp(SNSOUT) (2.5 V typical) during
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Objective data sheet Rev. 1 — 27 January 2012 14 of 46

NXP Semiconductors TEA1716T
Resonant power supply control IC with PFC

start-up. Under normal conditions, the output voltage is present before the protection time
is expired and no protective action is taken. However, the Restart state is activated if the
FSP output event is still active when the protection time has expired.

7.5.6 OverTemperature Protection (OTP)

Accurate internal overtemperature protection is provided in the TEA1716. When the
junction temperature exceeds the overtemperature protection activation temperature, Totp
(150 C typical), the IC enters the Thermal hold state. The TEA1716 exits the Thermal
hold state when the temperature drops again, to around 10 C below Totp.

7.6 Burst mode operation (pin SNSBURST)

The HBC and PFC controllers can be operated in Burst mode. In Burst mode, the
controllers is on for a period, then off for a period. Burst mode operation increases
efficiency under low-load conditions.

The voltage on pin SNSBURST defines the transition from Operational supply state
(= burst-on period) to Burst stop state (= burst-off period) and back).

The voltage on pin SNSFB represents the level of power that is converted. The voltage on
pin SNSBURST can be related to SNSFB using an external resistor divider. Pin
SNSBURST has an internal switching level Vburst(SNSBURST) (3.5 V typical) and a fixed
hysteresis Vburst(hys)(SNSBURST) (24 mV typical). In addition, a switched current flowing into
pin SNSBURST, Iburst(hys)(SNSBURST) (3 A typical) and the resistance of the external
divider determines the effective hysteresis. The current flows when SNSBURST is below
Vburst(SNSBURST).

The operation of the PFC and HBC controller is suspended when the voltage on
SNSBURST drops below Vburst(SNSBURST). The PFC continues as long as the Boost
voltage is still below the regulation level. Then it stops with a soft stop. The HBC stops
almost directly when the GateLs becomes active. The Burst stop state is entered when
both PFC and HBC have stopped switching. In the Burst stop state, the current
consumption of the IC is low and pin SNSOUT is pulled low. This SNSOUT signal can be
used for additional functionality in the application.

When the voltage on SNSBURST increases to above

Vburst(SNSBURST) + Vburst(hys)(SNSBURST), the TEA1716 leaves the Burst stop state and
enters the Operational supply state. The PFC starts its operation with a soft start. The
HBC resumes without a soft start sequence.

Burst mode operation is not enabled until pin SNSOUT has reached the Vfsp(SNSOUT) level
once to avoid unwanted activation of the burst mode during start-up.

7.7 PFC controller

The PFC controller converts the rectified universal mains voltage into an accurately
regulated boost voltage of 400 V (DC). It operates in quasi-resonant or discontinuous
conduction mode and is controlled via an on-time control system. The resulting mains
harmonic current emissions of a typical application easily meet the class-D MHR
requirements.

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NXP Semiconductors TEA1716T
Resonant power supply control IC with PFC

The PFC controller uses valley switching to minimize losses. A primary stroke is only
started once the previous secondary stroke has ended and the voltage across the PFC
MOSFET has reached a minimum value.

7.7.1 PFC gate driver (pin GATEPFC)

The circuit driving the gate of the power MOSFET has a high current sourcing capability
Isource(GATEPFC) (500 mA typical) and a high current sink capability Isink(GATEPFC)
(1.2 A typical). This permits fast turn-on and turn-off of the power MOSFET to ensure
efficient operation. The driver is supplied from the regulated SUPREG supply.

7.7.2 PFC on-time control

The PFC operates under on-time control. The on-time of the PFC MOSFET is determined
by:

• The error amplifier and the loop compensation via the voltage on pin COMPPFC
At Vton(COMPPFC)zero (3.5 V typical), the on-time is reduced to zero. At Vton(COMPPFC)max
the on-time is at a maximum
• Mains compensation via the voltage on pin SNSMAINS
7.7.2.1 PFC error amplifier (pins COMPPFC and SNSBOOST)
The boost voltage is divided via a high-ohmic resistive divider. It is fed to the SNSBOOST
pin. The transconductance error amplifier, which compares the SNSBOOST voltage with
an accurate trimmed reference voltage Vreg(SNSBOOST), is connected to this pin. The
external loop compensation network at the COMPPFC pin filters the output current. In a
typical application, a resistor and two capacitors set the bandwidth of the regulation loop.

The transconductance of the error amplifier is not constant. This improves the start-up
behavior and transient response. The transconductance significantly increases resulting
in a higher output current to pin COMPPFC when the SNSBOOST voltage is more than
80 mV above or below the reference voltage.

The COMPPFC voltage is clamped at a maximum of Vclamp(COMPPFC). This avoids a long

recovery time if the boost voltage rises above the regulation level for a certain period.

7.7.2.2 PFC mains compensation (pin SNSMAINS)

The mathematical equation for the transfer function of a power factor corrector contains
the square of the mains input voltage. In a typical application, this results in a low
bandwidth for low mains input voltages, while at high mains input voltages the MHR
requirements can be hard to meet.

The TEA1716 contains a correction circuit to compensate for this effect. The average
mains voltage is measured via the SNSMAINS pin and this information is fed to an
internal compensation circuit. Figure 7 illustrates the relationship between the SNSMAINS
voltage, the COMPPFC voltage, and the on-time. This compensation makes it is possible
to keep the regulation loop bandwidth constant over the full mains input range. This yields
a fast transient response on load steps, while still complying with class-D MHR
requirements.

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NXP Semiconductors TEA1716T
Resonant power supply control IC with PFC

ton(max)(lowmains)
VSNSMAINS = 0.9 V

on-time

VSNSMAINS = 3.3 V
ton(max)(highmains)

0
Vton(COMPPFC)max Vton(COMPPFC)zero VCOMPPFC
014aaa855

Fig 7. Relationship between on-time, SNSMAINS voltage and COMPPFC voltage

7.7.3 PFC demagnetization sensing (pin SNSAUXPFC)

The voltage on the SNSAUXPFC pin is used to detect transformer demagnetization.
During the secondary stroke, the transformer is magnetized and current flows in the boost
output. During this time, VSNSAUXPFC < Vdemag(SNSAUXPFC) (100 mV typical) and the PFC
MOSFET is kept off.

After some time, the transformer becomes demagnetized and current stops flowing in the
boost output. From that moment, VSNSAUXPFC > Vdemag(SNSAUXPFC) and valley detection is
started. The MOSFET remains off.

The MOSFET is forced to switch on if the magnetizing of the transformer

(VSNSAUXPFC < Vdemag(SNSAUXPFC)) is not detected within tto(mag) (50 s typical) after
GATEPFC goes LOW to ensure that switching continues under all circumstances.

It is recommended that a 5 k series resistor is connected to this pin to protect the

internal circuitry, against lightning for example. Place the resistor close to the IC on the
printed circuit board to prevent incorrect switching due to external disturbances.

7.7.4 PFC valley sensing (pin SNSAUXPFC)

The PFC MOSFET is switched on for the next stroke to reduce switching losses and EMI
if the voltage at the drain of the MOSFET is at its minimum (valley switching),
see Figure 8.

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NXP Semiconductors TEA1716T
Resonant power supply control IC with PFC

on
GATEPFC
off

VBoost

VRect
Dr(PFC)

0
VRect/N

Aux(PFC)
0
Vdemag(SNSAUXPFC)
(VBoost − VRect)/N

lTr(PFC)
0

demagnetized
Demagnetization
magnetized

Valley
(= top for detection)
t
014aaa856

Fig 8. Demagnetization and valley detection

The valley sensing block connected to the SNSAUXPFC pin detects valleys. This block
measures the voltage at the auxiliary winding of the PFC transformer, which is a reduced
and inverted copy of the MOSFET drain voltage. When a valley of the drain voltage (= top
at SNSAUXPFC voltage) is detected, the MOSFET is switched on.

If no top is detected on the SNSAUXPFC pin (= valley at the drain) within tto(vrec)
(4 s typical) after demagnetization was detected, the MOSFET is forced to switch on.

7.7.5 PFC frequency and off-time limiting

For transformer optimization and to minimize switching losses, the switching frequency is
limited to fmax(PFC). If the frequency for quasi-resonant operation is above fmax(PFC), the
system switches to Discontinuous conduction mode. The PFC MOSFET is switched on
when the drain-source voltage is at a minimum (valley switching).

The minimum off-time is limited to toff(PFC)min to ensure proper control of the PFC MOSFET
under all circumstances.

7.7.6 PFC soft start and soft stop (pin SNSCURPFC)

The PFC controller features a soft start function, which slowly increases the primary peak
current at start-up. It also features a soft stop function which slowly decreases the
transformer peak current, before operations are halted. This is to prevent transformer
rattle at start-up or during Burst mode operation.

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NXP Semiconductors TEA1716T
Resonant power supply control IC with PFC

This is achieved by connecting a resistor Rss(PFC) and a capacitor Css(PFC) between

pin SNSCURPFC and the current sense resistor Rcur(PFC). At start-up, an internal current
source, Ich(ss)(PFC), charges the capacitor to VSNSCURPFC = Ich(ss)(PFC)  Rss(PFC). The
voltage is limited to the maximum PFC soft start clamp voltage, Vclamp(ss)PFC. The
additional voltage across the charged capacitor results in a reduced peak current. After
start-up, the internal current source is switched-off, capacitor Css(PFC) discharges across
Rss(PFC) and the peak current increases.

The start level and the time constant of the rising primary current can be adjusted
externally by changing the values of Rss(PFC) and Css(PFC).

V ocr  PFC  –  I ch  ss   PFC   R ss  PFC  

I Cur  PFC   pk  = ---------------------------------------------------------------------------------------------
R cur  PFC 

 = R ss  PFC   C ss  PFC 

Soft stop is achieved by switching on the internal current source Ich(ss)(PFC). This current
charges Css(PFC). The increasing capacitor voltage reduces the peak current. The charge
current flows as long as the voltage on pin SNSCURPFC is below the maximum PFC soft
start voltage (0.5 V typical). If VSNSCURPFC exceeds the maximum PFC soft start voltage,
the soft start current source starts limiting the charge current. The voltage is only
measured during the off-time of the PFC power switch to determine accurately if the
capacitor is charged. The operation of the PFC is stopped when
VSNSCURPFC > Vstop(ss)(PFC).

In the Burst stop state with the PFC not operating, pin SNSCURPFC is kept at the
maximum PFC soft start voltage. This allows an immediate start of the soft start sequence
when the PFC must operate after the Burst stop state.

7.7.7 PFC overcurrent regulation, OCR-PFC (pin SNSCURPFC)

The maximum peak current is limited cycle-by-cycle by sensing the voltage across an
external sense resistor (Rcur(PFC)) connected to the source of the external MOSFET. The
voltage is measured via the SNSCURPFC pin and is limited to Vocr(PFC).

A voltage peak appears on VSNSCURPFC when the PFC MOSFET is switched on due to the
discharging of the drain capacitance. The leading edge blanking time, tleb(PFC), ensures
that the overcurrent sensing block does not react to this transitory peak.

7.7.8 PFC mains undervoltage protection/brownout protection, UVP-mains

(pin SNSMAINS)
The voltage on the SNSMAINS pin is sensed continuously to prevent the PFC trying to
operate at very low mains input voltages. PFC switching stops as soon as VSNSMAINS
drops below Vuvp(SNSMAINS). Mains undervoltage protection is also called brownout
protection.

VSNSMAINS is clamped to a minimum value of Vpu(SNSMAINS) for fast restart as soon as the
mains input voltage recovers after a mains-dropout. The PFC (re)starts once VSNSMAINS
exceeds the start level Vstart(SNSMAINS).

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NXP Semiconductors TEA1716T
Resonant power supply control IC with PFC

7.7.9 PFC boost overvoltage protection, OVP-boost (pin SNSBOOST)

An overvoltage protection circuit has been built in to prevent boost overvoltages during
load steps and mains transients.

Switching of the power factor correction circuit is inhibited as soon as the voltage on the
SNSBOOST pin rises above Vovp(SNSBOOST). PFC switching resumes as soon as
VSNSBOOST drops below Vovp(SNSBOOST) again.

Overvoltage protection is also triggered in the event of an open circuit at the resistor
connected between SNSBOOST and ground.

7.7.10 PFC short circuit/open-loop protection, SCP/OLP-PFC (pin SNSBOOST)

The power factor correction circuit does not start switching until the voltage on the
SNSBOOST pin rises above Vscp(SNSBOOST). This acts as short circuit protection for the
boost voltage (SCP-boost).

The SNSBOOST pin draws a small input current Iprot(SNSBOOST). If this pin gets
disconnected, the residual current pulls down VSNSBOOST, triggering short circuit
protection (SCP-boost). This combination creates an open-loop protection (OLP-PFC).

7.8 HBC controller

The HBC controller converts the 400 V boost voltage from the PFC into one or more
regulated DC output voltages. It drives two external MOSFETS in a half-bridge
configuration connected to a transformer. The transformer, which has a leakage
inductance and a magnetizing inductance, forms the resonant circuit in combination with
the resonant capacitor and the load at the output. The regulation is realized via frequency
control.

7.8.1 HBC high-side and low-side driver (pin GATEHS and GATELS)
Both drivers have identical driving capability. The output of each driver is connected to the
equivalent gate of an external high-voltage power MOSFET.

The low-side driver is referenced to pin PGND and is supplied from SUPREG.

The high-side driver is floating. The reference for the high-side driver is pin HB, connected
to the midpoint of the external half-bridge. The high-side driver is supplied from SUPHS
which is connected to the external bootstrap capacitor CSUPHS. The bootstrap capacitor is
charged from SUPREG via external diode DSUPHS when the low-side MOSFET is on.

7.8.2 HBC boost undervoltage protection, UVP-boost (pin SNSBOOST)

The voltage on the SNSBOOST pin is sensed continuously to prevent the HBC controller
trying to operate at very low boost input voltages. Once VSNSBOOST drops below
Vuvp(SNSBOOST), HBC switching stops the next time GATELS goes HIGH. HBC switching
resumes as soon as VSNSBOOST rises above Vstart(SNSBOOST).

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NXP Semiconductors TEA1716T
Resonant power supply control IC with PFC

7.8.3 HBC switch control

HBC switch control determines when the MOSFETs switch on and off. It uses the output
from several other blocks.

• A divider is used to realize alternate switching of the high- and low-side MOSFETs for
each oscillator cycle. The oscillator frequency is twice the half-bridge frequency.
• The controlled oscillator determines the switch-off point.
• Adaptive non-overlap time sensing determines the switch-on point. This is the
adaptive non-overlap time function.
• Several protection circuits and the state of the SSHBC/EN input determine whether
the resonant converter is allowed to start switching.

Figure 9 provides an overview of typical switching behavior.

GATEHS

GATELS

VBoost

HB

ITr(HBC) 0

CFMIN
t
014aaa857

Fig 9. Switching behavior of the HBC

7.8.4 HBC Adaptive Non-Overlap (ANO) time function (pin HB)

7.8.4.1 Inductive mode (normal operation)

The high efficiency characteristic of a resonant converter is the result of Zero-Voltage
Switching (ZVS) of the power MOSFETs, also called soft switching. To facilitate soft
switching, a small non-overlap time is required between the on-times of the high- and
low-side MOSFETs. During this non-overlap time, the primary resonant current charges or
discharges the capacitance of the half-bridge between ground and the boost voltage. After
this charge/discharge, the body diode of the MOSFET starts conducting. Because the
voltage across the MOSFET is zero, there are no switching losses when the MOSFET is
switched on. This mode of operation is called inductive mode because the switching
frequency is above the resonance frequency and the resonant tank has an inductive
impedance.

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NXP Semiconductors TEA1716T
Resonant power supply control IC with PFC

The time required for the HB transition depends on the amplitude of the resonant current
at the instant of switching. There is a complex relationship between this amplitude, the
frequency, the boost voltage and the output voltage. Ideally the IC switch on the MOSFET
as soon as the HB transition has been completed. If it waits any longer, the HP voltage
can swing back, especially at high output loads. The advanced adaptive non-overlap time
function takes care of this timing, so that choosing a fixed dead time (which is always a
compromise) is not required. This saves on external components.

Adaptive non-overlap time sensing measures the HB slope after one MOSFET has been
switched off. Normally, the HB slope starts immediately (the voltage starts rising or falling).
Once the transition at the HB node is complete, the slope ends (the voltage stops
rising/falling), which the ANO time sensor detects. The other MOSFET is switched on. In
this way, the non-overlap time is optimized automatically, minimizing switching losses,
even if the HB transition cannot be fully completed. Figure 10 illustrates the operation of
the adaptive non-overlap time function in Inductive mode.

GATEHS

GATELS

VBoost

HB

0 t
fast HB slope slow HB slope incomplete HB slope
014aaa858

Fig 10. Adaptive non-overlap time function (normal inductive operation)

The non-overlap time depends on the HB slope, but has upper and lower limits.

An integrated minimum non-overlap time, tno(min), prevents cross conduction occurring

under any circumstances.

The maximum non-overlap time is limited to the oscillator charge time. If the HB slope
lasts longer than the oscillator charge time (= 1⁄4 of HB switching period), the MOSFET is
forced to switch on. In this case, the MOSFET is not soft switching. This limitation ensures
that, at very high switching frequencies, the MOSFET on-time is at least 1⁄4 of the HB
switching period.

7.8.4.2 Capacitive mode

The description above holds for normal operation with a switching frequency above the
resonance frequency. When an error condition occurs (for example, output short, load
pulse too high) the switching frequency can be lower than the resonance frequency. The
resonant tank then has a capacitive impedance. In Capacitive mode, the HB slope does
not start after the MOSFET has switched off. Switching on the other MOSFET is not
recommended in this situation. The absence of soft switching increases dissipation in the

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NXP Semiconductors TEA1716T
Resonant power supply control IC with PFC

MOSFETs. In Capacitive mode, the body diode in the switched-off MOSFET can start
conducting. Switching on the other MOSFET at this instant can result in the immediate
destruction of the MOSFETs.

The advanced adaptive non-overlap time of the TEA1716 always waits until the slope at
the half-bridge node starts. It guarantees safe switching of the MOSFETs in all
circumstances. Figure 11 illustrates the operation of the adaptive non-overlap time
function in Capacitive mode.

In Capacitive mode, half the resonance period can elapse before the resonant current
changes back to the correct polarity and starts charging the half-bridge node. The
oscillator is slowed down until the half-bridge slope starts to allow this relatively long
waiting time. See Section 7.8.5 for more details on the oscillator.

GATEHS
0

GATELS
0

VBoost

no HB slope
HB

wrong polarity

ITr(HBC) 0

CFMIN
0 t
delayed
oscillator
014aaa939

delayed switch-on
during capacitive mode

Fig 11. Adaptive non-overlap time function (capacitive operation)

The MOSFET is forced to switch on if the half-bridge slope fails to start and the oscillator
voltage reaches Vu(CFMIN).

The switching frequency is increased to eliminate the problems associated with

Capacitive mode operation (see Section 7.8.11).

7.8.5 HBC slope controlled oscillator (pin CFMIN)

The slope-controlled oscillator determines the switching frequency of the half-bridge. The
oscillator generates a triangular waveform between Vu(CFMIN) and Vl(CFMIN) at the external
capacitor Cfmin.

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NXP Semiconductors TEA1716T
Resonant power supply control IC with PFC

Figure 12 shows how the frequency is determined.

FEEDBACK CURRENT
VOLTAGE PIN SSHBC
PIN SNSFB

POLARITY INVERSION CONVERSION TO

(max 2.5 V) VOLTAGE (max 1.5 V)

VOLTAGE ACROSS
Rfmax

CONVERSION TO CURRENT
FIXED fmin CURRENT
via Rfmax

(DIS-)CHARGE CURRENT
PIN CFMIN

CONVERSION TO
FRQUENCY via Cfmin
aaa-000767

Fig 12. Determination of frequency

Two components determine the frequency range:

• Capacitor Cfmin connected between pin CFMIN and ground sets the minimum
frequency in combination with an internally trimmed current source Iosc(min)
• The internal resistor Rfmax sets the frequency range and thus the maximum frequency.
Resistor Rfmax has a fixed value (18 k typical)

The oscillator frequency depends on the charge and discharge currents of Cfmin. The
charge /discharge current contains a fixed component, Iosc(min). This component
determines the minimum frequency. It also contains a variable component that is 4.9 times
greater than the current flowing through resistor Rfmax:

• The voltage across resistor Rfmax is Vfmin(RFMAX) (0 V typical) at the minimum

frequency
• The voltage across resistor Rfmax is Vfmax(fb)(RFMAX) (1.5 V typical) at the maximum
feedback frequency
• The voltage across resistor Rfmax is Vfmax(ss)(RFMAX) (2.5 V typical) at the maximum
soft start frequency

The maximum frequency of the oscillator is limited internally. The HB frequency is limited
to flimit(HB) (minimum 500 kHz).

the slope of the half-bridge controls the oscillator. The oscillator charge current is initially
set to a low value Iosc(red) (30 A typical). When the start of the half-bridge slope is
detected, the charge current is increased to its normal value. This feature is used in
combination with the adaptive non-overlap time function as described in Section 7.8.4.2
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NXP Semiconductors TEA1716T
Resonant power supply control IC with PFC

and Figure 11. Since the half-bridge slope normally starts directly after the MOSFET is
switched off, the length of time the oscillator current is low is negligible under normal
operating conditions.

7.8.6 HBC feedback input (pin SNSFB)

In a typical power supply application, the output voltage is compared and amplified on the
secondary side. The output of the error amplifier is transferred to the primary side via an
optocoupler. This optocoupler can be connected to the SNSFB pin. The current setting of
the optocoupler can be selected using the external pull-up resistor.

The SNSFB pin is a voltage input. At an SNSFB voltage of Vfmin(SNSFB) (6.4 V typical) the
frequency is at a minimum. The maximum frequency is reached at Vfmax(SNSFB)
(4.1 V typical). The maximum frequency that can be reached using pin SNSFB is lower
(60 % typical) than the maximum frequency that can be reached using pin SSHBC/EN.

7.8.7 HBC open-loop protection, OLP-HBC (pin SNSFB)

Under normal operating conditions, the optocoupler current is between Ifmin(SNSFB) and
Ifmax(SNSFB) and pulls down the voltage at pin SNSFB. Due to an error in the feedback
loop, the current could be less than Ifmin(SNSFB) with the HBC controller delivering
maximum output power.

The HBC controller features open-loop protection (OLP-HBC), which monitors the voltage
on pin SNSFB. When VSNSFB exceeds Volp(SNSFB), the protection timer is started. The
Restart state is activated if the OLP condition is still present after the protection time has
elapsed.

7.8.8 HBC soft start (pin SSHBC/EN)

The relationship between switching frequency and output current is not constant. It
depends strongly on the output voltage and the boost voltage. This relationship can be
complex. The TEA1716 contains a soft start function to ensure that the resonant converter
starts or restarts with safe currents. This soft start function forces a start at such a high
frequency that currents are acceptable under all conditions. Soft start then slowly
decreases the frequency. Normally, output voltage regulation has taken over frequency
control before soft start has reached its minimum frequency. Limiting the output current
during start-up also limits the rate at which the output voltage rises and prevents an
overshoot.

Soft start utilizes the voltage on pin SSHBC/EN. external capacitor Css(HBC) sets the timing
of the soft start. Pin SSHBC/EN is also used as an enable input. Soft start voltage levels
are above the enable voltage thresholds.

7.8.8.1 Soft start voltage levels

Figure 13 shows the relationship between the soft start voltage at pin SSHBC/EN and the
voltage across resistor Rfmax, which is directly related to the frequency.

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NXP Semiconductors TEA1716T
Resonant power supply control IC with PFC

VRFMAX fmax
fHB
Vfmax,ss(RFMAX)
fHB

Vfmax,fb(RFMAX)
VRFMAX
fmin

0
0 Vfmax(SSHBC) Vclamp(SSHBC)
Vpu(EN) Vfmin(SSHBC)
VSSHBC

ISNSFB < Ifmin(SNSFB)

Ifmin(SNSFB) < ISNSFB < Ifmax(SNSFB)
014aaa863

Fig 13. Relation between SSHBC/EN voltage and frequency

VRFMAX and VSSHBC/EN are of opposite polarity. At initial start-up, VSSHBC/EN is below
Vfmax(SSHBC) (3.2 V typical), which corresponds to the maximum frequency. During
start-up, Css(HBC) is charged, VSSHBC/EN rises and the frequency decreases. The
contribution of the soft start function is zero when VSSHBC/EN is above Vfmin(SSHBC)
(7.9 V typical).

VSSHBC/EN is clamped at a maximum of Vclamp(SSHBC) (8.4 V typical) (frequency is at a

minimum) and at a minimum ( 3 V). Below Vfmax(SSHBC) (maximum frequency), the
discharge current is reduced to a maximum-frequency soft start current of typically 5 A
The voltage is clamped at a minimum of Vpu(EN) (3 V typical). Both clamp levels are just
outside the operating area of Vfmax(SSHBC) to Vfmin(SSHBC). The margins avoid frequency
disturbance during normal output voltage regulation, but ensure that overcurrent
regulation can respond quickly.

7.8.8.2 Soft start charge and discharge

At initial start-up, the soft start capacitor Css(HBC) is charged to obtain a decreasing
frequency sweep from maximum to operating frequency. In addition to being used to soft
start-up the resonant converter, the soft start functionality is used for regulation purposes
(such as overcurrent regulation). Css(HBC) can therefore be charged or discharged. If
overcurrent regulation occurs, a continuous alternation between charging and discharging
takes place. In this way, VSSHBC/EN can be regulated, overruling the signal from the
feedback input.

The charge/discharge current can have a high value, Iss(hf)(SSHBC) (160 A typical),
resulting in a fast charge/discharge. Or it can have a low value, Iss(lf)(SSHBC) (40 A
typical), resulting in a slow charge/discharge. This two-speed soft start sweep allows for a
combination of a short start-up time for the resonant converter and stable regulation loops
(such as overcurrent regulation).

The high charge/discharge speed is used for the upper frequency range where
VSSHBC/EN is below Vss(hf-lf)(SSHBC) (5.6 V typical). In the upper frequency range, the
currents in the converter do not react strongly to frequency variations.

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Resonant power supply control IC with PFC

The low charge/discharge speed is used for the lower frequency range where
VSSHBC/EN exceeds Vss(hf-lf)(SSHBC) (5.6 V typical). In the lower frequency range, the
currents in the converter react strongly to frequency variations.

Section 7.8.10.2 describes how the two-speed soft start function is used for overcurrent
regulation.

The soft start capacitor is not charged or discharged during non-operation time in Burst
mode. The soft start voltage does not change during this time.

7.8.8.3 Soft start reset

Some protection functions, such as overcurrent protection, require fast correction of the
operating frequency set point, but do not require switching to stop. See the protection
overview in Section 7.9 for details on which protection functions use this step to the
maximum frequency. The TEA1716 has a special fast soft start reset feature for the HBC
controller that forces Vfmax(ss)(RFMAX) on pin RFMAX. Soft start reset is also used when the
HBC controller is enabled via the SSHBC/EN pin or after a restart to ensure a safe start at
maximum frequency. Soft start reset is not used when the operation was stopped in Burst
mode.

When a protection function is activated, the oscillator control input is disconnected from
the soft start capacitor, Css(HBC), which is connected between pin SSHBC/EN and ground.
The switching frequency is immediately set to a maximum. Setting the switching
frequency to a maximum restores safe switching operation in most cases. At the same
time, the capacitor is discharged to the maximum frequency level, Vfmax(SSHBC). Once
VSSHBC/EN has reached this level, the oscillator control input is connected to the pin again
and the normal soft start sweep follows. Figure 14 shows the soft start reset and the
two-speed frequency sweep downwards.

on
Protection
off

Vfmin(SSHBC)

VSSHBC/EN Vss(hf-lf)(SSHBC)

Vfmax(SSHBC)

fmax

fHB
fmin

0 t
regulation fmax fast slow sweep regulation
forced sweep
014aaa864

Fig 14. Soft start reset and two-speed soft start

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7.8.9 HBC high-frequency protection, HFP-HBC

Normally the converter does not operate continuously at maximum frequency because it
sweeps down to much lower values. Certain error conditions, such as a disconnected
transformer, can cause the converter to operate continuously at maximum frequency. If
zero-voltage switching conditions are no longer present, the MOSFETs can overheat. The
TEA1716 features High-Frequency Protection (HFP) for the HBC controller to protect it
from being damaged in such circumstances.

HFP senses the voltage across the internal resistor Rfmax. This voltage indicates the
current frequency. When the frequency is higher than 75 % of the soft start frequency
range, the protection timer is started. The 75 % level corresponds to an Rfmax voltage of
Vhfp(RFMAX) (1.83 V typical).

7.8.10 HBC overcurrent regulation and protection, OCR and OCP

(pin SNSCURHBC)
The HBC controller is protected against overcurrent in two ways:

• Overcurrent regulation (OCR-HBC) which increases the frequency slowly; the

protection timer is also started.
• Overcurrent protection (OCP-HBC) which steps to maximum frequency.
A boost voltage compensation function is included to reduce the variation in the output
current protection level.

7.8.10.1 Boost voltage compensation

The primary current, also known as the resonant current, is sensed via pin SNSCURHBC.
It senses the momentary voltage across an external current sense resistor Rcur(HBC). The
use of the momentary current signal allows for fast overcurrent protection and simplifies
the stabilizing of overcurrent regulation. The OCR and OCP comparators compare
VSNSCURHBC with the maximum positive and negative values.

For the same output power, the primary current is higher when the boost voltage is low. A
boost compensation is included to reduce the dependency of the protected output current
level on the boost voltage. The boost compensation sources and sinks a current from the
SNSCURHBC pin. This current creates a voltage drop across the series resistor Rcurcmp.

The amplitude of the current depends linearly on the boost voltage. At nominal boost
voltage, the current is zero and the voltage VCur(HBC) across the current sense resistor is
also present at the SNSCURHBC pin. At the UVP-boost start level Vuvp(SNSBOOST), the
current is at a maximum. The direction of the current, sink or source, depends on the
active gate signal. The voltage drop created across Rcurcmp reduces the amplitude at the
pin, resulting in a higher effective current protection level. The value of Rcurcmp sets the
amount of compensation. Figure 15 shows how the boost compensation works for an
artificial current signal. The sinking compensation current only flows when VSNSCURHBC is
positive because of the circuit implementation.

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NXP Semiconductors TEA1716T
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Vreg
VBoost
Vuvp

GATEHS
t

GATELS
t

sink
sink current only with positive VSNSCURHBC
ISNSCURHBC 0 t
source

VCur(HBC) = Rcur(HBC) × ICur(HBC)

Iocp(high)
Iocr(high)
Iocp(nom)
Iocr(nom)
ICur(HBC) 0 t
−Iocr(nom)
−Iocp(nom)
−Iocr(high)
−Iocp(high)

VSNSCURHBC

Vocp(HBC)
Vocr(HBC)
VSNSCURHBC
0 t
−Vocr(HBC)
−Vocp(HBC)

nominal VBoost nominal VBoost low VBoost low VBoost

no compensation no compensation strong compensation strong compensation
nominal OCR nominal OCP high OCR high OCP
014aaa865

Fig 15. Boost voltage compensation

7.8.10.2 Overcurrent regulation, OCR-HBC

The lowest comparator levels at the SNSCURHBC pin, Vocr(HBC) (0.5 V and
+0.5 V typical), relate to the overcurrent regulation voltage. There are comparators for
both the positive and negative polarities. The positive comparator is active during the
high-side on-time and the following high-side to low-side non-overlap time. The negative
comparator is active during the remaining time. If either level is exceeded, the frequency
is slowly increased. Discharging the soft start capacitor accomplishes this. Each time the
OCR level is exceeded, the event is latched until the next stroke and the soft start
discharge current is enabled. When both the positive and negative OCR levels are
exceeded, the soft start discharge current flows continuously.

Overcurrent regulation is very effective at limiting the output current during start-up. A
smaller soft start capacitor can be used to achieve a faster start-up. Using a smaller
capacitor can result in an output current that is too high at times. However, the OCR
function slows down the frequency sweep when required to keep the output current within
the specified limits. Figure 16 shows the operation of the OCR during output voltage
start-up.

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Iocr

ICur(HBC) 0 t

−Iocr

Iss(hf)(SSHBC)

ISSHBC/EN Iss(If)(SSHBC)
−Iss(If)(SSHBC) t

−Iss(hf)(SSHBC)

Vfmin(SSHBC)
VSSHBC/EN
Vss(hf-lf)(SSHBC)

Vfmax(SSHBC)

0 t

Vreg

VOutput

0 t

Fast soft-start sweep (charge and discharge) Slow soft-start sweep (charge and discharge)

014aaa866

Fig 16. Overcurrent regulation during start-up

The protection timer is also started. The Restart state is activated when the OCR-HBC
condition is still present after the protection time has elapsed.

7.8.10.3 Overcurrent protection, OCP-HBC

Under normal operating conditions, OCR is able to ensure the current remains below the
specified maximum values. If certain error conditions occur, however, it is probably not
fast enough to limit the current. OCP is implemented to protect against those error
conditions. The OCP level, Vocp(HBC) (1.75 V and +1.75 V typical), is higher than the
OCR level Vocr(HBC).

When the OCP level is reached, the frequency immediately jumps to the maximum value
via the soft start reset, followed by a normal sweep down.

7.8.11 HBC capacitive mode regulation, CMR (pin HB)

The MOSFETs in the half-bridge drive the resonant circuit. Depending on the output load,
the output voltage, and the switching frequency this resonant circuit can have an inductive
impedance or a capacitive impedance. Inductive impedance is preferred because it
facilitates efficient zero-voltage switching.

The adaptive non-overlap time function (see Section 7.8.4.2) prevents harmful switching
in Capacitive mode. An extra action is performed which results in Capacitive Mode
Regulation (CMR). CMR causes the half-bridge circuit to return to Inductive mode from
Capacitive mode.
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Capacitive mode is detected when the HB slope does not start within tto(cmr) after the
MOSFETs have switched off. Detection of Capacitive mode increases the switching
frequency. Discharging the soft start capacitor with a relatively high current Icmr(hf)(SSHBC)
from the moment tto(cmr) has expired until the half-bridge slope has started realizes this
increase. The frequency increase regulates the HBC to the border between capacitive
and inductive mode.

7.9 Protection overview

Table 4. Overview protections
Protected Symbol Protection Affected Action Description
Part
IC UVP-SUPIC Undervoltage protection SUPIC IC disable Section 7.2.1
IC UVP-SUPREG Undervoltage protection SUPREG IC disable Section 7.2.2
IC UVP-supplies Undervoltage protection supplies IC disable and reset Section 7.3
IC SCP-SUPIC Short circuit protection SUPIC IC low HV start-up current Section 7.2.4
IC OVP-output Overvoltage protection output IC shut-down Section 7.5.4
IC FSP-output Failed start protection output IC restart after protection time Section 7.5.5
IC OTP Overtemperature protection IC disable Section 7.5.6
PFC OCR-PFC Overcurrent regulation PFC PFC switch off cycle-by-cycle Section 7.7.7
PFC UVP-mains Undervoltage protection mains PFC suspend switching Section 7.7.8
PFC OVP-boost Overvoltage protection boost PFC suspend switching Section 7.7.9
PFC SCP-boost Short circuit protection boost IC restart Section 7.7.10
PFC OLP-PFC Open-loop protection PFC IC restart Section 7.7.10
HBC UVP-boost Undervoltage protection boost HBC disable Section 7.8.2
HBC OLP-HBC Open-loop protection HBC IC restart after protection time Section 7.8.7
HBC HFP-HBC High-frequency protection HBC IC restart after protection time Section 7.8.9
HBC OCR-HBC Overcurrent regulation HBC HBC increase frequency Section 7.8.10.2
IC restart after protection time
HBC OCP-HBC Overcurrent protection HBC HBC step to maximum Section 7.8.10.3
frequency
HBC CMR Capacitive mode regulation HBC increase frequency Section 7.8.11
HBC ANO Adaptive non-overlap HBC prevent hazardous Section 7.8.4
switching

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8. Limiting values
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).; All voltages are measured with respect to pin SGND;
Currents are positive when flowing into the IC; The voltage ratings are valid provided other ratings are not violated; Current
ratings are valid provided the maximum power rating is not violated.
Symbol Parameter Conditions Min Max Unit
Voltages
VSUPHV voltage on pin SUPHV continuous 0.4 +630 V
VSUPHS voltage on pin SUPHS DC 0.4 +570 V
t < 0.5 s 0.4 +630 V
referenced to pin HB 0.4 +14 V
VSUPIC voltage on pin SUPIC 0.4 +38 V
VSNSAUXPFC voltage on pin SNSAUXPFC 25 +25 V
VSUPREG voltage on pin SUPREG 0.4 +12 V
VSNSOUT voltage on pin SNSOUT 0.4 +12 V
VRCPROT voltage on pin RCPROT 0.4 +12 V
VSNSFB voltage on pin SNSFB 0.4 +12 V
VSSHBC/EN voltage on pin SSHBC/EN 0.4 +12 V
VSNSBURST voltage on pin SNSBURST 0.4 +12 V
VGATEHS voltage on pin GATEHS t < 10 µs for I > 10 mA 0.4 VSUPHS + 0.4 V
VGATELS voltage on pin GATELS t < 10 µs for I > 10 mA 0.4 VSUPREG + 0.4 V
VGATEPFC voltage on pin GATEPFC t < 10 µs for I > 10 mA 0.4 VSUPREG + 0.4 V
VSNSCURHBC voltage on pin SNSCURHBC 5 +5 V
VSNSBOOST voltage on pin SNSBOOST 0.4 +5 V
VSNSMAINS voltage on pin SNSMAINS 0.4 +5 V
VSNSCURPFC voltage on pin SNSCURPFC current limited 0.4 +5 V
VCOMPPFC voltage on pin COMPPFC 0.4 +5 V
VCFMIN voltage on pin CFMIN 0.4 +5 V
VPGND voltage on pin PGND 1 +1 V
Currents
IGATEPFC current into pin GATEPFC duty cycle < 10 % 0.8 +2 A
ISNSCURPFC current into pin SNSCURPFC 1 +10 mA
General
Ptot total power dissipation Tamb < 75 C - 0.8 W
Tstg storage temperature 55 +150 C
Tj junction temperature 40 +150 C

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Table 5. Limiting values …continued

In accordance with the Absolute Maximum Rating System (IEC 60134).; All voltages are measured with respect to pin SGND;
Currents are positive when flowing into the IC; The voltage ratings are valid provided other ratings are not violated; Current
ratings are valid provided the maximum power rating is not violated.
Symbol Parameter Conditions Min Max Unit
ESD
VESD electrostatic discharge voltage Human body model
Pin 12 (SUPHV) [1] - 1500 V
Pin 13,14,15 (HS driver) [1] - 1000 V
other pins [1] - 2000 V
Machine model
All pins [2] - 200 V
Charged device model
All pins - 500 V

[1] Equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor.

[2] Equivalent to discharging a 200 pF capacitor through a 0.75 H coil and a 10  resistor.

9. Thermal characteristics
Table 6. Thermal characteristics
Symbol Parameter Conditions Typ Unit
Rth(j-a) thermal resistance from junction to ambient In free air; JEDEC single 90 K/W
layer test board

10. Characteristics
Table 7. Characteristics
Tamb = 25 C; VSUPIC = 20 V; VSUPHV > 40 V; all voltages are measured with respect to SGND; currents are positive when
flowing into the IC; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
High-voltage start-up source (pin SUPHV)
Idism(SUPHV) disable mode current on pin Disabled IC state - 150 - A
SUPHV
Ired(SUPHV) reduced current on pin SUPHV VSUPIC < Vscp(SUPIC) - 1.1 - mA
Inom(SUPHV) nominal current on pin SUPHV VSUPIC < Vstart(hvd)(SUPIC) - 5.1 - mA
Itko(SUPHV) takeover current on pin SUPHV VSUPIC > Vstart(hvd)(SUPIC) - 7 - A
Vdet(SUPHV) detection voltage on pin SUPHV - - 25 V
Vrst(SUPHV) reset voltage on pin SUPHV VSUPIC < Vrst(SUPIC) - 7 - V
Low-voltage IC supply (pin SUPIC)
Vstart(hvd)(SUPIC) start voltage with high voltage VSUPHV > Vdet(SUPHV) - 20 - V
detected
Vstart(nohvd)(SUPIC) start voltage with no high voltage VSUPHV < Vdet(SUPHV) or open - 15 - V
detected
Vstart(hys)(SUPIC) hysteresis of start voltage on pin - 0.3 - V
SUPIC

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Table 7. Characteristics …continued

Tamb = 25 C; VSUPIC = 20 V; VSUPHV > 40 V; all voltages are measured with respect to SGND; currents are positive when
flowing into the IC; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Vuvp(SUPIC) undervoltage protection voltage on - 13 - V
pin SUPIC
Vrst(SUPIC) reset voltage on pin SUPIC VSUPHV < Vrst(SUPHV) - 7 - V
Vscp(SUPIC) short-circuit protection voltage on 0.55 0.65 0.75 V
pin SUPIC
Ich(red)(SUPIC) reduced charge current on pin VSUPIC < Vscp(SUPIC) - 0.95 - mA
SUPIC
Ich(nom)(SUPIC) nominal charge current on pin - 4.8 - mA
SUPIC
Idism(SUPIC) current on pin SUPIC in disabled Disabled IC state - 0.25 - mA
mode
Iprotm(SUPIC) current on pin SUPIC in protection SUPIC charge, SUPREG - 0.4 - mA
mode charge; Restart or
Shut-down state
Ioper(SUPIC) current on pin SUPIC in operating Operational supply state; - 3 - mA
mode Driver pins open.
Iburstm(SUPIC) burst mode current on pin SUPIC Burst stop state - 0.7 - mA
Regulated supply (pin SUPREG)
Vreg(SUPREG) regulation voltage on pin SUPREG ISUPREG = 40 mA [1] - 11.3 - V
Vstart(SUPREG) start voltage on pin SUPREG [1] - 10.7 - V
Vuvp(SUPREG) undervoltage protection voltage on [1] - 10 - V
pin SUPREG
Ich(SUPREG)max maximum charge current on pin VSUPREG > Vuvp(SUPREG) 40 100 - mA
SUPREG
Ich(red)(SUPREG) reduced charge current on pin VSUPREG < Vuvp(SUPREG); - 5.5 - mA
SUPREG T = 25 C.
T = 140 C 2.5 - - mA
Enable input (pin SSHBC/EN)
Ven(PFC)(EN) PFC enable voltage on pin EN PFC only [2] 0.8 1.2 1.4 V
Ven(IC)(EN) IC enable voltage on pin EN PFC + HBC [2] 1.8 2.2 2.4 V
Ipu(EN) pull-up current on pin EN VSSHBC/EN = 2.5 V - 42 - A
Vpu(EN) pull-up voltage on pin EN - 3.0 - V
Fast shut-down reset (pin SNSMAINS)
Vrst(SNSMAINS) reset voltage on pin SNSMAINS [2] - 0.8 - V
Protection and restart timer (pin RCPROT)
Vu(RCPROT) upper voltage on pin RCPROT 3.8 4.0 4.2 V
Vl(RCPROT) lower voltage on pin RCPROT 0.4 0.5 0.6 V
Ich(fast)(RCPROT) fast-charge current on pin RCPROT - 2.2 - mA
Ich(slow)(RCPROT) slow-charge current on pin 120 100 80 A
RCPROT
Output voltage protection sensing, OVP/FSP output (pin SNSOUT)
Vovp(SNSOUT) overvoltage protection voltage on [2] 3.40 3.50 3.60 V
pin SNSOUT

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Table 7. Characteristics …continued

Tamb = 25 C; VSUPIC = 20 V; VSUPHV > 40 V; all voltages are measured with respect to SGND; currents are positive when
flowing into the IC; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Vfsp(SNSOUT) failed start protection voltage on pin [2] - 2.5 - V
SNSOUT
Ipu(SNSOUT) pull-up current on pin SNSOUT - 75 - nA
Overtemperature protection
Totp overtemperature protection trip [2] 130 150 160 C
Burst mode activation (pin SNSBURST)
Vburst(SNSBURST) burst mode voltage on pin [2] - 3.5 - V
SNSBURST
Vburst(hys)SNSBURST burst mode hysteresis voltage on [2] - 24 - mV
pin SNSBURST
Iburst(hys)SNSBURST burst mode hysteresis current on VSNSBURST < Vburst(SNSBURST) - 3 - A
pin SNSBURST
PFC driver (pin GATEPFC)
Isource(GATEPFC) source current on pin GATEPFC VGATEPFC = 2 V - 0.5 A
Isink(GATEPFC) sink current on pin GATEPFC VGATEPFC = 2 V - 0.7 - A
VGATEPFC = 10 V - 1.2 - A
PFC on-timer (pin COMPPFC)
Vton(COMPPFC)zero zero on-time voltage on pin - 3.5 - V
COMPPFC
Vton(COMPPFC)max maximum on-time voltage on pin - 1.25 - V
COMPPFC
fmax(PFC) PFC maximum frequency 100 125 150 kHz
toff(PFC)min minimum PFC off-time - 1.4 - s
PFC error amplifier (pin SNSBOOST and COMPPFC)
Vreg(SNSBOOST) regulation voltage on pin ICOMPPFC = 0 2.475 2.500 2.525 V
SNSBOOST pin
gm transconductance VSNSBOOST to ICOMPPFC - 80 - A/V
Isink(COMPPFC) sink current on pin COMPPFC VSNSBOOST = 3.3 V - 39 - A
Isource(COMPPFC) compensation source current VSNSBOOST = 2.0 V - <tbd> - A
Vclamp(COMPPFC) clamp voltage on pin COMPPFC [3] - <tbd> - V
PFC mains compensation (pin SNSMAINS)
ton(max) maximum on-time high mains; 3.5 4.7 5.9 s
VSNSMAINS = 3.3 V
low mains; 29 44 59 s
VSNSMAINS = 0.97 V
Vmvc(SNSMAINS)max maximum mains voltage 4.0 - - V
compensation voltage on pin
SNSMAINS
PFC demagnetization sensing (pin SNSAUXPFC)
Vdemag(SNSAUXPFC) demagnetization voltage on pin 150 100 50 mV
SNSAUXPFC
tto(mag) magnetization time-out time 40 50 60 s

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Table 7. Characteristics …continued

Tamb = 25 C; VSUPIC = 20 V; VSUPHV > 40 V; all voltages are measured with respect to SGND; currents are positive when
flowing into the IC; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Iprot(SNSAUXPFC) protection current on pin VSNSAUXPFC = 50 mV 75 33 - nA
SNSAUXPFC
PFC valley sensing (pin SNSAUXPFC)
(dV/dt)vrec(min) minimum valley recognition rate of - - 1.7 V/s
voltage change
tslope(vrec)min minimum valley recognition slope VSNSAUXPFC = 1 Vpp [4] - - 300 ns
time demagnetization to V/t = 0 [5] - - 50 ns
td(val-dem)max maximum - 200 - ns
valley-to-demagnetization delay
time
tto(vrec) valley recognition time-out time 3 4 6 s
PFC soft start (pin SNSCURPFC)
Ich(ss)(PFC) PFC soft-start charge current - 60 - A
Vclamp(ss)(PFC) PFC soft-start clamp voltage [1] 0.46 0.50 0.54 V
Vstop(ss)(PFC) PFC soft-start stop voltage [1] - 0.45 - V
Rss(PFC) PFC soft-start resistor 12 - - k
PFC overcurrent sensing (pin SNSCURPFC)
Vocr(PFC) PFC overcurrent regulation voltage dV/dt = 50 mV/s 0.49 0.52 0.55 V
dV/dt = 200 mV/s 0.51 0.54 0.57 V
tleb(PFC) PFC leading edge blanking time 250 310 370 ns
Iprot(SNSCURPFC) protection current on pin 50 33 - nA
SNSCURPFC
PFC mains voltage sensing and clamp (pin SNSMAINS)
Vstart(SNSMAINS) start voltage on pin SNSMAINS [1] 1.11 1.15 1.19 V
Vuvp(SNSMAINS) undervoltage protection voltage on [1] 0.84 0.89 0.94 V
pin SNSMAINS
Vpu(SNSMAINS) pull-up voltage on pin SNSMAINS UVP-mains active [1] - 1.05 - V
Ipu(SNSMAINS) maximum clamp current UVP-mains active - 42 35 A
Iprot(SNSMAINS) Protection current on pin VSNSMAINS > Vuvp(SNSMAINS) - 33 100 nA
SNSMAINS
PFC boost voltage protection sensing, SCP/UVP/OVP boost (pin SNSBOOST)
Vscp(SNSBOOST) short-circuit protection voltage on 0.35 0.40 0.45 V
pin SNSBOOST
Vstart(SNSBOOST) start voltage on pin SNSBOOST - 2.30 2.40 V
Vuvp(SNSBOOST) undervoltage protection voltage on 1.50 1.60 - V
pin SNSBOOST
Vovp(SNSBOOST) overvoltage protection voltage on 2.59 2.63 2.67 V
pin SNSBOOST
Iprot(SNSBOOST) protection current on pin VSNSBOOST = 2.5 V - 45 100 nA
SNSBOOST
HBC high-side and low-side driver (pin GATEHS and GATELS)
Isource(GATEHS) source current on pin GATEHS VGATEHS  VHB = 4 V - 310 - mA

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Objective data sheet Rev. 1 — 27 January 2012 36 of 46

NXP Semiconductors TEA1716T
Resonant power supply control IC with PFC

Table 7. Characteristics …continued

Tamb = 25 C; VSUPIC = 20 V; VSUPHV > 40 V; all voltages are measured with respect to SGND; currents are positive when
flowing into the IC; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Isource(GATELS) source current on pin GATELS VGATELS  VPGND = 4 V - 310 - mA
Isink(GATEHS) sink current on pin GATEHS VGATEHS  VHB = 2 V; - 560 - mA
VGATEHS  VHB = 11 V - 1.9 - A
Isink(GATELS) sink current on pin GATELS VGATELS  VPGND = 2 V - 560 - mA
VGATELS  VPGND = 11 V - 1.9 - A
Vrst(SUPHS) reset voltage on pin SUPHS - 4.5 - V
Iq(SUPHS) quiescent current on pin SUPHS VSUPHS  VHB = 11 V - 37 - A
HBC adaptive non-overlap time (pin HB)
(dV/dt)ano(min) minimum adaptive non-overlap time - - 120 V/s
rate of voltage change
tno(min) minimum non-overlap time - - 160 ns
HBC current controlled oscillator (pin CFMIN)
fmin(HB) minimum frequency on pin HB Cfmin = 390 pF; 40 44 48 kHz
VSSHBC/EN > Vfmin(SSHBC)
VSNSFB > Vfmin(SNSFB)
Iosc(min) minimum oscillator current charge and discharge - 150 - A
Iosc(max) maximum oscillator current VSSHBC/EN < Vfmax(SSHBC) - 830 - A
Iosc(red) reduced oscillator current Slowed-down oscillator - 30 - A
flimit(HB) limit frequency on pin HB Cfmin = 20 pF 500 670 - kHz
Vu(CFMIN) upper voltage on pin CFMIN - 3.0 - V
Vl(CFMIN) lower voltage on pin CFMIN - 1.0 - V
HBC feedback input (pin SNSFB)
Volp(SNSFB) open-loop protection voltage on pin [2] - 8.1 - V
SNSFB
Vfmin(SNSFB) minimum frequency voltage on pin 6.1 6.4 6.9 V
SNSFB
Vfmax(SNSFB) maximum frequency voltage on pin VSSHBC/EN > Vfmin(SSHBC) 3.9 4.1 4.3 V
SNSFB
HBC soft-start (pin SSHBC/EN)
Vfmax(SSHBC) maximum frequency voltage on pin - 3.2 - V
SSHBC
Vfmin(SSHBC) minimum frequency voltage on pin VSNSFB > Vfmin(SNSFB) 7.5 7.9 8.3 V
SSHBC
Vclamp(SSHBC) clamp voltage on pin SSHBC - 8.4 - V
Vss(hf-lf)(SSHBC) high-low frequency soft-start [2] - 5.6 - V
voltage on pin SSHBC
Iss(hf)(SSHBC) high-frequency soft start current on VSSHBC < Vss(lf-hf)(SSHBC)
pin SSHBC charge current - 160 - A
discharge current - 160 - A
Iss(lf)(SSHBC) low-frequency soft start current on VSSHBC > Vss(lf-hf)(SSHBC)
pin SSHBC charge current - 40 - A
discharge current - 40 - A

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Objective data sheet Rev. 1 — 27 January 2012 37 of 46

NXP Semiconductors TEA1716T
Resonant power supply control IC with PFC

Table 7. Characteristics …continued

Tamb = 25 C; VSUPIC = 20 V; VSUPHV > 40 V; all voltages are measured with respect to SGND; currents are positive when
flowing into the IC; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Icmr(hf)(SSHBC) high frequency CMR current on pin VSSHBC < Vss(lf-hf)(SSHBC) - 1800 - A
SSHBC discharge only
Icmr(lf)(SSHBC) low frequency CMR current on pin VSSHBC > Vss(lf-hf)(SSHBC) - 440 - A
SSHBC discharge only
HBC high frequency sensing, HFP - HBC
Vhfp High-frequency protection voltage across resistor Rfmax [2] 1.70 1.83 2.00 V
HBC overcurrent sensing, OCR/OCP - HBC (pin SNSCURHBC)
Vocr(HBC) HBC overcurrent regulation voltage
positive level; 0.45 +0.50 0.55 V
HS on + HS-LS non-overlap
time
negative level; 0.55 0.50 0.45 V
LS on + LS-HS non-overlap
time
Vocp(HBC) HBC overcurrent protection voltage
positive level; - +1.75 - V
HS on + HS-LS non-overlap
time
negative level; - 1.75 - V
LS on + LS-HS non-overlap
time
Ibstc(SNSCURHBC)max maximum boost compensation VSNSBOOST = 1.8 V
current on pin SNSCURHBC source current; - 170 - A
VSNSCURHBC = 0.5 V
sink current; - 170 - A
VSNSCURHBC = 0.5 V
HBC Capacitive Mode Protection (CMP) (pin HB)
tto(cmr) time-out capacitive mode regulation - 690 - ns

[1] The marked levels on this pin are correlated. The voltage difference between the levels has much less spread than the absolute value of
the levels themselves.
[2] Switching level has some hysteresis. The hysteresis falls within the limits.
[3] For a typical application with a compensation network on pin COMPPFC, like the example in Figure 17.
[4] Minimum required voltage change time for valley recognition on pin SNSAUXPFC.
[5] Minimum time required between demagnetization detection and V/t = 0 on pin SNSAUXPFC.

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Objective data sheet Rev. 1 — 27 January 2012 38 of 46

NXP Semiconductors TEA1716T
Resonant power supply control IC with PFC

11. Application information

Rect Tr(PFC) Boost

CSUPIC

Aux(PFC) DSUPHS
Cboost
Mains Crect CSUPREG
CSUPHS

SUPHV SUPIC SUPREG SUPHS HB

GATEHS Tr(HBC)

HB CRes
SNSBOOST

Dr(PFC) SNSAUXPFC GATELS CHB

SNSMAINS Output
SNSCURHBC Cur(HBC)
GATEPFC Rcurcmp
Resonant Rcur(HBC)
Rss(PFC) Power Factor
Half-Bridge SNSOUT
SNSCURPFC Controller
Cur(PFC) Controller

Css(PFC)
Rcur(PFC)
SUPREG
COMPPFC SNSFB

SNSBURST
Rprot
Cfmin
RCPROT CFMIN
TEA1716
Css(HBC)
Cprot SSHBC/EN

PGND SGND
Disable

aaa-000768

Fig 17. Application diagram of TEA1716

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NXP Semiconductors TEA1716T
Resonant power supply control IC with PFC

12. Package outline

SO24: plastic small outline package; 24 leads; body width 7.5 mm SOT137-1

D E A
X

y HE v M A

24 13

Q
A2 A
A1 (A 3)

pin 1 index
θ
Lp
L

1 12 detail X
e w M
bp

0 5 10 mm
scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A
UNIT A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z
(1)
θ
max.
0.3 2.45 0.49 0.32 15.6 7.6 10.65 1.1 1.1 0.9
mm 2.65 0.25 1.27 1.4 0.25 0.25 0.1
0.1 2.25 0.36 0.23 15.2 7.4 10.00 0.4 1.0 0.4 8o
o
0.012 0.096 0.019 0.013 0.61 0.30 0.419 0.043 0.043 0.035 0
inches 0.1 0.01 0.05 0.055 0.01 0.01 0.004
0.004 0.089 0.014 0.009 0.60 0.29 0.394 0.016 0.039 0.016

Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC JEITA PROJECTION

99-12-27
SOT137-1 075E05 MS-013
03-02-19

Fig 18. Package outline SOT137 (SO24)

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NXP Semiconductors TEA1716T
Resonant power supply control IC with PFC

13. Abbreviations
Table 8. Abbreviations
Acronym Description
ANO Adaptive Non-Overlap
CMOS Complementary Metal-Oxide-Semiconductor'
CMR Capacitive Mode Regulation
DMOS Double-diffused Metal-Oxide-Semiconductor
EMI ElectroMagnetic Interference
FSP Failed Start Protection
HBC Half-Bridge Converter or Controller. Resonant converter which generates the
regulated output voltage.
HFP High-Frequency Protection
HV High-voltage
OCP OverCurrent Protection
OCR OverCurrent Regulation
OLP Open-Loop Protection
OTP OverTemperature Protection
OVP OverVoltage Protection
PFC Power Factor Converter or Controller. Converter which performs the power factor
correction.
UVP UnderVoltage Protection
SCP Short-Circuit Protection

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Objective data sheet Rev. 1 — 27 January 2012 41 of 46

NXP Semiconductors TEA1716T
Resonant power supply control IC with PFC

14. Revision history

Table 9. Revision history
Document ID Release date Data sheet status Change notice Supersedes
TEA1716T v.1 20120127 Objective data sheet - -

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Resonant power supply control IC with PFC

15. Legal information

15.1 Data sheet status

Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.

[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.

15.2 Definitions Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
Draft — The document is a draft version only. The content is still under
malfunction of an NXP Semiconductors product can reasonably be expected
internal review and subject to formal approval, which may result in
to result in personal injury, death or severe property or environmental
modifications or additions. NXP Semiconductors does not give any
damage. NXP Semiconductors and its suppliers accept no liability for
representations or warranties as to the accuracy or completeness of
inclusion and/or use of NXP Semiconductors products in such equipment or
information included herein and shall have no liability for the consequences of
applications and therefore such inclusion and/or use is at the customer’s own
use of such information.
risk.
Short data sheet — A short data sheet is an extract from a full data sheet
Applications — Applications that are described herein for any of these
with the same product type number(s) and title. A short data sheet is intended
products are for illustrative purposes only. NXP Semiconductors makes no
for quick reference only and should not be relied upon to contain detailed and
representation or warranty that such applications will be suitable for the
full information. For detailed and full information see the relevant full data
specified use without further testing or modification.
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the Customers are responsible for the design and operation of their applications
full data sheet shall prevail. and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
Product specification — The information and data provided in a Product design. It is customer’s sole responsibility to determine whether the NXP
data sheet shall define the specification of the product as agreed between Semiconductors product is suitable and fit for the customer’s applications and
NXP Semiconductors and its customer, unless NXP Semiconductors and products planned, as well as for the planned application and use of
customer have explicitly agreed otherwise in writing. In no event however, customer’s third party customer(s). Customers should provide appropriate
shall an agreement be valid in which the NXP Semiconductors product is design and operating safeguards to minimize the risks associated with their
deemed to offer functions and qualities beyond those described in the applications and products.
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
15.3 Disclaimers customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Limited warranty and liability — Information in this document is believed to
Semiconductors products in order to avoid a default of the applications and
be accurate and reliable. However, NXP Semiconductors does not give any
the products or of the application or use by customer’s third party
representations or warranties, expressed or implied, as to the accuracy or
customer(s). NXP does not accept any liability in this respect.
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no Limiting values — Stress above one or more limiting values (as defined in
responsibility for the content in this document if provided by an information the Absolute Maximum Ratings System of IEC 60134) will cause permanent
source outside of NXP Semiconductors. damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
In no event shall NXP Semiconductors be liable for any indirect, incidental,
the Recommended operating conditions section (if present) or the
punitive, special or consequential damages (including - without limitation - lost
Characteristics sections of this document is not warranted. Constant or
profits, lost savings, business interruption, costs related to the removal or
repeated exposure to limiting values will permanently and irreversibly affect
replacement of any products or rework charges) whether or not such
the quality and reliability of the device.
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory. Terms and conditions of commercial sale — NXP Semiconductors
Notwithstanding any damages that customer might incur for any reason products are sold subject to the general terms and conditions of commercial
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards sale, as published at http://www.nxp.com/profile/terms, unless otherwise
customer for the products described herein shall be limited in accordance agreed in a valid written individual agreement. In case an individual
with the Terms and conditions of commercial sale of NXP Semiconductors. agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
Right to make changes — NXP Semiconductors reserves the right to make applying the customer’s general terms and conditions with regard to the
changes to information published in this document, including without purchase of NXP Semiconductors products by customer.
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior No offer to sell or license — Nothing in this document may be interpreted or
to the publication hereof. construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.

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Export control — This document as well as the item(s) described herein product for such automotive applications, use and specifications, and (b)
may be subject to export control regulations. Export might require a prior whenever customer uses the product for automotive applications beyond
authorization from competent authorities. NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
Non-automotive qualified products — Unless this data sheet expressly
liability, damages or failed product claims resulting from customer design and
states that this specific NXP Semiconductors product is automotive qualified,
use of the product for automotive applications beyond NXP Semiconductors’
the product is not suitable for automotive use. It is neither qualified nor tested
standard warranty and NXP Semiconductors’ product specifications.
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
15.4 Trademarks
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer Notice: All referenced brands, product names, service names and trademarks
(a) shall use the product without NXP Semiconductors’ warranty of the are the property of their respective owners.

16. Contact information

For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]

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Resonant power supply control IC with PFC

17. Contents
1 General description . . . . . . . . . . . . . . . . . . . . . . 1 7.7.2.2 PFC mains compensation
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 2 (pin SNSMAINS) . . . . . . . . . . . . . . . . . . . . . . 16
2.1 General features . . . . . . . . . . . . . . . . . . . . . . . . 2 7.7.3 PFC demagnetization sensing
2.2 PFC controller features. . . . . . . . . . . . . . . . . . . 2 (pin SNSAUXPFC). . . . . . . . . . . . . . . . . . . . . 17
2.3 HBC controller features . . . . . . . . . . . . . . . . . . 2 7.7.4 PFC valley sensing
2.4 Protection features . . . . . . . . . . . . . . . . . . . . . . 2 (pin SNSAUXPFC). . . . . . . . . . . . . . . . . . . . . 17
7.7.5 PFC frequency and off-time limiting . . . . . . . . 18
3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
7.7.6 PFC soft start and soft stop
4 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 (pin SNSCURPFC) . . . . . . . . . . . . . . . . . . . . 18
5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7.7.7 PFC overcurrent regulation, OCR-PFC
6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 (pin SNSCURPFC) . . . . . . . . . . . . . . . . . . . . 19
6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7.7.8 PFC mains undervoltage protection/brownout
6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 protection, UVP-mains
7 Functional description . . . . . . . . . . . . . . . . . . . 6 (pin SNSMAINS) . . . . . . . . . . . . . . . . . . . . . . 19
7.1 Overview of IC modules . . . . . . . . . . . . . . . . . . 6 7.7.9 PFC boost overvoltage protection,
7.2 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . 7 OVP-boost (pin SNSBOOST) . . . . . . . . . . . . 20
7.2.1 Low-voltage supply input 7.7.10 PFC short circuit/open-loop protection,
(pin SUPIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 SCP/OLP-PFC (pin SNSBOOST) . . . . . . . . . 20
7.2.2 Regulated supply 7.8 HBC controller . . . . . . . . . . . . . . . . . . . . . . . . 20
(pin SUPREG) . . . . . . . . . . . . . . . . . . . . . . . . . 8 7.8.1 HBC high-side and low-side driver
7.2.3 High-side driver floating supply (pin GATEHS and GATELS) . . . . . . . . . . . . . 20
(pin SUPHS) . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 7.8.2 HBC boost undervoltage protection,
7.2.4 High-voltage supply input UVP-boost (pin SNSBOOST) . . . . . . . . . . . . 20
(pin SUPHV) . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 7.8.3 HBC switch control. . . . . . . . . . . . . . . . . . . . . 21
7.3 Flow diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 9 7.8.4 HBC Adaptive Non-Overlap (ANO)
7.4 Enable input (pin SSHBC/EN) . . . . . . . . . . . . 11 time function (pin HB) . . . . . . . . . . . . . . . . . . 21
7.5 IC protection . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7.8.4.1 Inductive mode (normal operation) . . . . . . . . 21
7.5.1 IC restart and shut-down . . . . . . . . . . . . . . . . 12 7.8.4.2 Capacitive mode . . . . . . . . . . . . . . . . . . . . . . 22
7.5.2 Protection and restart timer . . . . . . . . . . . . . . 13 7.8.5 HBC slope controlled oscillator
7.5.2.1 Protection timer . . . . . . . . . . . . . . . . . . . . . . . 13 (pin CFMIN) . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.5.2.2 Restart timer . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7.8.6 HBC feedback input (pin SNSFB) . . . . . . . . . 25
7.5.3 Fast shutdown reset 7.8.7 HBC open-loop protection, OLP-HBC
(pin SNSMAINS). . . . . . . . . . . . . . . . . . . . . . . 14 (pin SNSFB). . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.5.4 Output overvoltage protection, 7.8.8 HBC soft start (pin SSHBC/EN) . . . . . . . . . . . 25
OVP-output 7.8.8.1 Soft start voltage levels . . . . . . . . . . . . . . . . . 25
(pin SNSOUT) . . . . . . . . . . . . . . . . . . . . . . . . 14 7.8.8.2 Soft start charge and discharge . . . . . . . . . . . 26
7.5.5 Output failed start protection, 7.8.8.3 Soft start reset . . . . . . . . . . . . . . . . . . . . . . . . 27
FSP-output (pin SNSOUT) . . . . . . . . . . . . . . . 14 7.8.9 HBC high-frequency protection,
7.5.6 OverTemperature Protection (OTP) . . . . . . . . 15 HFP-HBC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.6 Burst mode operation 7.8.10 HBC overcurrent regulation and protection,
(pin SNSBURST) . . . . . . . . . . . . . . . . . . . . . . 15 OCR and OCP (pin SNSCURHBC) . . . . . . . . 28
7.7 PFC controller. . . . . . . . . . . . . . . . . . . . . . . . . 15 7.8.10.1 Boost voltage compensation . . . . . . . . . . . . . 28
7.7.1 PFC gate driver 7.8.10.2 Overcurrent regulation, OCR-HBC . . . . . . . . 29
(pin GATEPFC). . . . . . . . . . . . . . . . . . . . . . . . 16 7.8.10.3 Overcurrent protection, OCP-HBC. . . . . . . . . 30
7.7.2 PFC on-time control . . . . . . . . . . . . . . . . . . . . 16 7.8.11 HBC capacitive mode regulation,
7.7.2.1 PFC error amplifier CMR (pin HB). . . . . . . . . . . . . . . . . . . . . . . . . 30
(pins COMPPFC 7.9 Protection overview . . . . . . . . . . . . . . . . . . . . 31
and SNSBOOST) . . . . . . . . . . . . . . . . . . . . . . 16 8 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 32

continued >>

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Objective data sheet Rev. 1 — 27 January 2012 45 of 46

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Resonant power supply control IC with PFC

9 Thermal characteristics . . . . . . . . . . . . . . . . . 33
10 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 33
11 Application information. . . . . . . . . . . . . . . . . . 39
12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 40
13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 41
14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 42
15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 43
15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 43
15.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
15.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 44
16 Contact information. . . . . . . . . . . . . . . . . . . . . 44
17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.

© NXP B.V. 2012. All rights reserved.

For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 27 January 2012
Document identifier: TEA1716T