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Lab 1

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24 views

Lab 1

Uploaded by

vamsi262005
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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LAB 1 – Raja Aadhithan

Design - Full adder using Half adder:

Code:
module half_adder(input a,b,
output sum,carry);

//Understand the Data-flow abstraction


assign sum = a ^ b;
assign carry = a & b;

endmodule

module full_adder( input a_in,


b_in,
c_in,
output sum_out,
carry_out);

wire w1,w2,w3;

half_adder ha1(.a(a_in), .b(b_in), .sum(w1), .carry(w2));


half_adder ha2(.a(c_in), .b(w1), .sum(sum_out), .carry(w3));
or or1(carry_out, w2,w3);

endmodule

Test bench:
module full_adder_tb();

//Testbench global variables


reg a,b,cin;
wire sum,carry;

//Variable for loop iteration


integer i;

//Step1 : Instantiate the full adder with order based port mapping
full_adder DUT(a,b,cin,sum,carry);
//Process to initialize the variables at 0ns
initial
begin
a = 1'b0;
b = 1'b0;
cin = 1'b0;
end

//Process to generate stimulus using for loop


initial
begin
for (i=0;i<8;i=i+1)
begin
{a,b,cin}=i;
#10;
end
end

//Process to monitor the changes in the variables


initial
$monitor("Input a=%b, b=%b, c=%b, Output sum =%b, carry=%b",a,b,cin,sum,carry);

//Process to terminate simulation after 100ns


initial #100 $finish;

endmodule

Wave:

Output:
RTL:
Exercises:

Design : Ripple adder

Code:
module ripple_adder(input [3:0] a,b, input cin,
output[3:0] sum,output carry);
wire [2:0] w;

full_adder FA1(a[0],b[0],cin,sum[0],w[0]);
full_adder FA2(a[1],b[1],w[0],sum[1],w[1]);
full_adder FA3(a[2],b[2],w[1],sum[2],w[2]);
full_adder FA4(a[3],b[3],w[2],sum[3],carry);
endmodule

Test bench:
module ripple_adder_tb();
reg [3:0]a,b;
reg c;
wire [3:0]s;
wire cy;
integer i;
initial begin
a=0;
b=0;
c=0; end

ripple_adder DUT(a,b,c,s,cy);
initial begin
for (i=0;i<16;i=i+1)
begin
a=i;
b=i;
c=!c;
#10;
end
end
initial
$monitor("Input a=%b, b=%b, c=%b, Output sum =%b, carry=%b",a,b,c,s,cy);

//Process to terminate simulation after 100ns


initial #100 $finish;

endmodule
Wave:

Output:

RTL:
Design : 4:1 mux using 2:1 mux

Code:
module mux2(input a,b,s, output x);
assign x = s ? b : a;
endmodule

module mux4(input a,b,c,d,s1,s2,output x);


wire w1,w2;
mux2 mu1(a,b,s2,w1);
mux2 mu2(c,d,s2,w2);
mux2 mu3(w1,w2,s1,x);
endmodule

Test bench:
module mux4_tb();
reg a,b,c,d,s1,s2;
wire x;
integer i;
mux4 DUT(a,b,c,d,s1,s2,x);
initial begin
a=0;b=0;c=0;d=0;s1=0;s2=0;
end
initial begin
for(i=0;i<64;i=i+1)
begin
{s1,s2,a,b,c,d}=i;
#10;
end
end
initial #1000 $finish;
endmodule

Wave:
Output:
RTL:
Assignment:

Design: RTL for full adder.

Code:
module dataflow_fulladder(input a,b,c,d,s2,s1, output x);
assign x = s1 ? (s2 ? d : c) : (s2 ? b :a );
endmodule

RTL:
Design: 2x4 decoder.

Code:
module decoder(
input [1:0] in,
output [3:0] out
);
assign out[0] = (~in[1]) & (~in[0]) ;
assign out[1] = ( in[1]) & (~in[0]) ;
assign out[2] = (~in[1]) & ( in[0]) ;
assign out[3] = ( in[1]) & ( in[0]) ;

endmodule

RTL:
Design: 8x3 priority encoder.

Code:
module encoder(input [7:0]in , output [2:0] out);
wire[4:0] x;
wire[5:0] n;
not(n[5],in[5]);
not(n[4],in[4]);
not(n[3],in[3]);
not(n[2],in[6]);
not(n[1],in[2]);
or(out[2],in[7],in[6],in[5],in[4]);
and(x[0],in[3],n[5],n[4]);//!5,!4,3
and(x[1],n[5],n[4],n[3],in[2]);//!5,!4,!3,2
and(x[2],x[0],n[2]);//!6,!5,!4,3
and(x[3],n[2],in[5]);//!6,5
and(x[4],n[2],n[5],n[4],n[3],n[1],in[1]);//!6,!5,!4,!3,!2,1
or(out[1],in[7],in[6],x[0],x[1]);
or(out[0],in[7],x[3],x[4],x[2]);
endmodule

Test bench:
module encoder_tb();
reg [7:0] x;
wire [2:0] y;
integer i;
encoder dat(x,y);
initial begin
for(i=0; i<8; i = i+1)
begin
x = 2**i;
#10;
x=2*i;
#10;
end
$finish;
end

initial $monitor("@ time: %3dps the input is %8b output is %3b",$time,x,y);

endmodule
Wave:

Output:

RTL:
Design: 4x1 mux.

Code:
module mux_dec(input A,B,C,D, input [1:0] in, output Y);
wire [3:0] out;
reg x;
assign out[0] = (~in[1]) & (~in[0]) ;
assign out[1] = ( in[1]) & (~in[0]) ;
assign out[2] = (~in[1]) & ( in[0]) ;
assign out[3] = ( in[1]) & ( in[0]) ;
always@(*)begin
case(in)
2'b00:x <= out[0] ? A : 1'bz;
2'b01:x <= out[2] ? B : 1'bz ;
2'b10:x <= out[1] ? C : 1'bz ;
2'b11:x <= out[3] ? D : 1'bz ;
endcase
end
assign Y = x;
endmodule

Test bench:
module mux4_tb();
reg a,b,c,d;
reg [1:0] s;
wire x;
integer i;
mux_dec DUT(a,b,c,d,s,x);
initial begin
a=0;b=0;c=0;d=0;s = 0;
end
initial begin
for(i=0;i<64;i=i+1)
begin
{s,a,b,c,d}=i;
#10;
end
end
initial #1000 $finish;
endmodule
Wave:

RTL:
Design: Bidirectional buffer

Code:
module bufer(inout a,b, input c);
bufif1(b,a,c);
bufif0(a,b,c);
endmodule

Testbench:
module bufer_tb();
wire a,b;
reg c,ta,tb;
integer i;
bufer dut(a,b,c);
initial begin
for(i=0;i<8;i=i+1)
begin
{ta,tb,c}=i[2:0];
#10;
end
end
assign a = c ? ta : 1'bz;
assign b = c ? 1'bz : tb;
endmodule

Wave:
Output:

RTL:

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