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/ 164
SUBJECT CODE : €S3691
Silly 0s per Revised Syllabus of
ANNA UNIVERSITY
Choice Based Credit System (CBCS) 3
Semester - V (IT/ CS & BS) cil
Semester - VI (CSE/ Al & DS) £
EMBEDDED SYSTEMS AND IOT
Iresh A. Dhotre
ME, (Information Technology)
ExFaculy, Sinhgod College of Engineering,
Pune.
Atul P Godse
M.S, Sofware Systems (ITS Pilon)
BE. Industrial Electronics
Formerly Lecturer in Department of Electonics Engg.
Viehwokarme Insftue of Technology
Pune
== TECHNICAL
PUBLICATIONS
4a Up heel orKoowledge SYL
HABE TABLE OF CONTENTS
Embedded Systems and IoT - (CS3691) ST a
TT &-Bit Microcontroller Architecture it a
UNITI _8-BIT EMBEDDED PROCESSOR ore GPa GrE
5 Bit Atcrasontoler Introduction. z
5 BK ton Arctece-Ison Se and Poganmite-Popanning Fale a Be
ons Timers and Serial Pot -Inlerup Handling. (Chapters -1,2,3) 1.2 Features of 8051 Microcontroler 2
5 13. Architecture of 851 a4
UNIT EMBEDDED C PROGRAMMING 1.3.1 Centra Processing Unit (CPU) 14
Memory And 1'0 Devices entrlProcesing Uni i
Mery A 10 Devs neti - Popuming Embed Sys in Nee For RTOS aan rene oo.
ile Tasks and Processes - Context Switching - Prorty Based Scheduling Policies.
(Chapter -4) 4133. bata Pointer (OFTR) 1s
134 The Program Counter : vw LS
i M10 AND ARDUINO PROGRAMMING 1.35 8051 Flag Bits and the PSW Register. aD
noduction tothe Concept of IoT Devi
not he Coney of oT Dees = 1 Devs Vass Computes oT Congas 136 special Function Register of 51... meee
Bae Component « ardnionw Adio «Types of Ain» Ain Toni Ano Aplin penrnecras a
ProsamningStce Sheth - i Ipt/ Ost From Pans Using Sethe notuton Cee ‘
uino Shiels - Integration of Sensors and Actors with Arduino. (Chapter ~5) 1.5 Internal and External Memories ea
WN 4.5.1 Internal RAM Organization ute
UNITIV1OT COMMUNICATION AND OPEN PLATFORMS | eee ee vi
ToT Communication Mode 1.5.4.1 051 Reiter Banks (Working Regier
In Comuniton Nades end APIs oT Commit Pratens~Bluoch - Wi ~2igBee -ia Somer i
- GSM modules - Open Platform (ike Raspberry Pi) - Architecture -Prograning - interfacing Sot =a ;
Accessing GPIO Pins - Sending and Receiving Signals Using GPIO Pins a ee ae a
acing Clu
a 15.2 ROM Space in the 8051.
1s stackand stack oie
UNITV APPLICATIONS DEVELOPMENT an
1.7 Two Marks Questions with Answers
Complete Design of Embedded Systems - Development of loT Applications - Home Automation -
Smare Agriculture - Smart Cities - Smart Heskthare. (Chapter -7) “Guage F —Trotrction Set and Prosrammning —@- to 56)
2 8051 Addressing Modes nn 2-2
2aa Register Addressing 12-2
2.1.2 Direct Byte Addressing. 22
23
2.1.3 Reglster Indirect Addressing ..
24.4 Immediate Addressing. 23
wy Ne
o Chapter -3
2.1.8 Register Specific 24
2.1.6 Index ~ sense 24
2.1.7. Stack Addressing Mode... so 2-4
2.2. Classification of Instruction Set of 8051... 2-5
2.3. Data Transfer instructions. 2-5
23:1. Instructions to Access External Data Memory. soe B27
2.3.2. Instructions to Access External ROM/Program MemorY.nwnnnmennnnns 2-7
23:3 Data Transfer wit Stack (PUSH and POP) Instructions wo 8
23.4 Data Exchange instructions .sssrsssnesnn soos 2-9
2.4 Byte Level Logical Instructions .. 2-10
2.5 Arithmetic instructions, 2-18
2.5.1 Incrementing and Deerementig.. 23
252 Addition. sone 2218
2.5.3. Subtraction — os 2-18
25.4 Mukiplcation and Division : incase 218
2.55 Decimal Arithmetic. “ sn 2-16;
2.6 Bit Level Logical instructions 2-16
2.7 Rotate and Swap Instructions 2-19
2,8. Jump and CALL instructions 2-20
2.8.1 Jump and CallProgram Range... . 2-21
2.82. Jump. es 2-21
2.83. CALLand Subroutines
29° Time Delay for 8051
2.10 Program Examples.
2.11. Two Marks Questions with Answers .
Parallel Ports, Timers, Serial Port and Interrupts
(3-1) to (8-74)
3.1 8051 /0 Ports Structure 3-2
|
3.2/0 Bit Manipulation Programming
3,3. 8051 Timers.
33.1 Structure of TMOD Register.
3.3.2 Structure of TCON Register
3.4 8051 Tmer Modes and Programming
3.5 8051 Counter Programming.
35. Programming Timers in 8051 C.
3.6 8051 Serial Port ee
3.6:1 Operating Modes for SerialPort.
362 Generating Baud Rates.
3.63 Programming 8051 for Serial Date Transfer.
3,64 Programming 8051 for Receiving Data Serial.
365 Doubling the Baud Rate in the 8051
3.6.6 8051 Connection to RS 232¢
3.67 Serial Communication Programming in .
3.78051 Interrupt Structure.
3.74 Interrupt Control (Enabling and Disabling Interrupts using E)
5.7.2 Interrupt Priority and Interrupt Destinations (Vector Locations)
3.8 Programming Interrupts
3.81 Programming Timer Interrupts
3.8.2. Programming External Hardwarelnterrupts
3.83 Programming the Serial Communication Interrupts
3.9. Two Marks Questions with Answers
Thapter-4 Embedded C Programming
4.1 Memory Interfacing
44:14. Interfacing and Timing Diagrams for Memory interfacing
4.1.24 Bxternal Program Memory
44.412 Eternal Data Memory
3-4
3-25
on 3-28
3-28
3-27
3-33
od AD
3-50
3-82
3-53
3-55
3-57
3-58
3-58
3-59
3-64
3-65
3-66
3-68
3-68
3-70
3-71
3-3 43
44
46
47
3 “rsportant Pints to Rerrember in Accessing External Memory
‘ress Decoding.
Examples,
9 External Data Memory in 8051C.
terfacing
vwerfacing,
» key Debounce using Hardware
Debouncing using Sefware
Simple Keyboard interface
stixkeyboord interface
> interfacing.
.2xed 1-Segment Display interfacing,
1 Interfacing LED Displays
424 LCD interfacing.
ving Embedded Systems in C
‘erence between C Language and Embedded C
Need for RTOS.
Difference between Hard and Soft Real Time System
eal Time OS,
443. Qualities of God RTOS
444 Characteristics of RTOS.
4.45 How to Choos
ToS.
Multiple Tasks and Processes.
45.1 Muliate Systems
45.2 Process State and Scheduling.
453° Scheduling Policies.
Context Switching,
Priority Based Scheduling Police.
47.1 Earliest Deadline First Scheduling
47.2 Rate Monotonic Scheduling.
4-46
4-46
4-48
4-49
4-49
4-50
4-52
4-52
4-53
4-54
4-55
4-55
4-58
48
Chapter - 5
SL
5.2
53
54
5s
56
87
47.2.1 Comparison between RMS and EDF.
47.3. Priority Inversion,
‘Two Marks Questions and Answers.
ToT and Arduino Programming
Introduction to the Concept of loT Devices:
S.L1 oT System Building Blocks.
$41.2 lot Devices Versus Computers
Introduction to Arduino
5.2.1 Features of Arduino Board.
Types of Arduino
‘Arduino Toolchain
Arduino Programming Structure
55 Sketches.
552 Pins
Introduction to Arduino ShieldS.....n.0u
Integration of Sensors and Actuators with Arduino
571 Sensor
5.7.2 Sensor Component.
5.7.3 Sensor Types
5.7.4 Actuators.
5.75 Difference between Actuator and Sensor.
5.7.6 Controlling LED by using IR Sensor and Remote
5.7.7 Reading Switch
‘Two Marks Questions with Answers
5-23
ea Ua
‘Chapter-6 — loT Communication and Open Platforms (6 - 1) to (6 - 60)
6
62
63
64
6s
66
67
68
loT Communication Models and APIs
6.4.1 [oT Communication API...
loT Communication Protocols ..
6.2.1 Bluetocth...
622 WiFi
ZigBee ..
63.1 ZigBee Architecture
63.2 Logical Device Types.
633 Network Layer.
634 Simple Tree Routing Protocol.
635. Zigbee-AoDv(zaov)
63.6 APS Layers
63.7 ZigBee Applications
GPs
GSM Modules
65.1 Base Station Subsystem
65.2 Network Switching Subsystem.
653. Mobile Station,
65.4 GSM Channel.
(Open Platform : Raspberry Pi Architecture.
6.6. About the Boatd sen -
6.6.2 Unuxon Raspberry i
6.63 Difference between Raspberry Ps and Desktop Computers.
Raspberry Pi Interfacing
Raspberry Pi Programming...
6.8.1 Controlling LED with Raspberry Pi
6.8.2 Interfacing an LED and Switch with Raspberry Pi
6-2
6-4
6-5
6-6
67
6-9
6D
on
ee
6-16
6-17
6-18
6-19
6-20
6-21
6-47
69
6.10 Two Marks Questions with Answers.
(7-1) to (7-24)
6.83 Interfacing Light Sensor.
Connecting to the Cloud.
69.1 WAMP: AutoBahn for lo.
69.2 Xively Cloud forloT..
Chapter -7 Applications Development
ma
72
73
74
75
Complete Design of Embedded Systems...
741 Design Metrics. —
7.4.2 Abstraction Steps inthe Design Process.
724 Requirement
74.22 Speciation
7A.23 Achiectue Deien
7.4.24 Designing Hardware and Software Components
5 System integration
7.13. Challenges in Embedded Computing System Design
Development of ioT Applications
Home Automation
73.1 Smart Lighting
732 Smart Appliances.
7.3.3. Intrusion Detection
7.34 Smoke for Gas Detection...
Smart Agriculture
7.4.1 Smart irrigation.
742 Green House Control
Smart Cites...
754. Smart Parking...
752 Smart Lighting
153 Smart Roads
6-47
6-50
6-50
6-54
6-57
7-2
se TMB
718
7-28
7
we
r) 76
‘Smart Healthcare...
7.6. Health and Fitness Monitoring...
7.62 Wearable Electroni on
‘Two Marks Questions with Answers
oa
14
12
13
1
15
16
Syllabus
&-Bit Mieroconoller - Architecture,
Contents
Introduction
Features of 8051 Microcontroller... . Dee.-04, May-42, °° +--+ Marks 2
Architecture of 8051 css: My-06,08,09,10,14,12,19,96,97,18,
7 Dec.-04,09,10,11,14,19, -- Marks 16
Pin Description of 8061... Dee.-19,18, May-11, -+>- Marks 19.
Intemal and Extemal Memories,
Marks 16
‘Stack and Stack Pointer
Two Marks Questions with Answers 4:2 2-8 Merecontroer Architecture
Embedded Systems ond
Introduction
complete microcomputer system, only microprocessor is not sufficient. It is
sel a tr pps sat so Read On Memay BOM, ea
rmemory (RAN), decodes, drivers, number ef inpufotput devices to make «complete
tcocomputer yten, In addon special purpose device sucha interupt contol,
pogammable timers, programmable UO devices, DMA conmollrs may be,
Improve the capability and performance and flexibility of a microcomputer system
“The microcontroller incorporates all the features that ate found in microprocessor.
However, it has also added features to make a complete microcomputer system on its
‘own. The microcontroller has builtin ROM, RAM, parallel VO, serial /O, counters and a
dlock circuit
‘The advantages of built-in peripheral devices of microcontrller are
«+ Built-in peripherals have smaller access times hence speed is more
+ Hlardware reduces due to single chip microcomputer system.
«Less hardowere, reduces PCB size and increases reliability ofthe system.
fed interrupt Grit
|e ioe ieee |
ie ‘
pemmmperurmnmeyry |
| pene rin cont eas eh SEER
|
Pe ger
Sbearenl santos
incr is to move data)
any to move data Is fas one or two insucions
> eens nemaryand CH between inemery and CPU:
3. Tehas one or two bithanding instrctions,_ thse many bit handing instructions
; set
ecess tes for stemocy and 1/0 devies Lee acess mes fr Buin memory and
se i VO dense.
3 res less
5. Microprocessor basa system requires more Mieroconilas based system res Jess,
—— se musing CH age nd cresting
3 Sa
| esign point of vie.
6 icoprocmtor. tend syten 1 ore. tae Aen
Seppe |
|
[7% tae sgl memory sap for date and Tat apie memory map ft da a
code. code a
& Less number of pins are mulifunctione,
“Table 41.1 Comparison between microprocessor and microcontrol
Embedded Systeme and oT 1:3 8.8 Merocontate Arhtectire
&
w Question]
1,_Distinguish betoen microprecestor and microcontroller.
Features of 8051 Microcontroller
‘The 8051 is an 8-bit microcontroller designed by Intel. It was optimized for 6-bit math
and single bit Boolean operations. Its family includes 8031, 8051, 8052 and 8751
microcontrollers. Let us see the features of 8051 microcontroller.
The features of the 8051 family are as follows
1, 4096 bytes on - chip program memory.
2. 128 bytes on - chip data memory.
3. Four register banks,
4. 128 user-defined software fags.
5, 64 kilobytes each program and extemal RAM addressability.
6. One microsecond instruction cycle with 12 MElz crystal
7, 32 bidirectional VO lines organized as four 8-bit ports (16 lines on 808!)
8. Multiple mode, high-speed programmable serial port
9. Two multiple mode, 16-bit timers/counters.
20, Twolevel prioritized interrupt structure
11, Full depth stack for subroutine return linkage and data storage
12. Direct byte and bit addressability
13, Binary or decimal arithmetic.
14, Signed-overflow detection and parity computation
15, Hardware multiple and divide in 4 ysec
Integrated boolean processor for control applications.
17. Upwardly compatible with existing 8084 software
List the fotures of 8051 micrcontrole.
(Compare the 8051, 8031 and 8751 microcontroller.
2
2
3 List ou he hardware resources coil n 805 =
44 What ee the man features of 8052 microcontroller ?
TECHNICAL PUBLICATIONS® «an upuhst for knonedge
an ups or trong Embeds Systems and oT 1 2.tMerconraterArchtectre =| Embedied Systems and loT 18 at iageectekr ieee
Architecture of 8051 A and B CPU Registers -
EEE TOCA ONT WERE CRAPPER Aus
Fig. 131 shows the intemal block diagram of 801. It consists ofa CPU, two kinds of
memory sedtions (dala memory - RAM and. program memory - EPROMIROM),
Inpulourput ports, specal funcéon risers and contol logle needed for a
timer / counter serial port and interupt functions. These elements communicate through
an eight bit data bus which rans throughout the chip refered a intemal data bus. This
bus is buffered to the outside world through an YO port when memory or UO
expansion is desired,
extra
inom Cr Coumer ips
wre} vrs | nee
‘or py
egian OER
za rae
cweaeyes)| Fer
=] [=
PEtd Tt
wgioes AO Pt P2 PS THD RD
,, stararess fat
rtd Hera orer JL gwunctonat
normally 11,0582 Miz her
Fig. 1.3.4 Block dlagram of 8051
Central Processing Unit (CPU) E
The CPU of 8051 consists of eightbit arithmetic and logic unit with associated
registers ike A, B, PSW, SP, the sixteen bit program counter and “Data pointer” (DPTR)
registers, Along with these registers it has a set of special function registers.
‘The unique feature of the 851 architecture i thatthe ALU can also manipulate one
bit aswell as eghtbit data types
Register A (Accumulator)
It is an S-bit segister called accumulator. It holds a source operand and receives the
"esult ofthe arithmetic instructions (addition, subtraction, multipliealon and division). « —
Several functions apply exclusively to the accumulator : Rotate,
rity computation,
Register 8
tek0PTR ae
In addition to accumulator, an *
Sit Beregister is available as a ne
general purpose register. It is used. Pe 7 Mack
for the hardware multiply/divide iad
oe eke
operation .
Data Pointer (DPTR)
‘The data pointer (DPTR) consist ‘high byte (DPH) and 2 low byte (DPL). Its
function is fo hold a 16bit address, I may be manipulated a a 16-bit dota register or as
{wo independent S-bit registers. T serves as pase register ining
{ab[e instructions and exieral data transfer_The DPTR does 10 hi
address; DPH (GSH) and DPL (62H) have separate intemal addressee
KEE] the Program Counter
The 8051 has a 16-bit program counter, It is used to hold the address of memory
location from which the next instruction is to be fetched.
8051 Flag Bits and the PSW Register
‘The Fig. 1.32 shows the bit pattern of Program Status Word (PSW) of 8051, PSW is
also known as flag register,
Fig. 4.32
‘The 8051 consists of following flags.
* C¥-Camry Flag : This flag is set if there isan overflow out of bit Z.The carry fag
also serves a5 a borrow fag for subtraction. In both the examples shown telow,
the cary fag is set
‘+ AC-Auuiliary Carry Flag : This flag is et if there is an overflow out of bt 3ie.,
carry from lower nibble to higher nibble (D, bit to D, bit
TECHNICAL PUBLICATIONS® - an uprast for knowedge
TECHNICAL PUBLICATIONS® «an up-tt fr knowledge Embedded Systems and oT 16 2-5 Microcontroter Architecture
+ FO- Available for user for general purpose
«RSI ~ RSO (Register Bank Select) : They select the working sepister bank as
follows: oer: .
aoomon susrRAcTION
wx wor 08 sou LL toobtbb -
= BE on o1ot = Sn sooo *
aayteh Toros) coor Tper Evormo
are Bank
+ OV-Over Flow Flag : This flag is set whenever the result of @ signed number
operation is too large, causing the highorder bit to overflow into the sign bit
«+ P-Party Flag: Parity is defined by the number of ones present in the accumulator
P=0, if number of ones ae even and P= 1, i umber of ones are odd
1 [Example : The status of CY, AC and P flags after the addition of 9BH and 65H is a5
fellows
CY=1,AC=1andP
; There are instructions in 051, that tests the condition of flags
and rake decision based on the status of flags. Thus, programmer use these flags fo
perform some arithmetic operations which invelves carry or borrow or to change the
‘program control (using conditional branching)
‘As mention earlier, programmer can select register bank by setting correspons
in PSW.
in the PSW register
ing bits
Embedded Systoms and oT a 2-5 Mirocontroer Architecture
Special Function Register of 8051
‘The group of registers, implemented to perform special functions and are located
immediately above the 128 bytes of RAM are called special function registers. All access
to the four JO ports, the CPU registers, interrupt control registers, the timer/counter,
ART and power control are performed through registers between 80H and FFH.
Diet neat Harare
bate regater
See aso) ase) 7b
oF :
pe ovos [er] rs] =|] ] 2] Fi] ro] 8
619 vs
¢: ocon [EP]ES] es] e#] 2] ET] ea) ace _
bv
coo | BF] Be] os] oa] es] oe] oi] pal Pew
oS’ ose [T= = Tae[ es] ea] oe] ee]
6%
a .) — obon [er] ae] as] es] 2] a2] et] so} ro
_ ones [ETT =
san [B=] Se] #0] ec] eB] oA] eo] es] sco
om Tee]
sen |] =] 20] oc] eo] ea] ea] ce] toon
wlele]efefe| vo
Fig. 1.3. SFR bit address
i || TEANGA PUBLICATIONS? an ut rove
TECHNICAL PUBLICATIONS® - en upthast for dncwiodse te 8-8 Mevocontotr Architecture
Special Function Registers (SERs) are a sort of conbol table used for running and
‘monitoring the operation of the microcontroller. Each of these registers as well as each
bit they inchude, has its name, address in the scope of RAM and precisely defined
‘Purpose such as timer control, interrupt control, serial communication control ete.
Even though there are 128 memory locations intended to be occupied by them, the
basic core, shared by all types of 6061 microcontrollers, has oly 21 such registers, Rest
of locations ate intentionally left unoccupied mm order to enable the manufacturers to
farther develop microcontrollers keeping them compatible with the previous versions
Fig. 133 shows special fumetion bit addresses. (See Fig 13.3 on previous page)
Zeble 13:1 contains a ist ofall the SFRS and their addveses and their value in binary
at reset.
‘Symbol Name Address Value inbinay |
aoc Accumutor eH 20000000
* oro 9000 0000
PW 0 000 ooo
Be an sooo ort
me aH 2000 000
2 a 9000 0000
Es cont trataatt
= on weet gaa
z ‘AH trataeny
80H yan sage
6H 8 Xxx0 0000
a e082 Xx00 0000
ra Intezrupt Enable Conia onan, es) 0xx0n9ne
52 0X00 0000
‘Tae/Couner Made Cont 20H 2900 000
TimeriCounter Coot ett e000 9000
“YTREON —Time/Coumter 2 Cpl cen 000 ono
TH “Tientounter 0 High Byte ack 2p00 0000
no TimerfCounter 9 Low Byte oat 9000 0000
ma ‘Tme/Counter 1 High Byte oH 2000 0000
Ti TimerCounter 1 Lew Byte ‘1 0000 0000
oT ‘TimesiGourter 2 High Byte cbr 2000 0000
2n2 Timea 3 Law Bye sect 0000 co0o
Techical PuBuicaTions®
0 upthrst er knonta
Embedded Systeme and loT 1-9 8-8 Micocontor Architecture
DE cope Bey aes Eee
“THC? Capa Reg Low Be
9000 0000
0000 0000
_ 9000 0000
indetoringe
HMOs. OXKX XXXx
f cimlos_oxxx 0000
“Table 1.3.1 List of al SFRs ("Bit addressable, + ~ 8052 only )
‘before register name indicates that itis a bit addressable,
before register name indicates that it is supported by only 8052.
1 Ge he das of PSW of TAC a1 a9, Was 2]
2 Quantify the mumber of register banks in 8051 and say how the CPU knows which bank is
EO
currently in use,
3. Explain the functional block diagram of S051 in det
[ETE
5, List he ovchippephrl of 051 micwcontrl.
5. Mosion esr of DPTRndsck pone in 551 icone, ESTATE
8. Esplin sh net lc diagram he wciecureof 8051 rectal
ET |
8 cccontellr, TCS C RTT
EEE] Pin Description of 8051
The 8051 is packaged in a 40-pin DIP. The Fig. 141 shows the pin diagram of 851
It is important to note that many pins of S051 are used for more than one function. The
alternative functions of pins aze shown in bold letters
‘The 8051 has 32 1/0 pins configured as four eightbit parallel ports (P0, Pl, P2
and P3). All four ports are bidirectional ie, each pin will be configured as input o
output (or both). All porpins are multiplexed except the pins of port 1. Each port
Consists of a latch, an output diver and an input butter. 2
Port 0 (Pins 32 - 38): Port 0 pins can be used as WO pins. The output drives and
Input buffers of port 0 are used to access external memory. Port 0 outputs the low order
byte of the external memory address; time A with the data being writen oF — |
read. Thus, port O can be used as a multiplexed address/data bus.
Port 1 pins can be used only as /O pins.
7. What is program status word of 8051 ?
Block diagram: of 8051
Port 1 (Pins 1 - 8)
TECHNICAL PUBLICATIONS® « an uptivst for inowledgo se! Embedded Systems and oT 1 2-8 Mierocontlor Architecture
Enondded Stems an ioT 110 a8 tcreconler Arhtacre
43|-— Voor
30 |_[Fo0, bal
4 2 Po (AD)
< 7 PO2 (AD2)
= OPN) pono
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caer se} 607 apa)
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pay mm || 4, “98 ag — auc proay <8"!
2 }
samen | | 3 ~
Poss |P34 | 4 14 z
FSS Ty)}— 15 8
p36 (WR) 18 aa
370) cu 2s |} P29taa
osstatee FAA] 1° al} zie)
signals “XTAL 1 9 2 P21 (Ag)
ond —| 20 x || raoite
Fig. 1.41 Pincut of 6051
Port 2 (Pins 24 - 28) : The output drives of port 2 are used to access external memory.
Port 2 outputs the high order byte - eer
fof the external memory address | Symbol Position Alternate tse |
when the address is 16 bits wide
Otherwise, port 2 is used as an 1/0 a =
port Wes
Port 3 (Pins 10-17): All port | 288
pine of port 3 aze multifunctional, | 7 PA
Therefore, each pin of port 3 can be | a
Nims
programmed to use as JO or as | aoe 4
ne of the allemate fonction. They | ID 78
fhove special functions a= shown | pp FAL
below » including to -exterral -
RxD PAS data put
interrupts, two counter inputs, two
special data lines and two timing
control strobes.
Table 1.44
TECHNICAL PUBLICATIONS® - an updrast for ronteeoe
Power-supply Pins Veg (Pin 40) and Vgg (Pin 20) : 8051 operates on dc. power
supply of +5 V with respect to ground. The +5 V is to be connected topin Voc and
ground to pin Vag with rated power supply current of 125 mA.
Oscillator Pins XTAL2 (Pin 18) and XTAL1 (Pin 19): For generating an internal clock
signal, the external oscillator is connected at these two pins. ~
|ALE (Address Latch Enable, Pin 30): AD, to AD, lines are multiplexed. To
demaltiplex these lines and for obtaining lower half of an address, an external atch and
ALE signal of 8051 is used.
RST (Reset, Pin 9): This pin is used to reset 8051. For proper reset operation, reset
signal must be held high at least for two machine cycles, while oseilator is running
SEN (Program Store Enable, Pin 28) : It is the active low output control signal used
to activate the enable signal of the external ROM/EPROM. It is activated every sbx
vcilator periods while reading the extemal memory. Thus, this signal acts as the read
strobe fo extemal program memory
ER (External Access, Pin 31) : When the FA pin is high (connected to Ve). progam
fetches to addresses Q000K through OFFEH{ are direcied to the intemal ROM and
rogram fetches addresses 1000H through FFFFHL are directed to extemal
ROMIEPROM. When EA Is low (grounded) all addresses (00H to FFFFH) fetched by
program are directed tothe extemal ROMIEPROM.
Review Ques
| Tr Draw the pin diagram of 8051 mierocontroler and explain its port.
2. List the eferative fonctions assigned to port 3 pins of 8051 microcontroller.
[au : oay-11 Maris 2]
DES
13. Explain the pinouts of 8051 mionocontroller
Internal and External Memories
REE
Fig, 151 shows the basic memory structure for S051, It can acess up 10 GC
program mamory and 6& K data memory. The 6051 has 4 K bytes of internal program
memory and 256 bytes of intemal data memory.
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EI internal RAM Organization ™ ofa Pe betebelelalals) 2
The 8051 has 128-byte infernal RAM, It is accessed using RAM address register. The 2, ate] asin tae aces aee| 1@
Fig. 1.52 shows the organization of internal RAM, AS shown in the Fig. 12 intemal oo [Ry] [or [08] 05 [ os} 03 | 02 | or] on 30
RAM of 8051 is organized into thiee distinct areas | Bi adresses Byte General purpore
‘© Register bank ew addresses,
© Bit addressable
+ General purpose,
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Fig. 1.5.2 Organization of infomal RAM of 8051
.
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8051 Register Banks (Working Registers)
‘The first 32-bytes from address QOH to IFH of internal RAM constitute 32 working
registers. They ate organized into four banks of eight registers each. The four register
banks are numbered 0 to 3 and are consists of eight registers named Rp to Rr.
Each register can be addressed by name or by its RAM address,
Only one register bank is in use at a time. Bits RSO and RSI in the PSW determine
‘which bank of registers is currently in use,
[Rei @sway — Rs0 sw) Bankesolecion |
| 0 ane |
| 1 ne
| °
L i |
‘On reset, the bank 0 is selected and hence it is a default register bank. Register banks
‘when not selected can be used as general purpose RAM.
Bit Byte Adéressable
“The 6051 provides 16 bytes ofa bitaddressable area, It occupies RAM byte addresses
from 20H to 2FH, forming a total of 128 (16 x 8) addressable bits
‘an addressable bit may be specified by its bit address of OOH to 7FH or 8 bits may
form any byte address from 20H to 2FH.
For example bit address 4EH refers bit 6 of the byte address 294
SEY Genoral Purpose RAM
The RAM area above bit addressable area
RAM. It is addressable as byte
from 30H to 7FH is called general purpose
ROM Space in the 8051
‘The 805i has 4 Kbyte of intemal ROM with address space from Q000H to OFFEH. Its
programmed by fhanifacturer when the chip i built Ths part cannot be erased or
altered after fabrication. Tris is used to store final version ofthe program. Tt is accessed
using program adress register.
&
Ga
1 Wht do you undretand by bit adaveeable RAM in 8051
movie? Ty
of the £051 microcontroller.
#
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2. Discuss the internal momory organi
Embedded Systoms and ioT 115 2-82 Miewconnoter Arentectire
Dies about He oronaton of ined RAM and sel incon vegies of 051
ricci in deat
4. Dives ai inert date monary orgnzton of oncom 0
5 apn te progam menry and dts mencry sar of 061 mirocntle.
TEST
6 Draw the te enory scr of 05 micelle and exp
Explain the RAM structure of 8051 microcontroller EE
Stack and Stack Pointer
‘The stack refers to an area of internal RAM that is used to store and retrieve data
quickly. The stack pointer register is used by the 8051 to hold an intemal RAM address
that is called top of stack. The stack pointer register is 8-bit wide. It is increased before
data is stored during PUSH and CALL instructions and decremented after data is
restored during POP and RET instructions.
‘The stack array can reside anywhere in on-chip RAM. The stack pointer is initialized
to O7H after a reset. This causes the stack to begin at location OSH. The operation of
stack and stack pointer is illustrated in Fig. 16.1.
Oncnip Rant onsrip Rady ntip RAN
z— ee
02
(a) Stats of stack ane
(0) Store operation
Baar] oo oe
Fe) 0s cs
7 pst or
ssacgeiner [BBS 07
(6) Reus operation
Fig. 1.84
TECHNICAL PUBLICATIONS® - an up-thtfor knowiedge Embedded Systems and oT 146 8.81 Merecontoler Architecture
‘The stack may overwrite data in the register banks, bitaddressable RAM and
scratch-pad RAM. Thus to avoid conflict with the register, bitaddressable RAM and
scratch-pad RAM data, the stack is initialized at a higher location in the intemal RAM.
ies
Expat operation of slack i 605%
2. Define SP,
Two Marks Questions with Answers
1 Name any four additional hardware features available in microcontrollers when
‘compared to microprocessors. ET
‘Ans.: The microcontroller has builtin ROM, RAM, parallel 1/0, setial 1/0,
timer/counters and a clock circuit.
2 Write the memory capacity of microcontroller 806%, n=
‘Ans. : The memory capacity of microcontroller 8051 is 64 Kbytes.
3 What are the flags availablo in 8051 7
‘OR What are the flags supported by 8051 microcontroller 7
‘Ans. : The flags available in 8051 aze : CY (Carry flag), AC (Auniary carry flag), OV
(over low flag) and P (Parity flag)
4 What is meant by SFR in 8051 7 Give an example.
‘Ans. : The group of registers, implemented to perform special function and are located
fmmediately above the 128 bytes of RAM are called special function registers for
‘example, all port registers, TCOM, SCON, IE, IP and so on.
5 Give the memory size of 8051 microcontroller. mE
Ans: The 8051 can access upto 64 Kbyte program memory and 64 Kbytes of data
memory
5 Give the details of PSW of 8054, (refer section 1.3.5)
7 Compare microprocessor and microcontroller. (Refer section 13) EEE
8 What are the appications of 8051 microcontroller?
‘Ans. : Microcontrollers are more preferred in embedded products. Some applications of
‘microcontroller are
Calculators # Accounting systems
+ Game machines ‘© Data acquisition systems
© Mobile systems © Complex industrial controllers
‘Trafic light control systems «Military applications
+ Communication systems
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Embedded Systems and loT 17 BB Microcontroller Architectre
9 Explain the significance of SFRs in 6051 microcontroller
‘Ans. : The group of registers, implemented to perform special function and are located
immediately above the 128 bytes of RAM are called special function registers. They are
responsible for operation of ALU, timer, serial port, parallel ports and interrupt control.
1.10 What is mean by microcontroller ?
‘Ans. A device which contains the microprocessor with integrated peripherals like
| memory, serial ports, parallel ports timer/counter, interrupt controller, data acquisition
interfaces like ADC, DAC is called microcontzolle.
1 List the features of 8051 microcontroller. (Refer section 3.2)
12. State the function of RS1 and RSO bits In the flag reglatr of Intel 8081
tmierocontrller 7
Ans: RSI and RSO are bank selection bits. They are used to select working register
bank of 651 as given below
+ 00 Banko +01 Bank 1
+10 Bank? +11 Bink3
13, Wve the alemate functions forthe port pins of port. (Rete Tele 1.41)
14 plain the function ofthe PEER pin of 61
Ane, : SEN : PSEN stands for program store enable. In 8051 based system in which
an extemal ROM holds the program code, this pin is connected tothe OE pin of the
ROM.
15 Explain the function of the EA pin of 6051.
fans. ER + it stands for extemal access, When the EA pin is connected to Vee,
program fetched to addresses CO0OH through OFFFH are directed to the intemal ROM
and program fetches to addresses 10008 through FFFFHL are directed to external
ROMIEPROM. When the FA pin is grounded, all addreses fetched by program are
directed tothe external ROM/EPROM,
.16 Explain tho 16-bit registers DPTR of 6051 or what is a function of DPTR 7
EE
Ans. DPIR : It stands for data pointer. DPTR consists of a high byte (DPH) and a
low byte (DPL). ls function is to hold a 16bit address, It may be manipulated as a
16-bie data register or a6 two independent bit registers. It serves asa base register in
{ndivect jumps, lookup table instructions and extemal data transfer
2.17 Explain the function of the SP register of 8051,
‘Ans. : SP : It stands for stack pointer. SP is 8- bit wide register. It is incremented
bofore data is stored during PUSH and CALL inctructions. The stack array can reside
anywhere in on-chip RAM. The stack pointer is initialised to O7H after a reset. This
causes the stack to begin at location 08H.
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{Qi8 Name the special function registers available in 8051 25 A given 8051 chip has a speed of 16 MHz, What is the range of frequency that
‘ean be applied to the XTAL 1 and XTAL 2 pins ?
‘Ans. : The special function registers available in 8051 are
‘ane. : The range of frequencies that can be applied to the XTAL 1 and XTAL 2 pins is
+ Accumulator B Register + Program Status Word. | 1 MHz to 16 MHz,
: ene = (Dae raien (0.26 What happens in power down mode of 8051 microcontroller ?
+ Port + Port 1 |
1 cars Pais ‘Ans. + In the Power Down Mode (PD = 0), the CPU puts the whole chip to sleep by
: tuming off the oscillator. In case i tis running from an external oscillator, it also gates
‘Interrupt priority control register. ‘+ Interrupt enable control register. ‘off the path to the internal phase generators, 50 no intemal clock is generated even if
2.19 How is stack implemented in 8051 7
‘ans. : The 8051 LIFO : Stack can reside anywhere in the intemal RAM, It has 8 bit
stack pointer to indicate the top of the stack using PUSH and POP instructions.
‘During PUSH the SP is incremented by one and POP the SP is decremented by one.
(0.20. What is the maximum frequency of the clock signal that can be counted by
8081 counter 7
‘Ans. : The maximum frequency of the clock signal that can be counted by 8051 counter
is Yl2 x crystal frequency,
1.21 What are the features of ROM and RAM In 8051 microcontroller?
‘ans. : The 8051 has 128-byte internal RAM. It is accessed using RAM address register.
‘The internal RAM of 8051 is organized into three distinct ereas
‘© Register Bank * Bit addressable + General purpose.
‘The 8051 has 4 Kbyte of internal ROM with address space from OOQIH to OFFFH. It is
programmed by manufacturer when the chip is built. Ths part cannot be erased or
altered after fabrication. This is used to store final version of the program. Its accessed
using program address register.
0.22 What is the function of program counter in 8051?
‘Ans. : The 8051 has a 16-bit program counter. It is used to hold the address of memory
location from which the next instruction is to be fetched,
0.23 List the advantages of microcontroller over microprocessor.
‘Ang, : The advantages of microcontroller over microprocessor are
Because of builtin peripheral support they provide single chip
‘microcontroller system,
‘© Less hardware required
‘© Less hardware increases reliability.
‘+ Supports intemal memory which reduces access time,
24 Which ports of 8061 are bit addressable 7 Pru: 00-12)
‘Ans. : All ports of 8051 - port 0, port 1, port 2 and port 3 are bit addressable.
the external oscillator is still nimning. The on-chip RAM, however, saves its data, as
ong 25 Vee is maintained. In this mode the only Ic that flows is leakage, which is
normally in the micro-amp range.
0.27 What Is the function of R registers in 8051 microcontrollor 7
(Refer section 1.5.1.2) Panty
0.28 What is the purpose of overflow flag in 8051 microcontroller 7
(Refer ection 1.35)
0.29 List the on-chip peripherals of 8051 microcontroller, (Refer section 1.3)
a
0.30 Mention the size of DPTR and stack pointer in 8051 microcontroller.
(Refer seeson 13) Pane}
0.31 List the alternative functions assigned to port 3 pins of 8051 microcontroller.
(ter seczon 14) EST
32 What are the main features of 8051 microcontroller 7
(Refer section 1.2),
33. What is program status word of 8051 7 (Refer section 1.3)
0.34 Mention the purpose of PSEN and EA in 8051 microcontroller.
(Refer section 1.4)
35. What is meant by PSW ? (Refer section 1.3.5)
| 36 State any four inbuilt features of 8051 microcontrollers
(Rafer section 2.2)
0.37 What is the use of PSW 7
‘Ans. : PSW (Program Status Word) is used to determine whether or not to execute
conditional instructions, In case of 8051, it is also used to select the working register
Dank
Q.38 What is the significance of PSEN and EA pin in 8081 microcontroller 7
{Refer section 1.4) Eso
goa
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‘TECHNICAL PUBLICATIONS® - an uphutfrknoateare Embedded Systems ond oT 1-20 2.81 MerocontolerArohteture
| UNIT I
Instruction Set and Programming
=
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Syllabus
Lnstrcton Se and Programming
Contents
24 805% Adtessing Modes June-08,11, ec -07,08,08,11,13,94,
eco May99,1446,47 Marks 16
Ctassteation of struction Set of 805%... May-10 Marks 4
Data Tranter instructions Dee-07, 08,11, May-11, «Marks 16
Byte Level Logical Insrucons May-10,11, Marks 10
25° Arthmetc nstuctons 1 May-05, 08, June-t# <--> Marks 2
26 BitLevel Logicel Instructions
2.7 Rotate and Swap Instructions
2.8 Jump and CALL Instructions
28 Time Deiay for 6051
2.10 Program €
May-08,10,19,17, Dec.-18, Marks 13
ec-08, June-09
Marks §
les May-10, Dec-12,
2.11._Two Marks Questions wie Answers
eT j
j
Embodied Systome and oT 202 Instruction Set and Programming
8051 Addressing Modes
RAT
13.13.1617
SEUATICATREAT
‘The way, using which the data sources or destination addresses are specified in the
instruction mnemonic for moving the data, is called ‘addressing mode’. ‘This section
explains addressing modes used in 8051 with examples.
Register Addressing
‘The 8051 can access eight "working registers” (RO-R7). Three bit code within the
instruction selects one of the eight registers from the selected register bank. The
programmer can select a register bank by modifying bits 4 and 3 in the PSW.
Destnaton regster —_ Source region
Example ; Add the contents of register R3 and R¢ from bank 2
Step: Select register bank.
MOV PSW, #000010008 : select register Bank 2
Step2 : Add the contents of R3 and Ri
MOV A, 33
ADD A, RG
FEE}
rect Byte Addressing
Maney
Direct addressing can access any on-chip variable or hardware register ie. on-chip
RAM and special function register. The most significant bit of the address decides
whether it is 2 location within on-chip RAM (MSB = 0) or in special function register
(SB = 1),
Example : Add the contents of locations S0H and 51H
‘MOV A, 50H load byte from edarees 60H into A
ADD A518 ‘Add the contents of A and the contents at memory location 51H.
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Embedses Systems and ioT
Instruction
and Programming
Register Indirect Addressing
In this addressing mode RO and RI of each register bank can be used as an index or
pointer register. RO and RI point to the contents in the RAM. The instruction with,
indirect addressing uses the ‘sign.
Indirect addressing accesses data in dynamic manner rather than static manner.
Looping is not possible in direct addressing mode. In indirect addressing we can
increment the index or pointer register to access successive locations.
emery
Rogier
‘sed to point memory
Destination eget
=
eae ed Oaeton |
eslciad memory
RO and Ri are the only registers that can be used for pointers in register indirect
addressing mode,
Example: ADD the contents of memory location addressed by register 1 to the
tents of RAM location pointed by register 0.
MOV A. @RO snted by RO in A
ADD A, @RI ntents of A end the contents pointed by Rt
Immediate Addressing
In this addressing mode souree operand.
constant rather than a variable. So the
constant can be incorporated in the Data sont
instruction. Sign “#" indicaies it isa
immediate addressing mode.
Example : Add the constant 52 decimal in accumulator.
MOV A, #52
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ERE Resistor specific
Inherent in the instruction, these refer to a specific register such as accumulator or
DPTR.
br. at Insincbon Set nd Programming
Example =
SWAP A
ERS incex
Only program memory can be accessed in the index addressing, Either the DPTR o
PC can be used as an index register,
: Swap nibbles within the Accumulato:
PTR Resistar
Program memory
Ais
== sa... ©
sateted may
|
Cones otregister A
Example : Read data from the program
Move a, é
+DPTR
Stack Addressing Mode
is subty
are used,
of direct addressing mode in which stack instructions (PUSH and POP)
nstruction such as PUSH A’ is invalid. Here, we have to specify the address
of register A. Thus, PUSH QEOH is a valid instruction; it pushes/stores the contents of
accumulator on the stack
Examples :
PUSH 04 Push Ré onto stack
PUSH 66 1 Push R6 onto stack
POP 02 q
op top of stack into R2
POP OFOH 1 Pop top of stack into register B
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Embedded Systems end oT 25 Instruction Sot and Programming
Classify the adavesing modes of 8051 microcontraller
2. Explain the diferent addresing modes in 8051 in det
9: What are the addresing modes of $051 micocontolr ? ERT TS CTT
4. What is register indirect addressing mode of microconriller 8051 ? Give exemple
rent addressing mades of 8051 microcontole.
© Whit ae the aiesing made alowed in 8051 Micro controler ? EXER ET
2. Explain the diferent addressing modes of 8051 microconboller. EXOD
5. Expl hed
[EZ] Ciassification of instruction Set of 8051
‘An instruction is a single operation of a processor defined by an instruction set
architecture. According to type of operations, the instruction set of 8051 is classified as,
Data Transfer Instructions
= Byte Level Logical Instructions
1» Bit Level Logical Instructions
‘Arithmetic Instructions
= Jump and CALI
Instructions.
Data Transfer instructions
An immediate, direct, register and indirect addressing modes are used in different
MOVE instructions. Table 23.1 lists all types of data moving (data transfer) instructions.
| MOV : Loz!
1 Table 24.1 gives the list of byte
Description :
ANE A, Ra
Example
ANL A, direc
Example:
ANL A, €RI
Euample:
ANL A, Fate
Example:
ANL dec, A
Example:
CANE divest ata
Example
ORL ,
‘Description *
ORLA Rn
Example
ORL A, direc
Example
ORLA, aR:
Example
ORL A, data
Example:
nstcton Set and Prograny
ANL pesfon
LD fos byle vatiables Bytes : 1/25 Cycles : 1/2
ihe binvite logisaAND operation between the vaciables
inalaled and stores the cons im the destination variable, No flags aze
sec
AND register to Accumulat
ANU A, R2: Logically ANDs A and RE ond store
resulta A.
[AND direct byte w Accumulator Byer
Pye
|AND indirect RAM to Accumulator Bye
ANE A, ®22 : Topieally ANDs contents of A and
‘ramon location whos addstss i given by RZ and
stores result in A.
[AND immediate dsia to Accumulator Bye?
[ANE A, «S014: Logically ANDs contents of A with
50H and snes ceva in A.
|AND Aceumulstor (0 direct byte bye?
'ANL 20H, A : Loglelly ANDs contents of A with the
Zonteals ck memory locaton 20H and stores reult at
samory lection 204,
AND immediate data to cles byte Bytes
‘ANE 204, 2208 : Logically ANDSs the contents of
temory location 20H sth dara 20H and stores cent
firmemory Iocatlon 20H,
cogicel-OR for
yee
cycle t
Gye 1
Geet
Cyde
ye?
voles Bytes : 23. Cycles : 12
‘ORE pefocms dhe bitwise logeal ren she indicted
‘ables, eooing No flags ate affected
OR register to Accumulator Byel Che!
ORL A, Ra : Logically OF the contents of A and R2
sind stoves esl = 8
OR direct byte to Accumalsor eyes Cycle
‘ORL A, 20H : Loghally ORs the contents of A and
remory faction 20H and stores result nA.
OR indizect RAM to Accumulator Byei Gydet
‘ORL A, €R2 : Logically ORs the contents of A and.
‘emer? location whose acess given by register
Ro and sores result in A.
‘OR immediate data to Accusulater Byte2 Cree
‘ORL A, #321; Logically ORS the contents of & sith
and stapes ress 8 A. OH Accum: (9 cies by Bye? Guet
ORL 5, A: Logically ORS Lis nlc of si |
{be cones oftasren lation UH and ores
| a. ea
| ORL dieecr #datn OR immediate data to direcs byte Bye 3 Cycle?
|. Bample: ‘ORL 20, s30H- Logically ORs the coment of
smermory fcatan 2
‘3k memory location: 20H
XL cdestoyten cmcbyer: Loge! EnusieOR for bye varablen Bytes 128 Cylee: 12. |
‘data 30H and stones result i
| Dessipion RL evo we ingens oprn Een he
indicated varus sing te res in the dstnation, No Begs are
Mises.
| xm a, Ra Excinsive-OR ropister to Accumulate Bytel Creed |
[ements War Ae Cogety ROR wl oS OATES a
td stn rel 1 A dial
[MLA dies tai din iyi Asana: Bie? Cyded |
Buampie: SL A, 30H : Logeally XORs the costes tA wth fle)
k ‘peor fll SFY ere toces ele
| xe Aen EedusiveOR ae RAM 0 A Smet Cyt
fi asampie REA, ORE: Losey SOTs the cantent of 8 ane
| the mina cso whose sess even By 2
se sores result 8
XRL A, fdata—_ Exchitve-OR immedi dts f0'A Bye? Gye
Bample: AML A, HH Loglealy XORe the covtents of 4 with
| dts tt aston rel A. y
J XR cect A Exchnive-GR Accilaioc te des bre are? Geel
Enample Lally ORs ibe contents a 208%
XRL dc, es Ga2
Enample cece 41S
CLR A : Clear Acc
io
Bytes 21 Cycles 21
vs zero). No Hage ate affected.
‘Accommiotor Is deere tall Fis se
ni Bytes: 1 Cycles :2
Description fhe Aceuneteay ie Iigeally complimented
emer), Bits whlch previously contained a one are changed
bah vianversa. Ne flaps ace aff
Table 244
cra
Compiement
fy meus XR A, dives
Erivedded Systrs ad oT
Arithmetic Instructions
‘The arithmetic operations of 8051 include increment, decrement, addition, subtraction,
multiplication, division and decimal operations.
Incrementing and Decremonting
Incrementing and decrementing instructions allow addition and subtraction of 1 from
a given number. These instructions not affect C, AC and OV flags. Table 25.1 lists the
increment and decrement instructions
INC -InerementBytes : 1/2 Cycles U2 |
Description > INC pence ate arabe by 1 An oii vale 0 FF wi
I eo 0 OE Ns geo all
NCA” neeners Aenomairty Bet Geek
INC En lnerement meer so ape (ose! |
‘Example : ANC R2 : Increments contenits of R2 by t 4
INC direct increment direct byte bye Cer
Femmple: INC 2H: recent cn of emu ncn whens a4
‘Sie von tints vomcton OH) BY oa)
INC eR name net Ba Brel Gent
Brample? INCOR? cere stn of yen hoe i
Sidon ges ty pate By 3
INCDPIR innerent Deu Pate? Bret Gk?
DEC ayer: Decrement Byles 22 Cyelens3
Sescipion: : nein vale of D8 wit
2 bel Gael
ge Bret See
Cecement donc at be? Get
DEC 0H Deven one of memory ein
‘howe asdins oa 4 |
a Be:
Buample: DEC as -Dermerts i eof mason beatin
‘whose addres f= gion By reget £2 by 1
Tobe 2.5.4,
TECHNICAL PuBLICATIONS® Embodied Syste and lo
Addition
‘Table shows the list of addition instructions supported by 805.
ADD A, : Add Bytes : 1/2
Cycles 1
Deseripton: Adds the byte variable indicated to the Accumulatr, leaving the result in
fhe Accuruiatgr. The cary and cowiery-aary flags are sab xespectively, |
here fs « coeryout fom tit 7 orbit 3 an cleared others
‘when adding signed integers OV indicates» negative namber produced as
{he sum of tivo postive operands, oF a postive sum from two negative
operand:
ADD A, Rn Ade ragister to Accumulator Bret cycled
Example: ADD A,B» Adds contents of A and R2 aid store i
raul in A |
ADA, dirt Add Shract byte to Accumidator Bye? Cycle
| Bumple: ADD A, 20 = Adds contonis of A and memory wliose i
‘dress is 20H and store result fn 8. 1
| ADD A,@RL Ade indirect RAM to Accumulator Bye cydet
Example: ADD A, aM + Addo the contents of A and memary
‘hose dre gven by register R2 snd ores resale x
4
| ADD A,edats Add lmmediste dats to Aesamulator Bye? eyelet
| Example: ADD A, 2208: Adds the contents of A an
ADDC A, + Add with C:
Bytes :1/2 Cycles #1
Description ADDC simultaneously adds the byte vaslable indicated, the camry flag and
the Accurnalater, expectiveh, if there fs carr-out from Bit? or BRS
ADDC A, Rn Ads rapiser (2 Ascamatec wth cary fag Bye “Gye
Example ADDC A 12: Adds the contents of A, RD and coy
ADDCA, direct Ade aisect byte to 8 wth cany 9g Bye? Eyee
Example Aad the content uf 4, memony
ADDC 4, Ri Byte! eye
Example congerss of nem
sven by cepate RD and che
ADDC A, fata Byte2 Cyaed
Example:
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Instruction Set ond Programming
FEEY subtraction
Table shows the list of subtraction instructions supported by 8051.
Bytes: U2 Cycles 2.
UBB stats the indicted vorabe sed the cry Rig together Som the
SUBB A, : Subtract with Borrow
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EEZG Muttiplication and Division
MUL AB : Multiply Bytes:1 Cycles:
Description: MUL AB ns it integers in the Accumulator and
ragister 8. The lot-ardes byte ofthe extent product is lft in the
Accomulator, and the hghvorder byte in Bl tke produc i grater than 255
(GEE) the overdow flog se set otherwise it 8 eared, The cary fag is alvays
dese.
Example: Originally thé Accumulator holds she vslue $9 GOH). Register B holds the
‘alae 160 (QAOH), The instruction, MUL AB will give the product 12,800
(G20, <9 8 is changed to 3H (01100108) an the Accumulator is cence.
The overlow Flog is Scary is dered, Embodied Systems ana
DIV AB Diviae Byteast Gyaeea |
Description
‘Thad originally contained OOF, th vale reimed i the
Assumulaior and Buugister willbe undefined and the overflow Hg will be |
The cry Bagi eared ir any cave
‘The Accunnulotor contains 250 (OFBH ot 111170108) and'B-contains 18 (028 or |
0: C010 The nue DIV. AB ofl wee 13m ihe Asmar Ole |
20011018) an the wave To (OH ae RACINE) in Bsc ASO Ss ah
1e Ch end OF val bo cana an aH 9
Example:
Decimal Arithmetic
DA A: Decimal-adjust Accumulator for addition. Bytes
Cycles 21
‘lt value In the Actuator resulting from the earlier
rabies (ench in packed BCD formst) to produce
Description: Adiuars the eigh
adeison of be
ecked:BCO venue
I the lowes nib ofthe ascurilator i greater than 9 or AP is et it corects
zest by adding G6 in the lower nibble Ifthe upper nibble ofthe
‘Serra gover than 9 Cs eit cnet te seul by ang 6 ta
Beample: A551: H=68H and CF ot ‘The iatretion saqeae
Be
Bei 6H
14 BED sim
8051 ricrocontroler ?
Legicai instructions
Bit level manipulations are very conveniené wh
particular bit in the i
cessary to set or reset a
nal RAM or SFRs. The internal RAM of 8051 from address,
246 nsrscton Sot and Programming Embedded Systoms and loT 27
struction Set and Programming
through 2FH is both byte addressable and bit addzessable. However, byte and bit
addresses are different. The Table 2.6.1 shows the correspondence between byte and bit
addresses.
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Table 26.1 Bit and byte addresses of intemal RAM
‘As shown in the Table 261, p=
addresses of bit 0 and bit 7 of
intemal RAM byte address 20H |
are OOH and O7H respectively
From Table 261 we can easily
»
interpolate addresses of bit 1 and ia
bit 6 of internal RAM byte address
26H as 31H and 36H, respectively B
Like intemal RAM, some SFRs ®
ae bit addressable. The Table 262 2
shows the bit addressable SFR and a
the corresponding bit addresses. -
bo.
8
58
‘Table 2.6.2 Bit and byte addresses of SFRS
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ms and eT 218 ian Set and Programming
Table 263 gives thei ; ;
ects Caos en
Le: Cen re wai Gao
Teitsea endear ae
Ea For has previsly ean writen wich FF (1112098). The marco,
i Gi Baa Wil ene the port cet to FB CHTNIB)
SETB C:: Set Carry flag Bytes 1 Gyclen:1 |
|SETB bit: Set direct bit Byles :2 Cycles 1 |
DDeseption; _SETB sls he Indicated BW one SETB can operate on the o
a diy cecyedaresale bie No ther Bap act seeds S|
Bample: The cry is cleted, Ourpat Port as bem ween withthe value 381
(OIIONE) The natn,
semc
SE Po
| vel eae th cary ag eet to | and change th data output on Port] 50
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} CPL C : Complement Carry fagBytes :1. Cycles:
I CEL bit : Complement direct bitiytes :2 Cycles 1
[eecipion; The bc avible specified i complmented. No other fags ae afcod
Pace ort as puvloly bean writen with FFH (11110028). The instvetion
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