Digital technology roadmap

Digital Circuits and Systems (CSD)

Large volume of production

Systems on Chip
Verilog, VHDL & System C (SoC) & ASICS
(GA)
Intel/Lattice/Xilinx FPGA
Systems on
(>100k logic gates) Professional applications in
Programmable
Chip (SoPC) Telecommunications Systems and
Networks
Intel/Lattice/AMD CPLD and FPGA
(2,5k – 100k logic gates) Chapter 3:
Microcontrollers (µC)

Schematics The versatile sPLD 22V10

PIC18F /16F / ATmega families of
& (500 logic gates) microcontrollers

VHDL Chapter 2: Sequential

systems and FSM Dedicated processors
Theory and examples from
(Datapath + control unit)
classic 74 TTL and CMOS
subsystems and peripherals
(SSI & MSI)

Introductory circuits & FSM

Chapter 1:
Combinational Advanced optional subjects or
circuits Digital Circuits & Systems research
 Digital Circuits and Systems (CSD)

Lab training boards and target chips

Intel/Lattice/AMD FPGA Microchip PIC18F

Chapter 1: Chapter 2: Sequential

Chapter 3:
Combinational systems and FSM (Finite
Microcontrollers (µC)
circuits State Machines)
 Digital Circuits and Systems (CSD)

CSD competencies
Programmable logic devices
and VHDL Team work Self-directed learning

Project management English

Microcontrollers and C (time and due date)
Oral and written
communication
Lab skills (UPC email address)

Learning goal:
Using cross-curricular competences and PBL methodology, let us systematically
analyse, design, simulate, implement, report, present and reflect about digital
circuits and systems using state-of-the-art programmable devices, CAD/EDA
software tools and laboratory equipment
 CSD specific content Digital Circuits and Systems (CSD)

Chapter 1 Chapter 2 Chapter 3

Combinational Circuits Finite State Machines (FSM) Microcontrollers (C)

(50 h) – 2 ECTS (50 h) – 2 ECTS (50h) – 2 ECTS

Laboratory skills: logic analysers, timing diagrams, debuggers/programmers, simulators, etc. …

• Proteus-VSM (virtual lab), WolframAlpha, Minilog, VHDL for developing and testing • Proteus-VSM (Labcenter Electronics)
• Quartus Prime (Intel), ispLEVER Classic – Diamond (Lattice Semiconductor), ISE – Vivado (AMD) • MPLABX (Microchip)
• Intel Integrated Synthesis, Synplify Pro synthesis (Synopsys), XST (Xilinx synthesis tools) • XC8 compiler (Microchip)
• ModelSim (Questa) Intel FPGA Edition (Siemens), Active HDL (Aldec) Lattice Edition, ISE simulator (Isim)

• Programmable logic devices (CPLD and FPGA) from Intel, Lattice, AMD.
• Classic IC’s • Training boards (DE10.Lite, DE2-115, Spartan 3AN Starter Kit, MachXO • PIC 16F/18F, ATmega families of microcontrollers,
• sPLD GAL22V10 USB Starter Kit, NEXYS 2, etc. Training boards PICDEM2+, etc.
 Digital Circuits and Systems (CSD)

CSD generic skills

English Oral and written Self-directed learning Teamwork Project management
language communication
• Mindmaps, • Gantt charts
• Use English • Pen & paper CMapTools,
everywhere in CSD
• Thunderbird / Meet
• Video recordings

• Cooperative learning

• Be systematic and try to write high quality reports asking for feedback
• Draw sketches, diagrams, concept maps, schematics and flowcharts
• Be active and participate. Be curious and ask questions
• Be constant, motivated and committed for the full semester
 Digital Circuits and Systems (CSD)

Planning activities and study time in and out of classroom

(6 ECTS – 150 h)

Activities Weekly study plan

15 weeks
Classroom lectures (3 h)
Theory and tutorial projects (P1 .. P12)

Guided learning
General discussion, theory, project
tutorials and examples

Laboratory project solving (2 h) 10h per

Laboratory projects P_Ch1, P_Ch2 Teamwork sessions, etc. week
and P_Ch3 (including oral presentations)

Student-conducted

learning
Self-directed
Individual questionnaires (Q1_4, Q5_8, Q9_12)
teamwork sessions 6 ECTS
and other classroom activities

Extra individual work

(> 5 h)
 Digital Circuits and Systems (CSD)

Activities/projects  Designing real-world applications

• using PLD/VHDL
• using microcontrollers/C

Comparison of alternative designs

 Digital Circuits and Systems (CSD)

Cooperative learning for designing projects

• Positive interdependence
Team members are obliged to rely on one another to achieve their common goal

• Individual accountability
All students in a group are held accountable for doing their share of the work and for mastery of all of
the content to be learned

• Face-to-face promotive interaction

Group members providing one another with feedback, challenging one another’s conclusions and
reasoning, and teaching and encouraging one another

• Appropriate use of collaborative skills

Students are encouraged and helped to develop and practise skills in communication,
leadership, decision-making, conflict management, and other aspects of effective teamwork

• Regular self-assessment of group functioning

Team members periodically assess what they are doing well as a team and what
they need to work on for functioning more effectively in the future
 Web pagesDigitalasCircuits
anand ebook
Systems (CSD)
and agenda

digsys.upc.edu
 Digital Circuits and Systems (CSD)

Planning session by session

 Digital Circuits and Systems (CSD)

Example projects and support

• Exams and discussion from previous semesters

• Collection of sample and tutorial problems and projects
• Example questionnaires
• Threads of comments and queries related to tutorial and post-lab projects
• Combined with (asynchronous) email support ( rules ) and (synchronous) meet

BIBLIOGRAPHY  digsys.upc.edu/csd/books/books.html
 Digital Circuits and Systems (CSD)

Assessment scheme • Exams = 50%

• Questionnaires and class activities 20%
• Projects (P_Ch) = 30%
Provisional grading available at Atenea.

Project organisation (at least four sheets of paper):

1)Specifications
2)Planning
3)Development
4)Test and verification
5)Report (handwritten)
6)Prototyping and laboratory measurements
 Course policies
Digital Circuits and Systems (CSD)

NOTE: To get marks  project solutions have to be submitted in the established format
and before the due date.

Exams will be sit at school premises. Only pen, paper and scientific calculator.

Class attendance is requested (even if it is not an obligation). You must engage

participating actively in class and promoting cooperation in your lab group.

Laboratory attendance is compulsory.

Academic dishonesty. Cheating penalties:

- First instance  0 on corresponding assignment

- Second  0 for entire course

Grades will NOT change because you really worked hard on class, or you need to graduate, or because
otherwise you will lose your grant.

Do you want a good grade? Earn it with your full commitment and designing high quality projects.