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8086 Microprocessor TYBSc

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8 views

8086 Microprocessor TYBSc

Uploaded by

Cricket Lover
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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8086 microprocessor

Architecture
Features of 8086
The most features of a 8086 microprocessor are as follows −
It has an instruction queue, which is capable of storing six instruction
bytes from the memory resulting in faster processing.

It is the first 16-bit processor having 16-bit ALU, 16-bit registers,


internal data bus, and 16-bit external data bus resulting in faster processing.
It is available in 3 versions based on the frequency of operation −
8086 → 5MHz
8086-2 → 8MHz
8086-1 → 10 MHz
It uses two stages of pipelining, i.e. Fetch Stage and Execute Stage,
which improves performance.
Fetch stage can prefetch up to 6 bytes of instructions and stores them in
the queue,Execute unit executes these instructions.
It has 256 vectored interrupts.
• It requires single phase clock with 33% duty cycle to provide
internal timing.

• 8086 is designed to operate in two modes, Minimum and


Maximum.

• It can prefetches upto 6 instruction bytes from memory and


queues them in order to speed up instruction execution.

• It requires +5V power supply.

• A 40 pin dual in line package.


Internal Architecture of 8086
• 8086 has two blocks BIU and EU.
• The BIU performs all bus operations such as
instruction fetching, reading and writing
operands for memory and
• calculating the addresses of the memory
operands.
• The instruction bytes are transferred to the
instruction queue.
• EU executes instructions from the instruction
system byte queue.
Internal Architecture of 8086
• Both units operate asynchronously to give the
8086 an overlapping instruction fetch and
execution mechanism which is called as
Pipelining. This results in efficient use of the
system bus and system performance.
• BIU contains Instruction queue, Segment
registers, Instruction pointer, Address adder.
• EU contains Control circuitry, Instruction
decoder, ALU,Pointer and Index register, Flag
register
• Bus Interfacr Unit:
• It provides a full 16 bit bidirectional data bus and 20 bit
address bus.

• The bus interface unit is responsible for performing all


external bus operations.

• Specifically it has the following functions:

• Instruction fetch, Instruction queuing, Operand fetch and


storage, Address relocation and Bus control.

• The BIU uses a mechanism known as an instruction stream


queue to implement a pipeline architecture.
• This queue permits prefetch of up to six bytes of
instruction code. When ever the queue of the BIU is not
full, it has room for at least two more bytes and at the same
time the EU is not requesting it to read or write operands
from memory, the BIU is free to look ahead in the program
by prefetching the next sequential instruction.

• These prefetching instructions are held in its FIFO queue.


With its 16 bit data bus, the BIU fetches two instruction
bytes in a single memory cycle.

• After a byte is loaded at the input end of the queue, it


automatically shifts up through the FIFO to the empty
location nearest the output.
• The BIU also contains a dedicated adder which is used to
generate the 20 bit physical address that is output on the
address bus. This address is formed by adding an appended
16 bit segment address and a 16 bit offset address.

• For example, the physical address of the next instruction to


be fetched is formed by combining the current contents of
the code segment CS register and the current contents of
the instruction pointer IP register.

• The BIU is also responsible for generating bus control


signals such as those for memory read or write and I/O
read or write

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