5 4 3 2 1

D D

Kyloren MLK 15" Schematics

WhiskyLake - U
C
2018-07-16 C

REV :A00

B B

A DY : None Installed <Core Design> A

UMA: UMA only installed Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

OPS: DISCRTE OPTIMUS installed Title

Taipei Hsien 221, Taiwan, R.O.C.

Cover Page
Size Document Number Rev
A3
Kyloren MLK 15" WHL A00
Date: Monday, July 16, 2018 Sheet 1 of 106
5 4 3 2 1
 5 4 3 2 1

Kylo Ren MLK 15" CPU 15W + GPU 18W Block Diagram Project code: 4PD0FF010001
PCB P/N: 17948
Revision: A00
GPU DDR4
VRAM(GDDR5) *2 Channel A
NVIDIA PCIE x 4
2GB*32 SODIMM A
N17S-G1 25W
12
78-79 GDDR5 76-77 PCIE Lane1~Lane4
D D

Intel CPU DDR4

HDMI2.0 LPSCON Channel B

HDMI V2.0 HDMI Parade DDI1
Whiskey Lake U SODIMM B
57 PS175 57 13
15W

WHL PCH-LP
eDP 10 USB 2.0/1.1 ports DP 1.2
15.6" SS MUX
(HD/FHD/UHD) 6 USB 3.0 ports
DP1.2/USB 3.1 Gen2
USB3.1 Gen2 TypeC
55 I2C High Definition Audio TI
Touch panel 3 SATA ports
USB3.1 Gen2
TUSB546A 71
Port1
USB3.0 LANE4
6 PCIE ports
I2C USB 2.0
LPC I/F TPS65982DC
SATA/PCIex2(Optane)/PCIEx4 ACPI 5.0 USB2.0 CC1
M.2 SSD 63 USB2.0 LANE4 72 73

C C

7mm HDD SATA SATA LANE0

CardReader
60 SD 3.0 SD Card Slot
USB2.0 LANE8
USB2.0 x 1
Realtak
RTS5176E
USB3.0 USB3.0 LANE1

USB3.0 Port2
USB PowerShare PCIE LANE5
PCIe
TI USB2.0
Power share 36
TPS2544RTER 34 NGFF WLAN
USB2.0 LANE1 USB2.0 LANE6
USB2.0

USB3.0 USB3.0 LANE2

USB3.0 Port3 USB 3.0

USB2.0
USB3.0 USB3.0 LANE3 re-driver USB3.0
IO Board
36 USB2.0 LANE2
PARADE USB3.0 Port4
PS8713B

USB2.0 USB2.0 LANE3

B B

Free fall
Gsensor I2C
ST PCIE x 1 Giga LAN RJ45
LNG2DM 70 Conn.
Realtak 32
31
RTL8111HSD
Xtal
31
25MKHz

MIC_IN/GND
eSPI debug port eSPI BUS Universal Jack
68
HDA HP_R/L
USB2.0 x 1
USB2.0 LANE5

Thermal KBC TPM D-MIC 55

NUVOTON SMBUS MICROCHIP NUVOTON
NCT7718W 26 NPCT750 SPI HDA
MEC1416 2CH SPEAKER
24
91
CODEC (2CH 2W/4ohm)
Realtek
Fan Control Flash ROM
Camera (HD)

PS2
ALC3254-VA3
A
PWM
16MB 27
A

26 Quad Read 25

<Core Design>

Int. Touch PAD I2C

FAN Image sensor Wistron Corporation
KB 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
Block Diagram
Size Document Number Rev
C
Kyloren MLK 15" WHL X00
Date: Friday, July 27, 2018 Sheet 2 of 106
5 4 3 2 1
 5 4 3 2 1

#544669 CRB Rev0.52

SSID = CPU 1V_VCCST_CPU

1
R308
1KR2J-1-GP

2
THERMTRIP#_CPU

H_CPUPWRGD

24 PECI_CPU

1
24,44,46 PROCHOT#_CPU
55 TOUCH_PANEL_INTR#
24,65 TP_WAKE_KBC# DY ED301
D D
55 TOUCH_PANEL_PD# AZ5125-02S-R7G-GP
17 H_CPUPWRGD 1V_VCCSTG
+VCCSTG = 1.0 V
75.05125.07D

3
1
+VCCSTG = 1.0 V
R301
[PECI] and [PROCHOT#] Rb 1KR2J-1-GP RO13_20171001
CPU1D 4 OF 20 1V_VCCSTG
Impedance control: 50 ohm

2
TPAD14-OP-GP 1 CATERR#_CPU AA4 T6 XDP_TCLK 1
TP301 CATERR# PROC_TCK TP309 TPAD14-OP-GP
PECI_CPU AR1 U6 XDP_TDI 1
PROCHOT#_CPU PROCHOT#_CPU_R PECI PROC_TDI XDP_TDO_CPU TP310 TPAD14-OP-GP
499R2F-2-GP 1 R302 2 Y4 Y5 1
TP311
THERMTRIP#_CPU BJ1 PROCHOT# PROC_TDO T5 XDP_TMS 1 TPAD14-OP-GP
Ra THRMTRIP# PROC_TMS XDP_TRST# TP312 TPAD14-OP-GP
AB6 1
BPM_CPU_N0 PROC_TRST# TP313 TPAD14-OP-GP XDP_TDO_CPU
1 U1 R310 1 2 51R2J-2-GP
TPAD14-OP-GP TP307 BPM_CPU_N1 BPM#0 PCH_JTAG_TCK 1
1 U2 W6
TPAD14-OP-GP TP308 BPM_CPU_N2 BPM#1 PCH_TCK TP314 TPAD14-OP-GP
1 U3 U5 1
TPAD14-OP-GP TP302 BPM_CPU_N3 BPM#2 PCH_TDI TP315 TPAD14-OP-GP XDP_TCLK
1 U4 W5 1 R317 1 2 51R2J-2-GP
TPAD14-OP-GP TP303 BPM#3 PCH_TDO TP316 TPAD14-OP-GP
P5 1
PCH_TMS TP317 TPAD14-OP-GP
Y6
PCH_TRST# P6
PCH_JTAGX
1 GPP_E3/CPU_GP0 CE9 W2 XDP_PREQ# 1
TPAD14-OP-GP TP304 TOUCH_PANEL_INTR# CN3 GPP_E3/CPU_GP0 PROC_PREQ# XDP_PRDY# TP305 TPAD14-OP-GP
W1 1
TOUCH_PAD_INTR# GPP_E7/CPU_GP1 PROC_PRDY# TP306 TPAD14-OP-GP
CB34
TOUCH_PANEL_PD# CC35 GPP_B3/CPU_GP2
3D3V_S5_PCH GPP_B4/CPU_GP3
R303 49D9R2F-GP 2 R304 1 CPU_POPIRCOMP BP27
1 2 49D9R2F-GP 2 R305 1 PCH_POPIRCOMP BW25 PROC_POPIRCOMP
DY PCH_OPIRCOMP
100KR2J-1-GP

WHISKEY-LAKE-GP
R319
TP_WAKE_KBC# 1 2
0R0402-PAD

C C

(#543016) PROCHOT# Routing Guidelines

B B
M1,2,3,4,5: <3 inches
M6: 1-11 inches
MCPU: 0.3-1.5 inches
Mt <0.3 mils
Main route(M1+M2+M3+M4+M5+M6+MCPU): 1-12 inches

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
(Reserved)
Size Document Number Rev
A2
Kyloren MLK 15" WHL X00
Date: Friday, July 13, 2018 Sheet 3 of 106
5 4 3 2 1
 5 4 3 2 1

SSID = CPU

DP to HDMI2.0 HDMI_DDI_TX_N0 AL5

CPU1A 1 OF 20
AG4 eDP_TX_CPU_N0
HDMI_DDI_TX_P0 AL6 DDI1_TXN0 EDP_TXN0 AG3 eDP_TX_CPU_P0
57 HDMI_DDI_TX_N0 DDI1_TXP0 EDP_TXP0
HDMI_DDI_TX_N1 AJ5 AG2 eDP_TX_CPU_N1
57 HDMI_DDI_TX_P0 DDI1_TXN1 EDP_TXN1
2016/11/01modify HDMI_DDI_TX_P1 AJ6 AG1 eDP_TX_CPU_P1
57 HDMI_DDI_TX_N1
57 HDMI_DDI_TX_P1 DP to HDMI2.0 HDMI_DDI_TX_N2 AF6 DDI1_TXP1
DDI1_TXN2
EDP_TXP1
EDP_TXN2
AJ4 eDP_TX_CPU_N2
HDMI_DDI_TX_P2 AF5 AJ3 eDP_TX_CPU_P2
57 HDMI_DDI_TX_N2 DDI1_TXP2 EDP_TXP2
3D3V_S0 HDMI_DDI_TX_N3 AE5 AJ2 eDP_TX_CPU_N3
57 HDMI_DDI_TX_P2 DDI1_TXN3 EDP_TXN3
HDMI_DDI_TX_P3 AE6 AJ1 eDP_TX_CPU_P3
57 HDMI_DDI_TX_N3 DDI1_TXP3 EDP_TXP3
57 HDMI_DDI_TX_P3 RN401 DP2_DDI_TX_N0 AC4
57 DP1_AUX_CPU_N 1 4 CPU_DP1_CTRL_DATA DP2_DDI_TX_P0 AC3 DDI2_TXN0 AH4 eDP_AUX_CPU_N
57 DP1_AUX_CPU_P 2 3 CPU_DP1_CTRL_CLK DP2_DDI_TX_N1 AC1 DDI2_TXP0 EDP_AUX_N AH3 eDP_AUX_CPU_P
57 HDMI_HPD_CPU DP2_DDI_TX_P1 AC2 DDI2_TXN1 EDP_AUX_P
D D
DDI2_TXP1
SRN2K2J-1-GP DP for Type-C Mux DP2_DDI_TX_N2
DP2_DDI_TX_P2
AE4
AE3 DDI2_TXN2 DISP_UTILS
AM7

DP2_DDI_TX_N3 AE1 DDI2_TXP2 AC7 DP1_AUX_CPU_N

DDI2_TXN3 DDI1_AUX_N
DP for Type-C Mux 3D3V_S0
DP2_DDI_TX_P3 AE2
DDI2_TXP3 DDI1_AUX_P
AC6
AD4
DP1_AUX_CPU_P
DP2_AUX_CPU_N
for HDMI2.0
DDI2_AUX_N AD3 DP2_AUX_CPU_P
71 DP2_DDI_TX_N0 SRN2K2J-1-GP DDI2_AUX_P AG7
71 DP2_DDI_TX_P0 1 4 CPU_DP2_CTRL_DATA DDI3_AUX_N AG6
71 DP2_DDI_TX_N1 2 3 CPU_DP2_CTRL_CLK DDI3_AUX_P
71 DP2_DDI_TX_P1
71 DP2_DDI_TX_N2 CN6 HDMI_HPD_CPU
71 DP2_DDI_TX_P2 RN403 GPP_E13/DDPB_HPD0/DISP_MISC0 CM6 DP1_HPD_CPU_R
71 DP2_DDI_TX_N3 GPP_E14/DDPC_HPD1/DISP_MISC1 CP7 SIO_EXT_SMI#
71 DP2_DDI_TX_P3 GPP_E15/DPPD_HPD2/DISP_MISC2 CP6
71 DP2_AUX_CPU_P Design Guideline: GPP_E16/DPPE_HPD3/DISP_MISC3 CM7 eDP_HPD_CPU
GPP_E17/EDP_HPD/DISP_MISC4
71 DP2_AUX_CPU_N Skylake processor signal eDP_RCOMP should be connected to the VCCIO rail via a single 24.9 ±1% Ω resistor.
CK11 L_BKLT_EN
55 eDP_TX_CPU_N0 EDP_BKLTEN CG11 EDP_VDD_EN
55 eDP_TX_CPU_P0 RO13_20170626 EDP_VDDEN CH11 L_BKLT_CTRL
55 eDP_TX_CPU_N1 EDP_BKLTCTL
55 eDP_TX_CPU_P1 1V_VCCIO
55 eDP_TX_CPU_N2
55 eDP_TX_CPU_P2 CHECK WHL design guide: DISP_RCOMP R401
55 eDP_TX_CPU_N3 1 2 eDP_RCOMP_CPU AM6
55 eDP_TX_CPU_P3 (#543016) eDP_RCOMP Guideline DISP_RCOMP
55 eDP_AUX_CPU_N 24D9R2F-L-GP CPU_DP1_CTRL_CLK CC8
55 eDP_AUX_CPU_P
Signal Trace Isolation Resistor Length CPU_DP1_CTRL_DATA CC9 GPP_E18/DPPB_CTRLCLK/CNV_BT_HOST_WAKE#
55 eDP_HPD_CPU
Width Spacing Value GPP_E19/DPPB_CTRLDATA
CPU_DP2_CTRL_CLK CH4
71,72 DP1_HPD_CPU eDP_RCOMP 20 mils 25 mils 24.9 Ω ±1% Max = 100 mils CPU_DP2_CTRL_DATA CH3 GPP_E20/DPPC_CTRLCLK
GPP_E21/DPPC_CTRLDATA
24 L_BKLT_EN
55 L_BKLT_CTRL CP4
TP401
55 EDP_VDD_EN 1GPP_E23_STRAP CN4 GPP_E22/DPPD_CTRLCLK
TPAD14-OP-GP
GPP_E23/DPPD_CTRLDATA
15 GPP_H17_STRAP CR26
(#543016) DDI Disabling and Termination Guidelines GPP_H17_STRAP CP26 GPP_H16/DDPF_CTRLCLK
GPP_H17/DDPF_CTRLDATA
Port Strap Enable Port Disable Port
WHISKEY-LAKE-GP

C
PU to 3.3 V with 2.2-k C
Port 1 DDPB_CTRLDATA ±5% resistor NC
PU to 3.3 V with 2.2-k
Port 2 DDPC_CTRLDATA ±5% resistor NC

3D3V_S0

SIO_EXT_SMI# 1 R402 2

10KR2J-3-GP
RTC Gen 9 reset circuit_20170814
DP1_HPD_CPU_R R404 1 2 0R2J-L-GP DP1_HPD_CPU
Add RTC Gen 9 reset circuit_20170814
leakage issue NON_RTC_RST

2
3D3V_S5_PCH 3D3V_S5_PCH R403 DP for Type-C Mux
100KR2J-1-GP

1
1
1
R405
R406
RTC_RST10KR2J-3-GP RTC_RST10KR2J-3-GP
RO13_20171011

2
2
Q401
1 6 DP1_HPD_CPU_R

Note:ZZ.27002.F7C01
2 5 DP1_HPD_CPU

CPU_DP_HPD_P 3 4

2
R407
common part DY
2N7002KDW-1-GP 100KR2J-1-GP
75.27002.F7C
B B

1
RTC_RST

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
CPU_(JTAG/CPU SIDE BAND)
Size Document Number Rev
A2 X00
Kyloren MLK 15" WHL
Date: Friday, July 13, 2018 Sheet 4 of 106
5 4 3 2 1
 5 4 3 2 1

Main Func = CPU

M_B_DQ0
M_B_DQ1
13
13
M_A_DQ0
M_A_DQ1
12
12
DDR4 ball type: Interleaved Type
M_B_DQ2 13 M_A_DQ2 12
M_B_DQ3 13 M_A_DQ3 12
M_B_DQ4 13 M_A_DQ4 12
M_B_DQ5 13 M_A_DQ5 12
M_B_DQ6 13 M_A_DQ6 12
M_B_DQ7 13 M_A_DQ7 12
M_B_DQ8 13 M_A_DQ8 12
M_B_DQ9 13 M_A_DQ9 12
M_B_DQ10 13 M_A_DQ10 12
M_B_DQ11 13 M_A_DQ11 12
M_B_DQ12 13 M_A_DQ12 12
M_B_DQ13 13 M_A_DQ13 12
M_B_DQ14 13 M_A_DQ14 12
D M_B_DQ15 13 CPU1B 2 OF 20 D
M_A_DQ15 12
M_B_DQ32 13 CPU1C 3 OF 20
M_A_DQ32 12 M_A_DQ0 M_A_CLK#0 M_B_DQ0 M_B_CLK#0
M_B_DQ33 13 A26 V32 J22 AF28
M_A_DQ33 12 M_A_DQ1 DDR0_DQ0/DDR0_DQ0 DDR0_CKN0/DDR0_CKN0 M_A_CLK0 M_B_DQ1 DDR1_DQ0/DDR0_DQ16 DDR1_CKN0/DDR1_CKN0 M_B_CLK0
M_B_DQ34 13 D26 V31 H25 AF29
M_A_DQ34 12 M_A_DQ2 DDR0_DQ1/DDR0_DQ1 DDR0_CKP0/DDR0_CKP0 M_A_CLK#1 M_B_DQ2 DDR1_DQ1/DDR0_DQ17 DDR1_CKP0/DDR1_CKP0 M_B_CLK#1
M_B_DQ35 13 D28 T32 G22 AE28
M_A_DQ35 12 M_A_DQ3 DDR0_DQ2/DDR0_DQ2 DDR0_CKN1/DDR0_CKN1 M_A_CLK1 M_B_DQ3 DDR1_DQ2/DDR0_DQ18 DDR1_CKN1/DDR1_CKN1 M_B_CLK1
M_B_DQ36 13 C28 T31 H22 AE29
M_A_DQ36 12 M_A_DQ4 B26 DDR0_DQ3/DDR0_DQ3 DDR0_CKP1/DDR0_CKP1 M_B_DQ4 F25 DDR1_DQ3/DDR0_DQ19 DDR1_CKP1/DDR1_CKP1
M_B_DQ37 13 M_A_DQ37 12 M_A_DQ[0:7] M_A_DQ5 DDR0_DQ4/DDR0_DQ4 M_A_CKE0
M_B_DQ[0:7] M_B_DQ5 DDR1_DQ4/DDR0_DQ20 M_B_CKE0
M_B_DQ38 13 C26 U36 J25 T28
M_A_DQ38 12 M_A_DQ6 DDR0_DQ5/DDR0_DQ5 DDR0_CKE0/DDR0_CKE0 M_A_CKE1 M_B_DQ6 DDR1_DQ5/DDR0_DQ21 DDR1_CKE0/DDR1_CKE0 M_B_CKE1
M_B_DQ39 13 B28 U37 G25 T29
M_A_DQ39 12 M_A_DQ7 DDR0_DQ6/DDR0_DQ6 DDR0_CKE1/DDR0_CKE1 M_B_DQ7 DDR1_DQ6/DDR0_DQ22 DDR1_CKE1/DDR1_CKE1
M_B_DQ40 13 A28 U34 F22 V28
M_A_DQ40 12 M_A_DQ8 DDR0_DQ7/DDR0_DQ7 DDR0_CKE2/NC M_B_DQ8 DDR1_DQ7/DDR0_DQ23 DDR1_CKE2/NC
M_B_DQ41 13 B30 U35 D22 V29
M_A_DQ41 12 M_A_DQ9 DDR0_DQ8/DDR0_DQ8 DDR0_CKE3/NC M_B_DQ9 DDR1_DQ8/DDR0_DQ24 DDR1_CKE3/NC
M_B_DQ42 13 D30 C22
M_A_DQ42 12 M_A_DQ10 DDR0_DQ9/DDR0_DQ9 M_A_CS#0 M_B_DQ10 DDR1_DQ9/DDR0_DQ25 M_B_CS#0
M_B_DQ43 13 B33 AE32 C24 AL37
M_A_DQ43 12 M_A_DQ11 DDR0_DQ10/DDR0_DQ10 DDR0_CS#0/DDR0_CS#0 M_A_CS#1 M_B_DQ11 DDR1_DQ10/DDR0_DQ26 DDR1_CS#0/DDR1_CS#0 M_B_CS#1
M_B_DQ44 13 D32 AF32 D24 AL35
M_A_DQ44 12 M_A_DQ12 DDR0_DQ11/DDR0_DQ11 DDR0_CS#1/DDR0_CS#1 M_A_DIMA_ODT0 M_B_DQ12 DDR1_DQ11/DDR0_DQ27 DDR1_CS#1/DDR1_CS#1 M_B_DIMB_ODT0
M_B_DQ45 13 M_A_DQ[8:15] A30 AE31 M_B_DQ[8:15] A22 AL36
M_A_DQ45 12 M_A_DQ13 DDR0_DQ12/DDR0_DQ12 DDR0_ODT0/DDR0_ODT0 M_A_DIMA_ODT1 M_B_DQ13 DDR1_DQ12/DDR0_DQ28 DDR1_ODT0/DDR1_ODT0 M_B_DIMB_ODT1
M_B_DQ46 13 C30 AF31 B22 AL34
M_A_DQ46 12 M_A_DQ14 DDR0_DQ13/DDR0_DQ13 NC/DDR0_ODT1 M_B_DQ14 DDR1_DQ13/DDR0_DQ29 NC/DDR1_ODT1 M_B_A0
M_B_DQ47 13 B32 A24 AG36
M_A_DQ47 12 M_A_DQ15 DDR0_DQ14/DDR0_DQ14 M_A_A0 M_B_DQ15 DDR1_DQ14/DDR0_DQ30 DDR1_CAB9/DDR1_MA0 M_B_A1
M_B_DQ16 13 C32 AC37 B24 AG35
M_A_DQ16 12 M_A_DQ16 DDR0_DQ15/DDR0_DQ15 DDR0_CAB9/DDR0_MA0 M_A_A1 M_B_DQ16 DDR1_DQ15/DDR0_DQ31 DDR1_CAB8/DDR1_MA1 M_B_A2
M_B_DQ17 13 H37 AC36 G31 AF34
M_A_DQ17 12 M_A_DQ17 DDR0_DQ16/DDR0_DQ32DDR0_DQ[16]
DDR0_CAB8/DDR0_MA1 M_A_A2 M_B_DQ17 DDR1_DQ16/DDR0_DQ48 DDR1_CAB5/DDR1_MA2 M_B_A3
M_B_DQ18 13 H34 AC34 G32 AG37
M_A_DQ18 12 M_A_DQ18 DDR0_DQ17/DDR0_DQ33DDR0_DQ[17]
DDR0_CAB5/DDR0_MA2 M_A_A3 M_B_DQ18 DDR1_DQ17/DDR0_DQ49 NC/DDR1_MA3 M_B_A4
M_B_DQ19 13 K34 AC35 H29 AE35
M_A_DQ19 12 M_A_DQ19 K35 DDR0_DQ18/DDR0_DQ34 DDR0_DQ[18] NC/DDR0_MA3 AA35 M_A_A4 M_B_DQ19 H28 DDR1_DQ18/DDR0_DQ50 NC/DDR1_MA4 AF35 M_B_A5
M_B_DQ20 13 M_A_DQ20 12 DDR0_DQ19/DDR0_DQ35 DDR0_DQ[19] NC/DDR0_MA4 DDR1_DQ19/DDR0_DQ51 DDR1_CAA0/DDR1_MA5
M_A_DQ[16:23] M_A_DQ20 H36 AB35 M_A_A5 M_B_DQ[16:23] M_B_DQ20 G28 AE37 M_B_A6
M_B_DQ21 13 M_A_DQ21 12 DDR0_DQ20/DDR0_DQ36 DDR0_DQ[20]
DDR0_CAA0/DDR0_MA5 DDR1_DQ20/DDR0_DQ52 DDR1_CAA2/DDR1_MA6
M_A_DQ21 H35 AA37 M_A_A6 M_B_DQ21 G29 AC29 M_B_A7
M_B_DQ22 13 M_A_DQ22 12 DDR0_DQ21/DDR0_DQ37 DDR0_DQ[21]
DDR0_CAA2/DDR0_MA6 DDR1_DQ21/DDR0_DQ53 DDR1_CAA4/DDR1_MA7
M_A_DQ22 K36 AA36 M_A_A7 M_B_DQ22 H31 AE36 M_B_A8
M_B_DQ23 13 M_A_DQ23 12 DDR0_DQ22/DDR0_DQ38 DDR0_DQ[22]
DDR0_CAA4/DDR0_MA7 DDR1_DQ22/DDR0_DQ54 DDR1_CAA3/DDR1_MA8
M_A_DQ23 K37 AB34 M_A_A8 M_B_DQ23 H32 AB29 M_B_A9
M_B_DQ24 13 M_A_DQ24 12 DDR0_DQ23/DDR0_DQ39 DDR0_DQ[23]
DDR0_CAA3/DDR0_MA8 DDR1_DQ23/DDR0_DQ55 DDR1_CAA1/DDR1_MA9
M_A_DQ24 N36 W36 M_A_A9 M_B_DQ24 L31 AG34 M_B_A10
M_B_DQ25 13 M_A_DQ25 12 DDR0_DQ24/DDR0_DQ40 DDR0_CAA1/DDR0_MA9 DDR1_DQ24/DDR0_DQ56 DDR1_CAB7/DDR1_MA10
M_A_DQ25 N34 Y31 M_A_A10 M_B_DQ25 L32 AC28 M_B_A11
M_B_DQ26 13 M_A_DQ26 12 DDR0_DQ25/DDR0_DQ41 DDR0_CAB7/DDR0_MA10 DDR1_DQ25/DDR0_DQ57 DDR1_CAA7/DDR1_MA11
M_A_DQ26 R37 W34 M_A_A11 M_B_DQ26 N29 AB28 M_B_A12
M_B_DQ27 13 M_A_DQ27 12 DDR0_DQ26/DDR0_DQ42 DDR0_CAA7/DDR0_MA11 DDR1_DQ26/DDR0_DQ58 DDR1_CAA6/DDR1_MA12
M_A_DQ27 R34 AA34 M_A_A12 M_B_DQ27 N28 AK35 M_B_A13
M_B_DQ28 13 M_A_DQ28 12 DDR0_DQ27/DDR0_DQ43 DDR0_CAA6/DDR0_MA12 DDR1_DQ27/DDR0_DQ59 DDR1_CAB0/DDR1_MA13
M_A_DQ28 N37 AC32 M_A_A13 M_B_DQ28 L28
M_B_DQ29 13 M_A_DQ29 12 M_A_DQ[24:31] M_A_DQ29 DDR0_DQ28/DDR0_DQ44 DDR0_CAB0/DDR0_MA13 M_B_DQ[24:31] M_B_DQ29 DDR1_DQ28/DDR0_DQ60 M_B_A14
M_B_DQ30 13 N35 L29 AJ35
M_A_DQ30 12 M_A_DQ30 DDR0_DQ29/DDR0_DQ45 M_A_A14 M_B_DQ30 DDR1_DQ29/DDR0_DQ61 DDR1_CAB2/DDR1_MA14 M_B_A15
M_B_DQ31 13 R36 AC31 N31 AK34
M_A_DQ31 12 M_A_DQ31 DDR0_DQ30/DDR0_DQ46 DDR0_CAB2/DDR0_MA14 M_A_A15 M_B_DQ31 DDR1_DQ30/DDR0_DQ62 DDR1_CAB1/DDR1_MA15 M_B_A16
M_B_DQ48 13 R35 AB32 N32 AJ34
M_A_DQ48 12 M_A_DQ32 DDR0_DQ31/DDR0_DQ47 DDR0_CAB1/DDR0_MA15 M_A_A16 M_B_DQ32 DDR1_DQ31/DDR0_DQ63 DDR1_CAB3/DDR1_MA16
M_B_DQ49 13 AN35 Y32 AJ29
M_A_DQ49 12 M_A_DQ33 DDR0_DQ32/DDR1_DQ0 DDR0_CAB3/DDR0_MA16 M_B_DQ33 DDR1_DQ32/DDR1_DQ16 M_B_BA0
M_B_DQ50 13 AN34 AJ30 AJ37
M_A_DQ50 12 M_A_DQ34 DDR0_DQ33/DDR1_DQ1 M_A_BA0 M_B_DQ34 DDR1_DQ33/DDR1_DQ17 DDR1_CAB4/DDR1_BA0 M_B_BA1
M_B_DQ51 13 AR35 W32 AM32 AJ36
M_A_DQ51 12 M_A_DQ35 DDR0_DQ34/DDR1_DQ2 DDR0_CAB4/DDR0_BA0 M_A_BA1 M_B_DQ35 DDR1_DQ34/DDR1_DQ18 DDR1_CAB6/DDR1_BA1 M_B_BG0
M_B_DQ52 13 AR34 AB31 AM31 W29
M_A_DQ52 12 M_A_DQ36 DDR0_DQ35/DDR1_DQ3 DDR0_CAB6/DDR0_BA1 M_A_BG0 M_B_DQ36 DDR1_DQ35/DDR1_DQ19 DDR1_CAA5/DDR1_BG0
M_B_DQ53 13 M_A_DQ[32:39] AN37 V34 M_B_DQ[32:39] AM30
M_A_DQ53 12 M_A_DQ37 DDR0_DQ36/DDR1_DQ4 DDR0_CAA5/DDR0_BG0 M_B_DQ37 DDR1_DQ36/DDR1_DQ20 M_B_BG1
M_B_DQ54 13 AN36 AM29 Y28
M_A_DQ54 12 M_A_DQ38 DDR0_DQ37/DDR1_DQ5 M_A_ACT_N M_B_DQ38 DDR1_DQ37/DDR1_DQ21 DDR1_CAA9/DDR1_BG1 M_B_ACT_N
M_B_DQ55 13 AR36 V35 AJ31 W28
M_A_DQ55 12 M_A_DQ39 DDR0_DQ38/DDR1_DQ6 DDR0_CAA8/DDR0_ACT# M_A_BG1 M_B_DQ39 DDR1_DQ38/DDR1_DQ22 DDR1_CAA8/DDR1_ACT#
C M_B_DQ56 13 AR37 W35 AJ32 C
M_A_DQ56 12 M_A_DQ40 DDR0_DQ39/DDR1_DQ7 DDR0_CAA9/DDR0_BG1 M_B_DQ40 DDR1_DQ39/DDR1_DQ23 M_B_DQS_DN0
M_B_DQ57 13 AU35 AR31 H24
M_A_DQ57 12 M_A_DQ41 DDR0_DQ40/DDR1_DQ8 M_A_DQS_DN0 M_B_DQ41 DDR1_DQ40/DDR1_DQ24 DDR1_DQSN0/DDR0_DQSN2 M_B_DQS_DP0
M_B_DQ58 13 M_A_DQ58 12
AU34
DDR0_DQ41/DDR1_DQ9 DDR0_DQSN0/DDR0_DQSN0
C27 AR32
DDR1_DQ41/DDR1_DQ25 DDR1_DQSP0/DDR0_DQSP2
G24 M_B_DQO
M_B_DQ59 13 M_A_DQ59 12
M_A_DQ42 AW35 D27 M_A_DQS_DP0 M_A_DQO M_B_DQ42 AV30 C23 M_B_DQS_DN1
M_A_DQ43 AW34 DDR0_DQ42/DDR1_DQ10 DDR0_DQSP0/DDR0_DQSP0 D31 M_A_DQS_DN1 M_B_DQ43 AV29 DDR1_DQ42/DDR1_DQ26 DDR1_DQSN1/DDR0_DQSN3 D23 M_B_DQS_DP1 M_B_DQ1
M_B_DQ60 13 M_A_DQ60 12 DDR0_DQ43/DDR1_DQ11 DDR0_DQSN1/DDR0_DQSN1 DDR1_DQ43/DDR1_DQ27 DDR1_DQSP1/DDR0_DQSP3
M_B_DQ61 13 M_A_DQ61 12 M_A_DQ[40:47] M_A_DQ44 AU37 C31 M_A_DQS_DP1 M_A_DQ1 M_B_DQ[40:47] M_B_DQ44 AR30 G30 M_B_DQS_DN2
M_A_DQ45 AU36 DDR0_DQ44/DDR1_DQ12 DDR0_DQSP1/DDR0_DQSP1 J35 M_A_DQS_DN2 M_B_DQ45 AR29 DDR1_DQ44/DDR1_DQ28 DDR1_DQSN2/DDR0_DQSN6 H30 M_B_DQS_DP2 M_B_DQ2
M_B_DQ62 13 M_A_DQ62 12 DDR0_DQ45/DDR1_DQ13 DDR0_DQSN2/DDR0_DQSN4 DDR1_DQ45/DDR1_DQ29 DDR1_DQSP2/DDR0_DQSP6
M_B_DQ63 13 M_A_DQ63 12
M_A_DQ46 AW36 J34 M_A_DQS_DP2 M_A_DQ2 M_B_DQ46 AV32 L30 M_B_DQS_DN3
M_A_DQ47 AW37 DDR0_DQ46/DDR1_DQ14 DDR0_DQSP2/DDR0_DQSP4 P34 M_A_DQS_DN3 M_B_DQ47 AV31 DDR1_DQ46/DDR1_DQ30 DDR1_DQSN3/DDR0_DQSN7 N30 M_B_DQS_DP3 M_B_DQ3
M_A_DQ48 BA35 DDR0_DQ47/DDR1_DQ15 DDR0_DQSN3/DDR0_DQSN5 P35 M_A_DQS_DP3 M_A_DQ3 M_B_DQ48 BA32 DDR1_DQ47/DDR1_DQ31 DDR1_DQSP3/DDR0_DQSP7 AL31 M_B_DQS_DN4
M_A_DQ49 BA34 DDR0_DQ48/DDR1_DQ32 DDR0_DQSP3/DDR0_DQSP5 AP35 M_A_DQS_DN4 M_B_DQ49 BA31 DDR1_DQ48/DDR1_DQ48 DDR1_DQSN4/DDR1_DQSN2 AL30 M_B_DQS_DP4 M_B_DQ4
M_A_DQ50 BC35 DDR0_DQ49/DDR1_DQ33 DDR0_DQSN4/DDR1_DQSN0 AP34 M_A_DQS_DP4 M_A_DQ4 M_B_DQ50 BD31 DDR1_DQ49/DDR1_DQ49 DDR1_DQSP4/DDR1_DQSP2 AU31 M_B_DQS_DN5 1D2V_S3
M_B_CLK#0 13 M_A_CLK#0 12 M_A_DQ51 DDR0_DQ50/DDR1_DQ34 DDR0_DQSP4/DDR1_DQSP0 M_A_DQS_DN5 M_B_DQ51 DDR1_DQ50/DDR1_DQ50 DDR1_DQSN5/DDR1_DQSN3 M_B_DQS_DP5
M_B_CLK#1 13 M_A_CLK0 12
BC34
DDR0_DQ51/DDR1_DQ35 DDR0_DQSN5/DDR1_DQSN1
AV34 BD32
DDR1_DQ51/DDR1_DQ51 DDR1_DQSP5/DDR1_DQSP3
AU30 M_B_DQ5
M_A_DQ[48:55] M_A_DQ52 BA37 AV35 M_A_DQS_DP5 M_A_DQ5 M_B_DQ[48:55] M_B_DQ52 BA30 BC31 M_B_DQS_DN6
M_B_CLK0 13 M_A_CLK#1 12 DDR0_DQ52/DDR1_DQ36 DDR0_DQSP5/DDR1_DQSP1 DDR1_DQ52/DDR1_DQ52 DDR1_DQSN6/DDR1_DQSN6

1
M_A_DQ53 BA36 BB35 M_A_DQS_DN6 M_B_DQ53 BA29 BC30 M_B_DQS_DP6 M_B_DQ6
M_B_CLK1 13 M_A_CLK1 12 M_A_DQ54 BC36 DDR0_DQ53/DDR1_DQ37 DDR0_DQSN6/DDR1_DQSN4 BB34 M_A_DQS_DP6 M_A_DQ6 M_B_DQ54 BD29 DDR1_DQ53/DDR1_DQ53 DDR1_DQSP6/DDR1_DQSP6 BH31 M_B_DQS_DN7 R505
M_A_DQ55 BC37 DDR0_DQ54/DDR1_DQ38 DDR0_DQSP6/DDR1_DQSP4 BF34 M_A_DQS_DN7 M_B_DQ55 BD30 DDR1_DQ54/DDR1_DQ54 DDR1_DQSN7/DDR1_DQSN7 BH30 M_B_DQS_DP7 M_B_DQ7 470R2F-GP
M_B_CKE0 13 M_A_CKE0 12 M_A_DQ56 BE35 DDR0_DQ55/DDR1_DQ39 DDR0_DQSN7/DDR1_DQSN5 BF35 M_A_DQS_DP7 M_A_DQ7 M_B_DQ56 BG31 DDR1_DQ55/DDR1_DQ55 DDR1_DQSP7/DDR1_DQSP7
M_B_CKE1 13 M_A_CKE1 12 M_A_DQ57 BE34 DDR0_DQ56/DDR1_DQ40 DDR0_DQSP7/DDR1_DQSP5 M_B_DQ57 BG32 DDR1_DQ56/DDR1_DQ56 Y29 M_B_ALERT_N

2
M_A_DQ58 BG35 DDR0_DQ57/DDR1_DQ41 W37 M_A_ALERT_N M_B_DQ58 BK32 DDR1_DQ57/DDR1_DQ57 NC/DDR1_ALERT# AE34 M_B_PARITY R504
M_B_CS#0 13 M_A_CS#0 12 M_A_DQ59 BG34 DDR0_DQ58/DDR1_DQ42 NC/DDR0_ALERT# W31 M_A_PARITY M_B_DQ59 BK31 DDR1_DQ58/DDR1_DQ58 NC/DDR1_PAR BU31 SM_DRAMRST# 1 2 DDR4_DRAMRST#
M_B_CS#1 13 M_A_CS#1 12 M_A_DQ60 BE37 DDR0_DQ59/DDR1_DQ43 NC/DDR0_PAR F36 V_SM_VREF_CNTA M_B_DQ60 BG29 DDR1_DQ59/DDR1_DQ59 DRAM_RESET#
M_B_DIMB_ODT0 13 M_A_DIMA_ODT0 12 M_A_DQ[56:63] M_A_DQ61 DDR0_DQ60/DDR1_DQ44 DDR_VREF_CA M_B_DQ[56:63] M_B_DQ61 DDR1_DQ60/DDR1_DQ60 SM_RCOMP_0
0R0402-PAD
BE36 D35 BG30 BN28 1 R501 2 121R2F-GP
M_B_DIMB_ODT1 13 M_A_DIMA_ODT1 12 M_A_DQ62 BG36 DDR0_DQ61/DDR1_DQ45 DDR0_VREF_DQ0 D37 M_B_DQ62 BK30 DDR1_DQ61/DDR1_DQ61 DDR_RCOMP0 BN27 SM_RCOMP_1 1 R502 2 80D6R2F-L-GP
M_A_DQ63 BG37 DDR0_DQ62/DDR1_DQ46 DDR0_VREF_DQ1 E36 V_SM_VREF_CNTB M_B_DQ63 BK29 DDR1_DQ62/DDR1_DQ62 DDR_RCOMP1 BN29 SM_RCOMP_2 1 R503 2 100R2F-L1-GP-U
M_B_A5 13 M_A_A5 12 DDR0_DQ63/DDR1_DQ47 DDR1_VREF_DQ DDR1_DQ63/DDR1_DQ63 DDR_RCOMP2
C35 SM_PGCNTL
M_B_A9 13 M_A_A9 12 DDR_VTT_CTL
M_B_A6 13 M_A_A6 12
M_B_A8 13 M_A_A8 12 WHISKEY-LAKE-GP #543016

1
M_B_A7 13 M_A_A7 12 WHISKEY-LAKE-GP
M_B_BG0 13 M_A_BG0 12 ED502
3D3V_S5 PESD5V0U2BT-215-GP
M_B_A12 13 M_A_A12 12
M_B_A11 13 M_A_A11 12
M_B_ACT_N 13 M_A_ACT_N 12 075.52215.007D
Design Guideline:
M_B_BG1 13 M_A_BG1 12
SM_RCOMP keep routing length less than 500 mils. Layout Note: 2nd=75.05125.07D
M_B_A13 13 M_A_A13 12 DQ Bit Swapping is allowed within the same byte, and Byte Swapping is allowed within the same channel.

3
1
M_B_A15 13 M_A_A15 12 Clock (CLK and CLK#) and Strobe (DQS and DQS#) differential signal swapping within a pair is not allowed. Also differential
M_B_A14 13 M_A_A14 12 clock pair to clock pair swapping within a channel is not allowed. R507 close to CPU
10KR2J-3-GP 3D3V_S0
M_B_A16 13 M_A_A16 12
M_B_BA0 13 M_A_BA0 12
M_B_A2 13 M_A_A2 12

2
B B
M_B_BA1 13 M_A_BA1 12

1
M_B_A10 13 M_A_A10 12 Q501
M_B_A1 13 M_A_A1 12 Q502 R506
SM_PGCNTL G 2N7002K-2-GP 220KR2F-GP
M_B_A0
M_B_A3
M_B_A4
13
13
13
M_A_A0
M_A_A3
M_A_A4
12
12
12
PDG: DDR/ODT D Q502_G G

2
S D SM_PGCNTL_R
M_B_ALERT_N 13 M_A_ALERT_N 12
M_B_PARITY 13 M_A_PARITY 12 PJA138KA-GP S
DDR4_DRAMRST# 12,13 V_SM_VREF_CNTA 12 084.00138.0A31 Notice:ZZ.2N702.J3101

SM_PGCNTL_R 51 V_SM_VREF_CNTB 13
2nd = 84.05067.031
84.2N702.J31

M_A_DQS_DN[7:0] 12
M_A_DQS_DN0
M_A_DQS_DN1
M_A_DQS_DN2
M_A_DQS_DN3
M_A_DQS_DN4
M_A_DQS_DN5
M_A_DQS_DN6
M_A_DQS_DN7

M_A_DQS_DP0 M_A_DQS_DP[7:0] 12
M_A_DQS_DP1
M_A_DQS_DP2
M_A_DQS_DP3
M_A_DQS_DP4
M_A_DQS_DP5
M_A_DQS_DP6
M_A_DQS_DP7

A A
M_B_DQS_DN0 M_B_DQS_DN[7:0] 13
M_B_DQS_DN1
M_B_DQS_DN2
M_B_DQS_DN3
M_B_DQS_DN4
M_B_DQS_DN5 <Core Design>
M_B_DQS_DN6
M_B_DQS_DN7
Wistron Corporation
M_B_DQS_DP[7:0] 13 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
M_B_DQS_DP0 Taipei Hsien 221, Taiwan, R.O.C.
M_B_DQS_DP1
M_B_DQS_DP2
Title
M_B_DQS_DP3
M_B_DQS_DP4
M_B_DQS_DP5
CPU_(DDR)
Size Document Number Rev
M_B_DQS_DP6
M_B_DQS_DP7
Custom Kyloren MLK 15" WHL X00
Date: Friday, July 13, 2018 Sheet 5 of 106
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