WDM/OTN Clock

Synchronization Solution
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 Foreword
⚫ The chapter describes:
 Why clock synchronization is required on a WDM network
 Clock synchronization requirements of service networks
 Frequency synchronization and phase synchronization
 E2E WDM/OTN network clock solutions: physical clock, IEEE 1588v2, and ITU-T
G.8275.1/8273.2

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 Objectives
⚫ Upon completion of this course, you will be able to:
 Understand the clock synchronization solutions for WDM/OTN networks.

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 Contents
1. Why Does the WDM/OTN Network Need Clock Synchronization?

2. Clock Synchronization Requirements of Service Networks

3. Frequency Synchronization Solution

4. Phase Synchronization Solution

5. E2E WDM/OTN Network Clock Solution

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Why Does WDM Network Need Clock Synchronization?
⚫ The WDM/OTN network itself does not need to implement clock synchronization.
 The mobile backhaul network requires the WDM/OTN network to implement clock synchronization.
◼ In a mobile backhaul network, clock synchronization must be strictly implemented between base stations. To
provide a synchronous clock source for mobile base stations, the entire WDM/OTN transport network must
support clock synchronization.

 SDH modernization requires the WDM/OTN network to implement clock synchronization.

◼ When a WDM/OTN network is used to replace the SDH network, SDH services are directly processed as a
part of the SDH network. Therefore, the WDM/OTN network must support clock synchronization.

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Architecture of WDM/OTN Clock Sync Network
⚫ A complete clock synchronous
network consists of clock sources,
transport network, and base
stations. Huawei WDM/OTN
devices are located in the transport
network.

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 Contents
1. Why Does the WDM/OTN Network Need Clock Synchronization?

2. Clock Synchronization Requirements of Service Networks

3. Frequency Synchronization Solution

4. Phase Synchronization Solution

5. E2E WDM/OTN Network Clock Solution

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Clock Synchronization Requirements of Service Networks
⚫ Clock synchronization includes both frequency synchronization and phase synchronization. Frequency
synchronization is the basis of phase synchronization. That is, the frequencies of devices with
synchronized phases are also synchronized.

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Clock Synchronization Requirements of Service Networks
(Continued)
⚫ Clock synchronization requirements of mobile communication networks
Required Frequency Required Phase Synchronization
Wireless Access Mode Recommended Synchronization Mode of the Transport Network
Synchronization Precision Precision
Phase synchronization is not
GSM 0.05 ppm Physical clocks
required.
Phase synchronization is not
WCDMA 0.05 ppm Physical clocks
required.

TD-SCDMA 0.05 ppm ±1.5 µs Physical clocks + IEEE 1588v2/ITU-T G.8275.1/G.8273.2

CDMA2000 0.05 ppm ±3 µs Physical clocks + IEEE 1588v2/ITU-T G.8275.1/G.8273.2

Phase synchronization is not

WiMax FDD 0.05 ppm Physical clocks
required.

WiMax TDD 0.011 ppm/3.5G, 7 carriers ±1 µs Physical clocks + IEEE 1588v2/ITU-T G.8275.1/G.8273.2

Phase synchronization is not

LTE FDD 0.05 ppm Physical clocks
required.

LTE TDD 0.05 ppm ±1.5 µs Physical clocks + IEEE 1588v2/ITU-T G.8275.1/G.8273.2

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Clock Synchronization Requirements of Service Networks
(Continued)
⚫ Phase synchronization requirements of other common systems

System Required Time Synchronization Precision Recommended Synchronization Mode of the Transport
Network

Billing system 500 ms IEEE 1588v2/ITU-T G.8275.1/G.8273.2

Communication network management

500 ms IEEE 1588v2/ITU-T G.8275.1/G.8273.2
system

Signaling system No. 7 1 ms IEEE 1588v2/ITU-T G.8275.1/G.8273.2

1 µs (equivalent to a positioning precision of

Positioning system IEEE 1588v2/ITU-T G.8275.1/G.8273.2
300 m)

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 Q&A
(True/False) Frequency synchronization is the basis of phase synchronization.
That is, the frequencies of devices with synchronized phases must also be
synchronized.

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 Q&A
1. (Single-answer question) Which of the following networks has
requirements on phase synchronization precision?
A. GSM

B. WCDMA

C. LTE-FDD

D. LTE-TDD

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 Contents
1. Why Does the WDM/OTN Network Need Clock Synchronization?

2. Clock Synchronization Requirements of Service Networks

3. Frequency Synchronization Solution

4. Phase Synchronization Solution

5. E2E WDM/OTN Network Clock Solution

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Frequency Synchronization Solution
⚫ WDM/OTN devices support the following frequency synchronization solutions:
 (Recommended) Physical clock synchronization:
◼ The device directly recovers clock frequencies from physical signals. The device hardware, however, must
support clock extraction. Therefore, each node must support physical clocks to implement frequency
synchronization on the entire network.
◼ The performance is stable and reliable, and is not subject to network load changes.
◼ The technology is mature, easy to implement, and easy to maintain.
 PTP frequency synchronization:
◼ PTP (IEEE 1588v2 or ITU-T G.8275.1) is used to implement frequency synchronization based on the
timestamps in Sync messages. It is a frequency estimation and correction mode and has a lower
synchronization precision than the physical clock synchronization mode.
◼ In a synchronous network, synchronization is implemented hop by hop, which requires that each node in the
synchronous network must support IEEE 1588v2/ITU-T G.8275.1/G.8273.2.

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Frequency Synchronization Solution (Continued)
⚫ Frequency source input/output:
 (Recommended) 2M external clock port: When the frequency source needs to be obtained from the BITS or the
clocks of the master and slave subracks need to be cascaded, the frequency source can be obtained through the
2M external clock port.
 Ethernet port: When the WDM/OTN devices are interconnected with PTN devices, SDH devices, or routers, you
are advised to obtain the frequency source from the Ethernet port.

⚫ Internal frequency synchronization of a WDM/OTN network

 (Recommended) OSC mode: The optical supervisory channel (OSC) board is used to transmit frequency
information.
 ESC mode: The OTU board, tributary/line board, or packet service board is used to transmit frequency
information.

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Frequency Synchronization Solution (Continued)
⚫ Networking of a typical physical clock scenario

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 Contents
1. Why Does the WDM/OTN Network Need Clock Synchronization?

2. Clock Synchronization Requirements of Service Networks

3. Frequency Synchronization Solution

4. Phase Synchronization Solution

5. E2E WDM/OTN Network Clock Solution

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Phase Synchronization Solution
⚫ Phase synchronization solutions supported by WDM devices
Solution Description
(Recommended) Physical clock frequency
The synchronization precision is high, and the bandwidth usage is low.
synchronization + IEEE 1588v2 phase synchronization
This solution features easy deployment and simple O&M. Compared with
physical clock frequency synchronization + IEEE 1588v2 phase synchronization,
IEEE 1588v2 frequency and phase synchronization
this solution provides lower synchronization precision but requires higher
bandwidth usage.
This solution applies only to the telecommunication field. Compared with
physical clock frequency synchronization + IEEE 1588v2 phase synchronization,
Physical clock frequency synchronization + ITU-T
this solution uses the BMCA algorithm to trace the Grand Master clock on the
G.8275.1 phase synchronization
shortest path, which ensures higher synchronization precision and prevents
reverse tracing.
ITU-T G.8275.1 for frequency synchronization and
The BMCA algorithm is used to prevent reverse tracing.
phase synchronization

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Phase Synchronization Solution
⚫ Phase source input/output
 (Recommended) 1PPS+TOD external time port: When the phase source needs to be obtained from
the BITS or the master and slave time subracks need to be cascaded, the 1PPS+TOD external time
port can be used to obtain the phase source.
 Ethernet port: When the WDM/OTN devices are interconnected with PTN devices, SDH devices, or
routers, you are advised to obtain the phase source from the Ethernet port.

⚫ Internal phase synchronization of the WDM/OTN network

 (Recommended) OSC mode: The OSC board is used to transmit phase information.
 ESC mode: The OTU board, tributary/line board, or packet service board is used to transmit phase
information.

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Phase Synchronization Solution
⚫ Networking of a typical phase synchronization scenario

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 Q&A
(True/False) PTP frequency synchronization has a higher precision than
physical-layer synchronization, and is recommended for WDM/OTN devices.

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 Q&A
1. (Multi-answer question) Which of the following ports on WDM/OTN
devices can transmit phase synchronization information?
A. 2M external clock port

B. OSC

C. OTN tributary/line port

D. Packet service port

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 Contents
1. Why Does the WDM/OTN Network Need Clock Synchronization?

2. Clock Synchronization Requirements of Service Networks

3. Frequency Synchronization Solution

4. Phase Synchronization Solution

5. E2E WDM/OTN Network Clock Solution

5.1 Physical Clock Synchronization Solution

5.2 IEEE 1588v2 Synchronization Solution

5.3 ITU-T G.8275.1 Synchronization Solution

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E2E WDM/OTN Network Clock Solution
⚫ E2E clock networking diagram

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Physical Clocks
⚫ At the physical layer, clock
reference information is
transported to each control
point with high accuracy based
on the master-slave
relationship between nodes
and the clock synchronization
mechanism.

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Master/Slave Synchronization Mode
⚫ The physical clock synchronization mode supported by WDM/OTN devices is master/slave
synchronization. In master/slave synchronization mode, clocks of various levels are used. Clocks of each
level are synchronized with clocks at higher levels. On a network, clocks of the highest level are referred
to as primary reference clocks (PRCs).
⚫ The main advantages of the master/slave synchronization mode are that the network is stable, the
networking is flexible, tree and star networking topologies are applicable, the control is simple, and the
network anti-jitter capability is good. The main disadvantage is that this mode is sensitive to faults of
PRCs and transmission links. Once a PRC is faulty, the entire network is adversely affected. Therefore, a
PRC must have multiple backups to enhance reliability.

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Working Mode of the Slave Clock
⚫ Tracing mode
 It is a normal working mode, indicating that the local clock is synchronized with the PRC. The tracing mode is the
common working mode of transmission network NEs.

⚫ Holdover mode
 After all external timing reference signals are lost, the slave clock node changes to the holdover mode. The slave
clock node uses the latest frequency signals that are saved before the clock loss as the clock reference.

⚫ Free-run mode
 The slave clock node of an NE works in free-run mode when the slave clock node loses all external timing
reference signals and memories or runs in the holdover mode for a long time.

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Clock Protection
⚫ Physical clock synchronization supports selecting and switching a clock source under three SSM protocol modes:
 Non-SSM protocol
◼ When the SSM protocol is disabled, clock signals do not contain clock quality information. Clocks are selected based on the specified clock
source priorities. In this mode, clock loops may occur.
◼ This mode is used on a non-ring network with multiple clock sources. The clock source is selected according to the clock source priority list.
 Standard SSM protocol
◼ When the standard SSM protocol is enabled, clock quality levels are used to prevent clock loops.
◼ This mode is used on a non-ring network with multiple clock sources. The clock signal carries quality information. It is used when the
WDM/OTN device interconnects with a third-party device.
 Extended SSM protocol
◼ When the extended SSM protocol is enabled, clock source IDs are introduced to prevent clock loops.
◼ This protocol is applicable only to a ring network. It is a Huawei proprietary protocol and cannot be used when the WDM/OTN device
interconnects with a third-party device. If the extended SSM protocol is enabled on an NE, the standard SSM protocol can be configured on
the downstream NEs; however, if the standard SSM protocol is enabled on an NE, the extended SSM protocol cannot be configured on the
downstream NEs. It is recommended that the extended SSM protocol be enabled on ring networks.

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Priority Table
⚫ A clock priority table is the basis of clock source
selection and switching when the SSM protocol is
disabled. Each clock source is assigned with a unique
priority. NEs select a clock source with the highest
priority from the priority table as their clock source.

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Standard SSM Protocol
⚫ SSM stands for Synchronous Status Message. Priorities of clocks traced by the NEs on a common WDM/OTN network
can be specified manually to provide clock synchronization and protection. However, in some special OTN networks,
clock loops may be generated if only clock priorities are specified. To prevent clock loops, users need to enable the
standard SSM protocol.
⚫ After the standard SSM protocol is enabled for an NE, automatic clock switching is performed based on the following
principles:
 The NE takes precedence to select a clock source with the highest quality from the specified clock priority table.
 If there are multiple clock sources with the highest quality, then the NE selects the clock source with the highest priority from
them.
 The NE broadcasts the quality level of the selected clock source to the downstream NEs using S1 bytes. Meanwhile, the NE
informs the upstream NEs of its clock quality using other S1 bytes along the reverse synchronization path, telling the upstream
NEs not to synchronize to its clock.

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Extended SSM Protocol
⚫ Huawei has developed the extended SSM protocol by adding clock source IDs to the standard SSM protocol. By using the extended
SSM protocol, users can assign any clock source ID. The clock source ID of a synchronization source is transmitted together with
SSM bytes. The clock IDs and SSM bytes together determine automatic clock switching. A clock source ID identifies whether the
clock is from the local NE. If the clock is from the local NE, the clock source is considered invalid to prevent clock loops.
⚫ After the extended SSM protocol is enabled for an NE, automatic clock switching is performed based on the following principles:
 The NE takes precedence to select a clock source with the highest quality from the specified clock priority table.
 If the ID of a clock source indicates that the clock source is synchronized to the NE's clock, then the NE will not select this clock source to trace.
 If there are multiple clock sources with the highest quality, then the NE selects the clock source with the highest priority from them.
 The NE broadcasts the quality and ID of the selected clock source to the downstream NEs using S1 bytes. Meanwhile, the NE informs the
upstream NEs of its clock quality using other S1 bytes along the reverse synchronization path, telling the upstream NEs not to synchronize to its
clock.

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Clock Source ID
⚫ Set the clock source ID according to the
following principles:
 Allocate a clock source ID to each external BITS
device.
 Allocate a clock source ID to the internal clock
source of each node that has an external BITS
device.
 Allocate a clock source ID to the internal clock
source of each node that enters into another ring
network from one chain or ring network.
 Allocate a clock source ID to the line clock source of
the node that enters into another ring network
from one chain or ring network when the line clock
source exists.

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Clock Source Ports
⚫ WDM/OTN devices support the following types of clock sources:
 External clock source: timing information that is extracted from 2 Mbit/s or 2 MHz signals received at an external clock port.
 OSC clock source: clock information that is extracted from OSC signal streams.
 Line clock source: a clock source that is extracted from WDM-side service signals by boards that support physical clocks on the
WDM/OTN network. System clock sources are transmitting using electrical-layer or optical-layer boards.
 E1 tributary clock source: timing information that is extracted from E1 signal streams.
 Synchronous Ethernet clock source: clock information that is extracted from Ethernet signal streams.
 Clock synchronization GE optical port: clock information that is extracted from Ethernet signal streams.
 Internal clock source: a clock that is generated from free-run oscillation of the built-in clock of an NE. The internal clock source
has the lowest priority among all clock sources.

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Clock Source Port Types
Clock Source Port
Supported Format Port Mode Function
Type
⚫ Receives clock signals from the BITS or other devices that
2.048 MHz or 2.048
have the same port.
Mbit/s signals compliant
External clock port RJ45 or SMB ⚫ Cascades with other devices of the same type at the same
with ITU-T G.703 in a
site.
synchronous system ⚫ Connects to lower-layer PTN/MSTP devices.

Supports clock synchronization with interconnected WDM

OSC clock source OSC dedicated port OSC optical port
devices.

OTUk optical port, STM-N

Supports clock synchronization with interconnected
Line clock source OTUk port, STM-N port optical port/electrical port, SDH
OTN/SDH devices.
virtual port

Ethernet services,
Connects to lower-layer PTN/MSTP devices without
Ethernet service port including GE, 10GE, and Ethernet optical port
restrictions on equipment room sharing and site sharing.
40GE

Used for clock synchronization between NEs or clock

Clock
cascading between master and slave subracks. Only clock
synchronization GE Ethernet frame GE optical port
synchronization and time synchronization are supported.
optical port
Ethernet services cannot be transmitted.

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External Clock Connection Mode
⚫ The external clock port of a subrack supports two
working modes:
 External clock mode
 Cascading clock mode

⚫ External clock input/output

 It is used to interconnect with BITS or other devices. The
output clock can be synchronized with the system clock of
an NE or the line source specified by the NMS. An external
clock input port can participate in clock source selection
only after it is added to the system clock source priority
table.

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External Clock Connection Mode (Continued)
⚫ The external clock port of a subrack supports two
working modes:
 External clock mode
 Cascading clock mode

⚫ Cascading clock input/output

 It is used only for interconnection between multiple subracks
of WDM/OTN products and is always synchronized with the
system clock. When a port works in the clock cascading mode,
the system automatically determines the clock tracing
relationship.

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Clock Synchronization GE Optical Port
⚫ The clock synchronization GE optical port is used for clock synchronization between NEs or clock
cascading between master and slave subracks.

Fiber connections of clock synchronization GE optical ports Fiber connections of clock synchronization GE optical ports (non-
(cascading mode and non-cascading mode) cascading mode, active/standby protection)

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Synchronous Ethernet
⚫ Synchronous Ethernet is an Ethernet physical clock frequency synchronization
technology that directly extracts clock signals from the serial bit streams on Ethernet
lines and transmits the clock signals.

Implementation principles of synchronous Ethernet

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Synchronous Ethernet Processing and Transparent
Transmission
⚫ The support for synchronous Ethernet varies depending on the service encapsulation types supported by
boards. Two implementation modes are available: synchronous Ethernet processing and transparent
transmission.

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Physical Clock Dependencies and Limitations (1/3)
⚫ Networks at the backbone and aggregation layers should be configured with clock protection and be set with the primary and
secondary PRCs for active/standby clock switching. For networks at the access layer, only one PRC is set on the central NE in most
cases, and other NEs trace the clock of the central NE.
⚫ If there is a Building Integrated Timing Supply (BITS) device or another external high-precision clock device on the network, it is
recommended that NEs trace external clock sources. If there is no BITS device or another external high-precision clock device on
the network, it is recommended that NEs trace line clock sources. The internal clock source usually has the lowest priority among
all the clock sources.
⚫ Clock signals need to be compensated after a long clock chain to avoid the drift of clock signals after they are transmitted through
multiple sites. ITU-T G.781 stipulates that clock compensation is required on a long chain consisting of 20 or more NEs. Considering
the transmission distance of fibers, clock compensation is performed in practice on a long chain consisting of more than 10 NEs.
⚫ If a long clock chain contains more than 20 NEs, clock signals need to be output to the BITS through a 2M clock port (CLK port) for
regeneration. Moreover, the regenerated clock signals should be sent back to the NEs and serve as the clock source to be
transmitted to the line side.

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Physical Clock Dependencies and Limitations (2/3)
⚫ If NEs need to trace a line clock source, ensure that the clock tracing path is the shortest:
 On a ring network consisting of fewer than six NEs, the NEs can trace the reference clock source in one direction.
 On a ring network consisting of six or more NEs, ensure that the tracing path is the shortest. That is, on a ring network consisting of N NEs, a half of the NEs trace the
reference clock source in one direction and the other half of the NEs trace the reference clock source in the other direction. (If N is an odd number, the intermediate NE
can trace the reference clock source in either of the directions.)

⚫ If the SSM protocol is disabled, the clock network can be configured to unidirectional only and cannot be configured into rings.
⚫ If the SSM protocol is enabled, the settings of the SSM protocol information for all NEs in the network should be consistent.
⚫ The following principles must be applied if different SSM protocols are enabled:
 If you enable the standard SSM protocol, you can configure the clock network to bidirectional but cannot configure the clock network into rings.
 If you enable the extended SSM protocol, you can configure the clock network to bidirectional or configure the clock network into rings. In this case, however,
intersecting and tangent rings are not permitted.

⚫ The same subnet number must be assigned to NEs that trace the same clock source.

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Physical Clock Dependencies and Limitations (3/3)
⚫ When the clock synchronization function is required by UPS/OSN 6800/OSN 8800/OSN 9800 M/1800 V/1800 V Pro, two clock
boards (either independent clock boards or system boards integrated with the clock function) must be configured to back up each
other.
⚫ When an ST2/AST2 board is configured in an OSN 8800 subrack, only the pass-through of physical clock signals and IEEE 1588v2
signals is supported. The processing of physical clock signals and IEEE 1588v2 signals is not supported.
⚫ When the ST2/AST2 board is used with the STG board in a universal platform subrack, the board can process physical clock signals
and IEEE 1588v2 clock signals.
⚫ When an OLA site is not configured with a clock board, the ST2/AST2 board at the site can transparently transmit physical clock
signals.
⚫ In the master/slave subrack scenario, the main AUX board must be configured on a master subrack.
⚫ For OTN line ports, physical clocks can be used only when lower-order ODUk cross-connections are configured for the ports.
⚫ For the tributary ports that receive Ethernet services, physical clocks can be used only after services are configured for the ports.

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 Q&A
1. (Multi-answer question) Which of the following slave clock working modes
are supported by WDM/OTN devices in the physical clock solution?
A. Tracing mode

B. Holdover mode

C. Listening mode

D. Free-run mode

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 Q&A
2. (True/False) WDM/OTN devices support the standard SSM protocol. Clock
source IDs can be used to prevent clock loops and implement clock
source protection based on priorities.

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 Q&A
3. (Single-answer question) Which of the following is an appropriate
sequence of clock source priorities?
A. Internal clock source > Line clock source > BITS clock source

B. Line clock source > BITS clock source > Internal clock source

C. BITS clock source > Internal clock source > Line clock source

D. BITS clock source > Line clock source > Internal clock source

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 Contents
1. Why Does the WDM/OTN Network Need Clock Synchronization?

2. Clock Synchronization Requirements of Service Networks

3. Frequency Synchronization Solution

4. Phase Synchronization Solution

5. E2E WDM/OTN Network Clock Solution

5.1 Physical Clock Synchronization Solution

5.2 IEEE 1588v2 Synchronization Solution

5.3 ITU-T G.8275.1 Synchronization Solution

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IEEE 1588v2 Synchronization Solution
⚫ IEEE 1588v2 enables precise clock synchronization between distributed and standalone devices in
measurement and control systems through the precision time protocol (PTP). The phase synchronization
precision reaches nanosecond level.

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Master-Slave Clock Hierarchy of IEEE 1588v2
⚫ An IEEE 1588v2 clock transfers the reference time to each control point accurately by building the master-slave relationship
between network nodes, and by using the time synchronization mechanism.
⚫ The best clock in the entire system is the GMC due to its stability, accuracy, and certainty. According to the precision and level of
clocks on each node and the traceability of UTC, the BMC algorithm selects the master clock in each subnet automatically.
⚫ In a PTP clock subnet, the master-slave hierarchy can be established between the OC and BC, between OCs, or between BCs.

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IEEE 1588v2 Clock Architecture
⚫ The clock architecture specified in the IEEE 1588v2 standard classifies NE clocks into three models:
ordinary clock (OC), boundary clock (BC), and transparent clock (TC).

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Clock Subnet and Clock Source ID of IEEE 1588v2
⚫ A clock synchronous network can be divided into independent clock subnets. In each clock subnet, a
clock participating in IEEE 1588v2 clock source selection needs to be assigned a unique identifier, which
is called a clock source ID.
⚫ Clock subnet
 An IEEE 1588v2 clock subnet is a logical set in which clocks are synchronized with each other using the IEEE
1588v2 protocol. A physical packet switched network can be divided into multiple logical clock subnets. The
clocks within a subnet are synchronized with each other. Each clock subnet uses its own synchronization source.
 In an IEEE 1588v2 packet, a clock subnet ID occupies one byte.
⚫ Clock source ID
 A clock source ID identifies a clock in an IEEE 1588v2 clock subnet. In an IEEE 1588v2 packet, a clock source ID
occupies eight bytes.

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Time Source Port
⚫ A synchronous network using the IEEE 1588v2 protocol obtains time signals from the reference time
source grandmaster clock using external time ports.
Time Port Type Supported Format Port Mode Function

⚫ Receives time signals from the BITS or other devices that

have the same port.
External time port 1PPS+TOD RJ45 ⚫ Cascades with other devices of the same type at the same
site.
⚫ Connects to the lower-layer PTN/SDH network.

Ethernet services,
Inband port that runs Connects to the lower-layer PTN/SDH network without
Service time port including GE, 10GE,
with services. equipment room or site sharing restrictions.
and 40GE

Supports time synchronization with interconnected WDM

OSC clock source OSC dedicated port OSC optical port
devices.

Used for time synchronization between NEs or time cascading

Clock synchronization GE between master and slave subracks. Only clock synchronization
Ethernet port GE optical port
optical port and time synchronization are supported. Ethernet services
cannot be transmitted.

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1PPS+TOD Time Signals
⚫ 1PPS+TOD time signals consist of 1PPS signals and TOD time information.
 1PPS
◼ 1PPS is short for one pulse per second. 1PPS signals are used for time scaling and work at the RS-422 levels.
The pulse frequency of 1PPS is 1 Hz. That is, one pulse is transmitted per second. The 1PPS signal pulse width
ranges from 20 ms to 200 ms. On the rising edge of the pulse, UTC time signals are aligned.

 TOD
◼ TOD is short for time of day. TOD messages provide time in ASCII format. TOD signals also work at the RS-422
levels and provide a baud rate of 9600 bit/s. A TOD message contains information such as current date/time,
time standard ID, 1PPS status flag, date/time adjusted based on UTC leap seconds, leap second adjustment
directive, and GPS time.

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BMC Algorithm
⚫ The best master clock (BMC) algorithm can determine the GMC in any network structure and build the master-slave hierarchy. In
addition, the BMC algorithm transfers the master clock and reference time to each node level by level for the best possible clock
precision.
⚫ The BMC algorithm is dynamic. That is, when the BMC algorithm runs in a clock synchronization system, the BMC algorithm
continuously calculates the port status based on the real-time data and then adjusts the status of each node and port dynamically
while also adjusting the route of transmitting the time signals. Hence, when the active master clock is faulty or its performance
deteriorates, the system may select another suitable node to serve as the master clock.
⚫ The BMC algorithm runs on each port of each clock locally. The BMC algorithm specifies the order in which data is compared and
the comparison rules, namely, clock level, clock identifier, clock variable, trail length, and so on. The current status of each port of
each clock can be obtained after the data is compared.
⚫ Static BMC can be set to either Enabled or Disabled to enable or disable the IEEE 1588v2 protocol. When it is set to Enabled, users
can manually configure the port status as master or slave.

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IEEE 1588v2-Compliant Phase Synchronization
⚫ The IEEE 1588v2 protocol is based on the most accurate match time at which synchronous data packets are
propagated and received. Each slave clock is synchronized with the master clock by exchanging the synchronous
packets with the master clock.
The method of calculating the time
difference between the master and
slave clocks and the link delay is as
follows:

t2-t1=Delay-Offset
t4-t3=Delay+Offset

Offset=[(t4-t3)-(t2-t1)]/2
Delay=[(t4-t3)+(t2-t1)]/2
Offset: The time difference
between the master and slave
clocks.
Delay: The delay time caused by
network transmission.

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IEEE 1588v2-Compliant Frequency Synchronization
⚫ IEEE 1588v2-compliant frequency synchronization involves two actions:
frequency gauging and frequency correction. The synchronization precision of
this method is lower than that of frequency synchronization based on physical
clocks.
⚫ Clock A (slave) can correct its clock frequency after comparing the interval
between two message transmitting timestamps with the interval between two
message receiving timestamps. In this manner, clock A synchronizes to clock B
(master). If the changes in the link delay and residence time are negligible, the
clock frequency of clock A can be corrected using the following formula:
(t1[N] - t1[0])/(t2[N] - t2[0])
 If the value of the "t2[N] - t2[0]" is equal to the value of "t1[N] - t1[0]": This means that clock A and
clock B run at the same rate.
 If the value of the "t2[N] - t2[0]" is greater than the value of "t1[N] - t1[0]": This means that clock A
runs faster than clock B and needs to slow down its frequency.
 If the value of the "t2[N] - t2[0]" is less than the value of "t1[N] - t1[0]": This means that clock A runs
slower than clock B and needs to accelerate its frequency.

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Delay Compensation
⚫ Delay compensation for PTP link asymmetry
 The PTP link asymmetry means that the cables for receiving and transmitting PTP messages between two devices have
different lengths. This causes a variation between the cable transmission delays in the receive and transmit directions.
 The IEEE 1588v2 packet delay measurement algorithm is based on the assumption that the PTP link transmission delays in the
receive and transmit directions are the same. If the receive and transmit cables on the PTP link are asymmetric, the computed
delay will differ from the actual transmission delay.
 The PTP asymmetry correction mechanism uses the asymmetric delay variation compensation value to correct the computed
value, thereby achieving accurate time synchronization.
 The delay compensation value for the transmission asymmetry can be obtained according to the length difference between the
cables in the signal receive and signal transmit directions. Alternatively, the value can be obtained according to the
transmission time of a signal on the cables in the receive and transmit directions using a test instrument. The compensation
value takes effect only after it is manually set for the PTP ports.

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Delay Compensation
⚫ Automatic calculation and compensation of ring network delay offset
 After a PTP time synchronization network is commissioned, the length difference between the
transmit and receive fibers on the line may change greatly and the asymmetric delay may change due
to fiber maintenance (such as fiber cut repair and fiber route change) in the O&M phase of the
network. If the compensation value cannot be set correctly, the time synchronization function will be
affected.
 The automatic ring network delay calculation function can be used to automatically calculate the
fiber asymmetry compensation value on time nodes with protection trails, such as on a ring network,
and provide a recommended compensation value. In addition, automatic compensation within the
compensation range is supported, requiring no manual measurement operations.

Copyright © Huawei Technologies Co., Ltd. All rights reserved. Page 56

IEEE 1588v2 Dependencies and Limitations (1/3)
⚫ The central node or the node with high reliability provides the clock source.
⚫ If the BITS or other external clock equipment with high precision exists, use the external timing mode for the NE.
Otherwise, use the line timing mode instead. You are advised to use the internal timing as a clock source of the
lowest level.
⚫ If there are multiple NEs at a core site of a WDM/OTN network, the frequency/phase information can be obtained in
either of the following ways:
 If physical OSC or ESC connections are established between the NEs, the OSC or ESC channels can be used to transmit IEEE
1588v2 frequency and phase information between the NEs.
 ESC two-fiber bidirectional phase synchronization is easily affected by factors such as protection switching and board latency
difference. If the east-west latency difference is too large, phase indicators change and deteriorate. As a result, frequent
network switching occurs and maintenance cannot be performed.
 If the NEs are deployed in the same equipment room and the intervals between them are less than 200 m, the external 2M
clock ports or 1PPS+TOD time ports on the NEs can be used to transmit the frequency and phase information between them.

Copyright © Huawei Technologies Co., Ltd. All rights reserved. Page 58

IEEE 1588v2 Dependencies and Limitations (2/3)
⚫ If both IEEE 1588v2 and intra-board 1+1 protection or optical line protection are configured, single-fiber bidirectional (OSC)
must be used to implement IEEE 1588v2 time synchronization. If IEEE 1588v2 time synchronization is implemented in two-
fiber bidirectional mode (ESC or OSC), fiber asymmetry will occur after a switchover of boards such as OLP, DCP, or OTU,
affecting the time synchronization precision.
⚫ Client 1+1 protection and IEEE 1588v2 are mutually exclusive. If both are configured, IEEE 1588v2 will become abnormal.
⚫ When SFIU boards (including DAPXF boards that function as SFIU boards) are used to configure or reserve the IEEE 1588v2
function, optical-layer ASON is not supported.
⚫ When overhead bytes (2 rows, 3 columns) used for latency measurement are the same as the IEEE 1588v2 overhead bytes
of the OTN interface (2 rows, 3 columns), and these overhead bytes transmit IEEE 1588v2 protocol packets concurrently,
the IEEE 1588v2 transmission will be interrupted during the measurement, adversely affecting services. Therefore, IEEE
1588v2 and latency measurement cannot be enabled at the same time.

Copyright © Huawei Technologies Co., Ltd. All rights reserved. Page 59

IEEE 1588v2 Dependencies and Limitations (3/3)
⚫ When the clock synchronization function is required by UPS/OSN 6800/OSN 8800/OSN 9800 M/1800 V/1800 V Pro, two clock
boards (either independent clock boards or system boards integrated with the clock function) must be configured to back up each
other.
⚫ For OTN line ports, IEEE 1588v2 can be used only when lower-order ODUk cross-connections are configured for the ports.
⚫ For the tributary ports that receive Ethernet services, IEEE 1588v2 can be used only after services are configured for the ports.
⚫ When no clock board is available, the ST2/AST2 board supports IEEE 1588v2 pass-through at OLA sites.
⚫ The ST2/AST2 board must be installed in a subrack with a clock board if the clock function is required.
⚫ When configured in a universal platform subrack and used with the STG board, the ST2/AST2 board supports physical clock
processing and IEEE 1588v2 clock processing.
⚫ The VLAN ID of IEEE 1588v2 packets must be different from the VLAN ID of the inband DCN. If they are the same, IEEE 1588v2
packets cannot be received normally and IEEE 1588v2 clocks cannot be synchronized.

Copyright © Huawei Technologies Co., Ltd. All rights reserved. Page 60

 Q&A
1. (Multi-answer question) In the IEEE 1588v2 clock architecture, which of
the following are the basic modes of NE clocks?
A. OC

B. BC

C. TC

D. SC

Copyright © Huawei Technologies Co., Ltd. All rights reserved. Page 61

 Q&A
2. (Multi-answer question) Which of the following ports can transmit IEEE
1588v2 time synchronization information?
A. 1PPS+TOD external time port

B. Ethernet service ports such as GE/10GE ports

C. OSC port

D. 2M clock port

Copyright © Huawei Technologies Co., Ltd. All rights reserved. Page 62

 Q&A
3. (True/False) The IEEE 1588v2 protocol can achieve only time
synchronization but not frequency synchronization in WDM/OTN
networks.

Copyright © Huawei Technologies Co., Ltd. All rights reserved. Page 63

 Q&A
4. (True/False) The IEEE 1588v2 protocol can detect the mean transmission
delay of two connected PTP ports, but cannot detect the transmission
delay caused by the PTP link asymmetry. Asymmetric delay must be
measured with a test instrument or computed based on the cable
lengths.

Copyright © Huawei Technologies Co., Ltd. All rights reserved. Page 64

 Contents
1. Why Does the WDM/OTN Network Need Clock Synchronization?

2. Clock Synchronization Requirements of Service Networks

3. Frequency Synchronization Solution

4. Phase Synchronization Solution

5. E2E WDM/OTN Network Clock Solution

5.1 Physical Clock Synchronization Solution

5.2 IEEE 1588v2 Synchronization Solution

5.3 ITU-T G.8275.1 Synchronization Solution

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ITU-T G.8275.1
⚫ ITU-T G.8275.1 is a precise time
synchronization telecommunications
standard defined based on the IEEE
1588v2 PTP protocol. Compared with
IEEE 1588v2, ITU-T G.8275.1 features the
following:
 Simplifies NE models and source selection
algorithms, making the standard more
suitable for the telecommunications field.
 Defines packets more specifically,
facilitating interconnection and
interworking.

Copyright © Huawei Technologies Co., Ltd. All rights reserved. Page 66

ITU-T G.8273.2
⚫ IEEE 1588v2 defines only the time synchronization protocol methods, but does not
define the synchronization performance. ITU-T G.8273.2 clearly defines the time
synchronization performance of each single device from the following aspects: time
error, noise tolerance, noise transfer, transient phase response, and holdover.
⚫ WDM devices comply with the ITU-T G.8275.1 and G.8273.2 standards and satisfy the
carrier-level time synchronization precision requirements.

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ITU-T G.8275.1 Synchronization Solution
⚫ ITU-T G.8275.1 implements frequency and phase synchronization through PTP packet exchanges, as
shown in the following figure. The synchronization is implemented hop by hop, which requires that all
devices in the synchronization network must support the ITU-T G.8275.1 function.

Copyright © Huawei Technologies Co., Ltd. All rights reserved. Page 68

Three Clock Types of the ITU-T G.8275.1 System
⚫ The ITU-T G.8275.1 system uses the master/slave clock structure. The highest-priority clock, namely, telecom
grandmaster (T-GM), transmits clock information to terminal devices using the telecom boundary clock (T-BC) and
telecom time slave clock (T-TSC) clocks.

The T-BC clock functions

include the functions of the T-
GM and T-TSC clocks.

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Master-Slave Clock Hierarchy of ITU-T G.8275.1
⚫ In the entire clock system, the optimal clock is the T-GM clock that has the highest priority. The T-GM
clock has the best stability, precision, and certainty. Based on the precision and levels of clocks on each
node and traceability of Coordinated Universal Time (UTC), the best master clock algorithm (BMCA)
automatically selects the master clock on each subnet.
The T-GM clock is located at the root and therefore is called as
T-BC1 T-BC2 the grandmaster clock. Port 1 of T-BC1 functions as the slave
port of the grandmaster clock and marked as S. The other ports
of T-BC1 function as the master ports of the clock device
connected to T-BC1 and therefore are marked as M. Therefore,
port 1 of T-BC2 functions as a slave port of T-BC1.

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BMCA Algorithm
⚫ ITU-T G.8275.1 defines a new type of best master clock algorithm (BMCA), which optimizes the algorithms for
master-slave clock tracing and clock source tracing when compared with the BMCA defined in IEEE 1588v2.
⚫ notSlave attribute:
 This attribute is added to each port to ensure the tracing relationship in the ITU-T G.8275.1 synchronization network and to avoid the situation
that a T-GM traces a T-BC.
 In a network with a large number of devices and links, setting of the notSlave attribute guarantees a tree structure of the master-slave tracing
path from top to down and prevents devices at the aggregation layer from reversely tracing devices at the access layer.

⚫ localPriority attribute: This attribute refers to the local priority and is used to plan the device tracing sources. The
attribute is used only inside local devices and will not be forwarded to other devices through packets. The
localPriority attribute is applicable to the following scenarios:
 In a large-scale network, the entire network traces the same clock source. In this case, the time error may exceed the permitted range on T-BCs
far from the clock source.
 No manual intervention is involved during the source selection of the BMCA. In this case, no effective maintenance method can be taken in case
of a network fault.

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BMCA Networking
⚫ T-BC1 is connected to clock
source T-GM1, T-BC3 is
connected to clock source T-GM2,
and base stations are connected
to the network through T-BC6.
⚫ The BMCA computes the time
tracing topology of the entire
network.

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Delay Compensation
⚫ Delay compensation for PTP link asymmetry
 The PTP link asymmetry means that the cables for receiving and transmitting PTP messages between two devices have
different lengths. This causes a variation between the cable transmission delays in the receive and transmit directions.
 The ITU-T G.8275.1 packet delay measurement algorithm is based on the assumption that the PTP link transmission delays in
the receive and transmit directions are the same. If the receive and transmit cables on the PTP link are asymmetric, the
computed delay will differ from the actual transmission delay.
 The asymmetric delay correction mechanism defined in ITU-T G.8275.1 uses the compensation value of the asymmetric
transmission offset to correct the calculation result, thereby achieving accurate time synchronization.
 The delay compensation value for the transmission asymmetry can be obtained according to the length difference between the
cables in the signal receive and signal transmit directions. Alternatively, the value can be obtained according to the
transmission time of a signal on the cables in the receive and transmit directions using a test instrument. The compensation
value takes effect only after it is manually set for the PTP ports.

Copyright © Huawei Technologies Co., Ltd. All rights reserved. Page 73

ITU-T G.8275.1 Dependencies and Limitations (1/3)
⚫ The central node or the node with high reliability provides the clock source.
⚫ If the BITS or other external clock equipment with high precision exists, use the external timing mode for the NE.
Otherwise, use the line timing mode instead. You are advised to use the internal timing as a clock source of the
lowest level.
⚫ If there are multiple NEs at a core site of a WDM/OTN network, the frequency/phase information can be obtained in
either of the following ways:
 If physical OSC or ESC connections are established between the NEs, the OSC or ESC channels can be used to transmit ITU-T G.8275.1 frequency
and phase information between the NEs.
 ESC two-fiber bidirectional phase synchronization is easily affected by factors such as protection switching and board latency difference. If the
east-west latency difference is too large, phase indicators change and deteriorate. As a result, frequent network switching occurs and
maintenance cannot be performed.
 If the NEs are deployed in the same equipment room and the intervals between them are less than 200 m, the external 2M clock ports or
1PPS+TOD time ports on the NEs can be used to transmit the frequency and phase information between them.

Copyright © Huawei Technologies Co., Ltd. All rights reserved. Page 75

ITU-T G.8275.1 Dependencies and Limitations (2/3)
⚫ If both ITU-T G.8275.1 and intra-board 1+1 protection or optical line protection are configured, ITU-T G.8275.1 time
synchronization can be implemented only in single-fiber bidirectional mode (ST2+SFIU). If ITU-T G.8275.1 time synchronization is
implemented in two-fiber bidirectional mode (ESC or OSC), fiber asymmetry will occur after protection switching on the related
boards such as OLP, DCP, and OTU, affecting the time synchronization precision.
⚫ Client 1+1 protection and ITU-T G.8275.1 are mutually exclusive. If both are configured, ITU-T G.8275.1 will become abnormal.
⚫ When SFIU boards (including DAPXF boards that function as SFIU boards) are used to configure or reserve the ITU-T G.8275.1
function, optical-layer ASON is not supported.
⚫ When overhead bytes (2 rows, 3 columns) used for latency measurement are the same as the ITU-T G.8275.1 overhead bytes of
the OTN interface (2 rows, 3 columns), and these overhead bytes transmit ITU-T G.8275.1 protocol packets concurrently, the ITU-T
G.8275.1 transmission will be interrupted during the measurement, adversely affecting services. Therefore, ITU-T G.8275.1 and
delay measurement cannot be enabled at the same time in this scenario.

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ITU-T G.8275.1 Dependencies and Limitations (3/3)
⚫ When the clock synchronization function is required by UPS/OSN 6800/OSN 8800/OSN 9800 M/1800 V/1800 V Pro, two clock boards (either
independent clock boards or system boards integrated with the clock function) must be configured to back up each other.
⚫ When ITU-T G.8275.1 signals are transmitted between OTN devices, line boards or OSC boards are recommended. When an OTN device is
interconnected with a third-party device to transmit ITU-T G.8275.1 signals, tributary boards are recommended.
⚫ For OTN line ports, G.8275.1 time synchronization can be used only when lower-order ODUk cross-connections are configured for the ports.
⚫ For the tributary ports that receive Ethernet services, G.8275.1 time synchronization can be used only after services are configured for the
ports.
⚫ When no clock board is available, an ST2 board supports ITU-T G.8275.1 signal pass-through at an OLA site.
⚫ When an ST2 board is configured in an OSN 8800 platform subrack, only physical clock pass-through and ITU-T G.8275.1 clock pass-through
are supported. The processing of physical clocks and ITU-T G.8275.1 clocks is not supported.
⚫ When configured in a universal platform subrack, the ST2 board supports physical clock processing and ITU-T G.8275.1 clock processing.

Copyright © Huawei Technologies Co., Ltd. All rights reserved. Page 77

 Q&A
1. (True/False) ITU-T G.8275.1 is a precise time synchronization telecom
standard based on the Precision Time Protocol (PTP) defined in IEEE
1588v2. ITU-T G.8275.1 uses the same NE model and source selection
algorithm, but has a better delay compensation algorithm. Therefore, ITU-
T G.8275.1 is more applicable to the telecom field.

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 Q&A
1. (Single-answer question) In a system using the master-slave clock
hierarchy, which of the following ITU-T G.8275.1 clocks is the highest-level
one?
A. T-GM

B. T-BC

C. T-TC

D. T-TSC

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 Summary
⚫ E2E architecture of a WDM/OTN clock synchronization network
⚫ Frequency synchronization solution
 Master/slave synchronization modes, clock working modes, clock protection modes, clock priorities, clock source
port types, external clock connection modes, and synchronous Ethernet

⚫ Phase synchronization solution

 IEEE 1588v2 synchronization solution

Master-slave hierarchy, clock architecture OC/BC/TC, PTP synchronization principles, time source ports, BCM
algorithm, and delay compensation
 ITU-T 8275.1 synchronization solution

Differences from IEEE 1588v2, clock architecture T-GM/T-BC/T-TSC, and BCMA algorithm

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 Acronyms and Abbreviations
⚫ This page provides the acronyms and abbreviations of all terms and
product names. If there is no acronym or abbreviation, delete this page.

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 More Information

Huawei Training Institute Huawei Training Institute Huawei Training Institute

WeChat Official Account WeChat Channel App

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Thank You
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