Quectel FCM360W Hardware Design V1.0
Quectel FCM360W Hardware Design V1.0
Version: 1.0
Date: 2023-10-18
Status: Released
Wi-Fi&Bluetooth Module Series
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a) We acknowledge no liability for any injury or damage arising from the reliance upon the information.
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Copyright © Quectel Wireless Solutions Co., Ltd. 2023. All rights reserved.
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Safety Information
The following safety precautions must be observed during all phases of operation, such as usage,
service or repair of any terminal or mobile incorporating the module. Manufacturers of the terminal
should notify users and operating personnel of the following safety information by incorporating these
guidelines into all manuals of the product. Otherwise, Quectel assumes no liability for customers’ failure
to comply with these precautions.
Full attention must be paid to driving at all times in order to reduce the risk of an
accident. Using a mobile while driving (even with a handsfree kit) causes
distraction and can lead to an accident. Please comply with laws and regulations
restricting the use of wireless devices while driving.
Switch off the terminal or mobile before boarding an aircraft. The operation of
wireless appliances in an aircraft is forbidden to prevent interference with
communication systems. If there is an Airplane Mode, it should be enabled prior to
boarding an aircraft. Please consult the airline staff for more restrictions on the use
of wireless devices on an aircraft.
Terminals or mobiles operating over radio signal and cellular network cannot be
guaranteed to connect in certain conditions, such as when the mobile bill is unpaid
or the (U)SIM card is invalid. When emergency help is needed in such conditions,
use emergency call if the device supports it. In order to make or receive a call, the
terminal or mobile must be switched on in a service area with adequate cellular
signal strength. In an emergency, the device with emergency call function cannot
be used as the only contact method considering network connection cannot be
guaranteed under all circumstances.
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Revision History
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Contents
1 Introduction .......................................................................................................................................... 9
1.1. Special Marks.............................................................................................................................. 9
2 Product Overview............................................................................................................................... 10
2.1. Key Features ............................................................................................................................. 11
2.2. Functional Diagram ................................................................................................................... 12
5 RF Performances ............................................................................................................................... 30
5.1. Wi-Fi Performances .................................................................................................................. 30
5.2. Bluetooth Performances ........................................................................................................... 31
5.3. Antenna/Antenna Interfaces ..................................................................................................... 32
5.3.1. Pin Antenna Interface (ANT_WIFI/BT) ......................................................................... 32
5.3.1.1. Reference Design................................................................................................ 32
5.3.1.2. Antenna Design Requirements ........................................................................... 33
5.3.1.3. RF Routing Guidelines ........................................................................................ 33
5.3.1.4. RF Connector Recommendation ........................................................................ 35
5.3.2. PCB Antenna ................................................................................................................ 37
5.3.3. Coaxial RF Connector .................................................................................................. 38
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Table Index
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Figure Index
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1 Introduction
QuecOpen® is a solution where the module acts as the main processor. Constant transition and evolution
of both the communication technology and the market highlight its merits. It can help you to:
⚫ Realize embedded applications’ quick development and shorten product R&D cycle
⚫ Simplify circuit and hardware structure design to reduce engineering costs
⚫ Miniaturize products
⚫ Reduce product power consumption
⚫ Apply OTA technology
⚫ Enhance product competitiveness and price-performance ratio
⚫ Apply anti-copy encryption technology to enhance product safety
This document defines FCM360W in QuecOpen® solution and describes its air interfaces and hardware
interfaces, which are connected with your applications.
With this document, you can quickly understand module interface specifications, electrical and
mechanical details, as well as other related information of the module. The document, coupled with
application notes and user guides, makes it easy to design and set up mobile applications with the
module.
Mark Definition
Unless otherwise specified, when an asterisk (*) is used after a function, feature, interface, pin
name, AT command, argument, and so on, it indicates that the function, feature, interface, pin,
*
AT command, argument, and so on, is under development and currently not supported; and
the asterisk (*) after a model indicates that the sample of the model is currently unavailable.
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2 Product Overview
FCM360W is a high-performance MCU Wi-Fi and Bluetooth module supporting IEEE 802.11b/g/n/ax and
BLE 5.1 standards. The module provides multiple interfaces including UART, SPI, I2C*, I2S, SDIO*, ADC
and PWM for various applications.
FCM360W
Pin counts 39
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Basic Information
Antenna/Antenna Interface
1 The module is provided with two temperature design solutions. For more details, please contact Quectel Technical
Support. Within the operating temperature range, the module’s related performance meets IEEE and Bluetooth
specifications.
2 For more details about the EVB, see document [1].
3 The module is provided with one of the three antenna/antenna interface designs. For more details, please contact
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The following figure shows a block diagram of the module and illustrates the major functional parts.
VBAT
Flash
CHIP_EN
ANT_WIFI/BT
RF Matching RF Coaxial
Connector
UART
PCB Antenna
GPIOs 26 MHz
XO
NOTE
The module is provided with one of the three antenna/antenna interface designs. For more details,
please contact Quectel Technical Support.
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3 Application Interfaces
GND 1 FCM360W
A NT _WIFI /B T 2
GND 3 30 GND
V BA T 4 29 GP IO2
GP IO14 8 35 34 33 25 RES E RV ED
GND GND GND
GP IO4 9 24 RES E RV ED
36 39 32
GP IO16 10 GND GND GND 23 GP IO3
GP IO24 15 18 RES E RV ED
NOTE
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Parameter Description
DI Digital Input
DO Digital Output
PI Power Input
Power Supply
DC
Pin Name Pin No. I/O Description Comment
Characteristics
Vmax = 3.6 V It must be provided with
Power supply for the
VBAT 4 PI Vmin = 3.0 V sufficient current more
module
Vnom = 3.3 V than 0.6 A.
Vmax = 3.3 V
Power supply for
VDD_EFUSE 17 PI Vmin = 0 V If unused, keep it open.
eFuse programming
Vnom = 1.8 V
Control Signals
DC
Pin Name Pin No. I/O Description Comment
Characteristics
Internally pulled up to
RESET_N 11 DI Reset the module VBAT.
Active low.
VBAT
Internally pulled up to
CHIP_EN 5 DI Enable the module VBAT.
Active high.
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UARTs
DC
Pin Name Pin No. I/O Description Comment
Characteristics
GPIO Interfaces
DC
Pin Name Pin No. I/O Description Comment
Characteristics
General-purpose
GPIO20 6 DIO
input/output
General-purpose
GPIO15 7 DIO
input/output
General-purpose
GPIO14 8 DIO
input/output
General-purpose
GPIO4 9 DIO
input/output
General-purpose
GPIO16 10 DIO
input/output
General-purpose
GPIO21 12 DIO
input/output
General-purpose
GPIO22 13 DIO
input/output
VBAT
General-purpose
GPIO23 14 DIO
input/output
General-purpose
GPIO24 15 DIO
input/output
General-purpose
GPIO25 16 DIO
input/output
General-purpose
GPIO1 21 DIO
input/output
Interrupt wakeup.
General-purpose
GPIO0 22 DIO
input/output
General-purpose
GPIO3 23 DIO
input/output
General-purpose
GPIO2 29 DIO Interrupt wakeup.
input/output
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RF Antenna Interface
DC
Pin Name Pin No. I/O Description Comment
Characteristics
Wi-Fi/Bluetooth 50 Ω characteristic
ANT_WIFI/BT 2 AIO
antenna interface impedance.
RESERVED Pins
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The module provides 14 GPIO interfaces by default, and can support up to 18 GPIO interfaces in the case of multiplexing. Pins are defined as follows:
Alternate
Pin Alternate Alternate Alternate Alternate Alternate
Pin Name Function 0 Comment
No. Function 1 Function 2 Function 3 Function 4 Function 5
(GPIO No.)
GPIO4 9 GPIO4 TRST UART0_RTS PWM0 SPI_CS2 - TRST: JTAG test reset
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GPIO0 22 GPIO0 SPI_CLK TCK UART2_TXD PWM0 I2S_TX_SCK TCK: JTAG test clock
GPIO3 23 GPIO3 SPI_MISO TDI UART0_CTS PWM3 I2C_SDA TDI: JTAG test data input
GPIO2 29 GPIO2 SPI_MOSI TDO UART1_TXD PWM2 I2C_SCL TDO: JTAG test data output
NOTE
1. The GPIO0, GPIO1, GPIO2 and UART2_RXD can be used as interrupt wake-up to wake up the module and then make the module into operating state by
pulling them down.
2. The maximum number of application interfaces multiplexed through GPIOs isn't available simultaneously. For the maximum number of different application
interfaces that the module can support, see Chapter 3.4 for details.
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3.4.1. UARTs
The module supports 2 UARTs by default: UART0 and UART2. In the case of multiplexing, it supports 3
UARTs: UART0, UART1 and UART2.
Multiplexing
Pin Name Pin No. I/O Description Comment
Function
The UART0 can be used for data transmission with the baud rate of 115200 bps by default, and the
actual measurement can reach 2 Mbps. The UART0 can also be used for firmware upgrade with the
baud rate of 921600 bps by default, and the baud rate can be configurable. Among them, the default
UART0 (pins 26 and 27) can be used for data transmission, downloading, debugging, and log printing;
the UART0 multiplexed through pins 12 and 13 can only be used for data transmission and debugging.
The module provides 3.3 V UARTs. You can use a voltage-level translator between the module and
external MCU’s UART if the MCU is equipped with a 1.8 V UART.
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4.7K
VDD_1V8
VBAT
1 nF
10K
UART_TXD UART0_RXD
UART_RXD UART0_TXD
10K 1 nF
VDD_1V8 VDD_1V8
4.7K
GND GND
MCU Module
NOTE
The transistor level-shifting circuit above is not suitable for applications with baud rates exceeding
460800 bps.
The UART1 and UART2 can all be used for data transmission, AT command communication and
debugging with default baud rate of 115200 bps, but they are not recommended to be used for
downloading. The UART2 is used for AT command communication by default in the standard firmware.
UART1_TXD/
UART2_TXD
UART1_RXD/
Test Points
UART2_RXD
ESD
Module
NOTE
Test points must be reserved for UART1_TXD, UART2_TXD, UART1_RXD and UART2_RXD.
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3.4.2. SPI
In the case of multiplexing, the module provides one SPI that supports both master and slave modes.
The maximum clock frequency of the interface can reach 20 MHz in slave mode, and 40 MHz in master
mode.
SPI_CS0 SPI_CS0
SPI_CLK SPI_CLK
SPI_MOSI SPI_MOSI
SPI_MISO SPI_MISO
SPI_CS0 SPI_CS0
SPI_CLK SPI_CLK
SPI_MOSI SPI_MOSI
SPI_MISO SPI_MISO
Multiplexing
Pin Name Pin No. I/O Description Comment
Function
In master mode, it is an output
GPIO1 21 SPI_CS0 DIO SPI chip select signal;
In slave mode, it is an input signal.
In master mode, it is an output
GPIO0 22 SPI_CLK DIO SPI clock signal;
In slave mode, it is an input signal.
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slave-out signal;
In slave mode, it is an output
signal.
In master mode, it is an output
SPI master-out
GPIO2 29 SPI_MOSI DIO signal;
slave-in
In slave mode, it is an input signal.
In the case of multiplexing, the module provides one I2C interface that supports both master and slave
modes. It supports:
Multiplexing
Pin Name Pin No. I/O Description Comment
Function
I2C_SCL I2C_SCL
I2C_SDA I2C_SDA
Module Host
4.7K
4.7K
VBAT
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In the case of multiplexing, the module provides one SDIO interface that supports master mode only.
The SDIO interface connection between the module and the SD card connector is illustrated in the
following figure.
VBAT
VDD_3V3
470K
NM
NM
NM
NM
NM
NM
NM
VDD
100μF 100nF 33pF 10pF
0R
SDIO_CLK SDIO_CLK
0R
SDIO_CMD SDIO_CMD
0R
SDIO_DATA0 SDIO_DATA0
0R
SDIO_DATA1 SDIO_DATA1
0R
SDIO_DATA2 SDIO_DATA2
0R
SDIO_DATA3 SDIO_DATA3
SD_DET DETECTIVE
NM NM NM NM NM VSS
TVS Array
SD Card
Module
Connector
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To ensure compliance of interface design with the SDIO 3.0 specification, please comply with the
following principles for SDIO interface design.
⚫ To enhance signal quality, add 0 Ω resistors in series and reserve capacitors (not mounted by
default) between the module and the SD card connector. All resistors and capacitors should be
placed close to the connector.
⚫ Place the TVS array close to the SD card connector with a parasitic capacitance no greater than 2
pF.
⚫ Route the SDIO traces in inner layer of the PCB, and surround the traces with ground on that layer
and with ground planes above and below. The impedance of SDIO signal trace is 50 Ω ±10 %.
⚫ Keep SDIO signals far away from other sensitive circuits/signals, such as RF circuits and analog
signals, as well as noisy signals such as clock signals and DC-DC signals.
⚫ The distance between SDIO signals and other signals must be greater than twice the trace width,
and the bus load capacitance must be less than 15 pF.
⚫ SDIO signal traces need to be equal length (the distance between the traces should be less than
0.5 mm).
In the case of multiplexing, the module supports 6 PWM channels. Pin description of PWM interfaces are
as follows.
In the case of multiplexing, the module supports one I2S interface for transmission of digital audio data
between internal components of the system, such as Codec, DSP, digital input/output interface, ADC,
DAC and digital filter.
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Multiplexing
Pin Name Pin No. I/O Description Comment
Function
GPIO1 21 I2S_RXD DI I2S receive data
In the case of multiplexing, the module supports 3 ADC interfaces, whose voltage range is 0–3.3 V. To
improve ADC accuracy, surround ADC trace with ground.
NOTE
1. It is prohibited to directly supply any voltage to ADC interfaces when the module is not powered by
the VBAT.
2. It is recommended to use resistor divider circuit for ADC interface application with 1 % accuracy
resistor divider.
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4 Operating Characteristics
Power supply pin and ground pins of the module are defined in the following table.
Pin Name Pin No. I/O Description Min. Typ. Max. Unit
The module is powered by VBAT, and it is recommended that the power supply chip for VBAT provide
sufficient current of 0.6 A at least. For better power supply performance, it is recommended to parallel a
22 μF decoupling capacitor, and two filter capacitors (1 μF and 100 nF) near the module’s VBAT pin.
Reserve C4 for debugging which is not mounted by default. In addition, it is recommended to add a TVS
near the VBAT to improve the surge voltage bearing capacity of the module. In principle, the longer the
VBAT trace is, the wider it should be.
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VBAT
R1 0R
VBAT
D1
C1 C2 C3 C4
22 μF 1 μF 100 nF NM
Module
4.2. Turn On
After the module VBAT is powered on, keep the CHIP_EN pin at high level to realize the automatic startup
of the module.
˂ 10 ms
> 1 μs
VBAT
CHIP_EN
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4.3. Reset
Drive RESET_N low for at least 100 ms and then release it to reset the module.
The reference design for resetting the module is shown below. An open collector driving circuit can be
used to control the RESET_N pin.
RESET_N
Control 33 Ω
Q1
R1
47 kΩ
R2
Another way to control the RESET_N is by using a button directly. A TVS component should be placed
near the button for ESD protection.
S1
RESET_N
TVS
Closed to S1
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VBAT
T 100 ms
Keep RESET_N of the module at low level during resetting or power-up and the module will enter
download mode. In the download mode, the firmware can be download through the UART0. During the
hardware design, connect the RESET_N of the module to the RTS of the serial port chip, or control
RESET_N through the host GPIO according to the waveform in the figure, otherwise the download will
fail.
RESET_N
RTS
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5 RF Performances
Operating Frequency
Modulation
Operating Mode
⚫ AP
⚫ STA
Encryption Mode
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Operating Frequency
2.400–2.4835 GHz
Modulation
GFSK
Operating Mode
BLE
5
Typ.; Unit: dBm, Tolerance: ±2 dB
Condition (VBAT = 3.3 V; Temp. 25°C)
Transmitting Power Receiving Sensitivity
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Appropriate antenna type and design should be used with matched antenna parameters according to
specific application. It is required to perform a comprehensive functional test for the RF design before
mass production of terminal products. The entire content of this chapter is provided for illustration only.
Analysis, evaluation and determination are still necessary when designing target products.
The module is provided in one of the three antenna/antenna interface designs: pin antenna interface
(ANT_WIFI/BT), PCB antenna and RF coaxial connector. The RF coaxial connector is not available
when the module is designed with ANT_WIFI/BT antenna interface or PCB antenna.
50 Ω characteristic
ANT_WIFI/BT 2 AIO Wi-Fi/Bluetooth antenna interface
impedance.
The circuit of RF antenna interface is shown below. For better RF performance, it is necessary to reserve
a π matching circuit and add ESD protection components. Reserved matching components such as R1,
C1, C2, and D1 should be placed as close to the antenna as possible. C1, C2, and D1 are not mounted by
default. The parasitic capacitance of TVS should be less than 0.05 pF and R1 is recommended to be 0 Ω.
R1
ANT_WIFI/BT
0R
C1 C2 D1
NM NM NM
Module
6The module is provided with one of the three antenna/antenna interface designs. For more details, please contact
Quectel Technical Support.
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Parameter Requirement
VSWR ≤2
For user’s PCB, the characteristic impedance of all RF traces should be controlled to 50 Ω. The
impedance of the RF traces is usually determined by the trace width (W), the materials’ dielectric
constant, the height from the reference ground to the signal layer (H), and the spacing between RF
traces and grounds (S). Microstrip or coplanar waveguide is typically used in RF layout to control
characteristic impedance. The following are reference designs of microstrip or coplanar waveguide with
different PCB structures.
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Figure 18: Coplanar Waveguide Design on a 4-layer PCB (Layer 3 as Reference Ground)
Figure 19: Coplanar Waveguide Design on a 4-layer PCB (Layer 4 as Reference Ground)
To ensure RF performance and reliability, follow the principles below in RF layout design:
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⚫ The reference ground of RF traces should be complete. In addition, adding some ground vias
around RF traces and the reference ground could help to improve RF performance. The distance
between the ground vias and RF traces should be at least twice the width of RF signal traces (2 ×
W).
⚫ Keep RF traces away from interference sources, and avoid intersection and paralleling between
traces on adjacent layers.
If RF connector is used for antenna connection, it is recommended to use the U.FL-R-SMT connector
provided by Hirose.
U.FL-LP series mated plugs listed in the following figure can be used to match the U.FL-R-SMT
connector.
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Parameter Requirement
VSWR ≤3
Efficiency 26 %
When using the PCB antenna on the module, the module should be placed at the side of the motherboard.
The distance between the PCB antenna and connectors, vias, traces, ethernet port and any other metal
components on the motherboard should be at least 16 mm. All layers in the PCB of the motherboard
under the PCB antenna should be designed as a keepout area.
Do not routing at the RF test point at the bottom of the module to ensure its performances during PCB
design.
7The module is provided with one of the three antenna/antenna interface designs. For more details, please contact
Quectel Technical Support.
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The mechanical dimensions of the receptacle supported by the module are as follows.
8The module is provided with one of the three antenna/antenna interface designs. For more details, please contact
Quectel Technical Support.
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Item Specification
Nominal Impedance 50 Ω
The mated plug listed in the following figure can be used to match the connector.
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The pictures for plugging in a coaxial cable plug is shown below, θ = 90° is acceptable, while θ ≠ 90° is
not.
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The pictures of pulling out the coaxial cable plug is shown below, θ = 90° is acceptable, while θ ≠ 90° is
not.
The pictures of installing the coaxial cable plug with a jig is shown below, θ = 90° is acceptable, while θ ≠
90°is not.
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RF connectors and cables by I-PEX are recommended. For more details, visit https://www.i-pex.com.
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Absolute maximum ratings for power supply and voltage on digital and analog pins of the module are
listed in the following table.
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Static electricity occurs naturally and may damage the module. Therefore, applying proper ESD
countermeasures and handling methods is imperative. For example, wear anti-static gloves during the
development, production, assembly and testing of the module; add ESD protection components to the
ESD sensitive interfaces and points in the product design.
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7 Mechanical Information
This chapter describes the mechanical dimensions of the module. All dimensions are measured in
millimeters (mm), and the dimensional tolerances are ±0.2 mm unless otherwise specified.
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NOTE
The package warpage level of the module refers to the JEITA ED-7306 standard.
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NOTE
Keep at least 3 mm between the module and other components on the motherboard to improve
soldering quality and maintenance convenience.
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NOTE
1. Images above are for illustrative purposes only and may differ from the actual module. For
authentic appearance and label, please refer to the module received from Quectel.
2. The RF coaxial connector is not mounted on the module when using pin antenna interface
(ANT_WIFI/BT) or PCB antenna.
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The module is provided with vacuum-sealed packaging. MSL of the module is rated as 3. The storage
requirements are shown below.
1. Recommended Storage Condition: the temperature should be 23 ±5 °C and the relative humidity
should be 35–60 %.
3. Floor life: 168 hours 9 in a factory where the temperature is 23 ±5 °C and relative humidity is below
60 %. After the vacuum-sealed packaging is removed, the module must be processed in reflow
soldering or other high-temperature operations within 168 hours. Otherwise, the module should be
stored in an environment where the relative humidity is less than 10 % (e.g., a dry cabinet).
4. The module should be pre-baked to avoid blistering, cracks and inner-layer separation in PCB under
the following circumstances:
9 This floor life is only applicable when the environment conforms to IPC/JEDEC J-STD-033. It is recommended to start
the solder reflow process within 24 hours after the package is removed if the temperature and moisture do not conform to,
or are not sure to conform to IPC/JEDEC J-STD-033. Do not unpack the modules in large quantities until they are ready
for soldering.
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NOTE
1. To avoid blistering, layer separation and other soldering issues, extended exposure of the module to
the air is forbidden.
2. Take out the module from the package and put it on high-temperature-resistant fixtures before
baking. If shorter baking time is desired, see IPC/JEDEC J-STD-033 for the baking procedure.
3. Pay attention to ESD protection, such as wearing anti-static gloves, when touching the modules.
Push the squeegee to apply the solder paste on the surface of stencil, thus making the paste fill the
stencil openings and then penetrate to the PCB. Apply proper force on the squeegee to produce a clean
stencil surface on a single pass. To guarantee module soldering quality, the thickness of stencil for the
module is recommended to be 0.15–0.18 mm. For more details, see document [3].
The recommended peak reflow temperature should be 235–246 ºC, with 246 ºC as the absolute
maximum reflow temperature. To avoid damage to the module caused by repeated heating, it is
recommended that the module should be mounted only after reflow soldering for the other side of PCB
has been completed. The recommended reflow soldering thermal profile (lead-free reflow soldering) and
related parameters are shown below.
Temp. (°C)
Reflow Zone
Ramp-up slope: Cool-down slope:
0–3 °C/s C -3–0 °C/s
246
235
217
B D
200
Soak Zone
150 A
100
Ramp-to-soak slope:
0–3 °C/s
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Soak Zone
Reflow Zone
Reflow Cycle
NOTE
1. The above profile parameter requirements are for the measured temperature of solder joints. Both
the hottest and coldest spots of solder joints on the PCB should meet the above requirements.
2. During manufacturing and soldering, or any other processes that may contact the module directly,
NEVER wipe the module’s shielding can with organic solvents, such as acetone, ethyl alcohol,
isopropyl alcohol, trichloroethylene, etc. Otherwise, the shielding can may become rusted.
3. The shielding can for the module is made of Cupro-Nickel base material. It is tested that after 12
hours’ Neutral Salt Spray test, the laser engraved label information on the shielding can is still
clearly identifiable and the QR code is still readable, although white rust may be found.
4. If a conformal coating is necessary for the module, do NOT use any coating material that may
chemically react with the PCB or shielding cover, and prevent the coating material from flowing into
the module.
5. Avoid using ultrasonic technology for module cleaning since it can damage crystals inside the
module.
6. Due to the complexity of the SMT process, please contact Quectel Technical Support in advance
for any situation that you are not sure about, or any process (e.g. selective soldering, ultrasonic
soldering) that is not mentioned in document [3].
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This chapter describes only the key parameters and process of packaging. All figures below are for
reference only. The appearance and structure of the packaging materials are subject to the actual
delivery.
The module adopts carrier tape packaging and details are as follow:
W P T A0 B0 K0 K1 F E
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øD1 øD2 W
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9 Appendix References
Document Name
[1] Quectel_FCM360W_TE-B_User_Guide
[2] Quectel_RF_Layout_Application_Note
[3] Quectel_Module_SMT_Application_Note
Abbreviation Description
AP Access Point
CS Chip Select
DC Direct Current
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GND Ground
HT High Throughput
I/O Input/Output
OTA Over-the-Air
PA Power Amplifier
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RF Radio Frequency
STA Station
XO Crystal Oscillator
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