VLSI Design & Testing
VLSI DESIGN
(21EC63)
SEMESTER – VI
Module 3
Semiconductor Memories: Introduction, Dynamic Random Access Memory (DRAM) and
Static Random Access Memory (SRAM), Nonvolatile Memory, Flash Memory, Ferroelectric
Random Access Memory (FRAM) (10.1 to 10.6 of TEXT2)
Asst. Prof. Vivek V Kajagar, Dept. of ECE, JCER, Belagavi
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Semiconductor Memories- Introduction
Semiconductor memory arrays capable of storing large quantities of
digital information are essential to all digital systems. The amount of memory
required in a particular system depends on the type of application, but, in
general, the number of transistors utilized for the information (data) storage
function is much larger than the number of transistors used in logic operations
and for other purposes. The ever-increasing demand for larger data storage
capacity has driven the fabrication technology and memory development towards
more compact design rules and, consequently, toward higher data storage
densities.
The area efficiency of the memory array, i.e., the number of stored data
bits per unit area, is one of the key design criteria that determine the overall
storage capacity and, hence, the memory cost per bit. Another important issue is
the memory access time, i.e., the time required to store and/or retrieve a
particular data bit in the memory array. The access time determines the memory
speed, which is an important performance criterion of the memory array. Finally,
the static and dynamic power consumption of the memory array is a significant
factor to be considered in the design, because of the increasing importance of
low-power applications.
Read-write (R/W) memory circuits must permit the modification (writing)
of data bits stored in the memory array, as well as their retrieval (reading) on
demand. This requires that the data storage function be volatile, i.e., the stored
Asst. Prof. Vivek V Kajagar, Dept. of ECE, JCER, Belagavi
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data are lost when the power supply voltage is turned off. The read-write memory
circuit is commonly called Random Access Memory (RAM), mostly due to
historical reasons.
Compared to sequential-access memories such as magnetic tapes, any cell
in the R/W memory array can be accessed with nearly equal access time. Based
on the operation type of individual data storage cells, RAMs are classified into
two main categories: Static RAMs (SRAM) and Dynamic RAMs (DRAM).
A typical memory array organization is shown in Fig. 10.2. The data
storage structure, or core, consists of individual memory cells arranged in an
array of horizontal rows and vertical columns. Each cell is capable of storing one
bit of binary information. Also, each memory cell shares a common connection
with the other cells in the same row, and another common connection with the
other cells in the same column. To access a particular memory cell, i.e., a
particular data bit in this array, the corresponding bit line and the corresponding
word line must be activated (selected). The row and column selection operations
are accomplished by row and column decoders, respectively.
Asst. Prof. Vivek V Kajagar, Dept. of ECE, JCER, Belagavi
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Read-Only Memory (ROM) Circuits
NOR-based ROM array
The read-only memory array can also be seen as a simple combinational
Boolean network which produces a specified output value for each input
combination, i.e., for each address. Thus, storing binary information at a
particular address location can be achieved by the presence or absence of a data
path from the selected row (word line) to the selected column (bit line), which is
equivalent to the presence or absence of a device at that particular location. In
the following, we will examine two different implementations for MOS ROM
arrays. Consider first the 4-bit x4-bit memory array shown in Fig. 10.3. Here,
each column consists of a pseudo-nMOS NOR gate driven by some of the row
signals, i.e., the word lines.
As described in the previous section, only one word line is activated
(selected) at a time by raising its voltage to VDD, while all other rows are held
at a low voltage level. If an active transistor exists at the cross point of a column
and the selected row, the column voltage is pulled down to the logic low level by
that transistor. If no active transistor exists at the cross point, the column voltage
is pulled high by the pMOS load device. Thus, a logic " 1 "-bit is stored as the
absence of an active transistor, while a logic ""-bit is stored as the presence of
Asst. Prof. Vivek V Kajagar, Dept. of ECE, JCER, Belagavi
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an active transistor at the crosspoint. To reduce static power consumption, the
pMOS load transistors in the ROM array shown in Fig. 10.3 can also be driven
by a periodic precharge signal, resulting in a dynamic ROM.
In actual ROM layout, the array can be initially manufactured with nMOS
transistors at every row-column intersection. The " 1 "-bits are then realized by
omitting the drain or source connection, or the gate electrode of the
corresponding nMOS transistors in the final metallization step.
Figure 10.5 shows a larger portion of the ROM array, except for the pMOS
load transistors connected to the metal columns. Here, the 4-bit x 4-bit ROM
array shown in Fig. 10.3 is realized using the contact-mask programming
methodology. Note that only 8 of the 16 nMOS transistors fabricated in this
structure are actually connected to the bit lines via metal-to-diffusion contacts.
In reality, the metal column lines are laid out directly on top of diffusion columns
to reduce the horizontal dimension of the ROM array.
Asst. Prof. Vivek V Kajagar, Dept. of ECE, JCER, Belagavi
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NAND-based ROM array
In a NAND ROM, each bit line consists of a depletion-load NAND gate,
driven by some of the row signals, i.e., the word lines. In normal operation, all
word lines are held at the logic-high voltage level except for the selected line,
which is pulled down to logic-low level. If a transistor exists at the crosspoint of
a column and the selected row, that transistor is turned off and the column voltage
is pulled high by the load device.
On the other hand, if no transistor exists (shorted) at that particular
crosspoint, the column voltage is pulled low by the other nMOS transistors in the
multi-input NAND structure.
Thus, a logic "1 "-bit is stored by the presence of a transistor that can be
deactivated, while a logic "0"-bit is stored by a shorted or normally on transistor
at the crosspoint.
As in the NOR ROM case, the NAND-based ROM array can be fabricated
initially with a transistor connection present at every row-column intersection. A
"0-bit is then stored by lowering the threshold voltage of the corresponding
nMOS transistor at the cross point through a channel implant, so that the
transistor remains on regardless of the gate voltage (i.e., the nMOS transistor at
the intersection becomes a depletion-type device). The availability of this process
step is also the reason why depletion-type nMOS load transistors are used instead
of pMOS loads in the example shown above.
Asst. Prof. Vivek V Kajagar, Dept. of ECE, JCER, Belagavi
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Figure 10.9 shows a sample 4-bit x 4-bit layout of the implant-mask NAND
ROM array. Here, vertical columns of n-type diffusion intersect at regular
intervals with horizontal rows of polysilicon, which results in an nMOS transistor
at each intersection point.
Design of Row and Column Decoders
Asst. Prof. Vivek V Kajagar, Dept. of ECE, JCER, Belagavi
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The circuit structures of row and column address decoders select a particular
memory location in the array, based on the binary row and column addresses. A
row decoder designed to drive a NOR ROM array must, by definition, select one
of the 2^N word lines by raising its voltage to VOH. As an example, consider the
simple row address decoder shown in Fig. 10.10, which decodes a two-bit row
address and selects one out of four word lines by raising its level.
A most straightforward implementation of this decoder is another NOR
array, consisting of 4 rows (outputs) and 4 columns (two address bits and their
complements). Note that this NOR-based decoder array can be built just like the
NOR ROM array, using the same selective programming approach (Fig. 10.11).
The ROM array and its row decoder can thus be fabricated as two adjacent NOR
arrays, as shown in Fig. 10.12.
Asst. Prof. Vivek V Kajagar, Dept. of ECE, JCER, Belagavi
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Asst. Prof. Vivek V Kajagar, Dept. of ECE, JCER, Belagavi
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Static Read-Write Memory (SRAM) Circuits
Read-write (R/W) memory circuits are designed to permit the modification
(writing) of data bits to be stored in the memory array, as well as their retrieval
(reading) on demand. The memory circuit is said to be static if the stored data
can be retained indefinitely (as long as a sufficient power supply voltage is
provided), without any need for a periodic refresh operation.
The data storage cell, i.e., the 1-bit memory cell in static RAM arrays,
invariably consists of a simple latch circuit with two stable operating points
Asst. Prof. Vivek V Kajagar, Dept. of ECE, JCER, Belagavi
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(states). Depending on the preserved state of the two-inverter latch circuit, the
data being held in the memory cell will be interpreted either as a logic "0" or as
a logic " 1." To access (read and write) the data contained in the memory cell via
the bit line, we need at least one switch, which is controlled by the corresponding
word line, i.e., the row address selection signal (Fig.10.21(a)). Usually, two
complementary access switches consisting of nMOS pass transistors are
implemented to connect the 1-bit SRAM cell to the complementary bit lines
(columns).
Figure 10.2 1 (b) shows the generic structure of the MOS static RAM cell,
consisting of two cross-coupled inverters and two access transistors. The load
devices may be polysilicon resistors, depletion-type nMOS transistors, or pMOS
transistors, depending on the type of the memory cell. The pass gates acting as
data access switches are enhancement-type nMOS transistors.
Asst. Prof. Vivek V Kajagar, Dept. of ECE, JCER, Belagavi
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Typical voltage waveforms associated with the word line RS and the two
pseudo complementary bit lines are shown qualitatively in Fig. 10.23. Note that
the voltage difference between the two columns during a read operation may be
only a few hundred millivolts, which must be detected by the data-read circuitry.
The reason for this is that the two nMOS transistors in series (e.g., MI and M3
for read "0") pulling down the column during the read phase cannot discharge
the large column capacitance quickly.
Asst. Prof. Vivek V Kajagar, Dept. of ECE, JCER, Belagavi
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SRAM Write Circuitry
As already discussed in the preceding section, a "write" operation is
performed by forcing the voltage level of either column (bit line) to a logic-low
level. To accomplish this task, a low-resistance, conducting path must be
provided from each column to the ground, which can be selectively activated by
the data-write signals. A simplified view of the SRAM "write" circuitry designed
for this operation is shown in Fig. 10.28. Here, the nMOS transistors Ml and M2
are used to pull down the two column voltages, while the transistor M3 completes
the conducting path to ground. Note that M3 is driven by the column address
decoder circuitry, i.e., M3 turns on only when the corresponding column address
is selected. The column pull-down transistors, on the other hand, are driven by
two pseudo-complementary control signals, WB and WB. The "write-enable"
signal W(active low) and the data to be written (DATA) are used to generate the
control signals, as shown in the table in Fig. 10.28.
Asst. Prof. Vivek V Kajagar, Dept. of ECE, JCER, Belagavi
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The nMOS pull-down transistors MI and M2, as well as the column selection
transistor M3 must have sufficiently large (WIL) ratios so that the column
voltages can be forced to almost 0 V level during a "write" operation. Also note
that the data input circuitry consisting of two NOR2 gates can be shared by
several columns, assuming that one column is activated, i.e., selected by the
column address decoder, at any given time.
SRAM Read Circuitry
During the "data read" operation in the SRAM array, the voltage level on
either one of the columns drops slightly after the pass transistors are turned on
by the row address decoder circuit. In order to reduce the read access time, the
"read" circuitry must detect. a very small voltage difference between the two
complementary columns, and amplify this difference to produce a valid logic
output level.
Asst. Prof. Vivek V Kajagar, Dept. of ECE, JCER, Belagavi
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Dynamic Read-Write Memory (DRAM) Circuits
As the trend for high-density RAM arrays forces the memory cell size to
shrink, alternative data storage concepts must be considered to accommodate
these demands. In a dynamic RAM cell, binary data is stored simply as charge in
a capacitor, where the presence or absence of stored charge determines the value
of the stored bit. Note that the data stored as charge in a capacitor cannot be
retained indefinitely, because the leakage currents eventually remove or modify
the stored charge.
Thus, all dynamic memory cells require a periodic refreshing of the stored
data, so that unwanted modifications due to leakage are prevented before they
occur. The use of a capacitor as the primary storage device generally enables the
Asst. Prof. Vivek V Kajagar, Dept. of ECE, JCER, Belagavi
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DRAM cell to be realized on a much smaller silicon area compared to the typical
SRAM cell.
Three-Transistor DRAM Cell
The circuit diagram of a typical three-transistor dynamic RAM cell is
shown in Fig. 10.37 as well as the column pull-up (precharge) transistors and the
column read/write circuitry. Here, the binary information is stored in the form of
charge in the parasitic node capacitance Cl. The storage transistor M2 is turned
on or off depending on the charge stored in C1, and the pass transistors Ml and
M3 act as access switches for data read and write operations. The cell has two
separate bit lines for "data read" and "data write," and two separate word lines
to control the access transistors.
All "data read" and "data write" operations are performed during the
active 2 phase, i.e., when PC is low. Figure 10.38 depicts the typical voltage
Asst. Prof. Vivek V Kajagar, Dept. of ECE, JCER, Belagavi
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waveforms associated with the 3-T DRAM cell during a sequence of four
consecutive operations: write " 1," read "1," write "0," and read "0."
One-Transistor DRAM Cell
The circuit diagram of the one-transistor (1-T) DRAM cell consisting of
one explicit storage capacitor and one access transistor is shown in Fig. 10.44.
Here, C1 represents the storage capacitor which typically has a value of 30 to
100 fF. Similar to the 3-T DRAM cell, binary data are stored as the presence or
absence of charge in the storage capacitor.
Capacitor C2 represents the much larger parasitic column capacitance
associated with the word line. Charge sharing between this large capacitance
and the very small storage capacitance plays a very important role in the
operation of the 1-T DRAM cell.
Asst. Prof. Vivek V Kajagar, Dept. of ECE, JCER, Belagavi
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Flash Memory
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NOR Flash Memory Cell
Asst. Prof. Vivek V Kajagar, Dept. of ECE, JCER, Belagavi
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NAND Flash Memory Cell
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Ferroelectric Random Access Memory(FRAM)
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