International Journal of Reconfigurable and Embedded Systems (IJRES)

Vol. 13, No. 2, July 2024, pp. 244~252

ISSN: 2089-4864, DOI: 10.11591/ijres.v13.i2.pp244-252  244

FPGA in hardware description language based digital clock

alarm system with 24-hr format

Mohd Faris Izzwan Mohd Sayudzi1, Irni Hamiza Hamzah1, Azman Ab Malik2, Mohaiyedin Idris1,
Zainal Hisham Che Soh1, Alhan Farhanah Abd Rahim1, Nor Shahanim Mohamad Hadis1
1
Electrical Engineering Studies, College of Engineering, Universiti Teknologi MARA, Cawangan Pulau Pinang, Malaysia
2
School of Computer Sciences, Universiti Sains Malaysia, Pulau Pinang, Malaysia

Article Info ABSTRACT

Article history: Currently, digital clock adapts microprocessor or microcontroller system.
Performance of speed and reconfigurability issue become a main concern in
Received Jun 2, 2023 digital clocks. New additional feature may be introduced in digital clocks in
Revised Jan 2, 2024 the future. Field programmable gate array (FPGA) offer better performance
Accepted Jan 17, 2024 of speed and reconfiguration features. Based on these advantages, it is
essential to study or explore the digital clock with FPGA design. The
objective in this study is to create a hardware description language (HDL)-
Keywords: based digital clock with alarm system and implement it onto the Altera DE2-
115 board. Using Verilog HDL language in Quartus Prime 20.1 Lite Edition
Digital alarm clock software, all submodule components is developed and being test benched
Field programmable gate array using ModelSim-Altera Starter Edition 13.1 to ensure the correct
Hardware description language functionality. Then all inputs and outputs will be assigned through pin
Verilog assignment in the software. For verification purpose, it will be downloaded
Altera DE2-115 to the Altera DE2-115 board. In conclusion, the file has been successfully
Seven segment display implemented to the board and the digital clock with alarm is fully functional
as expected. This was proved by the alarm signal, time adjustment and
display of the three-display mode which is clock, alarm, and input where
each mode carries their own functions as expected.
This is an open access article under the CC BY-SA license.

Corresponding Author:
Irni Hamiza Hamzah
Electrical Engineering Studies, College of Engineering, Universiti Teknologi MARA
Cawangan Pulau Pinang, Permatang Pauh Campus, 13500 Pulau Pinang, Malaysia
Email: [email protected]

1. INTRODUCTION
An alarm clock is one of the devices which is very useful in human live. It solved a problem that
everyone faces, which is determining the current time and also helping up to wake after sleep using alarm
system. With this device, everyone can have a manageable and coordinated life.
Today, technology has progressed to the point where a system may be integrated onto a single chip,
a process called as system on chip (SOC) [1], [2]. Likewise, this also applies to the digital clock. The system
is currently comprised of a microprocessor [2], [3]. The problem related to the digital clock with the
microprocessor is the performance of processing speed [4], [5] and reprogrammability issue [6], [7].
Following the trend of the period, numerous additional features may be incorporated in the future [8].
Therefore, it is essential to study the implementation of field programmable gate array (FPGA) in a digital
clock [9]. Digital clocks use FPGA technology because it has a simpler circuit topology [10], quicker
development cycle [11], and faster running speed [12]. FPGA is also used to solve the issue regarding on
reprogrammability of the system [13]. FPGA can be used to solved complicated computational issues which
requires increased speed and reprogrammability advantage [14]. It is explained that FPGA implementation is

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Int J Reconfigurable & Embedded Syst ISSN: 2089-4864  245

superior to microcontroller or microprocessor since it is favourable in terms of performance and

reconfigurable [15], making it easier to enhance the existing system [13].
The objective of this project is to create an hardware description language (HDL)-based digital clock
with alarm system and implement it on an FPGA board in order to resolve the issue. To fulfil the objective, a
digital clock with alarm system must be designed utilizing the verilog HDL programming language. The
system's functionality will then be validated using ModelSim Altera Starter Edition for Quartus Prime 20.1
Lite Edition. It will then be implemented on an FPGA board for verification purposes. This study focuses on
a 24-hour clock with an alarm system. This comprised coding, code analysis and synthesis, input and output
pin assignments, compilation of the system, and download to the Altera DE2-115 FPGA board.
The main advantage of FPGA is its performance of speed. The high speed of an FPGA is a result of
the system's I/O bandwidth to local memory, pipelining, and parallelism features [16], [17]. Parallel
processing is one of the features that distinguishes FPGA from other processor types [18], [19]. FPGA is
substantially superior to microcontrollers in terms of speed, I/O count, and performance [20]. Rodriguez-
Andina et al. [21] stated that internal memory is essential for enhancing processing performance and
optimizing I/O pin utilization. In addition, internal memory blocks offer the benefit of constructing complex
functions, such as counters and multipliers. While digital clocks can be built using a variety of technologies,
FPGAs offer major benefits such as a greater number of I/O ports [17]. It is desirable to explore digital clocks
using FPGA due to their reduced system usage, increased system reliability, and increased working speed
[12], [22] likewise, due to the advantages of a simpler circuit construction and faster operation, explained it is
essential to analyze the digital clock using FPGA.
As compared to application-specific integrated circuits (ASICs), FPGAs have simpler design cycle
in which means the design tools take care of a major function by themselves, such as placement, routing, and
timing in reference to specifications that need to be set [23]. Apart from that, although the product has been
finalised, built, and delivered, it may be easily updated, adapted, and reprogrammable. FPGAs are ideal for
time-critical systems [24] and is the right solution if the application requires constant bug fixes, feature,
design changes, and software flexibility. Table 1 summarizes performance of FPGAs to microcontrollers and
ASICs across various aspects.
Like any other microcontrollers, FPGA also facing reprogrammable issues in which one of the
solutions presented in this paper is to simulate the developed Verilog coding using ModelSim-Altera Starter
Edition 13.1 software. The output is presented in timing waveforms. From these generated output waveforms,
it can be compared with the expected output.

Table 1. Comparison of FPGA to another microcontroller and ASIC [23], [25], [26]
Aspect Microcontroller FPGA ASIC
Flexibility during development High High High
Flexibility after development High High Low
Performance Low Medium High
Power consumption High Medium Low
Development cost Low Medium High

2. RESEARCH METHOD
Figure 1 depicts the design of the top module of a digital alarm clock. There are 14 inputs including
50 MHz clock and 8 outputs. The input ports were listed as shown in the following diagram. The inputs for 'Reset'
are used to reset all operations to zero. Consequently, the clock time, alarm time, input time, and alarm time switch
to zero. While 'clock_50 MHz' is generated from a 50 MHz clock source. The frequency was subsequently
decreased to 1 Hz to match the duration of 1 s during clock operation. Load data time (LD_time) is the switch that
loads the input time into the clock. While 'LD_alarm' loaded input time into the alarm time. The 'Increment button'
is utilized to assign values to inputs. As it is pressed, the time will be increased by 1 unit, depending on which
switch is active at the time: switch Hin_1, which corresponds to the most significant hour, or switch Hin_0, which
relates to the least significant hour. This was also applied to minutes. The 'ctime' switch is used to display the
current time. 'atime' is used to display alarm time, whereas 'stime' displays input time. The 'AL_ON' switch
activates the alarm system, while the 'STOP_al' switch deactivates it.
Figure 2 shows the overall components of submodule used for this study. It consists the submodules
of clock reducer, time input, clock function, clock output, current time, and alarm function. All submodules
were tested with their own testbench coding to ensure the functionality of each submodule. In clock reducer,
the input of this module is 50 MHz clock and reset. It was then reduced to 1 Hz clock which equivalent to 1 s
for operation in time input, clock function, and alarm function. In this module, it uses counter to count for 1 s
clock production. If the counter is equal to 25,000,000, the 1 s clock will change in state from high to low.

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Figure 1. Top module of a digital clock alarm system

Figure 2. Submodule for digital alarm clock system

The reason why 25,000,000 count is used as the clock consists of 2 states, high and low. Each will
be representing 0.5 s. To make 1 s clock, each state must have the count of 25,000,000 before changing to
another state. If the counter reaches its target, it will reset back to zero. In time input, the user need to insert
their desired time for clock time or alarm time using 4 switches which H_in1, H_in0, M_in1, and M in0.
These switches representing the hour and the minutes, most and least significant digit. Each push of
increment_button will increase the input value by 1. The value will reset if it exceeds the maximum pre-set
value of clock time. If reset switch is turned on, all input will reset to 0. In clock function, this is where the
input from user will be loaded either to clock time or alarm time. If LD time is switched on, the input will be
loaded to the clock time. While LD_alarm will load the input into alarm time. This module also where the

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clock time operates through counters through seconds, hour and minutes. In clock output, the internal clock
time know as temporary (tmp) will be converted to 6 types of output for clock time display. It includes most
significant and least significant of hours, minutes and seconds. In current time, it utilized 3 types of input
which is clock time, alarm time, and setting time. The users can choose to see which type of display they
want to see using 3 switches. The switches are ‘ctime’ which displays current clock time, ‘atime’ for
displaying the alarm time and ‘stime’ for input time. And all of the input will be assigned to 7 different
seven-segment displays. The arrangement of seven-segment display is 7’b (6 5 4 3 2 1 0). Seven segment
display is active low meaning than logic low will light up the character of display. While logic high will turn
off the character. In alarm function, it will compare the clock time and the alarm time. If both are similar and
the switch AL_ON is on, the alarm will be turned on. In this case, the red LED will represent the alarm. If
AL_ON is not on, the Alarm will not be turned on. To stop the alarm, user must switch STOP AL_ON. The
flowchart of a digital clock with alarm system is depicted in Figure 3. This digital clock has three display
modes. The user can choose between the clock, alarm, and set times. If the user selects reset switch, all time
modes are reset to 0. If the user does not activate any of the three display switches, the seven-segment display
will be blank. With input time mode, the user may also provide input to edit the clock time and alarm time.
There are four switches to choose which portion of time is to be modified. Two are the maximum and
minimum hours, while the other two are the maximum and minimum minutes. If the user presses the
increment button, the value will grow by one. If the value of H_in1 is more than 2, for instance, it will be
reset to zero. And it will continue if the button is still pressed. This will facilitate the user's input. If the user
activates the LD time switch, the input will be set to clock time. The input will be loaded at alarm time for
LD alarm. If AL_ON is enabled, the Alarm will be triggered if the clock time coincides with the alarm time.

Figure 3. Flowchart of digital clock alarm system

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3. RESULTS AND DISCUSSION

In this section, it is divided into 2 categories: software simulation and hardware implementation. In
the part of software simulation, ModelSim-Altera Starter Edition 13.1 had been used. Whereby for hardware
implementation, Cyclone IV of Altera DE2-115 development and education board had been utilized for
verification.

3.1. Software simulation

Figures 4 and 5 reflect the timing diagram for the top module of a digital alarm clock. When 'stime' is
enabled, the seven-segment displays the time input. In this instance, switch Min0 is activated. If the 'increment
button' was pressed, the input will be added to Min_0 by 1. Then, LD alarm is enabled, which loads the input
with the alarm time. The current alarm time is 0001 hours. Seven-segment display output HEX0-HEX7 displays
three types of display modes. It consists of 7'bit registers, with each of LED of a seven-segment display utilizing
a bit of register. 7'b describes the configuration of seven-segment display (6 5 4 3 2 1 0). Seven-segment
displays are low active type, therefore 0 input will illuminate the display while 1 will turn it off.

Figure 4. Timing diagram of time input for alarm time

Figure 5. Timing diagram of display mode change

3.2. Hardware implementation

In this project, the digital clock with alarm system accepts input from 12 switches, a 50 MHz clock,
and one push button. While the output is 7 unit of seven-segment display and a red LED. Figures 6, 7, and 8
show the implementation of digital clock with alarm system. It shows the types of display modes that can be
chosen by user via switches. The input and the output have been assigned through Pin Planner in Quartus
Prime 20.1 Lite Edition software. In clock time, HEX0 will display ‘C’ symbol which represents clock. In
alarm time, HEX0 will display ‘A’ symbol which represents alarm and HEX0 will display ‘E’ symbol which
represents entry or in input time.

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Figure 6. Display mode of alarm time on Altera DE2-115

Figure 7. Display mode of input time on Altera DE2-115

Figure 8. Display mode of clock time on Altera DE2-115

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4. CONCLUSION
In conclusion, the digital clock with alarm system has been successfully implemented into Altera
DE2-115 board. It consists of switches and button as input while seven-segment display and red LED as
output. This digital clock has 3 types of display which is clock, alarm, and input time. Therefore, this study
will improve the current technology of digital clock where with usage of microcontroller or microprocessor
having disadvantages in term of performance and reprogrammability issues.

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BIOGRAPHIES OF AUTHORS

Mohd Faris Izzwan Mohd Sayudzi was born in Alor Setar, Kedah on 21st June
1997. He obtained his bachelor of engineering (Hons) in electrical and electronic engineering
in 2022 from Universiti Teknologi MARA, Penang Branch Campus, Malaysia. He is a
registered Board of Engineers Malaysia (BEM) Graduate Engineer. He can be contacted at
email: [email protected].

Irni Hamiza Hamzah was born in Machang, Kelantan on 6th December 1974.
She obtained her bachelor of engineering (Hons) in electrical and electronic engineering in
1998, M.Sc. electronics system and design engineering in 2005 and Ph.D. in BioMEMs
sensors in 2013, which all had been obtained from School of of Electrical and Electronic
Engineering, Universiti Sains Malaysia, Malaysia. She is currently a senior lecturer in
Department of Electronic Engineering, Faculty of Electrical Engineering, Universiti Teknologi
MARA, Penang Branch Campus, Malaysia. Her research interests include biosensors,
BioMEMs, neural networks, and renewable energy. She is a registered Board of Engineers
Malaysia (BEM) Professional Engineer. She can be contacted at email:
[email protected].

Azman Ab Malik was born in Melaka on 12 October 2018. He obtained his

diploma in electronic technology from KKTM Pasir Mas in 2007, bachelor in electrical
engineering and technology from UNIKL BMI, master in electrical and electronic engineering
from USM and Ph.D. in electrical engineering from UITM. His interest in innovation towards
electrical and electronic and cross multi-disciplinary area to identify a new model or method in
engineering. His research interest included electrical power, power system, renewable energy,
hybrid system, embedded system, wireless power transfer, and energy storage. He is currently
a lecturer at School of Computer Sciences, Universiti Sains Malaysia, Penang, Malaysia. He
can be contacted at email: [email protected].

Mohaiyedin Idris obtained his diploma in electronic engineering

(communication) from Politeknik Ungku Omar Ipoh, Perak in 2000, bachelor of engineering
(Hons) in electrical-electronics from UTM Skudai, Johor in 2005 and M.Sc. electrical-
electronic engineering from USM in 2010. He is currently a senior lecturer in Department of
Electronic Engineering, Faculty of Electrical Engineering, Universiti Teknologi MARA,
Penang Branch Campus, Malaysia. His research interests include electronic system
development (hardware and software), microcontroller system and wireless sensor network,
database, and deep learning approach for medical image. He is a registered Board of Engineers
Malaysia (BEM) Graduate Engineer. He can be contacted at email:
[email protected].

Zainal Hisham Che Soh was born in Machang, Kelantan on 16th March 1974.
He obtained his bachelor of engineering (Hons) in electronic engineering from University of
Leeds, UK in 1997, M.Sc. in computer science in real-time software engineering from UTM in
2004 and Ph.D. in electrical and electronic from USM in 2013. His research interest in internet
of things, big data, distributed/parallel computing, artificial intelligence, microcontroller
system, and wireless sensor network. He works in UiTMPulau Pinang under Faculty of
Electrical Engineering, UiTM, Pulau Pinang. He is a member of IEE, IET, BEM, and
MySEIG. He can be contacted at email: [email protected].

FPGA in hardware description language based digital clock … (Mohd Faris Izzwan Mohd Sayudzi)
252  ISSN: 2089-4864

Alhan Farhanah Abd Rahim obtained her bachelor of engineering (Hons) in

electronics engineering from University of Southampton in 1998, M.Sc. and Ph.D. in solid
state physics from Universiti Sains Malaysia in 2003 and 2014 respectively. She is currently
senior lecturer at the Faculty of Electrical Engineering, Universiti Teknologi MARA,
Malaysia. Her research interests are in synthesizing and fabricating advance semiconductor
materials (group IV, III-V)) and devices utilizing low cost techniques. Her Ph.D. research work
entitle: Studies of Ge nanostructures Studies of Si and Ge Nanostructures Synthesized by
Electrochemical and Plasma Assisted Techniques for Sensing Applications. She is author and
co-author of over 20 scientific publications in this field. She is a companion member of
Institute of Engineer’s Malaysia (IEM) and a registered Board of Engineers Malaysia (BEM)
Professional Engineer. She can be contacted at email: [email protected].

Nor Shahanim Mohamad Hadis is a senior lecturer at the Electrical Engineering

Studies, College of Engineering, Universiti Teknologi MARA (UiTM) Cawangan Pulau
Pinang. She obtained her diploma in electrical (Electronics) engineering from Universiti
Teknologi MARA in 2002, bachelor (Hons) in electrical engineering from Universiti
Teknologi MARA in 2005, M.Sc. in microelectronics from Universiti Kebangsaan Malaysia in
2006 and Ph.D. in nano-material and device fabrication from University Sains Malaysia in
2018. Her main interests are microelectronics device fabrication and characterization, bio-
sensor, internet of things and embedded system. She can be contacted at email:
[email protected].

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