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GOVERNMENT OF TAMIL NADU

HIGHER SECONDARY SECOND YEAR

VOCATIONAL EDUCATION

BASIC ELECTRONICS ENGINEERING

Theory & Practical

A Publication Under Free Textbook Programme of Government of Tamil Nadu

Department of School Education

Untouchability is Inhuman and a Crime
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Government of Tamil Nadu

First Edition - 2019
Revised Edition - 2020, 2022, 2023

(Published under New Syllabus)

NOT FOR SALE

Content Creation

The wise
possess all

State Council of Educational Research

and Training
© SCERT 2019

Printing & Publishing

TamilNaduTextbook and Educational

Services Corporation
www.textbooksonline.tn.nic.in

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PREFACE

This book is the abridged and updated version of the curriculum to strengthen
the higher secondary education on par with the Global Standards and meet
the requirements of Industrial Standard 4.0 by providing skill-based learning
opportunities to promote holistic approach in technical education. The objectives
of this book on Basic Electronic Engineering are to shape the skill of understanding
and applying electronic concepts and ideas for designing, assembling, testing,
maintaining and troubleshooting basic and complex electronic gadgets.
Additionally, it covers the “Earn While Learn” concept for the students to pursue
their higher education with self-reliance and without financial hindrance.
This book covers the state-of-the-art techniques in the area of Electronics
and related fields to encourage the multidisciplinary approach of Electronics with
different subject areas. Each Chapter has been designed and written in such a way
to inculcate the basic and advanced knowledge of the Electronics to the students
and also to give opportunity to the stakeholders to provide a platform for exhibiting
their creativity. The success of this endeavor depends on the participation of the
students, subject teachers and school headmasters to kindle the students towards
self-learning in order to promote imaginative activities and inquisitiveness.
Each Chapter starts with specific learning objectives, learning outcomes
and detailed description of the concepts with the related figures, equations for
the easy and deep understanding of the subject matter. Further, several solved
problems and self-evaluation exercises are given in each Chapter to motivate the
students for self-learning and to develop self-confidence in the subject matter.

With best wishes,

Prof. Dr. Damodaran Nedumaran
Chairperson

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CONTENTS

Title Page No. Month

Chapter  1 Digital Circuit Applications 1-21 June

Chapter  2 Transmitters and Receivers 22-41 June - July

Chapter  3 C
 ommunication Devices and their
42-60 July
Technologies

Chapter  4 Communication Systems 61-77 August

Chapter  5 Digital Image Processing 78-95 September

Chapter  6 Sound Engineering 96-116 October

Chapter  7 Power Electronics 117-133 October

Chapter  8 Introduction to Biomedical Instruments 134-147 November

Chapter  9 C
 omputer Maintenance and
148-167 November
Troubleshooting with Safety Practices

Chapter 10 N
 etwork Maintenance-Troubleshooting
168-189 December
and IT Securities

Model Question Paper 190-192

Practical 193-250

E-book Assessment
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BASIC ELECTRONICS
ENGINEERING
Theory

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01

CHAPTER
Digital Circuit Applications

learning objective
The students can understand the 3. Encoder and Decoder
following in this chapter 4. Multiplexer
1. Construction and working of Basic 5. Flip-flops
Gates & Combinational Gates and 6. Counters and Registers
their applications.
2. Classification of Logic circuits

Introduction predefined voltage ranges (+5V and 0V).

These electronic switching circuits are
Though you are little familiar with digital
called as logic gates. Each logic gate can
electronics, its very important to learn
have one or more inputs and only one
about digital circuits, i.e., particularly the
output.
basic gates (AND, OR, NOT), the utility
of these circuits in constructing many All logic gates can be analysed by
discrete circuits for instrumentation constructing a truth table. A truth table
application are discussed in detail in this represents all possible input and the
chapter. Further, we are going to discuss corresponding output combinations.
about the combinational gates. The term “logic” is usually used to
refer to a decision making process. A logic
1. Logic Gates gate makes logical decisions regarding the
Logic gates are termed as digital circuits. existence of output depending upon the
Digital circuits operate in binary modes, nature of the input. Hence, such circuits
each input and output signal is either ‘1’ or are called logic circuits.
‘0’. The ‘1’ and ‘0’ designation represents

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1.1 Basic Logic Gates signal. The two input signal makes 4(22)
combination of outputs.
The three basic logic gates that makeup all
digital circuits are In OR gates, the output is high
when any one of the input is in high level.
i) OR gate, ii) AND gate and iii) NOT gate.
Conversely, the output is low when all the
The following points may be noted inputs are in low level.
about logic gates.
1 A binary ‘0’ represents 0V and binary 1.1.2 AND Gate
‘1’ represents +5V. It is common to An AND gate has two or more inputs and
refer to binary ‘0’ as LOW input or one output. An AND gate performs logical
output and binary ‘1’ as HIGH input multiplication. In an AND gates, the inputs
or output. A,B,C, etc., produce the output as A.B.C.
2. A logic gate has only one output and etc. The symbol and the truth table of two
the output will depend upon the input AND gate are shown in Figure 1.2.
input signals and the type of gates.
A
3. The operation of a logic gate may Y = A.B
be described either by truth table or B
Boolean algebra.
FIGURE 1.2 Symbol and Truth Table of AND Gate

1.1.1 OR Gate TABLE 1.2 AND Gate

An OR gate has two or more input signals A B Y= A⋅B
and only one output signal. An OR gate 0 0 0
performs logical addition. 0 1 0
1 0 0
In OR gate, the inputs A, B, C, etc., 1 1 1
produce the output as A+B+C+etc. The
symbol of two input OR gate is shown in It contains two input signals and only one
the Figure 1.1 and the Table 1.1 shows the output signal. In AND gates, the output is
truth table output. only high when all inputs are in high level.
Conversely, the output is low only when
A any one of the input is in low level.
Y=A+B
B 1.1.3 NOT Gate
FIGURE 1.1 Symbol and Truth Table of OR Gate A NOT gate has only one input and one
TABLE 1.1 OR Gate output. For the NOT gate, when the input
A B Y= A+B is ‘0’(LOW), the output is ‘1’ (HIGH)
0 0 0 and when the input is ‘1’ (HIGH), the
0 1 1 output is ‘0’ (LOW). That is, the output is
1 0 1 complement or inverse of the input.
1 1 1 Figure 1.3 shows the symbol and
truth table for the NOT gate. The input
A two input OR gate contains
is marked as A and the output is marked
two input signals and only one output
as Y=Ā. The output Ā can be read as

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complement of A or inverse of A or simply Operation of a NAND – gate

A bar. A NAND gate produces low output when
A Y=Ā
all the inputs are high. When any of the
input is low, the output will be HIGH.
Figure 1.4 shows a 2-input NAND gate
FIGURE 1.3 Symbol Table 1,3 exhibits the input-
with the inputs labelled as A and B and
output relation of a NOT gate
the output is labelled as Y. The operation
TABLE 1.3 NOT Gate can be stated as follows.
A Y=Ā
0 1
For a 2-input NAND gates, the output Y is
1 0
low only when, inputs A and B are HIGH.
Output ‘Y’ is HIGH when either A or B is
1.1.4 Application of Basic Gates low, or when both inputs A and B are low.
NOT – Gate Application - Example of 1’s
Complement circuit using inverters. The operation of a NAND gate
is opposite to that of a AND gate. In a
AND – Gate Application - A simple Car-
NAND gate, low-level (0) is the active
seat belt alarm circuit using AND Gate
output level, as indicated by the bubble
OR – Gate Application - Simple intrusion on the output. Table 1.4 shows the logical
detection alarm system operation of the 2 input NAND gate. The
logic expression for two input NAND gate
1.2 Combinational Gates is Y = A ⋅ B .

Now, let us see some of the other gates

constructed by using these basic gates, TABLE 1.4 Truth table of NAND gate
which are called as combinational gates. The A B Y = A⋅B
following are some of the important gates.
0 0 1
1. NAND Gate 3. EX-OR Gate
0 1 1
2. NOR Gate 4. EX-NOR Gate 1 0 1
1 1 0
1.2.1 NAND gate
The term NAND is derived from NOT- Application: NAND gate with its
AND gates. It is nothing but complemented two inputs connected to the tank level
output of AND gate. The standard logic sensor
symbol for 2-input NAND gate is shown
Figure 1.4.
1.2.2 NOR - gate
A

B
Y = A •Β The NOR–gate is derived from the
combination of NOT-OR gate. It is nothing
A but complemented output of OR gate. The
Y = A •Β
B standard logic symbols for 2-input NOR
gate is shown in Figure 1.5.
FIGURE 1.4 Symbol and Equivalent circuit of
2-input NAND gate
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derive the operations of any other gates

A
Y = A+B function.
B

2–input NOR gate

1.2.3 Exclusive-OR gate

A Exclusive-OR gate is formed by a

Y = A+B
B combination of the earlier gates that we
Equivalent circuit of NOR gate
discussed so far. These gates are used
in many fundamental applications and
FIGURE 1.5 Symbol and Equivalent Circuit of
treated as basic logic elements. Standard
NOR gate symbol for Exclusive OR (XOR as short)
gate is shown in Figure 1.6.
Operation of a NOR-gate The XOR gate has only two inputs.
A NOR-gate produces a LOW output when The output of XOR gate is HIGH, only
any of its input is HIGH. The output will be when the inputs of the gates are in opposite
HIGH when all the inputs are LOW. Figure logic levels. The output of the gate is low
1.5 shows the NOR gate labelled A and B are when the inputs are identical i.e., both are
inputs and Y as the output. The operations LOW or HIGH.
can be stated as follows.
A
For a 2-input NOR gate, output Y is LOW, when Y = A⊕Β
either input A or input B is HIGH or the output B
Y is HIGH only when both inputs are LOW.
FIGURE 1.6 Symbol of Ex-OR gate

The operation of NOR gate is

For an XOR gate the output Y is
opposite to that of OR gate. In a NOR gate,
HIGH only when inputs A is low and
the low output is the active output level
B is HIGH and vice versa. It will be
as indicated by the bubble on the output.
LOW on other conditions. The unique
Table 1.5 shows the logical operation of the
characteristic of XOR gate is that it
2-input NOR gate. The logic expression
produces HIGH output only when an odd
for two input NOR gate is Y = A + B .
number of HIGH inputs are present.
TABLE 1.5 Truth Table of NOR gate
TABLE 1.6 Truth table of XOR gate
A B Y = A+B
A B Y ( A B) ( A B)
0 0 1
0 0 0
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0 1 1 0

Universal gate The logical expression for XOR-gate

NAND and NOR gates are termed as Y ( A B) ( A B) . This can be often
universal gates. Because by using these shortened and given as Y = A ⊕ B . It is
gates (either NAND or NOR), we can also called as “Inequality Comparator”.
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1.2.4 Exclusive -NOR GATE 1.3 Boolean algebra

The standard symbol for Exclusive–NOR Though you have studied three important
(X-NOR) gate is shown in Figure 1.7. basic Boolean operations Addition (OR),
The bubble on the output of the X-NOR multiplication (AND), complementation
symbol indicates that its output is opposite or inversion (NOT). Other than these,
to that of the XOR gate, i.e., the output is there are three important basic laws as
complemented XOR gate. like in mathematical algebra. They are,
For an exclusive-NOR gate (X-NOR), output Y is 1. Commutative law
low when input A is LOW and input B is HIGH, 2. Associative law
or when A is HIGH and B is LOW. Y is HIGH
only when both A and B are HIGH or both LOW 3. Distributive law

The Boolean is used to simplify the gate

A (digital) circuits
Y = A⊕Β
B
FIGURE 1.7 Symbol of X-NOR
Boolean algebra was derived by
Table 1.7 shows the logical operation George Boole in 1854
of a two-input X-NOR gate. The
logical expression for X-NOR gate is
=Y ( AB ) + ( AB ) .
This can be often 1.3.1 Commutative law
standard and given as Y = A ⊕ B. The law by addition and multiplication
say that the order in which variable are
TABLE 1.7 Truth table of Ex-NOR gate OR-ed (or) AND-ed makes no different as
A B Y = A⊕ B the sum assured is arrived at either way.
These laws of addition and multiplication
0 0 1 for two variables are written algebraically
0 1 0 as follows.
1 0 0 Commutative law of addition of
1 1 1 two variables
A+B = B+A
Though NAND and NOR gates are called as
Commutative law of multiplication
universal gates, among them NAND gate is
for two variables
more versatile. So far, we have learned seven
types of gate circuits consisting AND, OR, A.B=B·A
NOT, NAND, NOR, XOR and X-NOR. We Figure 1.8 and Figure 1.9 illustrate the
can buy IC’s that perform any of these seven commutative law applied to the OR gate
basic functions. But, in the market NAND and the AND gate.
gate is the more widely available IC.
A B
Activity B
A+B
A
B+A

Write the Boolean expression for a three

Application of commutative law of addition.
input NAND gate. FIGURE 1.8 Commutative law using OR gate

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A B
AB BA
B A

FIGURE 1.9 Commutative law using AND gate

1.3.2. Associative law

The law of addition and multiplication say that the ORing or ANDing of several variables
(more than two) or grouping of the variables is immaterial and the addition results
obtained are the same. These laws of addition and multiplication for three variables are
written algebraically as follows. Figure 1.10 and Figure 1.11 illustrate the associative law
as applied to OR and AND gates.
Associative law of addition of three variables A + (B + C) = (A + B) + C
A A
A+(B+C) A+B
B
B
B+C (A+B)+C
C C
FIGURE 1.10 Associate law of three variables using OR gates

Associative law of multiplication of three variables A . (B . C) = (A . B) . C

A A
A(BC) AB
B
B
BC (AB)C
C C

FIGURE 1.11 Associate law of three variables using AND gates

1.3.3. Distributive law

This law states that ORing several variables and ANDing the result with the single variable
is equivalent to ANDing the single variable with each of several variables and the ORing
the products. The law is algebraically written as follows.
A · (B + C) = A . B + A · C
B A
B+C AB
C B

X X
A
A
AC
X = A(B+C) C

X = AB+AC

FIGURE 1.12 Distributive law using AND and OR gates

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1.3.4 Boolean Algebra Rules 1.4.2 Sequential Logic Circuit

The table 1.8. shows the Boolean Algebra It accepts input binary variables and
Rules. generates output variables depending on
the logical combination of logic gates. The
TABLE 1.8 Boolean Algebra Rules
combinational logic circuits with memory
1. A + 0 = A 7. A · A = A
element is called as sequential logic circuit,
2. A + 1 = 1 8. A · A = 0 which is shown in Figure 1.14.
3. A · 0 = 0 9. A = A Input Output

4. A · 1 = A 10. A + B = B + A Combinational
logic circuit
5. A + A = A 11. A ∙ B = B ∙ A Positive
feedback
Previous
6. A + A = 1 12. A ∙ (B +C ) = A ∙B + state
A∙C) Memory Clock
signal

1.4 Classification of Logic FIGURE 1.14 Block Diagram of Sequential Logic

Circuit
circuit
A combinational circuit connected with
Logic circuit may be classified into two feedback path termed as memory elements.
broad categories: The memory elements are device, capable of
1. Combinational logic circuits storing binary information within them.
2. Sequential logic circuits
1.5 Arithmetic Circuits
1.4.1 Combinational Logic One of the essential functions of most
circuits computers and calculators is the performance
of manipulating the arithmetic operations.
A combinational logic circuit contains
The logic gates discussed so for can be used
logic gates only but does not contain storage
to perform arithmetic operations such
elements. Sequential logic circuit contains
as addition, subtraction, multiplication
storage elements in addition to logic gates.
and division, which is used in electronic
When logic gates are connected together
calculators and digital instruments. Since
to provide a specified output for certain
these circuits are electronic, they are very fast.
specified combination of input variables
Performing an addition takes less than 1 µs.
without any storage, the resulting network
is known as combinational logic circuit. Now we will discuss some of the
The block diagram of logic combinational arithmetic operating circuits such as Half–
circuit is shown in Figure 1.13. adder, full-adder, parallel binary adder,
half-subtractor and full-subtractor. The
logic functions that are commonly used
are OR, AND, and EX-OR gates.
Inputs Combinational Outputs
(X) circuit Z = f(X)
1.5.1 Half-Adder
A logic circuits used for the addition of two
FIGURE 1.13 Combinational Logic Circuit
single bit numbers is referred as a Half-
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Adder. When we add two binary numbers, From the truth table a half-adder,
we start with the least significant column. the logical equations for CARRY and SUM
This means that we have to add two bits can be written as,
with the possibility of a carry. The circuit
CARRY C = A . B
of a half-adder is shown Figure 1.16(a).
Note in the Figure that the output sum is SUM S = A ⋅ B + A ⋅ B = A ⊕ B
denoted by the mathematical symbol Σ.
This Circuit is called as half-adder,
∑= A  B= AB + AB because it cannot accept a CARRY-IN
from previous additions. This is the
reason that half-adder circuits can be used
A
Cout=AB for binary additions of lower cost bit only.
B
For higher order columns, we use 3-input
FIGURE 1.15(A) Half-Adder adder called full-adder.

A  Sum 1.5.2 Full Adder
Input bits Outputs
Full adder circuit is nothing but two half–
B Cout Carry
adder circuits connected to an OR gate. As
we seen in half -adder circuit, it has only
FIGURE 1.15(B) Logic symbol for a half-adder two inputs and there is no provision to add
CARRY coming from the lower-bit order
It consists of an EX-OR gate and an AND when multi-bit addition is performed. For
gate. The output of an EX-OR gate is this purpose, we use a logic circuit, which
called SUM, while the output of the AND can add three bits.
gate is called as CARRY. As the AND gate A AB
generates a high output only, when both B
= (A  B) Cin
Cin
inputs are high i.e., the carry as 1. When
both inputs of EX-OR gate is high or low (A  B)Cin

the output i.e., the sum is low (0). When Cout = AB+(A  B)Cin
either of the input is high the output is AB
high. Thus its the binary addition. The
logic symbol of Half-adder is shown in (a) Complete logic circuit for a full-adder
Figure 1.15 (b). Truth table for a half

adder is given in the Table 1.9. A
Input bits  Sum
TABLE 1.9 Truth-Table of Half-Adder B
A B Σ C out Cout Output carry
0 0 0 0 Input carry Cin

0 1 1 0
(b) Logic symbol of full-adder
1 0 1 0
(each half-adder is enclosed by a shaded area)
1 1 0 1
Σ = sum FIGURE 1.16 A simple circuit of full adder (each
C out = output carry half-adder is enclosed by a shaded area)
A and B = input variables (operands)

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The third-bit is the CARRY from a numbers are to be added, there can be full-
lower column. This shows that we used a adder circuit for every column to perform
logic circuit with 3-inputs and 2-outputs. the addition. The number of full-adder
Such a circuit is called full-adder. Hence, in a parallel binary adder depends on the
full adder may be defined as logic circuits number of bits present in the number for the
that add 3-bits, i.e., two bits to be added addition. If 4-bit numbers are to be added,
and CARRY-bit from lower-bit order, which then there will be 4-full adder in the parallel
results in SUM and CARRY. Figures 1.16(a) binary adder. The parallel binary adder can
and (b) show the logic circuit and logic be designed with the help of basic logic
symbol of full-adder circuit, respectively. It gates. The sub-module in the logic circuit
has two inputs called A and B plus a third will resemble the logic gate of half-adder
input (CIN), called the CARRY IN and two and full-adder to understand it clearly. Let
outputs SUM and CARRY OUT(COUT). us put light on designing and working of the
Truth table of full-adder for all 2-bit parallel binary adder.
possible inputs/outputs is given in Table 1.10
Logic Circuit of 2-Bit parallel
and can be easily checked for its validity.
From the Figure 1.16(a), we can observe Binary Adder
that the output CARRY is high when two or The 2-Bit parallel binary adder can be
more number of inputs are high. Yet another designed with the help of Ex-OR gate and
output SUM will get high output, when an AND gate. If you carefully observe the logic
odd number of inputs are high. This can be circuit of 2-bit parallel binary adder, you can
verified from Table 1.10. The full adder can notice that 2-full adder circuits are connected
do more than a million additions per second. in a parallel manner. Now, we easily guess
and understand the working of this.
TABLE 1.10 Truth Table of Full-Adder Carry bit from
A B Cin Σ C out right column
1
0 0 0 0 0 11
0 0 1 1 0 In this case, the +01
0 1 0 1 0 carry bit from 100
second column
0 1 1 0 1 becomes a sum bit.
1 0 0 1 0
FIGURE 1.17(a) Addition of 2 parallel bits
1 0 1 0 1
A2 B2 A1 B1
1 1 0 0 1
1 1 1 1 1
Cin = input carry, sometimes designated as CI
C out = output carry, sometimes designated as Co 0
Σ = sum A B Cin A B Cin
A and B = input variables (operands)
FA2 FA1
Cout  Cout 
Parallel Binary Adder
The parallel binary adder is a combinational (MSB) 3 2 1 (LSB)
circuit of various full-adders in parallel
structure. When more than one 1-bit FIGURE 1.17(b) Block Diagram of 2-bit Parallel
Adder

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Figure 1.17(a) shows the method of 2-bit 1.5.3 Half-Subtractor

parallel addition and Figure 1.17(b) shows Half Subtractor is a digital circuit which
the schematic block diagram of the same. process the subtraction of two 1-bit (0,
As we know, from the difference between 1) numbers. In this, the two numbers
the half-adder and full-adder, that the involved are called as Minuend and
half-adder is a logic circuit which adds Subtrahend nothing but the inputs, named
two 1-bit circuits but, does not add carry as X and Y. X is the Minuend and Y is the
from previous addition. Therefore, full- Subtrahend. There are two outputs named
adders came into action. A full-adder as D (differences) and B (Borrow). The
can add two 1-bit numbers along with the word ‘HALF’ before the subtractor signifies
carry from previous addition. that it deals with only two 1-bit numbers,
Coming back to the parallel binary it has nothing to do with the borrow from
adder, it also has two full-adders. When the previous stage. Figure 1.18 clearly
we start add two numbers, the first step elaborates the subtraction rule of binary
we follow is the addition of LSB (Least numbers. The logic circuit of the Half-
Significant Bit) of two numbers. After Adder is shown in Figure 1.19(a) and the
this, if we have any carry, we forward it symbol is shown in Figure 1.19(b). The
to higher order columns. Now, the adder operation of this logic circuit is based on
performs the similar task. It adds the LSBs the rules of binary subtraction given in
of both the numbers and if any carry bit is truth table (Table 1.11) reproduce on the
there, it passes it to the carry-in terminal basis of subtraction process.
of another.
We may use half-adder for the Procedure for Subtraction
addition of LSBs of both numbers as for
1
the addition of LSBs there is no previous
carry from previous addition. But, for the 0 0 1 1
addition of bits present in higher order -0 -1 Borrow 1 ___
-0 _ ___
-1
____ ____
column, we must use full-adder because
0 1 1 0
there may be or may not be a carry from
previous addition.
FIGURE 1.18 Binary Subtraction Rules

A
Significance of Parallel Binary D
B A
Adder
With the help of full-adder, we cannot
Bo B
add numbers of more than 1-Bit. As the
number of bits increases in a number, the
FIGURED1.19 (A) Half Subtractor Circuit
+DOIVXEWUDFWRUFLUFXLW E 6
column of addition also increases. A full-
adder can Aadd only one column, thus for
D
each columnB we used a full-adder. This A D
combined design of all full adder results Half
subtractor
in a combinational circuit, which is called B Bo
Bo
parallel binary adder.
FIGURE 1.19 (B) Symbol of Half Subtractor
D +DOIVXEWUDFWRUFLUFXLW E 6\PERORI+DOI6XEWUDFWRU
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Circuit of Half-Subtractor a borrow from the previous bit position

The logic circuit of Half-Subtractor involves may also be there.
usage of logic circuits. In order to design It has 3-inputs viz., X (minuend),
logic circuit, we should understand two B (subtrahend) and Bin (borrow from the
concepts. First, the difference operation previous stage). It has two outputs such as
of half-subtractor resembles operation of D (difference) and B out (borrow) as shown
EX-OR gate. Thus, we can easily utilise in the symbol given in Figure 1.21(a)
the EX-OR gate for generating difference
bit. Similarly, the borrow generated by A D
half-subtractor can be easily obtained by Full
B subtractor
using the combination of NOT gate and
AND gate. Bin Bo

TABLE 1.11 T
 ruth Table of Half- FIGURE 1.20 (A) Symbol of Full-Subtractor
Subtractor
Input Output
A 0
A B Difference Borrow
0 0 0 0 B 0 0
Difference
0 1 1 1 C 0

1 0 1 0 borrow
0
1 1 0 0

FIGURE 1.20 (B) Circuit diagram of Full Subtractor

Truth Table of Half-Subtractor
In case of half subtractor there are two Full-Subtractor is formed by using
inputs. Thus the number of possible two half-subtractors and one OR gate.
combinations will be 4. The resultant of all Figure 1.21(b) shows the circuit diagram
the 4 inputs will be described as outputs. of Full-Subtractor. For subtraction of
The output of half-subtractor is described in n-bit numbers directly, we have to cascade
two columns. One will signify the difference n-full-subtractors. Truth table for full-
bit and another will signify the borrow bit. subtractor is given in Table 1.12.
To derive the truth table, just use the EX-
OR operation of two inputs for generating TABLE 1.12 Truth Table of Full-Subtractor
difference and NOT followed by AND A B C Difference Borrow
operation for generating the borrow bit. 0 0 0 0 0
0 0 1 1 1
1.5.4 Full-Subtractor 0 1 0 1 1
The binary subtraction half-subtractor 0 1 1 0 1
can handle only 2-bits at a time and can 1 0 0 1 0
be used for the least significant column 1 0 1 0 0
of a subtraction problem. Just like a full- 1 1 0 0 0
adder, a full-subtractor circuit is required
1 1 1 1 1
to perform a multi-bit subtraction, where

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1.6 Comparators
A0
LSBs G1
The basic function of comparator is to B0
A=B
compare the magnitudes of two binary HIGH indicates
quantities to determine the relationship of MSBs
A1
B1
G2
quality.

those quantities. General format: Binary number A  A1A0

Binary number B  B1B0

1.6.1 Equality
FIGURE 1.22 Logic diagram for equality
The Exclusive NOR gate can be used as comparison of two 2-bit numbers
a basic comparator, because its output is
In order to produce a single output
0, if the two input bits are not equal and
indicating an equality or inequality of two
1, if the input bits are equal. Figure 1.21
numbers, an AND gate can be combined
shows the Exclusive-NOR gate as 2-bit
with XNOR gates as shown in Figure 1.22.
comparator.
The output of each Exclusive-NOR gate
is applied to the AND gate input. When
0 1 TheExclusive-NOR
input bits
1 The input bits the two input bits for
0 each
0 are equal 0 are not equal
gates are equal, the corresponding bits of
the numbers are equal and a 0 appears
on at least one input of the AND gate
0 1 The input bits
0 The input bits to produce a 1 on 1its output. Thus, the
1 are not equal 1output of the AND gateare equal
indicates equality
(1) or inequality (0) of the two numbers.
1 The following example clearly explains
put bits 0 The input bits
ual 0 are not equal this operation for two specific cases.

Activity
put bits 1 The input bits
1 are equal Repeat the process for binary inputs of 01
ot equal 1 and 10.

FIGURE 1.21 Basic Comparator Operation Note

To compare two binary-bits The basic comparator can be expanded to
containing two bits each, an additional any number of bits. The AND gate sets
Exclusive-NOR gate is necessary. The the condition that all corresponding bits of
two least significant bits (LSBs) of the the two numbers must be equal if the two
two numbers are compared by gate G1, numbers themselves are equal.
and the two most significant bits (MSBs)
are compared by gate G2, as shown in 1.6.2 Inequality
Figure 1.22. If the two numbers are equal,
their corresponding bits are the same and In addition to the equality output, many
the output of each Exclusive-NOR gate is IC comparators provide additional
1. If the corresponding sets of bits are not outputs that indicate which of the two
equal, a 0 occurs on that Exclusive-NOR binary numbers being compared is larger.
gate output. That is, there is an output that indicates

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when number A is greater than number B indication must take precedence. This can
(A > B) and an output that indicates when be explained through an example.
number A is less than number B (A < B),
as shown in Figure 1.23. Activity
What are the outputs when A3A2A1A0 =
COMP 1001 and B3B2B1B0 = 1010?
A0 0
A1
A 1.7 Encoders
A2 A>B
Encoder is a device, circuit, transducer,
A3 3
A=B software program, algorithm or person
B0 0 that converts information from one format
B1 A<B or code to another for the purpose of
B standardisation or compression. An encoder
B2
is a combinational logic circuit that essentially
B3 3 performs a “reverse” decoder function. An
encoder accepts an active level on one of its
FIGURE 1.23 Logic symbol for a 4-bit comparator inputs representing a digit, such as a decimal
with inequality operation or octal digit and converts it to a coded
output, such as BCD or binary. Encoders can
To determine the inequality of binary also be devised to encode various symbols
numbers A and B, we first examine the and alphabetic characters. The process of
highest order bit in each number. The converting from familiar symbols or numbers
following conditions are possible: to a coded format is called encoding.
1. If A3 = 1 and B3 = 0, number A is greater
than number B. 1.7.1 Decimal-to-BCD Encoder
2. If A3 = 0 and B3 = 1, number A is less This type of encoder has ten inputs. One
than number B. for each decimal digit and four outputs
3. IF A3 = B3, then you must examine corresponding to the BCD code as shown
the next lower bit position for an in the Figure1.24. This is a basic 10-line-
inequality. to-4-line encoder.

DEC/BCD
These three operations are valid 0
for each-bit position in the numbers. The 1
general procedure used in a comparator is 2
3 1
to check for an inequality in a bit position, Decimal 4 2 BCD
starting with highest order bits (MSBs). input 5 4 ouput
6 8
When such an inequality is found,
7
the relationship of the two numbers is 8
established and any other inequalities in 9

lower-order bit positions must be ignored

because it is possible for an opposite FIGURE1.24 Logic symbol for a Decimal-to-BCD
indication to occur, the highest-order encoder

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The BCD (8421) code is listed 1

A0 (LSB)
in Table1.13. From this table, you can 2
determine the relationship between each 3
BCD bit and the decimal digits in order to A1
analyse the logic. For instance, the most
significant bit of the BCD code, A3, is always 4
5 A2
1 for decimal digit 8 or 9. An OR expression 6
7
for bit A3 in terms of the decimal digits can
8
therefore be written as A3 = 8 + 9. A3 (MSB)
9
TABLE 1.13 Decimal to BCD Encoder
BCD Code FIGURE 1.25 Basic logic diagram of Decimal-to-
BCD encoder.
DECIMAL
A3 A2 A1 A0
DIGIT
Note
0 0 0 0 0
A 0-digit input is not needed because the
1 0 0 0 1
BCD outputs are all low, when there are no
2 0 0 1 0
HIGH inputs.
3 0 0 1 1
4 0 1 0 0 The basic operation of the circuit shown in
5 0 1 0 1 Figure 1.25 is briefly described as follows:
6 0 1 1 0 When a HIGH appears on one of the decimal
7 0 1 1 1 input lines, the appropriate levels occur on
8 1 0 0 0 the four BCD output lines. For instance,
9 1 0 0 1 if input line 9 is HIGH (assuming all other
input lines are LOW), this condition will
Bit A2 is always 1 for decimal digit produce a HIGH on outputs A0 and A3 and
4, 5, 6 or 7 and can be expressed as an OR LOWs on outputs A1 and A2, which is the
function as follows: BCD code (1001) for decimal 9.
A2 = 4 + 5 + 6 + 7
1.8 Decoders
Bit A1 is always 1 for decimal digit 2, 3, 6
or 7 and can be expressed as An electronic device that converts signals
from one form to another i.e., code into
A1 = 2 + 3 + 6 + 7
set of signals. Decoding is the process
Finally, A0 is always for decimal digit 1, 3, of converting code into plain text or
5, 7 or 9 any format that is useful for subsequent
A0 = 1 + 3 + 5 + 7 + 9 processes. It does the reverse of encoding.
Now, let us implement the logic circuitry It converts encoded data communicated
required for encoding each decimal during transmission (like TV signals from
digit to a BCD code by using the logic satellite and Computer e-mails) and files
expressions just developed. It is simply a to their original states.
matter of ORing the appropriate decimal In digital electronics, a binary
input lines to form each BCD output. The decoder is a combinational logic circuit
basic encoder logic resulting from these that converts binary information from
expressions is shown in Figure 1.25. the ‘n’ coded inputs to a maximum of 2n
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(LSB)
1 A0
1 A1
0 A1

1 X = A3A2A1A0

0 A2
1 A2
1 A3
(MSB)
(a) (b)

FIGURE 1.26 Decoding logic for the binary code 1001 with an active-HIGH output

unique outputs. They are used in wide AND can be used as the basic decoding
variety of applications, including data element because it produces a HIGH output
demultiplexing, seven segment displays only when all of its inputs are HIGH.
and memory address decoding. Therefore, we must make sure that all of
the inputs to the AND gate are HIGH when
1.8.1 Basic Binary Decoder the binary number 1001 occurs. This can
We need to determine when a binary 1001 be done by inverting the two middle inputs
occurs on the inputs of a digital circuit. An (the 0s), as shown in Figure 1.26.

EXAMPLE 1.1 1.9 Multiplexer

Determine the logic required to decode the
A multiplexer (MUX) is a device allowing
binary number 1011 by producing a HIGH
one or more low speed analog or digital
level on the output.
signal to be selected, combined and
transmitted at a higher speed on a single
Solution
shared medium or within a single shared
The decoding function can be formed by device. A MUX function is a multiple-
complementing only the variables that input, single-output switch.
appear as 0 in the desired binary number
as follows: Multiple signals share one device or
transmission conductor such as copper or
X = A3 A2 A1 A0 (1011) fibre optic cable. In telecommunication,
This function can be implemented by the analog or digital signals transmitted
connecting the true (un-complemented) on several communication channels by
variables A0, A1 and A3 directly to the inputs a multiplex method. These signals are
of an AND gate and inverting the variables single-output higher-speed signals. A
A2 before applying it to the AND gate input. 4-to-1 multiplexer contains four input
The decoding logic is shown in Figure 1.27. signals and 2-to-1 multiplexer has two
A0 input signals and one output signal.
A1
A2
X = A3A2A1A0 A logic symbol for a 4-input
A2
multiplexer (MUX) is shown in Figure 1.28.
A3
Notice that there are two data-select lines
FIGURE 1.27 Decoding logic for producing a because with two select bits, any one of the
HIGH output when 1011 is on the inputs. four data-input lines can be selected.
CHAPTER 01 Digital Circuit Applications 15