EC 201 Basic Electronics

Instructor: Tarun Tripathi School of Electronics Engineering KIIT University

Logic Gates
Logic gates are electronic circuits that operates on one or more input signals to produce an output signal
AND Gate
x z = x.y y
x z=x+y y

OR Gate
x

NOT Gate
z = x

x 0 0

y 0 1

x.y 0 0

x 0 0

y 0 1

x+y 0 1

x 0 1

x 1 0

1
1

0
1

0
1

1 1

0 1

1 1
2

Switching Circuit

x x Voltage source y Lamp z Voltage source y Lamp z

Switches in series logic AND

Switches in parallel logic OR

NOR Gate
NOR Symbol, Equivalent Circuit, Truth Table

NAND Gate
A B Y

This is a NAND gate. It is a combination of an AND gate followed by an inverter. Its truth table shows this
A 0
0

B 0
1

Y 1
1

1
1

0
1

1
0

XOR Gate (Exclusive-OR)

A B Y

This is a XOR gate. The switching algebra symbol for this operation is , i.e. AB. A B=AB+AB.

A 0
0 1 1

B 0
1 0 1

Y 0
1 1 0

XNOR Gate (Exclusive-NOR)

A B

This is an Exclusive-NOR gate The complement of the XOR gate. The switching algebra symbol A for this operation is , i.e. 0 A B. 0 A B=AB+AB.
1
1

B 0 1 0
1

Y 1 0 0
1

 NAND, NOR gates are called universal gate.

AND, OR and NOT are called basic gates. XOR(EX-OR), XNOR(EX-NOR) are called derived gates.

S-R Latch with NOR Gates

R (reset)
Q(t+1)
S R Q(t+1) 0 1 0 1 0 0 1 1
Q(t) Memory 1 Set State 0 Reset State Undefined state

S (set)

Q(t+1)

S-R latch made from cross-coupled NORs If Q = 1, set state If Q = 0, reset state Usually S=0 and R=0 is called Memory state S=1 and R=1 generates undefined or indeterminate results.

S-R Latch with NAND Gates

S Q(t+1)
S R 1 0 1 0 1 1 0 0 Q(t+1)
Q(t) Memory 1 Set state 0 Reset state Undefined state

Q(t+1)

S-R Latch made from cross-coupled NANDs Sometimes called S-R latch Usually S=1 and R=1 is called Memory state S=0 and R=0 generates undefined or indeterminate results.

S-R Latches

Graphic symbol of S-R Latch

Q(t+1)

Q(t+1)

S-R Latch with control input

S-R Latch with control input is called Flip-Flop It is used to store one bit of information Occasionally, desirable to avoid latch changes C = 0 disables all latch state changes Control signal enables data change when C = 1 Right side of circuit same as ordinary S-R latch.

Clocks and synchronization

A clock is a special device that whose output continuously alternates between 0 and 1.
clock period

The time it takes the clock to change from 1 to 0 and back to 1 is called the clock period, or clock cycle time. The clock frequency is the inverse of the clock period. The unit of measurement for frequency is the hertz.

Graphic symbol of S-R Flip-Flop

Q(t+1)

Q(t+1)

J-K Flip-Flop

S-R Latch with control input is called Flip-Flop Replace the two input NAND gate with the three input NAND gate to get a J-K Flip Flop from a S-R FF. C = 0 disables all the data changes Control signal C=1 enables data change when C = 1

Flip-Flops
A flip-flop is a state of a latch that can be switched by momentary change in the control input. This momentary change is called a trigger and the transition it causes is said to trigger the flip-flop.
The flip-flop is triggered every time the pulse goes to a high or logic level 1.

Response to positive level(Level Triggering)

The problem with the flip-flops is that as long as the input clock pulse remains at this level, any changes in the input data will cause a change in the output and the state of the latch.
Race around condition or Racing.

Master Slave J-K Flip-Flop

The Solution
A clock pulse goes through two transition from 0 to 1 and the return from 1 to 0 The solution: by changing the operation of a flip-flop to trigger it only during a signal transition.
Two types of transition: the positive transition (from 0 t0 1) and the negative transition (from 1 to 0)

Positive-edge response

Negative-edge response

Flip-Flop Symbols
Input Input Q Q

Positive Edge Triggered Flip Flop

Negative Edge Triggered Flip Flop

J-K flip flop Symbols

Positive-edge Triggered FF

Negative-edge Triggered FF

D-Flip Flop
S

D C

Q
Y
D 0 1 X R

C
1 1 0

Q 0 1 Q0 (Memory)

Input value D is passed to output Q when C is high Input value D is ignored when C is low

Clocked D Flip-Flop
Stores a value on the positive edge of C Input changes at other times have no effect on output

Clocked J-K Flip Flop

Two data inputs, J and K J -> set, K -> reset, if J=K=1 then toggle output

Characteristic Table

Registers
A flip-flop can store only one bit data (0 or 1)
A single-bit register

Register consists of a group of flip-flops and gates

An n-bit register consists of n-bit flip-flops store n-bit information Shift register is used to store and shift data.

Types of Shift Register

Serial in serial out (SISO) Serial in Parallel out (SIPO) Parallel in serial out (SISO) Parallel in Parallel out (SISO)

Shift Registers(SISO)

Shifts binary information in one or both directions. On the positive edge of the first clock pulse, the signal on the in is latched in the first FF.
On the next clock pulse, the data of the first FF is stored in the second FF, and the data present at the in is stored is the first FF, etc.

Counters
Binary counter: sequence. follows the binary number

An n-bit binary counter:

Consists of n flip-flops Can count in binary from 0 to 2n - 1

A counter is a register that goes through a sequence of states.

Counters
Counter categories:
Ripple counters

Synchronous counters Ripple counters: The flip-flops output transition triggers other flip-flops. Synchronous counters: A common clock triggers all flip-flops simultaneously rather than one at a time in succession as in ripple counters.

Binary Ripple Counter

All the J and K inputs of all the flip-flops are connected to a logic 1.

Each flip-flop complement if the signal in its C input goes through a negative transition. The flip-flop holding the LSB receives the incoming count pulses.
The count starts with binary 0 and increments by one with each count pulse input.

3-bit Binary Ripple Counter

Q2
0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 Q1 0 1 0 1 0 1 0 1 0 Q0

Q0 is complemented with the count pulse. Since Q0 goes from 1 to 0, it triggers Q1 and complements it. As a result, Q1 goes from 1 0, which in turn complements Q2 changing it from 0 1. Q2 does not trigger Q3 because Q2 produces a positive transition. The flip-flops change one bit at a time in succession and the signal propagates through the counter in a ripple fashion from one stage to the next.

4-bit Binary Ripple Counter

J
Count C Q1

K
J C K J C

Q2

Q3

K J
C Logic-1

Q4

4-bit Binary Ripple Counter

Problems with Ripple Counter

Asynchronous or ripple counters are arranged in such a way that the output of one flip flop changes the state of the next.
In a long chain of ripple counter stages, the last flip flop changes its state considerably later than the first FF due to propagation delays in each stage. Problems occur if this delay is longer than the response time of other logic elements connected to the circuit.

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