A B C D E

1 1

EAT20 (Sakhir 10GC)

2 LA-2492 Schematics Document 2

Intel Dothan / AlvisoPM / DDR-1 / ICH6-M / Select Bay

(nVIDIA NV43M & NV44M/ ATi M22 & M24)

2004 / 12 / 22 3

Rev:1.0

4 4

Compal Electronics, Inc.

Title
SCHEMATIC, M/B LA-2492
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
401317 B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: ¬P 期一, 一月 03, 2005 Sheet 1 of 51
A B C D E
 A B C D E

Compal confidential
File Name : LA-2492 Fan Control Intel Dothan CPU Thermal Sensor Clock Generator
page 4
ADM1032ARM ICS954226
page 4,5
CRT/TV-OUT
page 4 page 14
page 15
1
H_A#(3..31) FSB H_D#(0..63)
1

400 / 533 Mhz

NV44 / M24
VGA Board
page 16
Intel Alviso GM(PM) DDR-1(DDR-2) DDR-SO-DIMM X2
BANK 0, 1, 2, 3page 11,12,13
PCBGA 1257
LCD CONN page 6,7,8,9,10 Signal Channel DDR-1
page 16 Two Channel DDR-2

DMI
MARVELL LAN
RJ45 CONN 88E8036 PCI-E BUS USB 2.0 USB conn x 3 RJ11 CONN
2
page 28 88E8053 page 31 page 29 2
page 27

Intel ICH6-M USB 2.0 BT Conn

page 31
PCI BUS mBGA-609
AC-LINK Audio CKT Docking AMP & Audio Jack
ALC250-D Audiopage
page 17,18,19,20 page 30 31 page 32
Mini PCI
socket TI Controller PCI7421
page 29
page 23,24
SATA SATA to PATA PATA HDD
conn
88SA8040 SATA HDD
page 21 page 21
5in1 CardReader LPC BUS
3
13 94 Slot 0 3
Conn. Slot 1 Slot page 25
page 24 page 26 PATA MODULE
Connector Docking CONN.
32
page 22 *RJ-11 / 45(LED*2)
Power On/Off CKT. *COMPOSITE Video Out
*TVOUT
page 34
*LINE IN / OUT
SMsC LPC47N217 ENE KB910/910L *PS/2
page 34 page 35 *Print port
DC/DC Interface CKT. RTC CKT.
page 40 page 19
*1394
*USB
*DC JACK
Int. KBD
Power Circuit DC/DC Power OK CKT. Parellel Serial page 36

Port Port Touch Pad page 40

4 page 44~51 page 39 4
page 34 page 38 CONN. page 34
BIOS
page 37

Compal Electronics, Inc.

Title
SCHEMATIC, M/B LA-2492
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
401317 B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: ¬P 期一, 一月 03, 2005 Sheet 2 of 51
A B C D E
 A B C D E

SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Voltage Rails
Full ON HIGH HIGH HIGH HIGH ON ON ON ON

Power Plane Description S1 S3 S5 S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW

VIN Adapter power supply (19V) N/A N/A N/A S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
1 B+ AC or battery power rail for power circuit. N/A N/A N/A 1
S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF
+CPU_CORE Core voltage for CPU ON OFF OFF
+1.05VS 1.05V switched power rail ON OFF OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+DDRVTT 1.25V switched power rail for DDR terminator ON OFF OFF
+1.5VALW 1.5V always on power rail ON ON ON*
+1.5VS 1.5V switched power rail ON OFF OFF Board ID / SKU ID Table for AD channel
+1.8VS 1.8V switched power rail ON OFF OFF Vcc 3.3V +/- 5%
+DDRVCC 2.5V power rail for DDR ON ON OFF Ra/Rc/Re 100K +/- 5%
+2.5VS 2.5V switched power rail ON OFF OFF Board ID Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max
+3VALW 3.3V always on power rail ON ON ON* 0 0 0 V 0 V 0 V
+3V 3.3V power rail ON ON OFF 1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V
+3VS 3.3V switched power rail ON OFF OFF 2 18K +/- 5% 0.436 V 0.503 V 0.538 V
+5VALW 5V always on power rail ON ON ON* 3 33K +/- 5% 0.712 V 0.819 V 0.875 V
+5VS 5V switched power rail ON OFF OFF 4 56K +/- 5% 1.036 V 1.185 V 1.264 V
+5VCD 5V switched power rail for Direct CD ON OFF OFF 5 100K +/- 5% 1.453 V 1.650 V 1.759 V
2 2
+5VMOD 5V switched power rail for Module Bay ON OFF OFF 6 200K +/- 5% 1.935 V 2.200 V 2.341 V
+12VALW 12V always on power rail ON ON ON* 7 NC 2.500 V 3.300 V 3.300 V
+RTCVCC RTC power ON ON ON

BOARD ID Table
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
Board ID PCB Revision
External PCI Devices 0 0.1
Device IDSEL# REQ#/GNT# Interrupts 1 NC
C ardB us AD20 2 PIRQA/PIRQB 2 0.2
1 3 94 AD20 2 PIRQA/PIRQB 3 1.0
SD AD20 2 PIRQA/PIRQB 4
Mini-PCI AD18 1 PIRQG/PIRQH 5
6
7
3 3

EC SM Bus1 address EC SM Bus2 address SKU ID Table

Device Address Device Address SKU_ID_CHECK_1 7 6 5
Smart Battery 0001 011X b ADM1032 1001 110X b SKU_ID_CHECK_0 1-Button 3-Buttons 7-Buttons
EEPROM(24C16/02) 1010 000X b 2'nd Battery 1001 011X b 0 10 1 0
(24C04) 1011 000Xb Docking 1010 000X b 1 10C 3 12 2
2 10G 5 4
3 10GC 7 13 6
4 10J 11 10
ICH6M SM Bus address 5
6
Device Address
4 4
Clock Generator 1101 001Xb
( ICS 952623)

DDR DIMM0 1001 000Xb

DDR DIMM2 1001 001Xb
Compal Electronics, Inc.
Title
SCHEMATIC, M/B LA-2492
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401317
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: ¬P 期一, 一月 03, 2005 Sheet 3 of 51
A B C D E
 5 4 3 2 1

H_D#[0..63]
H_D#[0..63] 6
+3VS
JP7A

H_A #[3..31] H_A#3 P4 A19 H _D#0

6 H_A#[3..31]
H_A#4
H_A#5
U4
A3#
A4#
Dothan D0#
D1# A25 H _D#1
H _D#2
V3 A5# D2# A22 1

1
H_A#6 R3 B21 H _D#3
H_A#7 A6# D3# H _D#4 C12 R20
V2 A7# D4# A24
D H_A#8 W1 B26 H _D#5 0.1U_0402_16V4Z @ 10K_0402_5% D
H_A#9 A8# D5# H _D#6 2
T4 A9# D6# A21 1
H_A#10 W2 B20 H _D#7 C17

2
H_A#11 A10# D7# H _D#8 U3
Y4 A11# D8# C20
H_A#12 Y1 B24 H _D#9 2200P_0402_50V7K THERMDA 2 1
H_A#13 A12# D9# H_D#10 2 D+ VDD1
U1 A13# D10# D24
H_A#14 AA3 E24 H_D#11 THERMDC 3 6
H_A#15 A14# D11# H_D#12 D- ALERT#
Y3 A15# D12# C26
H_A#16 AA2 B23 H_D#13 8 4
A16# D13# 30,34,39 EC_SMB_CK2 SCLK THERM#
H_A#17 AF4 E23 H_D#14
H_A#18 A17# D14# H_D#15
AC4 A18# D15# C25 30,34,39 EC_SMB_DA2 7 SDATA GND 5
H_A#19 AC7 H23 H_D#16
H_A#20 A19# D16# H_D#17
AC3 A20# D17# G25
H_A#21 AD3 L23 H_D#18 ADM1032ARM_RM8
H_A#22 A21# D18# H_D#19
AE4 A22# D19# M26
H_A#23 AD2 H24 H_D#20
H_A#24 A23# D20# H_D#21
AB4 A24# D21# F25
H_A#25 AC6 ADDR GROUP DATA GROUP G24 H_D#22
H_A#26 A25# D22# H_D#23
AD5 A26# D23# J23
H_A#27 AE2 M23 H_D#24
H_A#28 A27# D24# H_D#25
AD6 A28# D25# J25
H_A#29 AF3 L26 H_D#26
H_A#30 A29# D26# H_D#27
AE1 A30# D27# N24
H_A#31 AF1 M25 H_D#28
A31# D28# H_D#29
D29# H26
H_REQ #[0..4] H_REQ#0 R2 N25 H_D#30
6 H_REQ#[0..4] REQ0# D30#
H_REQ#1 P3 K25 H_D#31
H_REQ#2 REQ1# D31# H_D#32 +1.05VS
T2 REQ2# D32# Y26
H_REQ#3 P1 AA24 H_D#33
C H_REQ#4 REQ3# D33# H_D#34 C
T1 REQ4# D34# T25
U23 H_D#35
D35# H_D#36
6 H_ADSTB#0 U3 ADSTB0# D36# V23
AE5 R24 H_D#37 ITP_TDI R508 2 1 150_0402_5%
6 H_ADSTB#1 ADSTB1# D37#
R26 H_D#38
D38# H_D#39 ITP_TDO R29
D39# R23 2 1 @ 54.9_0402_1%
A16 AA23 H_D#40
ITP_CLK0 D40# H_D#41 H_CPURST# R28
A15 ITP_CLK1 D41# U26 2 1 @ 54.9_0402_1%
V24 H_D#42
D42# H_D#43 ITP_TMS R27 40.2_0402_1%
14 CLK_CPU_BCLK B15 BCLK0 D43# U25 2 1
B14 HOST CLK V26 H_D#44
14 CLK_CPU_BCLK# BCLK1 D44#
Y23 H_D#45 PRO_CHOT# R31 2 1 56_0402_5%
D45# H_D#46
D46# AA26
Y25 H_D#47 H_PW RGOOD R24 2 1 200_0402_5%
D47# H_D#48
6 H_ADS# N2 ADS# D48# AB25
L1 AC23 H_D#49 H_IER R# R23 2 1 56_0402_5%
6 H_BNR# BNR# D49#
J3 AB24 H_D#50
6 H_BPRI# BPRI# D50# H_D#51
6 H_BR0# N4 BR0# D51# AC20
L4 AC22 H_D#52
6 H_DEFER# DEFER# D52# H_D#53 +3VS
6 H _ D R DY# H2 DRDY# D53# AC25
K3 AD23 H_D#54
6 H_HIT# HIT# D54#
K4 CONTROL GROUP AE22 H_D#55
6 H_HITM# HITM# D55#
H_IER R# A4 AF23 H_D#56 ITP_DBRRESET# R26 2 1 150_0402_5%
IERR# D56# H_D#57
6 H_LOCK# J2 LOCK# D57# AD24
H_CPURST# B11 AF20 H_D#58
6 H_CPURST# RESET# D58# H_D#59
D59# AE21
AD21 H_D#60
H_RS# [0..2] H_RS#0 D60# H_D#61 ITP_TRST# R509 680_0402_5%
6 H_RS#[0..2] H1 RS0# D61# AF25 2 1
H_RS#1 K1 AF22 H_D#62
B H_RS#2 RS1# D62# H_D#63 ITP_TCK R30 27.4_0402_1% B
L2 RS2# D63# AF26 2 1
6 H_TRDY# M3 TRDY# TEST1 R25 2 1 @ 1K_0402_5%
DINV0# D25 H_DINV#0 6
J26 TEST2 R46 2 1 @ 1K_0402_5%
DINV1# H_DINV#1 6
C8 BPM0# DINV2# T24 H_DINV#2 6
B8 BPM1# DINV3# AD20 H_DINV#3 6
A9 BPM2#
C9 BPM3#
DSTBN0# C23 H_DSTBN#0 6
ITP_DBRRESET# A7 K24
DBR# DSTBN1# H_DSTBN#1 6
6 H_DBSY# M2 DBSY# DSTBN2# W25 H_DSTBN#2 6
18 H_DPSLP# B7 DPSLP# DSTBN3# AE24 H_DSTBN#3 6
18 H_DPRSTP# G1 DPRSTP# DSTBP0# C22 H_DSTBP#0 6
6 H_DPW R# C19 DPWR# DSTBP1# L24 H_DSTBP#1 6
A10 PRDY# MISC DSTBP2# W24 H_DSTBP#2 6
B10 PREQ# DSTBP3# AE25 H_DSTBP#3 6
PRO_CHOT# B17 PROCHOT#
H_PW RGOOD E4
18 H_PW RGOOD PWRGOOD
H_CPUSLP# A6
6,18 H_CPUSLP# SLP#
ITP_TCK A13
ITP_TDI TCK
C12 TDI A20M# C2 H_A20M# 18
ITP_TDO A12 D3
TDO FERR# H_FERR# 18
TEST1 C5 A3
TEST1 IGNNE# H_IGNNE# 18
TEST2 F23 B5
TEST2 INIT# H_INIT# 18
ITP_TMS C11 D1
TMS LINT0 H_INTR 18
ITP_TRST# B13 D4
TRST# LINT1 H_NMI 18
A LEGACY CPU A
THERMAL
THERMDA B18 C6
THERMDC THERMDA DIODE STPCLK# H_STPCLK# 18
A18 THERMDC SMI# B4 H_SMI# 18
6,18 H_THERMTRIP# C17 THERMTRIP#

TYCO_1612365-1_Dothan Compal Electronics, Inc.

Title
SCHEMATIC, M/B LA-2492
THERMDA & THERMDC Trace / Space = 10 / 10 mil THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
401317
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. D ate: ¬P 期一, 一月 03, 2005 Sheet 4 of 51
5 4 3 2 1
 5 4 3 2 1

+CPU_CORE +CPU_CORE
JP7B JP7C
330U_D_2VM
R85 1 2 @ 54.9_0402_1% V CCSENSE AE7 A2 1 1 F20 T26
R84 @ 54.9_0402_1% VSSSENSE VCCSENSE VSS VCC VSS
1 2 AF6 VSSSENSE VSS A5 F22 VCC VSS U2
A8 + C427 + C460 G5 U6
VSS VCC VSS
VSS A11 G21 VCC VSS U22
F26 VCCA0 VSS A14 H6 VCC VSS U24
2 2
B1 VCCA1 VSS A17 H22 VCC VSS V1
+VCCA N1 A20 J5 V4
VCCA2 VSS 330U_D_2VM VCC VSS
AC26 VCCA3 VSS A23 J21 VCC VSS V5
VSS A26 K22 VCC VSS V21
D
+1.05VS P23 VCCQ0 VSS B3 U5 VCC VSS V25 D
+CPU_CORE
1.8V FOR DOTHAN-A W4 VCCQ1 VSS B6 V6 VCC VSS W3
VSS B9 V22 VCC VSS W6
1 2 B12 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M W5 W22
+1.8VS R63 @ 0_1206_5% D10 VCCP
Dothan VSS
VSS B16 1 1
C46
1
C48
1 1
C31
1 1 W21
VCC
VCC
VSS
VSS W23
D12 B19 Y6 W26
D14
VCCP
VCCP
VSS
VSS B22
C47 C45 C30 C32
Y22
VCC
VCC
Dothan VSS
VSS Y2
D16 VCCP VSS B25 AA5 VCC VSS Y5
2 2 2 2 2 2 2
1.5V FOR DOTHAN-B E11 VCCP VSS C1
10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
AA7 VCC VSS Y21
E13 C4 AA9 Y24

POWER, GROUNG, RESERVED SIGNALS AND NC

VCCP VSS VCC VSS
+1.5VS 1 2 E15 VCCP VSS C7 AA11 VCC VSS AA1
R56 0_1206_5% F10 C10 AA13 AA4
VCCP VSS +CPU_CORE VCC VSS
F12 VCCP VSS C13 AA15 VCC VSS AA6
F14 VCCP VSS C15 AA17 VCC VSS AA8
1 1 F16 C18 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M AA19 AA10
VCCP VSS VCC VSS
K6 VCCP VSS C21 1 1 1 1 1 1 1 AA21 VCC VSS AA12
L5 C24 C42 C41 C444 AB6 AA14
C25 C26 VCCP VSS VCC VSS
L21 VCCP VSS D2 AB8 VCC VSS AA16
2 2 C33 C40 C39 C443
M6 VCCP VSS D5 AB10 VCC VSS AA18
0.01U_0402_16V7K 2 2 2 2 2 2 2
M22 VCCP VSS D7 AB12 VCC VSS AA20
10U_0805_6.3V6M N5 D9 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M AB14 AA22
VCCP VSS VCC VSS
N21 VCCP VSS D11 AB16 VCC POWER, GROUND VSS AA25
P6 VCCP VSS D13 AB18 VCC VSS AB3
P22 D15 +CPU_CORE AB20 AB5
VCCP VSS VCC VSS
R5 VCCP VSS D17 AB22 VCC VSS AB7
R21 D19 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M AC9 AB9
VCCP VSS VCC VSS
T6 VCCP VSS D21 1 1 1 1 1 1 1 AC11 VCC VSS AB11
T22 D23 C455 C65 C67 AC13 AB13
VCCP VSS VCC VSS
U21 VCCP VSS D26 AC15 VCC VSS AB15
C E3 C454 C64 C66 C68 AC17 AB17 C
VSS 2 2 2 2 2 2 2 VCC VSS
VSS E6 AC19 VCC VSS AB19
D6 E8 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M AD8 AB21
+CPU_CORE VCC VSS VCC VSS
D8 VCC VSS E10 AD10 VCC VSS AB23
D18 VCC VSS E12 AD12 VCC VSS AB26
D20 E14 +CPU_CORE AD14 AC2
VCC VSS VCC VSS
D22 VCC VSS E16 AD16 VCC VSS AC5
E5 E18 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M AD18 AC8
VCC VSS VCC VSS
E7 VCC VSS E20 1 1 1 1 1 1 1 AE9 VCC VSS AC10
E9 E22 C70 C470 C471 AE11 AC12
VCC VSS VCC VSS
E17 VCC VSS E25 AE13 VCC VSS AC14
E19 F1 C69 C429 C430 C516 AE15 AC16
VCC VSS 2 2 2 2 2 2 2 VCC VSS
E21 VCC VSS F4 AE17 VCC VSS AC18
F6 F5 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M AE19 AC21
VCC VSS VCC VSS
F8 VCC VSS F7 AF8 VCC VSS AC24
F18 VCC VSS F9 AF10 VCC VSS AD1
F11 +CPU_CORE AF12 AD4
VSS VCC VSS
VSS F13 AF14 VCC VSS AD7
49 PSI# E1 F15 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M AF16 AD9
PSI# VSS VCC VSS
VSS F17 1 1 1 1 1 1 1 AF18 VCC VSS AD11
+1.05VS 49 CPU_VID0 E2 F19 C510 C512 C514 AD13
VID0 VSS VSS
49 CPU_VID1 F2 VID1 VSS F21 VSS AD15
49 CPU_VID2 F3 F24 C509 C511 C513 C515 AD17
VID2 VSS VSS
1

2 2 2 2 2 2 2
49 CPU_VID3 G3 VID3 VSS G2 VSS AD19
R75 49 CPU_VID4 G4 G6 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M AD22
1K_0402_1% VID4 VSS VSS
49 CPU_VID5 H4 VID5 VSS G22 M4 VSS VSS AD25
VSS G23 M5 VSS VSS AE3
G26 M21 AE6
2

GTL_REF0 VSS VSS VSS

1 2 AD26 GTLREF VSS H3 M24 VSS VSS AE8
B R78 2K_0402_1% B
VSS H5 Vcc-core C,uF ESR, mohm ESL,nH N3 VSS VSS AE10
H21 N6 AE12
C16
VSS
H25
Decoupling N22
VSS VSS
AE14
14 CPU_BSEL0 BSEL0 VSS VSS VSS
14 CPU_BSEL1 C14 BSEL1 VSS J1 SPCAP,Polymer 2X330uF 7m ohm/2 3.5nH/2 N23 VSS VSS AE16
VSS J4 N26 VSS VSS AE18
COMP0 P25 J6 MLCC 0805 X5R 35X10uF 5m ohm/35 0.6nH/35 P2 AE20
COMP1 COMP0 VSS VSS VSS
P26 COMP1 VSS J22 P5 VSS VSS AE23
COMP2 AB2 J24 P21 AE26
COMP3 COMP2 VSS VSS VSS
AB1 COMP3 VSS K2 P24 VSS VSS AF2
VSS K5 R1 VSS VSS AF5
VSS K21 R4 VSS VSS AF9
VSS K23 R6 VSS VSS AF11
B2 RSVD VSS K26 R22 VSS VSS AF13
C3 RSVD VSS L3 R25 VSS VSS AF15
E26 L6 +1.05VS T3 AF17
RSVD VSS VSS VSS
AF7 RSVD VSS L22 T5 VSS VSS AF19
AC1 L25 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z T21 AF21
RSVD VSS VSS VSS
VSS M1 1 T23 VSS VSS AF24
1 1 1 1 1 1 1 1 1 1
+
TYCO_1612365-1_Dothan C435 C445 C16 C458 C13 C15 C14 C461 C453 C448 C442 TYCO_1612365-1_Dothan
2 2 2 2 2 2 2 2 2 2 2

150U_D2_6.3VM 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

R69 1 2 27.4_0402_1% COMP0

A A
R70 1 2 54.9_0402_1% COMP1

R83 1 2 27.4_0402_1% COMP2

R82 1 2 54.9_0402_1% COMP3

Compal Electronics, Inc.
TRACE CLOSELY CPU < 0.5' Title
SCHEMATIC, M/B LA-2492
COMP0, COMP2 layout : Width 18mils and Space 25mils THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
COMP1, COMP3 layout : Space 25mils Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401317 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: ¬P 期一, 一月 03, 2005 Sheet 5 of 51
5 4 3 2 1
 5 4 3 2 1

H_RS# [0..2] +1.5VS

H_RS#[0..2] 4
H_A #[3..31]
4 H_A#[3..31] CL K_DREF_SSC R51 1 2 PM@ 0_0402_5%
H_REQ #[0..4] H_D#[0..63]
4 H_REQ#[0..4] H_D#[0..63] 4
C LK_DREF_SSC# R52 1 2 PM@ 0_0402_5%
U5A
U5B
H_A#3 G9 E4 H _D#0
H_A#4 C9
HA3#
HA4#
Alviso HD0#
HD1# E1 H _D#1
19 DMI_ITX_MRX_N0
DMI_ITX_MRX_N0 AA31 DMIRXN0 CFG0 G16 CF G0
H_A#5 E9 F4 H _D#2 DMI_ITX_MRX_N1 AB35 H13 MCH_CLKSEL1
HA5# HD2# 19 DMI_ITX_MRX_N1 DMIRXN1 CFG1 MCH_CLKSEL1 14
H_A#6 B7 H7 H _D#3 DMI_ITX_MRX_N2 AC31 G14 MCH_CLKSEL0
HA6# HD3# 19 DMI_ITX_MRX_N2 DMIRXN2 CFG2 MCH_CLKSEL0 14
D H_A#7 A10 E2 H _D#4 DMI_ITX_MRX_N3 AD35 F16 D
HA7# HD4# 19 DMI_ITX_MRX_N3 DMIRXN3 CFG3
H_A#8 F9 F1 H _D#5 F15
H_A#9 HA8# HD5# H _D#6 DMI_ITX_MRX_P0 CFG4 CF G5
D8 HA9# HD6# E3 19 DMI_ITX_MRX_P0 Y31 DMIRXP0 CFG5 G15
H_A#10 B10 D3 H _D#7 DMI_ITX_MRX_P1 AA35 E16 CF G6 +2.5VS
HA10# HD7# 19 DMI_ITX_MRX_P1 DMIRXP1 CFG6
H_A#11 E10 K7 H _D#8 DMI_ITX_MRX_P2 AB31 D17 CF G7
HA11# HD8# 19 DMI_ITX_MRX_P2 DMIRXP2 CFG7
H_A#12 G10 F2 H _D#9 DMI_ITX_MRX_P3 AC35 J16
HA12# HD9# 19 DMI_ITX_MRX_P3 DMIRXP3 CFG8
H_A#13 D9 J7 H_D#10 D15 CF G9 CF G0 R40 1 2 10K_0402_5%
H_A#14 HA13# HD10# H_D#11 DMI_MTX_IRX_N0 CFG9
E11 HA14# HD11# J8 19 DMI_MTX_IRX_N0 AA33 DMITXN0 CFG10 E15
H_A#15 F10 H6 H_D#12 DMI_MTX_IRX_N1 AB37 D14
19 DMI_MTX_IRX_N1

DMI
H_A#16 HA15# HD12# H_D#13 DMI_MTX_IRX_N2 DMITXN1 CFG11 C FG12 CF G5 R413 1
G11 HA16# HD13# F3 19 DMI_MTX_IRX_N2 AC33 DMITXN2 CFG12 E14 2 @ 1K_0402_5%
H_A#17 G13 K8 H_D#14 DMI_MTX_IRX_N3 AD37 H12 C FG13
HA17# HD14# 19 DMI_MTX_IRX_N3 DMITXN3 CFG13
H_A#18 C10 H5 H_D#15 C14
H_A#19 HA18# HD15# H_D#16 DMI_MTX_IRX_P0 CFG14

CFG/RSVD
C11 HA19# HD16# H1 19 DMI_MTX_IRX_P0 Y33 DMITXP0 CFG15 H15
H_A#20 D11 H2 H_D#17 DMI_MTX_IRX_P1 AA37 J15 C FG16 CF G6 R407 1 2 @ 1K_0402_5%
HA20# HD17# 19 DMI_MTX_IRX_P1 DMITXP1 CFG16
H_A#21 C12 K5 H_D#18 DMI_MTX_IRX_P2 AB33 H14
HA21# HD18# 19 DMI_MTX_IRX_P2 DMITXP2 CFG17
H_A#22 B13 K6 H_D#19 DMI_MTX_IRX_P3 AC37 G22 C FG18 CF G7 R408 1 2 @ 1K_0402_5%
HA22# HD19# 19 DMI_MTX_IRX_P3 DMITXP3 CFG18
H_A#23 A12 J4 H_D#20 G23 C FG19
H_A#24 HA23# HD20# H_D#21 CFG19 CF G9 R404 1
F12 HA24# HD21# G3 CFG20 D23 2 @ 1K_0402_5%
H_A#25 G12 H3 H_D#22 AM33 G25
HA25# HD22# 11 DDRA_CLK1 SM_CK0 RSVD21
H_A#26 E12 J1 H_D#23 AL1 G24 C FG12 R409 1 2 @ 1K_0402_5%
HA26# HD23# 11 DDRA_CLK2 SM_CK1 RSVD22
H_A#27 C13 L5 H_D#24 AE11 J17
H_A#28 HA27# HD24# H_D#25 SM_CK2 RSVD23 C FG13 R412 1
B11 HA28# HD25# K4 12 DDRB_CLK1 AJ34 SM_CK3 RSVD24 A31 2 @ 1K_0402_5%
H_A#29 D13 J5 H_D#26 AF6 A30
HA29# HD26# 12 DDRB_CLK2 SM_CK4 RSVD25
H_A#30 A13 P7 H_D#27 AC10 D26 C FG16 R417 1 2 @ 1K_0402_5%
H_A#31 HA30# HD27# H_D#28 SM_CK5 RSVD26
F13 HA31# HD28# L7 RSVD27 D25
J3 H_D#29 AN33 CFG[17:3]: internal pull-up
HD29# 11 DDRA_CLK1# SM_CK0#

DDR MUXING
A11 P5 H_D#30 AK1
HOST

HPCREQ# HD30# 11 DDRA_CLK2# SM_CK1#

H_REQ#0 A7 L3 H_D#31 AE10
H_REQ#1 HREQ#0 HD31# H_D#32 SM_CK2# C FG18 R41
D7 HREQ#1 HD32# U7 12 DDRB_CLK1# AJ33 SM_CK3# 1 2 @ 1K_0402_5%
C H_REQ#2 B8 V6 H_D#33 AF5 C
HREQ#2 HD33# 12 DDRB_CLK2# SM_CK4#
H_REQ#3 C7 R6 H_D#34 AD10 C FG19 R42 1 2 @ 1K_0402_5%
H_REQ#4 HREQ#3 HD34# H_D#35 SM_CK5#
A8 HREQ#4 HD35# R5
B9 P3 H_D#36 DD RA_CKE0 AP21 CFG[19:18]: internal pull-down
4 H_ADSTB#0 HADSTB#0 HD36# 11 DDRA_CKE0 SM_CKE0
E13 T8 H_D#37 DD RA_CKE1 AM21
4 H_ADSTB#1 HADSTB#1 HD37# 11 DDRA_CKE1 SM_CKE1
R7 H_D#38 DD RB_CKE0 AH21
HD38# 12 DDRB_CKE0 SM_CKE2
AB1 R8 H_D#39 DD RB_CKE1 AK21
14 CLK_MCH_BCLK# HCLKN HD39# 12 DDRB_CKE1 SM_CKE3
AB2 U8 H_D#40 J23
14 CLK_MCH_BCLK HCLKP HD40# BM_BUSY# PM_BMBUSY# 19
R4 H_D#41 D DRA_SCS#0 AN16 J21 EXT_TS#0
HD41# 11 DDRA_SCS#0 SM_CS0# EXT_TS0#
G4 T4 H_D#42 D DRA_SCS#1 AM14 H22 EXT_TS#1
4 H_DSTBN#0 HDSTBN#0 HD42# 11 DDRA_SCS#1 SM_CS1# EXT_TS1#
K1 T5 H_D#43 D DRB_SCS#0 AH15 F5 H_THERMTRIP#
4 H_DSTBN#1 HDSTBN#1 HD43# 12 DDRB_SCS#0 SM_CS2# THRMTRIP# H_THERMTRIP# 4,18
R3 R1 H_D#44 D DRB_SCS#1 AG16 AD30
4 H_DSTBN#2 HDSTBN#2 HD44# 12 DDRB_SCS#1 SM_CS3# PWROK VGATE 14,19,49
V3 T3 H_D#45 AE29

CLK PM
4 H_DSTBN#3 HDSTBN#3 HD45# RSTIN# PLT_RST# 16,17,19,21,22,24,27,33,34
G5 V8 H_D#46 R426 1 2 @ 40.2_0402_1% M_OCDCOMP0 AF22
4 H_DSTBP#0 HDSTBP#0 HD46# H_D#47 R427 1 SM_OCDCOMP0
4 H_DSTBP#1 K2 HDSTBP#1 HD47# U6 2 @ 40.2_0402_1% M_OCDCOMP1 AF16 SM_OCDCOMP1
R2 W6 H_D#48 AP14 A24 CLK_DREF_96M#
4 H_DSTBP#2 HDSTBP#2 HD48# SM_ODT0 DREF_CLKN CLK_DREF_96M# 14
W4 U3 H_D#49 AL15 A23 CLK_DREF_96M
4 H_DSTBP#3 HDSTBP#3 HD49# SM_ODT1 DREF_CLKP CLK_DREF_96M 14
H8 V5 H_D#50 AM11 D37 CL K_DREF_SSC
4 H_DINV#0 HDINV#0 HD50# SM_ODT2 DREF_SSCLKP CLK_DREF_SSC 14
K3 W8 H_D#51 AN10 C37 C LK_DREF_SSC#
4 H_DINV#1 HDINV#1 HD51# SM_ODT3 DREF_SSCLKN CLK_DREF_SSC# 14
T7 W7 H_D#52
4 H_DINV#2 HDINV#2 HD52# H_D#53 R429 1
4 H_DINV#3 U5 HDINV#3 HD53# U2 +DDRVCC 2 80.6_0402_1% M_RCOMPN AK10 SMRCOMPN
U1 H_D#54 R430 1 2 80.6_0402_1% M_RCOMPP AK11 AP37 +2.5VS
HD54# H_D#55 SMVREF SMRCOMPP NC1
HD55# Y5 AF37 SMVREF0 NC2 AN37
H10 Y2 H_D#56 AD1 AP36 EXT_TS#0 R416 1 2 10K_0402_5%
4 H_CPURST# HCPURST# HD56# SMVREF1 NC3
V4 H_D#57 M_XSLEW AE27 AP2
HD57# H_D#58 SMXSLEWIN NC4 EXT_TS#1 R411 1
4 H_ADS# F8 HADS# HD58# Y7 AE28 SMXSLEWOUT NC5 AP1 2 10K_0402_5%
B5 W1 H_D#59 M_YSELW AF9 AN1
4 H_TRDY# HTRDY# HD59# H_D#60 SMYSLEWIN NC6
4 H_DPW R# G6 HDPWR# HD60# W3 AF10 SMYSLEWOUT NC7 B1
F7 Y3 H_D#61 A2
B 4 H _ D R DY# HDRDY# HD61# H_D#62 NC8 B
4 H_DEFER# E6 HDEFER# HD62# Y6 NC9 B37 Refer to sheet 6 for FSB
H_D#63

NC
F6 HEDRDY# HD63# W2
+1.05VS NC10 A36 CFG[2:0] frequency select
4 H_HITM# D6 HHITM# NC11 A37
D4 J11 H_ VREF Low = DMI x 2
4 H_HIT# HHIT# HVREF H_XRCOMP R50 2 24.9_0402_1%
B3 C1 1 (10mil:20mil) CFG5 High = DMI x 4
4
4
H_LOCK#
H_BR0# E7
HLOCK#
HBREQ0#
HXRCOMP
HXSCOMP C2 H_XSCOMP
H_YRCO MP
R47 1
R72 2
2 54.9_0402_1%
24.9_0402_1%
ALVISO_BGA1257 *
4 H_BNR# A5 HBNR# HYRCOMP T1 1 Low = DDR-II
D5 L1 H_YSCOMP R68 1 2 54.9_0402_1% CFG6 High = DDR-I
4
4
H_BPRI#
H_DBSY# CPU_SLP#
C6
HBPRI#
HDBSY#
HYSCOMP
HXSWING D1 H_XSW ING
H _YSW ING +DDRVCC
*
G8 HCPUSLP# HYSWING P1 Low = DT/Transportable CPU
H_RS#0 A4 CFG7 High = Mobile CPU
H_RS#1 C5
HRS0#
HRS1#
*

1
H_RS#2 B4 H_XRCOMP & H_YRCOMP Trace / Space = 10 / 20 mil CFG9 Low = Reverse Lane
HRS2# R423 High = Normal Operation
ALVISO_BGA1257 1K_0402_1%
*
Un-pop for Dothan-A 00 = Reserved
CFG[13:12] 01 = XOR Mode Enabled
2
R54 1 2 0_0402_5% CPU_SLP# 0.1U_0402_16V4Z SMVREF 10 = All Z Mode Enabled
4,18 H_CPUSLP#
11 = Normal Operation (Default)
R421
1

C488
1 1 *
CFG16
C489 Low = Disabled
+1.05VS +1.05VS +1.05VS 1K_0402_1% 0.1U_0402_16V4Z (FSB Dynamic High = Enabled
2 2
ODT) *
2
1

R388 R406 R420

CFG18
Low = 1.05V (Default)
100_0603_1% 221_0603_1% 221_0603_1% (VCC Select) High = 1.5V *
A A
(5mil:15mil) (12mil:10mil) CFG19
2

Low = 1.05V (Default)

H_ VREF H_XSW ING H _YSW ING (12mil:10mil) (VTT Select) High = 1.2V *
1

1 1 1
C436 R387 C423 R405 C459
R419 Compal Electronics, Inc.
0.1U_0402_16V4Z 200_0603_1% 0.1U_0402_16V4Z 100_0603_1% 0.1U_0402_16V4Z 100_0603_1% Title
2 2 2
SCHEMATIC, M/B LA-2492
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
401317 B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: ¬P 期一, 一月 03, 2005 Sheet 6 of 51
5 4 3 2 1
 5 4 3 2 1

DDRA_SD Q[0..63]
11 DDRA_SDQ[0..63]
DDRA_S DM[0..7]
11 DDRA_SDM[0..7]
DDRA_SD QS[0..7]
11 DDRA_SDQS[0..7]
DDR A_SMA[0..13] DDR B_SMA[0..13]
11 DDRA_SMA[0..13] 12 DDRB_SMA[0..13]
D D

U 5C U 5D
AK15 AG35 DD RA_SDQ0 AJ15 AE31
11 DDRA_SBS0 SA_BS0# SADQ0 12 DDRB_SBS0 SB_BS0# SBDQ0
AK16 AH35 DD RA_SDQ1 AG17 AE32
11 DDRA_SBS1 SA_BS1# SADQ1 12 DDRB_SBS1 SB_BS1# SBDQ1
AL21 AL35 DD RA_SDQ2 AG21 AG32
SA_BS2# SADQ2 DD RA_SDQ3 SB_BS2# SBDQ2
SADQ3 AL37 SBDQ3 AG36
DDRA_SDM0 AJ37 AH36 DD RA_SDQ4 AF32 AE34
DDRA_SDM1 SA_DM0 SADQ4 DD RA_SDQ5 SB_DM0 SBDQ4
AP35 SA_DM1 SADQ5 AJ35 AK34 SB_DM1 SBDQ5 AE33
DDRA_SDM2 AL29 AK37 DD RA_SDQ6 AK27 AF31
DDRA_SDM3 SA_DM2 SADQ6 DD RA_SDQ7 SB_DM2 SBDQ6
AP24 SA_DM3 SADQ7 AL34 AK24 SB_DM3 SBDQ7 AF30
DDRA_SDM4 AP9 AM36 DD RA_SDQ8 AJ10 AH33
DDRA_SDM5 SA_DM4 SADQ8 DD RA_SDQ9 SB_DM4 SBDQ8
AP4 SA_DM5 SADQ9 AN35 AK5 SB_DM5 SBDQ9 AH32
DDRA_SDM6 AJ2 AP32 D DRA_SDQ10 AE7 AK31
DDRA_SDM7 SA_DM6 SADQ10 D DRA_SDQ11 SB_DM6 SBDQ10
AD3 SA_DM7 SADQ11 AM31 AB7 SB_DM7 SBDQ11 AG30
AM34 D DRA_SDQ12 AG34
DD RA_SDQS0 SADQ12 D DRA_SDQ13 SBDQ12
AK36 SA_DQS0 SADQ13 AM35 AF34 SB_DQS0 SBDQ13 AG33
DD RA_SDQS1 AP33 AL32 D DRA_SDQ14 AK32 AH31
DD RA_SDQS2 SA_DQS1 SADQ14 D DRA_SDQ15 SB_DQS1 SBDQ14
AN29 SA_DQS2 SADQ15 AM32 AJ28 SB_DQS2 SBDQ15 AJ31
DD RA_SDQS3 AP23 AN31 D DRA_SDQ16 AK23 AK30
DD RA_SDQS4 SA_DQS3 SADQ16 D DRA_SDQ17 SB_DQS3 SBDQ16
AM8 SA_DQS4 SADQ17 AP31 AM10 SB_DQS4 SBDQ17 AJ30
DD RA_SDQS5 AM4 AN28 D DRA_SDQ18 AH6 AH29
DD RA_SDQS6 SA_DQS5 SADQ18 D DRA_SDQ19 SB_DQS5 SBDQ18
AJ1 SA_DQS6 SADQ19 AP28 AF8 SB_DQS6 SBDQ19 AH28
DD RA_SDQS7 AE5 AL30 D DRA_SDQ20 AB4 AK29
SA_DQS7 SADQ20 D DRA_SDQ21 SB_DQS7 SBDQ20
SADQ21 AM30 SBDQ21 AH30
AK35 AM28 D DRA_SDQ22 AF35 AH27
C SA_DQS0# SADQ22 D DRA_SDQ23 SB_DQS0# SBDQ22 C
AP34 AL28 AK33 AG28

DDR SYSTEM MEMORY B

SA_DQS1# SADQ23 D DRA_SDQ24 SB_DQS1# SBDQ23
AN30 AP27 AK28 AF24
DDR MEMORY SYSTEM A

SA_DQS2# SADQ24 D DRA_SDQ25 SB_DQS2# SBDQ24

AN23 SA_DQS3# SADQ25 AM27 AJ23 SB_DQS3# SBDQ25 AG23
AN8 AM23 D DRA_SDQ26 AL10 AJ22
SA_DQS4# SADQ26 D DRA_SDQ27 SB_DQS4# SBDQ26
AM5 SA_DQS5# SADQ27 AM22 AH7 SB_DQS5# SBDQ27 AK22
AH1 AL23 D DRA_SDQ28 AF7 AH24
SA_DQS6# SADQ28 D DRA_SDQ29 SB_DQS6# SBDQ28
AE4 SA_DQS7# SADQ29 AM24 AB5 SB_DQS7# SBDQ29 AH23
AN22 D DRA_SDQ30 AG22
DDRA_SMA0 SADQ30 D DRA_SDQ31 DDRB_SMA0 SBDQ30
AL17 SA_MA0 SADQ31 AP22 AH17 SB_MA0 SBDQ31 AJ21
DDRA_SMA1 AP17 AM9 D DRA_SDQ32 DDRB_SMA1 AK17 AG10
DDRA_SMA2 SA_MA1 SADQ32 D DRA_SDQ33 DDRB_SMA2 SB_MA1 SBDQ32
AP18 SA_MA2 SADQ33 AL9 AH18 SB_MA2 SBDQ33 AG9
DDRA_SMA3 AM17 AL6 D DRA_SDQ34 DDRB_SMA3 AJ18 AG8
DDRA_SMA4 SA_MA3 SADQ34 D DRA_SDQ35 DDRB_SMA4 SB_MA3 SBDQ34
AN18 SA_MA4 SADQ35 AP7 AK18 SB_MA4 SBDQ35 AH8
DDRA_SMA5 AM18 AP11 D DRA_SDQ36 DDRB_SMA5 AJ19 AH11
DDRA_SMA6 SA_MA5 SADQ36 D DRA_SDQ37 DDRB_SMA6 SB_MA5 SBDQ36
AL19 SA_MA6 SADQ37 AP10 AK19 SB_MA6 SBDQ37 AH10
DDRA_SMA7 AP20 AL7 D DRA_SDQ38 DDRB_SMA7 AH19 AJ9
DDRA_SMA8 SA_MA7 SADQ38 D DRA_SDQ39 DDRB_SMA8 SB_MA7 SBDQ38
AM19 SA_MA8 SADQ39 AM7 AJ20 SB_MA8 SBDQ39 AK9
DDRA_SMA9 AL20 AN5 D DRA_SDQ40 DDRB_SMA9 AH20 AJ7
DDRA_SMA10 SA_MA9 SADQ40 D DRA_SDQ41 DDRB_SMA10 SB_MA9 SBDQ40
AM16 SA_MA10 SADQ41 AN6 AJ16 SB_MA10 SBDQ41 AK6
DDRA_SMA11 AN20 AN3 D DRA_SDQ42 DDRB_SMA11 AG18 AJ4
DDRA_SMA12 SA_MA11 SADQ42 D DRA_SDQ43 DDRB_SMA12 SB_MA11 SBDQ42
AM20 SA_MA12 SADQ43 AP3 AG20 SB_MA12 SBDQ43 AH5
DDRA_SMA13 AM15 AP6 D DRA_SDQ44 DDRB_SMA13 AG15 AK8
SA_MA13 SADQ44 D DRA_SDQ45 SB_MA13 SBDQ44
SADQ45 AM6 SBDQ45 AJ8
AN15 AL4 D DRA_SDQ46 AH14 AJ5
11 DDRA_SCAS# SA_CAS# SADQ46 12 DDRB_SCAS# SB_CAS# SBDQ46
AP16 AM3 D DRA_SDQ47 AK14 AK4
11 DDRA_SRAS# SA_RAS# SADQ47 12 DDRB_SRAS# SB_RAS# SBDQ47
AF29 AK2 D DRA_SDQ48 AF15 AG5
SA_RCVENIN# SADQ48 D DRA_SDQ49 SB_RCVENIN# SBDQ48
AF28 SA_RCVENOUT# SADQ49 AK3 AF14 SB_RCVENOUT# SBDQ49 AG4
AP15 AG2 D DRA_SDQ50 AH16 AD8
11 DDRA_SW E# SA_WE# SADQ50 12 DDRB_SW E# SB_WE# SBDQ50
AG1 D DRA_SDQ51 AD9
B SADQ51 D DRA_SDQ52 SBDQ51 B
SADQ52 AL3 SBDQ52 AH4
AM2 D DRA_SDQ53 AG6
SADQ53 D DRA_SDQ54 SBDQ53
SADQ54 AH3 SBDQ54 AE8
AG3 D DRA_SDQ55 AD7
SADQ55 D DRA_SDQ56 SBDQ55
SADQ56 AF3 SBDQ56 AC5
AE3 D DRA_SDQ57 AB8
SADQ57 D DRA_SDQ58 SBDQ57
SADQ58 AD6 SBDQ58 AB6
AC4 D DRA_SDQ59 AA8
SADQ59 D DRA_SDQ60 SBDQ59
SADQ60 AF2 SBDQ60 AC8
AF1 D DRA_SDQ61 AC7
SADQ61 D DRA_SDQ62 SBDQ61
SADQ62 AD4 SBDQ62 AA4
AD5 D DRA_SDQ63 AA5
SADQ63 SBDQ63

ALVISO_BGA1257 ALVISO_BGA1257

A A

Compal Electronics, Inc.

Title
SCHEMATIC, M/B LA-2492
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
401317 B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: ¬P 期一, 一月 03, 2005 Sheet 7 of 51
5 4 3 2 1
 5 4 3 2 1

+3VS +2.5VS

PCIE_MTX_C_GRX_N[0..15]
16 PCIE_MTX_C_GRX_N[0..15]

1
PCIE_MTX_C_GRX_P[0..15]
16 PCIE_MTX_C_GRX_P[0..15]
R402
GM@ 2.2K_0402_5% PCEI_GTX_C_MRX_N[0..15]
16 PCEI_GTX_C_MRX_N[0..15]

2
G
2
PCEI_GTX_C_MRX_P[0..15]
16 PCEI_GTX_C_MRX_P[0..15]
1 3 LBKLT_EN
16,34 GMCH_ENBKL

S
D D
Q44
GM@ BSS138_SOT23 U5G
+2.5VS R38 1 2 @ 3K_0402_1% H24 D36 PEG_COMP 1 2 +1.5VS
R383 1 SDVOCTRL_DATA EXP_COMPI
2 @ 3K_0402_1% H25 SDVOCTRL_CLK EXP_ICOMPO D34 R48 24.9_0402_1%
AB29

MISC
14 CLK_MCH_3GPLL# GCLKN
AC29 PCEI_GTX_C_MRX_N0
14 CLK_MCH_3GPLL GCLKP EXP_RXN0/SDVO_TVCLKIN# E30 PCEI_GTX_C_MRX_N1
EXP_RXN1/SDVO_INT# F34 PCEI_GTX_C_MRX_N2
GMCH_TV_COMPS EXP_RXN2/SDVO_FLDSTALL# G30 PCEI_GTX_C_MRX_N3
A15 TVDAC_A EXP_RXN3 H34
GMCH_TV_LUMA C16 PCEI_GTX_C_MRX_N4
15 GMCH_TV_LUMA
GMCH_TV_CRMA TVDAC_B EXP_RXN4 J30 PCEI_GTX_C_MRX_N5
15 GMCH_TV_CRMA A17 TVDAC_C EXP_RXN5 K34
2 1 TV_REFSET J18 PCEI_GTX_C_MRX_N6
R418 4.99K_0402_1% TV_REFSET EXP_RXN6 L30 PCEI_GTX_C_MRX_N7
2 1 B15 TV_IRTNA EXP_RXN7 M34
R399 0_0402_5% B16 PCEI_GTX_C_MRX_N8
TV_IRTNB EXP_RXN8 N30 PCEI_GTX_C_MRX_N9
B17 EXP_RXN9 P34

TV
TV_IRTNC PCEI_GTX_C_MRX_N10
EXP_RXN10 R30 PCEI_GTX_C_MRX_N11
EXP_RXN11 T34 PCEI_GTX_C_MRX_N12
EXP_RXN12 U30 PCEI_GTX_C_MRX_N13
EXP_RXN13 V34 PCEI_GTX_C_MRX_N14
GMCH_CRT_CLK EXP_RXN14 W30 PCEI_GTX_C_MRX_N15
15 GMCH_CRT_CLK E24 DDCCLK EXP_RXN15 Y34
GMCH_CRT_DATA E23
15 GMCH_CRT_DATA DDCDATA
E21 D30 PCEI_GTX_C_MRX_P0
15 GMCH_CRT_B BLUE EXP_RXP0/SDVO_TVCLKIN
2 1 D21 E34 PCEI_GTX_C_MRX_P1
R384 150_0402_5% BLUE# EXP_RXP1/SDVO_INT PCEI_GTX_C_MRX_P2
15 GMCH_CRT_G C20 GREEN EXP_RXP2/SDVO_FLDSTALL F30
2 1 B20 G34 PCEI_GTX_C_MRX_P3
R385 150_0402_5% GREEN# EXP_RXP3 PCEI_GTX_C_MRX_P4
15 GMCH_CRT_R A19 RED EXP_RXP4 H30
2 1 B19 J34 PCEI_GTX_C_MRX_P5
C R386 150_0402_5% RED# EXP_RXP5 PCEI_GTX_C_MRX_P6 C
H21 K30

VGA
15 GMCH_CRT_VSYNC VSYNC EXP_RXP6
G21 L34 PCEI_GTX_C_MRX_P7
15 GMCH_CRT_HSYNC HSYNC EXP_RXP7

PCI - EXPRESS GRAPHICS

1 2 REFSET J20 REFSET EXP_RXP8 M30 PCEI_GTX_C_MRX_P8
R414 255_0402_1% N34 PCEI_GTX_C_MRX_P9
EXP_RXP9 PCEI_GTX_C_MRX_P10
EXP_RXP10 P30
R34 PCEI_GTX_C_MRX_P11
EXP_RXP11 PCEI_GTX_C_MRX_P12
EXP_RXP12 T30
U34 PCEI_GTX_C_MRX_P13
EXP_RXP13 PCEI_GTX_C_MRX_P14
EXP_RXP14 V30
W34 PCEI_GTX_C_MRX_P15
EXP_RXP15
E25 LBKLT_CTL
LBKLT_EN F25 E32 PCIE_MTX_GRX_N0 C57 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N0
LCTLA_CLK LBKLT_EN EXP_TXN0/SDVOB_RED# PCIE_MTX_GRX_N1 C59
C23 LCTLA_CLK EXP_TXN1/SDVOB_GREEN# F36 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N1
+2.5VS LCTLB_DATA C22 G32 PCIE_MTX_GRX_N2 C62 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N2
LDD C_CLK LCTLB_DATA EXP_TXN2/SDVOB_BLUE# PCIE_MTX_GRX_N3 C71
F23 LDDC_CLK EXP_TXN3/SDVOB_CLKN H36 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N3
R381 1 2 4.7K_0402_5% GMCH_CRT_CLK LDDC_DATA F22 J32 PCIE_MTX_GRX_N4 C74 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N4
GM CH_ENVDD LDDC_DATA EXP_TXN4/SDVOC_RED# PCIE_MTX_GRX_N5 C76
16 GMCH_ENVDD F26 LVDD_EN EXP_TXN5/SDVOC_GREEN# K36 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N5
R382 1 2 4.7K_0402_5% GMCH_CRT_DATA L IBG C33 L32 PCIE_MTX_GRX_N6 C78 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N6
LIBG EXP_TXN6/SDVOC_BLUE# PCIE_MTX_GRX_N7 C80
C31 LVBG EXP_TXN7/SDVOC_CLKN M36 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N7
R400 1 2 2.2K_0402_5% LCTLB_DATA F28 N32 PCIE_MTX_GRX_N8 C87 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N8
LVREFH EXP_TXN8 PCIE_MTX_GRX_N9 C91
F27 LVREFL EXP_TXN9 P36 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N9
R39 1 2 2.2K_0402_5% LCTLA_CLK R32 PCIE_MTX_GRX_N10 C97 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N10
GMCH_TXCLK- EXP_TXN10 PCIE_MTX_GRX_N11 C100 1
16 GMCH_TXCLK- B30 LACLKN EXP_TXN11 T36 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N11
GMCH_TXCLK+ B29 U32 PCIE_MTX_GRX_N12 C104 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N12
16 GMCH_TXCLK+ LACLKP EXP_TXN12

LVDS
GMCH_TZCLK- C25 V36 PCIE_MTX_GRX_N13 C109 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N13
16 GMCH_TZCLK- LBCLKN EXP_TXN13
R398 1 2 100K_0402_5% LBKLT_EN GMCH_TZCLK+ C24 W32 PCIE_MTX_GRX_N14 C114 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N14
16 GMCH_TZCLK+ LBCLKP EXP_TXN14
Y36 PCIE_MTX_GRX_N15 C116 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N15
R403 1 1.5K_0402_1% L IBG GMCH_TXOUT0- EXP_TXN15
2 16 GMCH_TXOUT0- B34 LADATAN0
GMCH_TXOUT1- B33
B 16 GMCH_TXOUT1- LADATAN1 B
R44 1 2 75_0402_1% GMCH_TV_COMPS GMCH_TXOUT2- B32 D32 PCIE_MTX_GRX_P0 C56 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P0
16 GMCH_TXOUT2- LADATAN2 EXP_TXP0/SDVOB_RED
E36 PCIE_MTX_GRX_P1 C58 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P1
R515 1 150_0402_5% GMCH_TV_LUMA EXP_TXP1/SDVOB_GREEN PCIE_MTX_GRX_P2 C60
2 EXP_TXP2/SDVOB_BLUE F32 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P2
GMCH_TXOUT0+ A34 G36 PCIE_MTX_GRX_P3 C63 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P3
16 GMCH_TXOUT0+ LADATAP0 EXP_TXP3/SDVOB_CLKP
R516 1 2 150_0402_5% GMCH_TV_CRMA GMCH_TXOUT1+ A33 H32 PCIE_MTX_GRX_P4 C73 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P4
16 GMCH_TXOUT1+ LADATAP1 EXP_TXP4/SDVOC_RED
GMCH_TXOUT2+ B31 J36 PCIE_MTX_GRX_P5 C75 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P5
16 GMCH_TXOUT2+ LADATAP2 EXP_TXP5/SDVOC_GREEN
K32 PCIE_MTX_GRX_P6 C77 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P6
EXP_TXP6/SDVOC_BLUE PCIE_MTX_GRX_P7 C79 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P7
EXP_TXP7/SDVOC_CLKP L36 1 2
M32 PCIE_MTX_GRX_P8 C83 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P8
GMCH_TZOUT0- EXP_TXP8 PCIE_MTX_GRX_P9 C89
16 GMCH_TZOUT0- C29 LBDATAN0 EXP_TXP9 N36 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P9
GMCH_TZOUT1- D28 P32 PCIE_MTX_GRX_P10 C92 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P10
16 GMCH_TZOUT1- LBDATAN1 EXP_TXP10
GMCH_TZOUT2- C27 R36 PCIE_MTX_GRX_P11 C98 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P11
16 GMCH_TZOUT2- LBDATAN2 EXP_TXP11
T32 PCIE_MTX_GRX_P12 C101 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P12
+2.5VS EXP_TXP12 PCIE_MTX_GRX_P13 C105 1
EXP_TXP13 U36 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P13
+3VS V32 PCIE_MTX_GRX_P14 C110 1 2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P14
GMCH_TZOUT0+ EXP_TXP14 PCIE_MTX_GRX_P15 C115 1 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P15
16 GMCH_TZOUT0+ C28 LBDATAP0 EXP_TXP15 W36 2
GMCH_TZOUT1+ D27
16 GMCH_TZOUT1+ LBDATAP1
2

GMCH_TZOUT2+ C26
16 GMCH_TZOUT2+ LBDATAP2
R45 R49
GM@ 4.7K_0402_5% GM@ 4.7K_0402_5%
2
G

ALVISO_BGA1257
1

LDD C_CLK 3 1 GMCH_LCD_CLK

GMCH_LCD_CLK 16
S

Q6
GM@ 2N7002_SOT23

A A
+2.5VS
+3VS
2

R397 R401
GM@ 4.7K_0402_5% GM@ 4.7K_0402_5% Compal Electronics, Inc.
2
G

Title
SCHEMATIC, M/B LA-2492
1

LDDC_DATA 3 1 GMCH_LCD_DATA
GMCH_LCD_DATA 16 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
S

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Q43 401317 B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
GM@ 2N7002_SOT23
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: ¬P 期一, 一月 03, 2005 Sheet 8 of 51
5 4 3 2 1
 5 4 3 2 1

+1.05VS
4000mA
U 5F C519
U5E 0.1U_0402_16V4Z C505 2.2U_0603_6.3V6K
0.1U_0402_16V4Z 0.1U_0402_16V4Z
+1.05VS K13 AM37 V 1.8_DDR_CAP1 2 1 0.1U_0402_16V4Z
VTT0 VCCSM0 V 1.8_DDR_CAP2
+1.05VS T29 VCC0 VCCA_TVDACA0 F17 +3VS J13 VTT1 VCCSM1 AH37 2 1 1 1 1 1 1 1
R29 E17 K12 AP29 V 1.8_DDR_CAP5 2 1 C457 C451 C452
VCC1 VCCA_TVDACA1 VTT2 VCCSM2 C520
N29 VCC2 VCCA_TVDACB0 D18 W11 VTT3 VCCSM3 AD28 +DDRVCC
M29 C18 120mA V11 AD27 0.1U_0402_16V4Z C450 C456 C447
VCC3 VCCA_TVDACB1 VTT4 VCCSM4 2 2 2 2 2 2
K29 VCC4 VCCA_TVDACC0 F18 U11 VTT5 VCCSM5 AC27
J29 E18 T11 AP26 22U_1206_16V4Z_V1
VCC5 VCCA_TVDACC1 VTT6 VCCSM6 2.2U_0603_6.3V6K 0.1U_0402_16V4Z
D V28 R11 AN26 D
U28
T28
VCC6
VCC7
VCC8 POWER VCCA_TVBG
VSSA_TVBG
H18
G18
P11
N11
VTT7
VTT8
VTT9
POWER VCCSM7
VCCSM8
VCCSM9
AM26
AL26 +DDRVCC
2200mA
R28 VCC9 M11 VTT10 VCCSM10 AK26
P28 D19 L11 AJ26 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
VCC10 VCCD_TVDAC VTT11 VCCSM11
N28 VCC11 VCCDQ_TVDAC H17 24mA K11 VTT12 VCCSM12 AH26 1
M28 VCC12 W10 VTT13 VCCSM13 AG26 1 1 1 1 1 1 1 1
L28 B26 V10 AF26 + C494 C86 C81 C483
VCC13 VCCD_LVDS0 +1.5VS VTT14 VCCSM14
K28 VCC14 VCCD_LVDS1 B25 U10 VTT15 VCCSM15 AE26
J28 A25 60mA T10 AP25 C88 C487 C498 C481 C486
VCC15 VCCD_LVDS2 VTT16 VCCSM16 330U_D2E_2.5VM 2 2 2 2 2 2 2 2 2
H28 VCC16 R10 VTT17 VCCSM17 AN25
G28 VCC17 VCCA_LVDS A35 +2.5VS P10 VTT18 VCCSM18 AM25
V27 10mA N10 AL25 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
VCC18 VTT19 VCCSM19
U27 VCC19 VCCHV0 B22 M10 VTT20 VCCSM20 AK25
T27 VCC20 VCCHV1 B21 2mA K10 VTT21 VCCSM21 AJ25
R27 VCC21 VCCHV2 A21 J10 VTT22 VCCSM22 AH25
P27 VCC22 Y9 VTT23 VCCSM23 AG25
+2.5VS
N27 VCC23 VCCTX_LVDS0 B28 W9 VTT24 VCCSM24 AF25 VCCHV(Ball A21,B21,B22)
M27 VCC24 VCCTX_LVDS1 A28 60mA U9 VTT25 VCCSM25 AE25
L27 VCC25 VCCTX_LVDS2 A27 R9 VTT26 VCCSM26 AE24
K27 VCC26 P9 VTT27 VCCSM27 AE23
J27 VCC27 VCCA_SM0 AF20 +1.5VS_DDRDLL N9 VTT28 VCCSM28 AE22 1 1 1 1 1 1
H27 AP19 M9 AE21 C417 C419 C413 C416 C21 C414
VCC28 VCCA_SM1 VTT29 VCCSM29
K26 VCC29 VCCA_SM2 AF19 L9 VTT30 VCCSM30 AE20
H26 VCC30 VCCA_SM3 AF18 J9 VTT31 VCCSM31 AE19
2 0.1U_0402_16V4Z 2 0.01U_0402_16V7K 2 4.7U_0805_10V4Z 2 0.1U_0402_16V4Z 2 4.7U_0805_10V4Z 2 0.1U_0402_16V4Z
K25 VCC31 N8 VTT32 VCCSM32 AE18
J25 VCC32 VCC3G0 AE37 +1.5VS_PEG M8 VTT33 VCCSM33 AE17
K24 VCC33 VCC3G1 W37 N7 VTT34 VCCSM34 AE16
K23 VCC34 VCC3G2 U37 M7 VTT35 VCCSM35 AE15
C K22 VCC35 VCC3G3 R37 1000mA N6 VTT36 VCCSM36 AE14 VCCA_LVDS (Ball A35) VCCTX_LVDS(Ball A27,A28,B28) C
K21 VCC36 VCC3G4 N37 M6 VTT37 VCCSM37 AP13
W20 VCC37 VCC3G5 L37 A6 VTT38 VCCSM38 AN13
+2.5VS
U20 VCC38 VCC3G6 J37
C23
N5 VTT39 VCCSM39 AM13 VCCA_CRTDAC(Ball F19,E19)
T20 VCC39 1 M5 VTT40 VCCSM40 AL13
K20 0.47U_0603_16V4Z N4 AK13
VCC40 VTT41 VCCSM41
V19 VCC41 M4 VTT42 VCCSM42 AJ13
U19 VCC42 VCCA_3GPLL0 Y29 +1.5VS_3GPLL N3 VTT43 VCCSM43 AH13 1 1 1 1
2 C22 C434 C424 C431
K19 VCC43 VCCA_3GPLL1 Y28 M3 VTT44 VCCSM44 AG13
W18 VCC44 VCCA_3GPLL2 Y27 N2 VTT45 VCCSM45 AF13
V18 VCC45 M2 VTT46 VCCSM46 AE13
2 4.7U_0805_10V4Z 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 2 0.022U_0402_16V7K
T18 VCC46 B2 VTT47 VCCSM47 AP12
K18 VCC47 VCCA_3GBG F37 0.15mA +2.5VS_3GBG V1 VTT48 VCCSM48 AN12
K17 VCC48 VSSA_3GBG G37 N1 VTT49 VCCSM49 AM12
1 M1 VTT50 VCCSM50 AL12
+1.5VS AC1 VCCD_HMPLL1 VCC_SYNC H20 +2.5VS G1 VTT51 VCCSM51 AK12 VCC_SYNC(Ball H20)
AC2 VCCD_HMPLL2 VCCSM52 AJ12
+1.5VS_DPLLA +1.5VS_DPLLA B23 F19 70mA C24 AH12
+1.5VS_DPLLB VCCA_DPLLA VCCA_CRTDAC0 0.47U_0603_16V4Z 2 VCCSM53
+1.5VS_DPLLB
+1.5VS_HPLL
C35 VCCA_DPLLB VCCA_CRTDAC1 E19 VCCSM54 AG12
+1.5VS VCCD_TVDAC (Ball D19)
+1.5VS_HPLL AA1 VCCA_HPLL VSSA_CRTDAC G19 1 VCCSM55 AF12
+1.5VS_MPLL +1.5VS_MPLL AA2 AE12 0.1U_0402_16V4Z 0.1U_0402_16V4Z
VCCA_MPLL VCCSM56
VCCSM57 AD11
C49 AC11
ALVISO_BGA1257 0.22U_0402_10V4Z 2 VCCSM58
VCCSM59 AB11 1 1 1 1 1 1
1 AB10 C82 C20 C415 C421 C425 C440 C437
VCCSM60 0.1U_0402_16V4Z C517
VCCSM61 AB9
VCCSM62 AP8 V 1.8_DDR_CAP6 2 1 0.1U_0402_16V4Z
C34 AM1 V 1.8_DDR_CAP4 2 1 4.7U_0805_10V4Z 2 2 2 2 2 2
0.22U_0402_10V4Z 2 VCCSM63
VCCSM64 AE1 V 1.8_DDR_CAP3 2 1
B C490 0.1U_0402_16V4Z 0.022U_0402_16V7K 0.022U_0402_16V7K B
0.1U_0402_16V4Z
ALVISO_BGA1257 VCCD_LVDS(Ball A25,B25,B26) VCCDQ_TVDAC (Ball H17)
+1.05VS
950mA

1 1 1 1
+1.5VS_DPLLA L6 +1.5VS_DPLLB L25 +1.5VS_DDRDLL R86 +1.5VS_PEG R415 C462 C463 C474 C469
60mA CHB1608U301_0603 60mA CHB1608U301_0603 0_0603_5% 0_0603_5%
1 2 +1.5VS 1 2 +1.5VS 1 2 +1.5VS 1 2 +1.5VS 2 2.2U_0603_6.3V6K 2 2.2U_0603_6.3V6K 2 2.2U_0603_6.3V6K 2 2.2U_0603_6.3V6K
Change to 0 ohm Change to 0 ohm 1
1 1 1 1 1 1 1 1 1
C412 C418 C426 C420 C84 C496 C446 C449 C439 + C53

2 22U_1206_16V4Z_V1 2 0.1U_0402_16V4Z 2 22U_1206_16V4Z_V1 2 0.1U_0402_16V4Z 2 22U_1206_16V4Z_V1 2 0.1U_0402_16V4Z 2 22U_1206_16V4Z_V1 2 4.7U_0805_10V4Z 2 4.7U_0805_10V4Z 2 470U_D2_2.5VM
VCCA_TVDAC VCCA_TVBG
+3VS_DAC (Ball H18)
+3VS 0.022U_0402_16V7K 0.022U_0402_16V7K

1 1 1 1
C432 C422 C433 C438

+1.5VS_HPLL L7 +1.5VS_MPLL L8 +1.5VS_3GPLL R79 L9 +2.5VS_3GBG

CHB1608U301_0603 CHB1608U301_0603 0.5_0603_1% CHB1608U301_0603 2 2 2 2
60mA 60mA
A 1 2 +1.5VS 1 2 +1.5VS 1 2+3GPLL 1 2 +1.5VS 1 2 +2.5VS A
Change to 0 ohm Change to 0 ohm R410 0_0603_5% 0.1U_0402_16V4Z 0.1U_0402_16V4Z
1 1 1 1 1 1 Change to 0 ohm 1
C50 C478 C52 C482 C55 120mA
C475 C428
0.1U_0402_16V4Z
2 22U_1206_16V4Z_V1 2 0.1U_0402_16V4Z 2 22U_1206_16V4Z_V1 2 0.1U_0402_16V4Z 2 10U_1206_16V4Z 2 0.1U_0402_16V4Z 2
Compal Electronics, Inc.
Title
SCHEMATIC, M/B LA-2492
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
401317 B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: ¬P 期一, 一月 03, 2005 Sheet 9 of 51
5 4 3 2 1
 5 4 3 2 1

U 5H
U5I U5J
+1.05VS L12 VTT_NCTF17 VCCSM_NCTF31 AB12 +DDRVCC
M12 VTT_NCTF16 VCCSM_NCTF30 AC12 Y1 VSS271 AL24 VSS267
N12 VTT_NCTF15 VCCSM_NCTF29 AD12 D2 VSS270 VSSALVDS B36 AN24 VSS266 VSS67 AC32
P12 VTT_NCTF14 VCCSM_NCTF28 AB13 G2 VSS269 A26 VSS265 VSS66 AD32
R12 VTT_NCTF13 VCCSM_NCTF27 AC13 J2 VSS268 VSS195 AA11 E26 VSS264 VSS65 AJ32
T12 VTT_NCTF12 VCCSM_NCTF26 AD13 L2 VSS260 VSS194 AF11 G26 VSS263 VSS64 AN32
U12 VTT_NCTF11 VCCSM_NCTF25 AC14 P2 VSS259 VSS193 AG11 J26 VSS262 VSS63 D33
D V12 VTT_NCTF10 VCCSM_NCTF24 AD14 T2 VSS258 VSS192 AJ11 B27 VSS261 VSS62 E33 D
W12 VTT_NCTF9 VCCSM_NCTF23 AC15 V2 VSS257 VSS191 AL11 E27 VSS129 VSS61 F33
L13 VTT_NCTF8 VCCSM_NCTF22 AD15 AD2 VSS256 VSS190 AN11 G27 VSS128 VSS60 G33
M13 VTT_NCTF7 VCCSM_NCTF21 AC16 AE2 VSS255 VSS189 B12 W27 VSS127 VSS59 H33
N13
P13
R13
T13
U13
VTT_NCTF6
VTT_NCTF5
VTT_NCTF4
VTT_NCTF3
VCCSM_NCTF20
VCCSM_NCTF19
VCCSM_NCTF18
VCCSM_NCTF17
AD16
AC17
AD17
AC18
AD18
AH2
AL2
AN2
A3
C3
VSS254
VSS253
VSS252
VSS251
VSS
VSS188
VSS187
VSS186
VSS185
D12
J12
A14
B14
F14
AA27
AB27
AF27
AG27
AJ27
VSS126
VSS125
VSS124
VSS123
VSS VSS58
VSS57
VSS56
VSS55
J33
K33
L33
M33
N33
VTT_NCTF2 VCCSM_NCTF16 VSS250 VSS184 VSS122 VSS54
V13 VTT_NCTF1 VCCSM_NCTF15 AC19 AA3 VSS249 VSS183 J14 AL27 VSS121 VSS53 P33
W13 VTT_NCTF0 VCCSM_NCTF14 AD19 AB3 VSS248 VSS182 K14 AN27 VSS120 VSS52 R33
VCCSM_NCTF13 AC20 AC3 VSS247 VSS181 AG14 E28 VSS119 VSS51 T33
VCCSM_NCTF12 AD20 AJ3 VSS246 VSS180 AJ14 W28 VSS118 VSS50 U33
Y12 VSS_NCTF68 VCCSM_NCTF11 AC21 C4 VSS245 VSS179 AL14 AA28 VSS117 VSS49 V33
AA12 VSS_NCTF67 VCCSM_NCTF10 AD21 H4 VSS244 VSS178 AN14 AB28 VSS116 VSS48 W33
Y13 VSS_NCTF66 VCCSM_NCTF9 AC22 L4 VSS243 VSS177 C15 AC28 VSS115 VSS47 AD33
AA13 VSS_NCTF65 VCCSM_NCTF8 AD22 P4 VSS242 VSS176 K15 A29 VSS114 VSS46 AF33
L14 VSS_NCTF64 VCCSM_NCTF7 AC23 U4 VSS241 VSS175 A16 D29 VSS113 VSS45 AL33
M14 VSS_NCTF63 VCCSM_NCTF6 AD23 Y4 VSS240 VSS174 D16 E29 VSS112 VSS44 C34
N14 VSS_NCTF62 VCCSM_NCTF5 AC24 AF4 VSS239 VSS173 H16 F29 VSS111 VSS43 AA34
P14 VSS_NCTF61 VCCSM_NCTF4 AD24 AN4 VSS238 VSS172 K16 G29 VSS110 VSS42 AB34
R14 VSS_NCTF60 VCCSM_NCTF3 AC25 E5 VSS237 VSS171 AL16 H29 VSS109 VSS41 AC34
T14 VSS_NCTF59 VCCSM_NCTF2 AD25 W5 VSS236 VSS170 C17 L29 VSS108 VSS40 AD34
U14 VSS_NCTF58 VCCSM_NCTF1 AC26 AL5 VSS235 VSS169 G17 P29 VSS107 VSS39 AH34
V14 VSS_NCTF57 VCCSM_NCTF0 AD26 AP5 VSS234 VSS168 AF17 U29 VSS106 VSS38 AN34
W14 VSS_NCTF56 B6 VSS233 VSS167 AJ17 V29 VSS105 VSS37 B35
Y14 VSS_NCTF55 VCC_NCTF78 L17 +1.05VS J6 VSS232 VSS166 AN17 W29 VSS104 VSS36 D35
AA14 VSS_NCTF54 VCC_NCTF77 M17 L6 VSS231 VSS165 A18 AA29 VSS103 VSS35 E35
AB14 VSS_NCTF53 VCC_NCTF76 N17 P6 VSS230 VSS164 B18 AD29 VSS102 VSS34 F35
C L15 P17 T6 U18 AG29 G35 C
VSS_NCTF52 VCC_NCTF75 VSS229 VSS163 VSS101 VSS33
M15 T17 AA6 AL18 AJ29 H35
NCTF

VSS_NCTF51 VCC_NCTF74 VSS228 VSS162 VSS100 VSS32

N15 VSS_NCTF50 VCC_NCTF73 U17 AC6 VSS227 VSS161 C19 AM29 VSS99 VSS31 J35
P15 VSS_NCTF49 VCC_NCTF72 V17 AE6 VSS226 VSS160 H19 C30 VSS98 VSS30 K35
R15 VSS_NCTF48 VCC_NCTF71 W17 AJ6 VSS225 VSS159 J19 Y30 VSS97 VSS29 L35
T15 VSS_NCTF47 VCC_NCTF70 L18 G7 VSS224 VSS158 T19 AA30 VSS96 VSS28 M35
U15 VSS_NCTF46 VCC_NCTF69 M18 V7 VSS223 VSS157 W19 AB30 VSS95 VSS27 N35
V15 VSS_NCTF45 VCC_NCTF68 N18 AA7 VSS222 VSS156 AG19 AC30 VSS94 VSS26 P35
W15 VSS_NCTF44 VCC_NCTF67 P18 AG7 VSS221 VSS155 AN19 AE30 VSS93 VSS25 R35
Y15 VSS_NCTF43 VCC_NCTF66 R18 AK7 VSS220 VSS154 A20 AP30 VSS92 VSS24 T35
AA15 VSS_NCTF42 VCC_NCTF65 Y18 AN7 VSS219 VSS153 D20 D31 VSS91 VSS23 U35
AB15 VSS_NCTF41 VCC_NCTF64 L19 C8 VSS218 VSS152 E20 E31 VSS90 VSS22 V35
L16 VSS_NCTF40 VCC_NCTF63 M19 E8 VSS217 VSS151 F20 F31 VSS89 VSS21 W35
M16 VSS_NCTF39 VCC_NCTF62 N19 L8 VSS216 VSS150 G20 G31 VSS88 VSS20 Y35
N16 VSS_NCTF38 VCC_NCTF61 P19 P8 VSS215 VSS149 V20 H31 VSS87 VSS19 AE35
P16 VSS_NCTF37 VCC_NCTF60 R19 Y8 VSS214 VSS148 AK20 J31 VSS86 VSS18 C36
R16 VSS_NCTF36 VCC_NCTF59 Y19 AL8 VSS213 VSS147 C21 K31 VSS85 VSS17 AA36
T16 VSS_NCTF35 VCC_NCTF58 L20 A9 VSS212 VSS146 F21 L31 VSS84 VSS16 AB36
U16 VSS_NCTF34 VCC_NCTF57 M20 H9 VSS211 VSS145 AF21 M31 VSS83 VSS15 AC36
V16 VSS_NCTF33 VCC_NCTF56 N20 K9 VSS210 VSS144 AN21 N31 VSS82 VSS14 AD36
W16 VSS_NCTF32 VCC_NCTF55 P20 T9 VSS209 VSS143 A22 P31 VSS81 VSS13 AE36
Y16 VSS_NCTF31 VCC_NCTF54 R20 V9 VSS208 VSS142 D22 R31 VSS80 VSS12 AF36
AA16 VSS_NCTF30 VCC_NCTF53 Y20 AA9 VSS207 VSS141 E22 T31 VSS79 VSS11 AJ36
AB16 VSS_NCTF29 VCC_NCTF52 L21 AC9 VSS206 VSS140 J22 U31 VSS78 VSS10 AL36
R17 VSS_NCTF28 VCC_NCTF51 M21 AE9 VSS205 VSS139 AH22 V31 VSS77 VSS9 AN36
Y17 VSS_NCTF27 VCC_NCTF50 N21 AH9 VSS204 VSS138 AL22 W31 VSS76 VSS8 E37
AA17 VSS_NCTF26 VCC_NCTF49 P21 AN9 VSS203 VSS137 H23 AD31 VSS75 VSS7 H37
AB17 VSS_NCTF25 VCC_NCTF48 T21 D10 VSS202 VSS136 AF23 AG31 VSS74 VSS6 K37
AA18 VSS_NCTF24 VCC_NCTF47 U21 L10 VSS201 VSS135 B24 AL31 VSS73 VSS5 M37
B B
AB18 VSS_NCTF23 VCC_NCTF46 V21 Y10 VSS200 VSS134 D24 A32 VSS72 VSS4 P37
AA19 VSS_NCTF22 VCC_NCTF45 W21 AA10 VSS199 VSS133 F24 C32 VSS71 VSS3 T37
AB19 VSS_NCTF21 VCC_NCTF44 L22 F11 VSS198 VSS132 J24 Y32 VSS70 VSS2 V37
AA20 VSS_NCTF20 VCC_NCTF43 M22 H11 VSS197 VSS131 AG24 AA32 VSS69 VSS1 Y37
AB20 VSS_NCTF19 VCC_NCTF42 N22 Y11 VSS196 VSS130 AJ24 AB32 VSS68 VSS0 AG37
R21 VSS_NCTF18 VCC_NCTF41 P22
Y21 VSS_NCTF17 VCC_NCTF40 R22
AA21 VSS_NCTF16 VCC_NCTF39 T22
AB21 U22 ALVISO_BGA1257 ALVISO_BGA1257
VSS_NCTF15 VCC_NCTF38
Y22 VSS_NCTF14 VCC_NCTF37 V22
AA22 VSS_NCTF13 VCC_NCTF36 W22
AB22 VSS_NCTF12 VCC_NCTF35 L23
Y23 VSS_NCTF11 VCC_NCTF34 M23
AA23 VSS_NCTF10 VCC_NCTF33 N23
AB23 VSS_NCTF9 VCC_NCTF32 P23
Y24 VSS_NCTF8 VCC_NCTF31 R23
AA24 VSS_NCTF7 VCC_NCTF30 T23
AB24 VSS_NCTF6 VCC_NCTF29 U23
Y25 VSS_NCTF5 VCC_NCTF28 V23
AA25 VSS_NCTF4 VCC_NCTF27 W23
AB25 VSS_NCTF3 VCC_NCTF26 L24
Y26 VSS_NCTF2 VCC_NCTF25 M24
AA26 VSS_NCTF1 VCC_NCTF24 N24
AB26 VSS_NCTF0 VCC_NCTF23 P24
VCC_NCTF22 R24
+1.05VS V25 VCC_NCTF10 VCC_NCTF21 T24
W25 VCC_NCTF9 VCC_NCTF20 U24
L26 VCC_NCTF8 VCC_NCTF19 V24
A M26 VCC_NCTF7 VCC_NCTF18 W24 A
N26 VCC_NCTF6 VCC_NCTF17 L25
P26 VCC_NCTF5 VCC_NCTF16 M25
R26 VCC_NCTF4 VCC_NCTF15 N25
T26 VCC_NCTF3 VCC_NCTF14 P25
U26 VCC_NCTF2 VCC_NCTF13 R25
V26 T25
W26
VCC_NCTF1 VCC_NCTF12
U25 Compal Electronics, Inc.
VCC_NCTF0 VCC_NCTF11 Title
SCHEMATIC, M/B LA-2492
ALVISO_BGA1257
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
401317 B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: ¬P 期一, 一月 03, 2005 Sheet 10 of 51
5 4 3 2 1
 5 4 3 2 1

+DDRVCC +DDRVCC +DIMM_VREF +DDRVCC RP25 RP55

JP24 DD RA_SDQ0 1 4 DDR A_DQ0 DD RA_SDQ1 1 4 DDR A_DQ1
1 2 DD RA_SDQ4 2 3 DDR A_DQ4 DD RA_SDQ5 2 3 DDR A_DQ5
VREF VREF

1
3 4 R92 +DDRVTT
DDR A_DQ1 VSS VSS DDR A_DQ0 10_0404_4P2R_5% 10_0404_4P2R_5%
5 DQ0 DQ4 6
DDR A_DQ5 7 8 DDR A_DQ4 RP24 RP54
DQ1 DQ5 1K_0402_1% DDRA_SDM0
9 VDD VDD 10 1 4 D DRA_DM0 DD RA_SDQS0 1 4 DD RA_DQS0
DD RA_DQS0 11 12 D DRA_DM0 DD RA_SDQ6 2 3 DDR A_DQ6 DD RA_SDQ7 2 3 DDR A_DQ7

2
DDR A_DQ7 DQS0 DM0 DDR A_DQ6
13 DQ2 DQ6 14
15 16 10_0404_4P2R_5% 10_0404_4P2R_5%
VSS VSS

1
D DDR A_DQ3 17 18 DDR A_DQ2 1 R91 RP23 RP53 RP30 D
DD RA_DQ13 DQ3 DQ7 DDR A_DQ8 DD RA_SDQ2
19 DQ8 DQ12 20 1 4 DDR A_DQ2 DD RA_SDQ3 1 4 DDR A_DQ3 DDRA_SMA11 2 3
21 22 DD RA_SDQ8 2 3 DDR A_DQ8 D DRA_SDQ13 2 3 DD RA_DQ13 DDRA_SMA8 1 4
DDR A_DQ9 VDD VDD DD RA_DQ12 1K_0402_1%
23 DQ9 DQ13 24
DD RA_DQS1 D DRA_DM1 2 10_0404_4P2R_5% 10_0404_4P2R_5% 56_0404_4P2R_5%
25 26

2
DQS1 DM1 RP29
27 28 RP22 RP52
DD RA_DQ15 VSS VSS DD RA_DQ14 D DRA_SDQ12
29 DQ10 DQ14 30 1 4 DD RA_DQ12 DD RA_SDQ9 1 4 DDR A_DQ9 DDRA_SMA6 2 3
DD RA_DQ11 31 32 DD RA_DQ10 C121 DDRA_SDM1 2 3 D DRA_DM1 DD RA_SDQS1 2 3 DD RA_DQS1 DDRA_SMA4 1 4
DQ11 DQ15 0.1U_0402_16V4Z
33 VDD VDD 34
35 36 10_0404_4P2R_5% 10_0404_4P2R_5% 56_0404_4P2R_5%
6 DDRA_CLK1 CK0 VDD
37 38 RP21 RP51 RP28
6 DDRA_CLK1# CK0# VSS
39 40 D DRA_SDQ14 1 4 DD RA_DQ14 D DRA_SDQ15 1 4 DD RA_DQ15 DDRA_SMA2 2 3
VSS VSS D DRA_SDQ10 2 3 DD RA_DQ10 D DRA_SDQ11 2 3 DD RA_DQ11 DDRA_SMA0 1 4

DD RA_DQ16 41 42 DD RA_DQ17 10_0404_4P2R_5% 10_0404_4P2R_5% 56_0404_4P2R_5%

DD RA_DQ20 DQ16 DQ20 DD RA_DQ21 RP27
43 44 RP20 RP50
DQ17 DQ21 D DRA_SDQ17 DD RA_DQ17 D DRA_SDQ16
45 VDD VDD 46 1 4 1 4 DD RA_DQ16 DDRA_SBS1 2 3
DD RA_DQS2 47 48 D DRA_DM2 D DRA_SDQ21 2 3 DD RA_DQ21 D DRA_SDQ20 2 3 DD RA_DQ20 D DRA_SRAS# 1 4
DD RA_DQ18 DQS2 DM2 DD RA_DQ19
49 DQ18 DQ22 50
51 52 10_0404_4P2R_5% 10_0404_4P2R_5% 56_0404_4P2R_5%
DD RA_DQ22 VSS VSS DD RA_DQ23 RP26
53 54 RP19 RP49
DD RA_DQ25 DQ19 DQ23 DD RA_DQ24 DDRA_SDM2 D DRA_DM2 DD RA_SDQS2
55 DQ24 DQ28 56 1 4 1 4 DD RA_DQS2 D DRA_SCAS# 2 3
57 58 D DRA_SDQ19 2 3 DD RA_DQ19 D DRA_SDQ18 2 3 DD RA_DQ18 D DRA_SCS#1 1 4
DD RA_DQ29 VDD VDD DD RA_DQ28
59 DQ25 DQ29 60
DD RA_DQS3 61 62 D DRA_DM3 10_0404_4P2R_5% 10_0404_4P2R_5% 56_0404_4P2R_5%
DQS3 DM3
63 64 RP18 RP48
DD RA_DQ27 VSS VSS DD RA_DQ26 D DRA_SDQ23 DD RA_DQ23 D DRA_SDQ22
65 DQ26 DQ30 66 1 4 1 4 DD RA_DQ22 RP35
DD RA_DQ30 67 68 DD RA_DQ31 D DRA_SDQ24 2 3 DD RA_DQ24 D DRA_SDQ25 2 3 DD RA_DQ25 DDRA_SMA12 2 3
DQ27 DQ31 DDRA_SMA9
69 VDD VDD 70 1 4
C 71 72 10_0404_4P2R_5% 10_0404_4P2R_5% C
CB0 CB4 56_0404_4P2R_5%
73 74 RP17 RP47
CB1 CB5 D DRA_SDQ28
75 VSS VSS 76 1 4 DD RA_DQ28 D DRA_SDQ29 1 4 DD RA_DQ29 RP34
77 78 DDRA_SDM3 2 3 D DRA_DM3 DD RA_SDQS3 2 3 DD RA_DQS3 DDRA_SMA7 2 3
DQS8 DM8 DDRA_SMA5
79 CB2 CB6 80 1 4
81 82 10_0404_4P2R_5% 10_0404_4P2R_5%
VDD VDD 56_0404_4P2R_5%
83 84 RP16 RP46
CB3 CB7 D DRA_SDQ26
85 DU DU/RESET# 86 1 4 DD RA_DQ26 D DRA_SDQ27 1 4 DD RA_DQ27 RP33
87 88 D DRA_SDQ31 2 3 DD RA_DQ31 D DRA_SDQ30 2 3 DD RA_DQ30 DDRA_SMA3 2 3
VSS VSS DDRA_SMA1
89 CK2 VSS 90 1 4
91 92 10_0404_4P2R_5% 10_0404_4P2R_5%
CK2# VDD 56_0404_4P2R_5%
93 94 RP15 RP45
DD RA_CKE1 VDD VDD DD RA_CKE0 D DRA_SDQ37
6 DDRA_CKE1 95 CKE1 CKE0 96 DDRA_CKE0 6 1 4 DD RA_DQ37 D DRA_SDQ36 1 4 DD RA_DQ36 RP32
97 98 D DRA_SDQ32 2 3 DD RA_DQ32 D DRA_SDQ33 2 3 DD RA_DQ33 DDRA_SMA10 2 3
DDRA_SMA12 DU/A13 DU/BA2 DDRA_SMA11 DDRA_SBS0
99 A12 A11 100 1 4
DDRA_SMA9 101 102 DDRA_SMA8 10_0404_4P2R_5% 10_0404_4P2R_5%
A9 A8 56_0404_4P2R_5%
103 104 RP14 RP44
DDRA_SMA7 VSS VSS DDRA_SMA6 DDRA_SDM4
105 A7 A6 106 1 4 D DRA_DM4 DD RA_SDQS4 1 4 DD RA_DQS4 RP31
DDRA_SMA5 107 108 DDRA_SMA4 D DRA_SDQ39 2 3 DD RA_DQ39 D DRA_SDQ38 2 3 DD RA_DQ38 DDRA_SW E# 2 3
DDRA_SMA3 A5 A4 DDRA_SMA2 D DRA_SCS#0
109 A3 A2 110 1 4
DDRA_SMA1 111 112 DDRA_SMA0 10_0404_4P2R_5% 10_0404_4P2R_5%
A1 A0 56_0404_4P2R_5%
113 114 RP13 RP43
DDRA_SMA10 VDD VDD DDRA_SBS1 D DRA_SDQ34
115 A10/AP BA1 116 DDRA_SBS1 7 1 4 DD RA_DQ34 D DRA_SDQ35 1 4 DD RA_DQ35
DDRA_SBS0 117 118 D DRA_SRAS# D DRA_SDQ45 2 3 DD RA_DQ45 D DRA_SDQ41 2 3 DD RA_DQ41 DDRA_SMA13 1 2
7 DDRA_SBS0 BA0 RAS# DDRA_SRAS# 7
DDRA_SW E# 119 120 D DRA_SCAS# R89 56_0402_5%
7 DDRA_SW E# WE# CAS# DDRA_SCAS# 7
D DRA_SCS#0 121 122 D DRA_SCS#1 10_0404_4P2R_5% 10_0404_4P2R_5% DD RA_CKE1 1 2
6 DDRA_SCS#0 S0# S1# DDRA_SCS#1 6
DDRA_SMA13 123 124 RP12 RP42 R90 56_0402_5%
DU DU D DRA_SDQ40
125 VSS VSS 126 1 4 DD RA_DQ40 D DRA_SDQ44 1 4 DD RA_DQ44 DD RA_CKE0 1 2
DD RA_DQ36 127 128 DD RA_DQ37 DDRA_SDM5 2 3 D DRA_DM5 DD RA_SDQS5 2 3 DD RA_DQS5 R87 56_0402_5%
B DD RA_DQ33 DQ32 DQ36 DD RA_DQ32 B
129 DQ33 DQ37 130
131 132 10_0404_4P2R_5% 10_0404_4P2R_5%
DD RA_DQS4 VDD VDD D DRA_DM4
133 134 RP11 RP41
DD RA_DQ38 DQS4 DM4 DD RA_DQ39 D DRA_SDQ42
135 DQ34 DQ38 136 1 4 DD RA_DQ42 D DRA_SDQ46 1 4 DD RA_DQ46
137 138 D DRA_SDQ43 2 3 DD RA_DQ43 D DRA_SDQ47 2 3 DD RA_DQ47 DDRA_DQ[0..63]
DD RA_DQ35 VSS VSS DD RA_DQ34 DDRA_DQ[0..63] 12
139 DQ35 DQ39 140
DD RA_DQ41 141 142 DD RA_DQ45 10_0404_4P2R_5% 10_0404_4P2R_5% DDRA_DM [0..7]
DQ40 DQ44 DDRA_DM[0..7] 12
143 144 RP10 RP40
DD RA_DQ44 VDD VDD DD RA_DQ40 D DRA_SDQ49 DDRA_DQS [0..7]
145 DQ41 DQ45 146 1 4 DD RA_DQ49 D DRA_SDQ52 1 4 DD RA_DQ52 DDRA_DQS[0..7] 12
DD RA_DQS5 147 148 D DRA_DM5 D DRA_SDQ48 2 3 DD RA_DQ48 D DRA_SDQ53 2 3 DD RA_DQ53
DQS5 DM5
149 VSS VSS 150
DD RA_DQ46 151 152 DD RA_DQ42 10_0404_4P2R_5% 10_0404_4P2R_5%
DD RA_DQ47 DQ42 DQ46 DD RA_DQ43
153 154 RP9 RP39
DQ43 DQ47 DDRA_SDM6
155 VDD VDD 156 1 4 D DRA_DM6 DD RA_SDQS6 1 4 DD RA_DQS6
157 158 D DRA_SDQ55 2 3 DD RA_DQ55 D DRA_SDQ54 2 3 DD RA_DQ54
VDD CK1# DDRA_CLK2# 6
159 VSS CK1 160 DDRA_CLK2 6
161 162 10_0404_4P2R_5% 10_0404_4P2R_5% DDRA_SD Q[0..63]
DD RA_DQ52 VSS VSS DD RA_DQ49 7 DDRA_SDQ[0..63]
163 164 RP8 RP38
DD RA_DQ53 DQ48 DQ52 DD RA_DQ48 D DRA_SDQ51 DDRA_S DM[0..7]
165 DQ49 DQ53 166 1 4 DD RA_DQ51 D DRA_SDQ50 1 4 DD RA_DQ50 7 DDRA_SDM[0..7]
167 168 D DRA_SDQ61 2 3 DD RA_DQ61 D DRA_SDQ60 2 3 DD RA_DQ60
DD RA_DQS6 VDD VDD D DRA_DM6 DDRA_SD QS[0..7]
169 DQS6 DM6 170 7 DDRA_SDQS[0..7]
DD RA_DQ54 171 172 DD RA_DQ55 10_0404_4P2R_5% 10_0404_4P2R_5%
DQ50 DQ54 DDR A_SMA[0..13]
173 174 RP7 RP37 7 DDRA_SMA[0..13]
DD RA_DQ50 VSS VSS DD RA_DQ51 D DRA_SDQ58
175 DQ51 DQ55 176 1 4 DD RA_DQ58 D DRA_SDQ56 1 4 DD RA_DQ56
DD RA_DQ60 177 178 DD RA_DQ61 DDRA_SDM7 2 3 D DRA_DM7 DD RA_SDQS7 2 3 DD RA_DQS7
DQ56 DQ60
179 VDD VDD 180
DD RA_DQ56 181 182 DD RA_DQ58 10_0404_4P2R_5% 10_0404_4P2R_5%
DD RA_DQS7 DQ57 DQ61 D DRA_DM7
183 184 RP6 RP36
DQS7 DM7 D DRA_SDQ63
A 185 VSS VSS 186 1 4 DD RA_DQ63 D DRA_SDQ57 1 4 DD RA_DQ57 A
DD RA_DQ57 187 188 DD RA_DQ63 D DRA_SDQ59 2 3 DD RA_DQ59 D DRA_SDQ62 2 3 DD RA_DQ62
DD RA_DQ62 DQ58 DQ62 DD RA_DQ59
189 DQ59 DQ63 190
191 192 10_0404_4P2R_5% 10_0404_4P2R_5%
D_CK_SDATA VDD VDD
12,14 D_CK_SDATA 193 SDA SA0 194
D_CK_SCLK 195 196
12,14 D_CK_SCLK SCL SA1
197 198
+3VS
199
VDD_SPD SA2
200 Compal Electronics, Inc.
VDD_ID DU Title
SCHEMATIC, M/B LA-2492
AMP_1565917-1 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
DIMM0 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401317 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: ¬P 期一, 一月 03, 2005 Sheet 11 of 51
5 4 3 2 1
 A B C D E

+DDRVCC +DDRVCC +DIMM_VREF

JP25
1 VREF VREF 2
+DDRVTT 3 4
DDR A_DQ1 VSS VSS DDR A_DQ0
5 DQ0 DQ4 6 1
DDRA_DQ[0..63] DDR A_DQ5 7 8 DDR A_DQ4 C120
11 DDRA_DQ[0..63] DQ1 DQ5
9 VDD VDD 10
RP80 RP94 DDRA_DM [0..7] DD RA_DQS0 11 12 D DRA_DM0 0.1U_0402_16V4Z
11 DDRA_DM[0..7] DQS0 DM0 2
DDR A_DQ0 1 4 3 2 DDR A_DQ1 DDR A_DQ7 13 14 DDR A_DQ6
DDR A_DQ4 DDR A_DQ5 DDRA_DQS [0..7] DQ2 DQ6
2 3 4 1 11 DDRA_DQS[0..7] 15 VSS VSS 16
DDR A_DQ3 17 18 DDR A_DQ2
56_0404_4P2R_5% 56_0404_4P2R_5% DDR B_SMA[0..13] DD RA_DQ13 DQ3 DQ7 DDR A_DQ8
7 DDRB_SMA[0..13] 19 DQ8 DQ12 20
RP79 RP95 21 22
D DRA_DM0 DD RA_DQS0 DDR A_DQ9 VDD VDD DD RA_DQ12
1 1 4 3 2 23 DQ9 DQ13 24 1
DDR A_DQ6 2 3 4 1 DDR A_DQ7 DD RA_DQS1 25 26 D DRA_DM1
DQS1 DM1
27 VSS VSS 28
56_0404_4P2R_5% 56_0404_4P2R_5% DD RA_DQ15 29 30 DD RA_DQ14
RP96 DD RA_DQ11 DQ10 DQ14 DD RA_DQ10
RP78 31 32
DDR A_DQ2 DDR A_DQ3 DQ11 DQ15
1 4 3 2 33 VDD VDD 34
DDR A_DQ8 2 3 4 1 DD RA_DQ13 35 36
6 DDRB_CLK1 CK0 VDD
6 DDRB_CLK1# 37 CK0# VSS 38
56_0404_4P2R_5% 56_0404_4P2R_5% 39 40
RP97 VSS VSS
RP77
DD RA_DQ12 1 4 3 2 DDR A_DQ9
D DRA_DM1 2 3 4 1 DD RA_DQS1 DD RA_DQ16 41 42 DD RA_DQ17
DD RA_DQ20 DQ16 DQ20 DD RA_DQ21
43 DQ17 DQ21 44
56_0404_4P2R_5% 56_0404_4P2R_5% 45 46
RP98 DD RA_DQS2 VDD VDD D DRA_DM2
RP76 47 48
DD RA_DQ14 DD RA_DQ15 DD RA_DQ18 DQS2 DM2 DD RA_DQ19
1 4 3 2 49 DQ18 DQ22 50
DD RA_DQ10 2 3 4 1 DD RA_DQ11 51 52
DD RA_DQ22 VSS VSS DD RA_DQ23
53 DQ19 DQ23 54
56_0404_4P2R_5% 56_0404_4P2R_5% DD RA_DQ25 55 56 DD RA_DQ24
RP99 DQ24 DQ28
RP75 57 58
DD RA_DQ17 DD RA_DQ16 DD RA_DQ29 VDD VDD DD RA_DQ28
1 4 3 2 59 DQ25 DQ29 60
DD RA_DQ21 2 3 4 1 DD RA_DQ20 DD RA_DQS3 61 62 D DRA_DM3
DQS3 DM3
63 VSS VSS 64
56_0404_4P2R_5% 56_0404_4P2R_5% DD RA_DQ27 65 66 DD RA_DQ26
RP100 DD RA_DQ30 DQ26 DQ30 DD RA_DQ31
RP74 67 68
D DRA_DM2 DD RA_DQS2 DQ27 DQ31
1 4 3 2 69 VDD VDD 70
DD RA_DQ19 2 3 4 1 DD RA_DQ18 71 72
CB0 CB4
73 CB1 CB5 74
56_0404_4P2R_5% 56_0404_4P2R_5% 75 76
2 RP101 VSS VSS 2
RP73 77 78
DD RA_DQ23 DD RA_DQ22 DQS8 DM8
1 4 3 2 79 CB2 CB6 80
DD RA_DQ24 2 3 4 1 DD RA_DQ25 +DDRVTT 81 82
VDD VDD
83 CB3 CB7 84
56_0404_4P2R_5% 56_0404_4P2R_5% 85 86
RP102 DU DU/RESET#
RP72 87 88
DD RA_DQ28 DD RA_DQ29 VSS VSS
1 4 3 2 89 CK2 VSS 90
D DRA_DM3 2 3 4 1 DD RA_DQS3 2 1 DDRB_SMA10 91 92
56_0402_5% R445 CK2# VDD
93 VDD VDD 94
56_0404_4P2R_5% 56_0404_4P2R_5% 2 1 DD RB_CKE1 DD RB_CKE1 95 96 DD RB_CKE0
6 DDRB_CKE1 CKE1 CKE0 DDRB_CKE0 6
RP71 RP103 56_0402_5% R444 97 98
DD RA_DQ26 DD RA_DQ27 DD RB_CKE0 DDRB_SMA12 DU/A13 DU/BA2 DDRB_SMA11
1 4 3 2 2 1 99 A12 A11 100
DD RA_DQ31 2 3 4 1 DD RA_DQ30 56_0402_5% R93 DDRB_SMA9 101 102 DDRB_SMA8
A9 A8
103 VSS VSS 104
56_0404_4P2R_5% 56_0404_4P2R_5% RP59 DDRB_SMA7 105 106 DDRB_SMA6
RP104 D DRA_DM6 DDRB_SMA5 A7 A6 DDRB_SMA4
RP70 4 1 107 108
DDRB_SMA11 DDRB_SMA12 DD RA_DQ55 DDRB_SMA3 A5 A4 DDRB_SMA2
1 4 3 2 3 2 109 A3 A2 110
DDRB_SMA8 2 3 4 1 DDRB_SMA9 DDRB_SMA1 111 112 DDRB_SMA0
56_0404_4P2R_5% A1 A0
113 VDD VDD 114
56_0404_4P2R_5% 56_0404_4P2R_5% RP58 DDRB_SMA10 115 116 DDRB_SBS1
A10/AP BA1 DDRB_SBS1 7
RP69 RP105 4 1 DD RA_DQ51 DDRB_SBS0 117 118 D DRB_SRAS#
7 DDRB_SBS0 BA0 RAS# DDRB_SRAS# 7
DDRB_SMA6 1 4 3 2 DDRB_SMA7 3 2 DD RA_DQ61 DDRB_SW E# 119 120 D DRB_SCAS#
7 DDRB_SW E# WE# CAS# DDRB_SCAS# 7
DDRB_SMA4 2 3 4 1 DDRB_SMA5 D DRB_SCS#0 121 122 D DRB_SCS#1
6 DDRB_SCS#0 S0# S1# DDRB_SCS#1 6
56_0404_4P2R_5% DDRB_SMA13 123 124
56_0404_4P2R_5% 56_0404_4P2R_5% DU DU
RP57 125 126
RP106 DD RA_DQ58 DD RA_DQ36 VSS VSS DD RA_DQ37
RP68 4 1 127 128
DDRB_SMA2 DDRB_SMA3 D DRA_DM7 DD RA_DQ33 DQ32 DQ36 DD RA_DQ32
1 4 3 2 3 2 129 DQ33 DQ37 130
DDRB_SMA0 2 3 4 1 DDRB_SMA1 131 132
56_0404_4P2R_5% DD RA_DQS4 VDD VDD D DRA_DM4
133 DQS4 DM4 134
3 56_0404_4P2R_5% 56_0404_4P2R_5% DD RA_DQ38 DD RA_DQ39 3
RP56 135 136
RP107 DD RA_DQ63 DQ34 DQ38
RP67 4 1 137 138
DDRB_SBS1 DDRB_SBS0 DD RA_DQ59 DD RA_DQ35 VSS VSS DD RA_DQ34
1 4 3 2 3 2 139 DQ35 DQ39 140
D DRB_SRAS# 2 3 4 1 DDRB_SW E# DD RA_DQ41 141 142 DD RA_DQ45
56_0404_4P2R_5% DQ40 DQ44
143 VDD VDD 144
56_0404_4P2R_5% 56_0404_4P2R_5% RP115 DD RA_DQ44 145 146 DD RA_DQ40
RP108 DD RA_DQS6 DD RA_DQS5 DQ41 DQ45 D DRA_DM5
RP66 3 2 147 148
D DRB_SCAS# D DRB_SCS#0 DD RA_DQ54 DQS5 DM5
1 4 3 2 4 1 149 VSS VSS 150
D DRB_SCS#1 2 3 4 1 DDRB_SMA13 DD RA_DQ46 151 152 DD RA_DQ42
56_0404_4P2R_5% DD RA_DQ47 DQ42 DQ46 DD RA_DQ43
153 DQ43 DQ47 154
56_0404_4P2R_5% 56_0404_4P2R_5% RP116 155 156
RP109 DD RA_DQ50 VDD VDD
RP65 3 2 157 158 DDRB_CLK2# 6
DD RA_DQ37 DD RA_DQ36 DD RA_DQ60 VDD CK1#
1 4 3 2 4 1 159 VSS CK1 160 DDRB_CLK2 6
DD RA_DQ32 2 3 4 1 DD RA_DQ33 161 162
56_0404_4P2R_5% DD RA_DQ52 VSS VSS DD RA_DQ49
163 DQ48 DQ52 164
56_0404_4P2R_5% 56_0404_4P2R_5% RP117 DD RA_DQ53 165 166 DD RA_DQ48
RP110 DD RA_DQ56 DQ49 DQ53
RP64 3 2 167 168
D DRA_DM4 DD RA_DQS4 DD RA_DQS7 DD RA_DQS6 VDD VDD D DRA_DM6
1 4 3 2 4 1 169 DQS6 DM6 170
DD RA_DQ39 2 3 4 1 DD RA_DQ38 DD RA_DQ54 171 172 DD RA_DQ55
56_0404_4P2R_5% DQ50 DQ54
173 VSS VSS 174
56_0404_4P2R_5% 56_0404_4P2R_5% RP118 DD RA_DQ50 175 176 DD RA_DQ51
RP111 DD RA_DQ57 DD RA_DQ60 DQ51 DQ55 DD RA_DQ61
RP63 3 2 177 178
DD RA_DQ34 DD RA_DQ35 DD RA_DQ62 DQ56 DQ60
1 4 3 2 4 1 179 VDD VDD 180
DD RA_DQ45 2 3 4 1 DD RA_DQ41 DD RA_DQ56 181 182 DD RA_DQ58
56_0404_4P2R_5% DD RA_DQS7 DQ57 DQ61 D DRA_DM7
183 DQS7 DM7 184
56_0404_4P2R_5% 56_0404_4P2R_5% 185 186
RP112 DD RA_DQ57 VSS VSS DD RA_DQ63
RP62 187 188
DD RA_DQ40 DD RA_DQ44 DD RA_DQ62 DQ58 DQ62 DD RA_DQ59
1 4 3 2 189 DQ59 DQ63 190
4
D DRA_DM5 2 3 4 1 DD RA_DQS5 191 192 4
D_CK_SDATA VDD VDD
11,14 D_CK_SDATA 193 SDA SA0 194 +3VS
56_0404_4P2R_5% 56_0404_4P2R_5% D_CK_SCLK 195 196
11,14 D_CK_SCLK SCL SA1
RP61 RP113 197 198
DD RA_DQ42 DD RA_DQ46 +3VS VDD_SPD SA2
1 4 3 2 199 VDD_ID DU 200
DD RA_DQ43 2 3 4 1 DD RA_DQ47

56_0404_4P2R_5% 56_0404_4P2R_5% AMP_1565918-1 Compal Electronics, Inc.

RP60 RP114 Title
DD RA_DQ49 1 4 3 2 DD RA_DQ52 SCHEMATIC, M/B LA-2492
DD RA_DQ48 2 3 4 1 DD RA_DQ53
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
56_0404_4P2R_5% 56_0404_4P2R_5% 401317 B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: ¬P 期一, 一月 03, 2005 Sheet 12 of 51
A B C D E
 A B C D E

Layout note :
Distrib ute as close as possible
to DDR-SODIMM.

+DDRVCC

1 1
1 1 1 1 1 1 1 1 1
C117 C103 C122 C102 C99 C118 C136 C119 C138
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2 2 2 2 2 2

+DDRVCC +DDRVCC

1 1 1 1 1 1
C137 C135 C124 C123 + +
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z C85 C139
2 2 2 2 150U_D2_6.3VM 150U_D2_6.3VM
2 2

Layout note :
2 Place o ne cap close to every 2 pull up resistors termination to 2

+1.25V

+DDRVTT

1 1 1 1 1 1 1 1
C133 C532 C533 C128 C550 C130 C525 C526
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2 2 2 2 2

+DDRVTT

1 1 1 1 1 1 1 1
C527 C528 C524 C131 C531 C549 C548 C132
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2 2 2 2 2

3 3

+DDRVTT

1 1 1 1 1 1 1 1
C547 C546 C545 C544 C543 C542 C541 C540
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2 2 2 2 2

+DDRVTT

+DDRVTT
1 1 1 1

1 1 1 1 1 1 1 1 C539 C538 C537 C536

0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
C127 C535 C534 C134 C126 C125 C529 C113 2 2 2 2
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2 2 2 2 2

+DDRVTT

4 4
1 1 1 1 1 1 1 1
C112 C129 C111 C530 C96 C95 C94 C93
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2 2 2 2 2

Compal Electronics, Inc.

Title
SCHEMATIC, M/B LA-2492
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
401317 B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: ¬P 期一, 一月 03, 2005 Sheet 13 of 51
A B C D E
 A B C D E F G H

L10
KC FBM-L11-201209-221LMAT_0805 40mil
+CLK_VDD1
Clock Generator
+CLK_VDD48 + CLK_VDDREF +3VS 1 2
FSC FSB FSA CPU SRC PCI 1 1 1 Change to 0 ohm 1 1 1 1 1
C555 C157
CLKSEL0 CLKSEL1 CLKSEL2 C156 C144 C149 C145 C147 C152
MHz MHz MHz 0.047U_0402_16V7K 2.2U_0603_6.3V6K 0.047U_0402_16V7K 0.047U_0402_16V7K 0.047U_0402_16V7K 0.047U_0402_16V7K
2 2.2U_0603_6.3V6K 2 0.047U_0402_16V7K 2 2 2 2 2 2
1 0 1 100 100 33.3
*
0 0 1 133 100 33.3
1 1

0 1 1 166 100 33.3 +CLK_VCCA 1 2 +CLK_VDD1

+CLK_VDD1 R449
U8
40mil 2.2_0402_5% L11 +CLK_VDD2
0 1 0 200 100 33.3 1 1
KC FBM-L11-201209-221LMAT_0805
+CLK_VDD2 40mil
21 VDDPCIEX_0 +3VS 1 2
28 37 C553 C150 Change to 0 ohm
VDDPCIEX_1 VDDA 2 2.2U_0603_6.3V6K 2 0.047U_0402_16V7K
+3VS Table : ICS 954206B 34 VDDPCIEX_2 1 1 1
GNDA 38
1 VDDPCI_0
7 C165 C159 C163
CLKSEL2 VDDPCI_1 STP_PCI# 2 2.2U_0603_6.3V6K 2 0.047U_0402_16V7K 2 0.047U_0402_16V7K
1 2 PCI/SRC_STOP# 55 PM_STP_PCI# 19
R139 10K_0402_5% +CLK_VDD1
54 STP_CPU#
CPU_STOP# PM_STP_CPU# 19,49
1 2 CL K_PCI0
R145 10K_0402_5% Y1 42 VDDCPU
1 2 + CLK_VDDREF 48 VDDREF
1 2 CL K_PCI2 14.318MHZ_20P_1BX14318CC1A R135 1_0402_5% 15mil
R153 10K_0402_5% 1 2 41 C LK_CPU1 R124 1 2 33_0402_5% CLK_MCH_BCLK
CPUCLKT1 CLK_MCH_BCLK 6
C162 1 2 +CLK_VDD48 11 VDD48
33P_0402_50V8J 1 R455 2.2_0402_5% 15mil CPUCLKC1 40 CLK_CPU1# R120 1 2 33_0402_5% CLK_MCH_BCLK#
CLK_MCH_BCLK# 6
1 2 CL K_PCI1 CLK_MCH_BCLK 1 2
R141 10K_0402_5% C161 XTALIN 50 R123 49.9_0402_1%
33P_0402_50V8J X1 CLK_MCH_BCLK# 1 2
2

1 2 XTALOUT 49 44 C LK_CPU0 R134 1 2 33_0402_5% CLK_CPU_BCLK R119 49.9_0402_1%

X2 CPUCLKT0 CLK_CPU_BCLK 4
CLK_ICH_48M R143 1 2 12_0402_5% CLK_CPU_BCLK 1 2
19 CLK_ICH_48M
43 CLK_CPU0# R128 1 2 33_0402_5% CLK_CPU_BCLK# R133 49.9_0402_1%
CPUCLKC0 CLK_CPU_BCLK# 4
2 CLK_SD_48M R147 1 2 12_0402_5% CLKSEL2 12 CLK_CPU_BCLK# 1 2 2
24 CLK_SD_48M FS_A/USB_48MHz
CLK_14M_CODEC 2 1 CLKSEL0 53 R127 49.9_0402_1%
30 CLK_14M_CODEC REF1/FSLC/TEST_SEL
R151 12_0402_5% CLK_CPU_ITP 1 2
R112 49.9_0402_1%
CLKSEL1 16 36 C LK_CPU2 R113 1 2 33_0402_5% CLK_CPU_ITP CLK_CPU_ITP# 1 2
FSLB/TEST_MODE CPUCLKT2_ITP/PCIEXT6 R108 49.9_0402_1%
35 CLK_CPU2# R109 1 2 33_0402_5% CLK_CPU_ITP# C LK_PCIE_LAN 1 2
CPUCLKC2_ITP/PCIEXC6 R104 49.9_0402_1%
5 CLK_PCIE_LAN# 1 2
PCICLK5 R98 49.9_0402_1%
CLK_PC I_MINI 1 2 CL K_PCI4 4 33 CLK_PCIE_SATA 1 2
29 CLK_PCI_MINI PCICLK4 PEREQ1#/PCIEXT5
R150 33_0402_5% R101 49.9_0402_1%
CLK _PCI_SIO 1 2 CL K_PCI3 3 32 CLK_PCIE_SATA# 1 2
33 CLK_PCI_SIO PCICLK3 PEREQ2#/PCIEXC5
R149 33_0402_5% R97 49.9_0402_1%
CLK_PCI_PCM 1 2 CL K_PCI2 56 CLK_MCH_3GPLL 1 2
24 CLK_PCI_PCM PCICLK2/REQ_SEL
R154 33_0402_5% 31 C LK_SRC5 R105 1 2 33_0402_5% C LK_PCIE_LAN R107 49.9_0402_1%
PCIEXT4 CLK_PCIE_LAN 27
C LK_PCI_LPC 1 2 CL K_PCI1 9 CLK_MCH_3GPLL# 1 2
34 CLK_PCI_LPC SELPCIEX_LCDCLK#/PCICLK_F1
R142 33_0402_5% 30 CLK_SRC5# R99 1 2 33_0402_5% CLK_PCIE_LAN# R103 49.9_0402_1%
PCIEXC4 CLK_PCIE_LAN# 27
CLK_PCIE_VGA 1 2
R115 49.9_0402_1%
CLK_PCI_ICH 1 2 CL K_PCI0 8 26 C LK_SRC4 R100 1 2 33_0402_5% CLK_PCIE_SATA CLK_PCIE_VGA# 1 2
17 CLK_PCI_ICH ITP_EN/PCICLK_F0 SATACLKT CLK_PCIE_SATA 18
R146 33_0402_5% R111 49.9_0402_1%
D_CK_SCLK 46 27 CLK_SRC4# R96 1 2 33_0402_5% CLK_PCIE_SATA# CLK_PC IE_ICH 1 2
11,12 D_CK_SCLK SCLK SATACLKC CLK_PCIE_SATA# 18
R122 49.9_0402_1%
CLK_P CIE_ICH# 1 2
D_CK_SDATA 47 24 C LK_SRC3 R106 1 2 33_0402_5% CLK_MCH_3GPLL R118 49.9_0402_1%
11,12 D_CK_SDATA SDATA PCIEXT3 CLK_MCH_3GPLL 8
CL K_DREF_SSC 1 2
25 CLK_SRC3# R102 1 2 33_0402_5% CLK_MCH_3GPLL# R130 49.9_0402_1%
PCIEXC3 CLK_MCH_3GPLL# 8
1 2 CLKIR EF 39 IREF
C LK_DREF_SSC# 1 2
3 R452 475_0402_1% 15mil R126 49.9_0402_1% 3

22 C LK_SRC2 R114 1 2 33_0402_5% CLK_PCIE_VGA CLK_DREF_96M 1 2

PCIEXT2 CLK_PCIE_VGA 16
R137 49.9_0402_1%
23 CLK_SRC2# R110 1 2 33_0402_5% CLK_PCIE_VGA# CLK_DREF_96M# 1 2
+3VS PCIEXC2 CLK_PCIE_VGA# 16
R132 49.9_0402_1%
R462
4.7K_0402_5% 19 C LK_SRC1 R121 1 2 33_0402_5% CLK_PC IE_ICH
PCIEXT1 CLK_PCIE_ICH 19
2
G

1 2 +3VS
20 CLK_SRC1# R117 1 2 33_0402_5% CLK_P CIE_ICH#
PCIEXC1 CLK_PCIE_ICH# 19
1 3 D_CK_SCLK 13
19 CK_SCLK GND_0
D

Q16 29 17 C LK_SRC0 R129 1 2 33_0402_5% CL K_DREF_SSC

GND_1 LCDCLK_SS/PCIEX0T CLK_DREF_SSC 6
2N7002_SOT23
2 18 CLK_SRC0# R125 1 2 33_0402_5% C LK_DREF_SSC#
GND_2 LCDCLK_SS/PCIEX0C CLK_DREF_SSC# 6
45 GND_3
+3VS 14 CLK_DOT R136 1 2 33_0402_5% CLK_DREF_96M
DOTT_96MHz CLK_DREF_96M 6
R461 51 15 CLK_DOT# R131 1 2 33_0402_5% CLK_DREF_96M#
GND_4 DOTC_96MHz CLK_DREF_96M# 6
4.7K_0402_5%
2
G

1 2 +3VS 6 GND_5
1 3 D_CK_SDATA +3VS 1 2
19 CK_SDATA VGATE 6,19,49
R138 10K_0402_5%
D

2
Q17

G
2N7002_SOT23
10 VTT_POWERGD# 1 3
VTT_PWRGD#/PD

S
52 C LK_REF 1 2 CLK_14M_SIO Q14
+1.05VS +1.05VS REF0 CLK_14M_SIO 33
4
R144 12_0402_5% 2N7002_SOT23 4

ICS954226AGT_TSSOP56 1 2 CLK_ICH_14M
CLK_ICH_14M 19
2

R456 R454 R148 12_0402_5%

@ 1K_0402_5% @ 1K_0402_5%

R460 R457 R453 R450

4.7K_0402_5% 0_0402_5% 4.7K_0402_5% 0_0402_5% Compal Electronics, Inc.
1

CLKSEL0 1 2 1 2 CLKSEL1 1 2 1 2 Title

MCH_CLKSEL0 6 MCH_CLKSEL1 6
SCHEMATIC, M/B LA-2492
1 2 2 1 CPU_BSEL0 5 1 2 2 1 CPU_BSEL1 5 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
R458 R459 R451 R448 Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
@ 0_0402_5% 0_0402_5% @ 0_0402_5% 0_0402_5% 401317 B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: ¬P 期一, 一月 03, 2005 Sheet 14 of 51
A B C D E F G H
 A B C D E

CRT Connector D_ CRT_R

D_CRT_G
R517 1
R518 1
2 470_0402_5%
2 470_0402_5%
D23 D22
@ DAN217_SC59 @ DAN217_SC59
+5VS +R_CRT_VCC
W=40mils
+CRT_VCC

D_CRT_B R519 1 2 470_0402_5% D1 W=40mils

1
2 1 F1
+5VS
RB411D_SOT23 POLYSW ITCH_1A
1
1 2 0.1U_0402_16V4Z D21
C18 @ DAN217_SC59 C4

3
U4 0.1U_0402_16V4Z
2
VCC 16 +3VS
DOCKIN# 1
34,39 DOCKIN# SEL
1 15 2 D_ CRT_R 1
OE# 1B1 D_CRT_G D_CRT_R 39
2B1 5 D_CRT_G 39
11 D_CRT_B
C RT_R_F 3B1 D_CRT_B 39 JP1
4 1A 4B1 14
R34 1 2 PM@ 0_0402_5% CRT_G_F 7 C RT_R 1 2 CRT_R_L 6
16 VGA_CRT_R 2A
1 2 CRT_B_F 9 L3 11
8 GMCH_CRT_R 3A
R33 GM@ 0_0402_5% 12 3 FCM2012C-800_0805 1
R32 4A 1B2
16 VGA_CRT_G 1 2 PM@ 0_0402_5%
2B2 6 CRT_G 1 2 CRT_G_L 7
1 2 10 L4 12
8 GMCH_CRT_G 3B2
R21 GM@ 0_0402_5% 13 FCM2012C-800_0805 2
R19 4B2
16 VGA_CRT_B 1 2 PM@ 0_0402_5% 8 GND
CRT_B 1 2 CRT_B_L 8 16
1 2 L5 13
8 GMCH_CRT_B
R18 GM@ 0_0402_5% W /D@ FCM2012C-800_0805 3 17

1
FSAV330MTC_TSSOP16 1 1 1 1 1 DDC_MD2 9
R1 R2 R3 C9 C8 C7 1 14
C1 C2 C3 4
@ 8P_0402_50V8K @ 8P_0402_50V8K 1 10
C RT_R_F 1 2 C RT_R 150_0402_5% 150_0402_5% 150_0402_5% 2 8P_0402_50V8K 2 8P_0402_50V8K 2 2 2 C408 15

2
R570 W O/D@ 0_0402_5% 8P_0402_50V8K 2
5
CRT_G_F 1 2 CRT_G @ 8P_0402_50V8K
R571 W O/D@ 0_0402_5% 2 SUYIN_070453FR015S208CU
CRT_B_F +CRT_VCC
1 2 CRT_B 1 2 H S YNC_L 100P_0402_50V8J
R572 W O/D@ 0_0402_5% L1 FCM1608C-121T_0603
1 2 2 1 DSUB_12
C10 0.1U_0402_16V4Z R6 10K_0402_5% VSYNC_L
Pop with No-Docking 1
L2
2
FCM1608C-121T_0603 1

5
1
1 1

OE#
P
1 2 C RT_HSYNC 2 4 D_CRT_HSYNC C6
16 VGA_CRT_HSYNC A Y
2 R8 PM@ 0_0402_5% C5 C409 2 2

G
1 2 U1 10P_0402_50V8J 10P_0402_50V8J 68P_0402_50V8K DSUB_15
8 GMCH_CRT_HSYNC 2 2
R7 GM@ 39_0402_5% SN74AHCT1G125GW_SOT353-5

3
+CRT_VCC 1
C407
1 2 68P_0402_50V8K
C410 0.1U_0402_16V4Z 2
D_CRT_HSYNC 39

5
1
OE#
P
1 2 CRT_VS YNC 2 4 D_CRT_V SYNC
16 VGA_CRT_VSYNC A Y D_CRT_VSYNC 39
R377 PM@ 0_0402_5%

G
1 2 U35
8 GMCH_CRT_VSYNC
R378 GM@ 39_0402_5% SN74AHCT1G125GW_SOT353-5

3
+2.5VS
2

+CRT_VCC
G

R9 1 2 PM@ 0_0402_5% +3VS

D _DDC_DATA 1 3 VGA_DDC_DATA
39 D_DDC_DATA
D

Q42 R10 1 2 GM@ 0_0402_5% +2.5VS

GM@ BSS138_SOT23

1
1 2
R380 PM@ 0_0402_5% R4 R11 GM@ 0_0402_5%
4.7K_0402_5% R5 2 1
+2.5VS GMCH_CRT_DATA 8

2
3 3

G
4.7K_0402_5%
2

DSUB_12 VGA_DDC_DATA
G

1 3
VGA_DDC_DATA 16

S
D_DD C_CLK 1 3 V GA_DDC_CLK Q1
39 D_DDC_CLK

2
BSS138_SOT23

G
D

Q41
GM@ BSS138_SOT23 DSUB_15 1 3 V GA_DDC_CLK
VGA_DDC_CLK 16

S
1 2 Q2
R379 PM@ 0_0402_5% BSS138_SOT23
2 1 GMCH_CRT_CLK 8
R12
GM@ 0_0402_5%
1 2 C485

2
1 2 @ 22P_0402_50V8J
16 VGA_TV_LUMA
R422 PM@ 0_0402_5% L33
1 2 L27 1 2 FBM-11-160808-121T_0603
8 GMCH_TV_LUMA
R424 GM@ 0_0402_5% FBM-11-160808-121T_0603
1

1 2 L28 1 2 JP10
16 VGA_TV_CRMA
R434 PM@ 0_0402_5% FBM-11-160808-121T_0603 1 1. Y ground
LUMA_1 1
8 GMCH_TV_CRMA 1 2 2 2 5 5 2. C ground
R433 GM@ 0_0402_5% 1 2 C506 3 6 3. Y (luminance+sync)
@ 22P_0402_50V8J CRMA_1 3 6
4 4
4. C (crominance)
1

R432 R428 C518 C495

1

SUYIN_030244FS004TX01ZA
2

4 4
150_0402_5% 150_0402_5% 270P_0402_50V7K 270P_0402_50V7K C44 C54
TV-OUT Conn.
2

330P_0402_50V7K 330P_0402_50V7K

Compal Electronics, Inc.

Title
SCHEMATIC, M/B LA-2492
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401317
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 15 51
D ate: ¬P 期一, 一月 03, 2005 Sheet of
A B C D E
 5 4 3 2 1

PCEI_GTX_C_MRX_N[0..15]
8 PCEI_GTX_C_MRX_N[0..15]
PCEI_GTX_C_MRX_P[0..15]
LCD POWER CIRCUITGM CH_ENVDD 8 PCEI_GTX_C_MRX_P[0..15]
PCIE_MTX_C_GRX_N[0..15]
8 GMCH_ENVDD 8 PCIE_MTX_C_GRX_N[0..15]
PCIE_MTX_C_GRX_P[0..15]
8 PCIE_MTX_C_GRX_P[0..15]
+3VALW
U44

5
1
GM@ SN74AHCT1G125GW_SOT353-5

OE#
P
+LCDVDD
2 4
D
2
A Y
VGA BOARD Conn. D

G
C663
1

2
3
GM@ 0.01U_0402_25V7K JP11
R53 1 +3VS
B+ 1 2 B+
GM@ 300_0402_5%
R62 3 4
1 2

1
GM@ 100_0402_5% 5 6
7 8

3
D DAC_B RIG V GA_DDC_CLK
9 10 VGA_DDC_CLK 15
Q8 2 2 Q9 DISP OFF# VGA_DDC_DATA VGA_DDC_DATA 15
GM@ 2N7002_SOT23 G GM@ SI2301DS_SOT23 INVT_PWM 11 12
13 14 VGA_TV_LUMA
S 1 VGA_TV_LUMA 15
3

15 16
2

+LCDVDD VGA_CRT_R
15 VGA_CRT_R 17 18 VGA_TV_CRMA VGA_TV_CRMA 15

1
R55 C27 VGA_CRT_G 19 20
2 15 VGA_CRT_G 21 22 VGA _CRT_VSYNC VGA_CRT_VSYNC 15
GM@ 100K_0402_5% GM@ 0.047U_0402_16V7K VGA_CRT_B 23 24 VGA_C RT_HSYNC
1 1 15 VGA_CRT_B VGA_CRT_HSYNC 15
1

C28 C29 25 26 SUSP#

27 28 SUSP# 26,32,34,36,37,41,47,48
+3VALW GMCH_ENBKL GMCH_ENBKL 8,34
GM@ 4.7U_0805_10V4Z GM@ 0.1U_0402_16V4Z 29 30
2 2 31 32
+2.5VS 33 34 +1.5VS
35 36 DVI_DET 39
39 DVI_TXC+ 37 38 DVI_SCLK 39
39 DVI_TXC- 39 40 DVI_SDATA 39
41 42
39 DVI_TXD0+ 43 44 +3VS
39 DVI_TXD0- 45 46
C 47 48 C
+3VS 39 DVI_TXD1+ 49 50 +5VS
39 DVI_TXD1- 51 52 +5VALW
53 54
39 DVI_TXD2+ 55 56
1 39 DVI_TXD2- 57 58 L CD_ID
C19 R510 1 59 60
19 PLTRST_VGA# 2 PM@ 0_0402_5% 61 62 CLK_PCIE_VGA 14
@ 0.1U_0402_16V4Z 6,17,19,21,22,24,27,33,34 PLT_RST# R511 1 2 @ 0_0402_5% CLK_PCIE_VGA# 14
2 63 64
PCIE_MTX_C_GRX_P0 65 66 PCEI_GTX_C_MRX_P0
PCIE_MTX_C_GRX_N0 67 68 PCEI_GTX_C_MRX_N0
69 70
PCIE_MTX_C_GRX_P1 71 72 PCEI_GTX_C_MRX_P1
PCIE_MTX_C_GRX_N1 73 74 PCEI_GTX_C_MRX_N1
+3VS 75 76
PCIE_MTX_C_GRX_P2 77 78 PCEI_GTX_C_MRX_P2
PCIE_MTX_C_GRX_N2 79 80 PCEI_GTX_C_MRX_N2
81 82
1

R477 PCIE_MTX_C_GRX_P3 83 84 PCEI_GTX_C_MRX_P3

PCIE_MTX_C_GRX_N3 85 86 PCEI_GTX_C_MRX_N3
4.7K_0402_5% 87 88
D32 PCIE_MTX_C_GRX_P4 89 90 PCEI_GTX_C_MRX_P4
2

BKOFF# 91 92
34 BKOFF# 1 2 RB751V_SOD323 DISP OFF# PCIE_MTX_C_GRX_N4
93 94
PCEI_GTX_C_MRX_N4

PCIE_MTX_C_GRX_P5 95 96 PCEI_GTX_C_MRX_P5
PCIE_MTX_C_GRX_N5 97 98 PCEI_GTX_C_MRX_N5
99 100
PCIE_MTX_C_GRX_P6 101 102 PCEI_GTX_C_MRX_P6
PCIE_MTX_C_GRX_N6 103 104 PCEI_GTX_C_MRX_N6
B 105 106 B
PCIE_MTX_C_GRX_P7 107 108 PCEI_GTX_C_MRX_P7
PCIE_MTX_C_GRX_N7 109 110 PCEI_GTX_C_MRX_N7
111 112
PCIE_MTX_C_GRX_P8 113 114 PCEI_GTX_C_MRX_P8
PCIE_MTX_C_GRX_N8 115 116 PCEI_GTX_C_MRX_N8
LCD/PANEL BD. Conn. PCIE_MTX_C_GRX_P9
117
119
118
120 PCEI_GTX_C_MRX_P9
PCIE_MTX_C_GRX_N9 121 122 PCEI_GTX_C_MRX_N9
JP6 123 124
DAC_B RIG PCIE_MTX_C_GRX_P10 125 126 PCEI_GTX_C_MRX_P10
B+ 1 1 2 2 DAC_BRIG 34 127 128
3 4 INVT_PWM PCIE_MTX_C_GRX_N10 PCEI_GTX_C_MRX_N10
3 4 INVT_PWM 34 129 130
5 6 DISP OFF#
5 6 PCIE_MTX_C_GRX_P11 131 132 PCEI_GTX_C_MRX_P11
+3VS 7 7 8 8 133 134
8 GMCH_LCD_CLK GMCH_LCD_CLK 9 10 +LCDVDD PCIE_MTX_C_GRX_N11 PCEI_GTX_C_MRX_N11
GMCH_LCD_DATA 9 10 135 136
8 GMCH_LCD_DATA 11 11 12 12 137 138
13 14 PCIE_MTX_C_GRX_P12 PCEI_GTX_C_MRX_P12
GMCH_TZOUT0- 13 14 GMCH_TXOUT0- PCIE_MTX_C_GRX_N12 139 140 PCEI_GTX_C_MRX_N12
8 GMCH_TZOUT0- 15 15 16 16 GMCH_TXOUT0- 8 141 142
GMCH_TZOUT0+ 17 18 GMCH_TXOUT0+
8 GMCH_TZOUT0+ 17 18 GMCH_TXOUT0+ 8 143 144
19 20 PCIE_MTX_C_GRX_P13 PCEI_GTX_C_MRX_P13
GMCH_TZOUT1+ 19 20 GMCH_TXOUT1- PCIE_MTX_C_GRX_N13 145 146 PCEI_GTX_C_MRX_N13
8 GMCH_TZOUT1+ 21 21 22 22 GMCH_TXOUT1- 8 147 148
GMCH_TZOUT1- 23 24 GMCH_TXOUT1+
8 GMCH_TZOUT1- 23 24 GMCH_TXOUT1+ 8 149 150
GMCH_TZOUT2+ 25 26 GMCH_TXOUT2+ PCIE_MTX_C_GRX_P14 PCEI_GTX_C_MRX_P14
8 GMCH_TZOUT2+ 25 26 GMCH_TXOUT2+ 8 151 152
GMCH_TZOUT2- 27 28 GMCH_TXOUT2- PCIE_MTX_C_GRX_N14 PCEI_GTX_C_MRX_N14
8 GMCH_TZOUT2- 27 28 GMCH_TXOUT2- 8 153 154
29 29 30 30 155 156
GMCH_TZCLK- 31 32 GMCH_TXCLK- PCIE_MTX_C_GRX_P15 PCEI_GTX_C_MRX_P15
8 GMCH_TZCLK- 31 32 GMCH_TXCLK- 8 157 158
GMCH_TZCLK+ 33 34 GMCH_TXCLK+ PCIE_MTX_C_GRX_N15 PCEI_GTX_C_MRX_N15
8 GMCH_TZCLK+ 33 34 GMCH_TXCLK+ 8 159 160
35 35 36 36
A 37 38 PM@ ACES_88081-1600 A
L CD_ID 37 38
17,33 L CD_ID 39 39 40 40

GM@ ACES_87216-4012

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-2492
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
401317 B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: ¬P 期一, 一月 03, 2005 Sheet 16 of 51
5 4 3 2 1
 5 4 3 2 1

RP89
1 8 PCI_SERR#
+3VS
2 7 PCI_TRD Y#
3 6 P CI_FRAME#
D 4 5 PCI_STOP# U17B D
24,29 PCI_AD[0..31]
PCI_AD0 E2 L5 P CI_REQ#0 Internal Pull-up.
8.2K_0804_8P4R_5% PCI_AD1 AD[0] REQ[0]# PCI_GNT#0
E5 AD[1] PCI GNT[0]# C1
PCI_AD2 C2 B5 P CI_REQ#1
PCI_REQ#1 29
Sample high destination is LPC.
PCI_AD3 AD[2] REQ[1]# PCI_GNT#1
F5 AD[3] GNT[1]# B6 PCI_GNT#1 29
PCI_AD4 F3 M5 P CI_REQ#2 PCI_GNT#5
AD[4] REQ[2]# PCI_REQ#2 24
RP88 PCI_AD5 E9 F1 PCI_GNT#2
AD[5] GNT[2]# PCI_GNT#2 24
1 8 PCI_PLOCK# PCI_AD6 F2 B8 P CI_REQ#3
+3VS AD[6] REQ[3]#

1
2 7 P C I_ I RDY# PCI_AD7 D6 C8 PCI_GNT#3
PCI_PERR# PCI_AD8 AD[7] GNT[3]# P CI_REQ#4 R231
3 6 E6 AD[8] REQ[4]#/GPI[40] F7
4 5 PCI_DEVSEL# PCI_AD9 D3 E7 PCI_GNT#4 @ 0_0402_5%
PC I_AD10 AD[9] GNT[4]#/GPO[48] P CI_REQ#5
A2 AD[10] REQ[5]#/GPI[1] E8 2 1 LCD_ID 16,33
8.2K_0804_8P4R_5% PC I_AD11 D2 F6 PCI_GNT#5 R575 @ 0_0402_5%

2
PC I_AD12 AD[11] GNT[5]#/GPO[17] P CI_REQ#6
D5 AD[12] REQ[6]#/GPI[0] B7 2 1 BT_DET# 33,35
PC I_AD13 H3 D8 PCI_GNT#6 R576 @ 0_0402_5%
PC I_AD14 AD[13] GNT[6]#/GPO[16]
B4 AD[14]
RP91 PC I_AD15 J5 J6 P CI_CBE#0 PCI_C/BE#0 24,29
PCI_PIRQD# PC I_AD16 AD[15] C/BE[0]# P CI_CBE#1
+3VS 1 8 K2 AD[16] C/BE[1]# H6 PCI_C/BE#1 24,29
2 7 PCI_ PIRQB# PC I_AD17 K5 G4 P CI_CBE#2
AD[17] C/BE[2]# PCI_C/BE#2 24,29
3 6 PCI_PIRQC# PC I_AD18 D4 G2 P CI_CBE#3
AD[18] C/BE[3]# PCI_C/BE#3 24,29
4 5 PCI_ PIRQA# PC I_AD19 L6
PC I_AD20 AD[19] P C I_ I RDY#
G3 AD[20] IRDY# A3 P C I_ IRDY# 24,29
8.2K_0804_8P4R_5% PC I_AD21 H4 E1 PCI_PAR
PC I_AD22 AD[21] PAR PCI_RST# PCI_PAR 24,29
H2 AD[22] PCIRST# R2 PCI_RST# 22,24,29,33,34
PC I_AD23 H5 C3 PCI_DEVSEL#
RP92 PC I_AD24 AD[23] DEVSEL# PCI_PERR# PCI_DEVSEL# 24,29
B3 AD[24] PERR# E3 PCI_PERR# 24,29
1 8 PCI_ PIRQE# PC I_AD25 M6 C5 PCI_PLOCK#
+3VS AD[25] PLOCK#
2 7 PCI_PIRQF# PC I_AD26 B2 G5 PCI_SERR#
AD[26] SERR# PCI_SERR# 24,29
3 6 PCI_ PIRQG# PC I_AD27 K6 J1 PCI_STOP#
AD[27] STOP# PCI_STOP# 24,29
C 4 5 P CI_REQ#6 PC I_AD28 K3 J2 PCI_TRD Y# C
AD[28] TRDY# PCI_TRDY# 24,29
PC I_AD29 A5
8.2K_0804_8P4R_5% PC I_AD30 AD[29]
L1 AD[30]
PC I_AD31 K4 AD[31] PLT_RST#
PLTRST# R5 PLT_RST# 6,16,19,21,22,24,27,33,34
RP87 G6 CLK_ICH _PCI CLK_PCI_ICH
PCICLK CLK_PCI_ICH 14
1 8 P CI_REQ#5 P CI_FRAME# J3 P6
+3VS 24,29 PCI_FRAME# FRAME# PME#
2 7 P CI_REQ#3

2
3 6 P CI_REQ#1 Interrupt I/F
4 5 P CI_REQ#4 PCI_ PIRQA# N2 D9
24 PCI_PIRQA# PIRQ[A]# PIRQ[E]#/GPI[2]
PCI_ PIRQB# L2 C7 R177
24 PCI_PIRQB# PIRQ[B]# PIRQ[F]#/GPI[3]
8.2K_0804_8P4R_5% PCI_PIRQC# M1 C6 PCI_ PIRQG# @ 10_0402_5%
24 PCI_PIRQC# PIRQ[C]# PIRQ[G]#GPI[4] PCI_PIRQG# 29
PCI_PIRQD# L3 M3 PCI_PIRQH#
24 PCI_PIRQD# PCI_PIRQH# 29

1
PIRQ[D]# PIRQ[H]#/GPI[5]

RP90 AC5
RESERVED 1
C192
SATA[1]RXN/RSVD[1] @ 10P_0402_50V8J
+3VS 1 8 AD5 SATA[1]RXP/RSVD[2]
2 7 P CI_REQ#0 AF4
P CI_REQ#2 SATA[1]TXN/RSVD[3] 2
3 6 AG4 SATA[1]TXP/RSVD[4]
4 5 PCI_PIRQH# AC9 SATA[3]RXN/RSVD[5]
AD9 SATA[3]RXP/RSVD[6]
8.2K_0804_8P4R_5% AF8 SATA[3]TXN/RSVD[7]
AG8 SATA[3]TXP/RSVD[8]
U3 TP[3]/RSVD[9]
ICH6_BGA609

B B

A A

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-2492
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401317
D ate: ¬P 期一, 一月 03, 2005 Sheet 17 of 51
5 4 3 2 1
 5 4 3 2 1

C269
12P_0402_50V8J
2 1 ICH_RTCX1
+RTCVCC

10M_0402_5%
Y3

1
3 NC OUT 4
1

R246
R244 32.768KHZ_12.5P_1TJS125DJ2A073 2 1
NC IN U17A
1M_0402_1% C270 +1.05VS

2
D 12P_0402_50V8J Y1 P2 LPC_LAD0 D
LPC_AD0 33,34
2

RTCX1 LAD[0]/FWH[0]

RTC
2 1 ICH_RTCX2 Y2 N3 LPC_LAD1
RTCX2 LAD[1]/FWH[1] LPC_AD1 33,34
INTRUD ER# N5 LPC_LAD2
LAD[2]/FWH[2] LPC_AD2 33,34
1 2 IC H_RTCRST# AA2 N4 LPC_LAD3 H_FE RR# 1 2

LPC
+RTCVCC RTCRST# LAD[3]/FWH[3] LPC_AD3 33,34
R439 R186 56_0402_5%
20K_0402_5% INTRUD ER# AA3 N6 H_DPRSTP# 1 2
INTVRMEN INTRUDER# LDRQ[0]# LPC_DRQ#1 R176 56_0402_5%
AA5 INTVRMEN LDRQ[1]#/GPI[41] P4 LPC_DRQ#1 33
+3VS
2 1 P3 LPC_FRAME#
LFRAME#/FWH[4] LPC_FRAME# 33,34
close to RAM door J1 JOPEN D12 EE_CS
1

B12 R190 1 2 10K_0402_5% +3VS

R512 EE_SHCLK EC_GA20
D11 EE_DOUT A20GATE AF22 EC_GA20 34
C271 F13 AF23 H_A20M#
EE_DIN A20M# H_A20M# 4
10K_0402_5% 1U_0402_6.3V4Z

LAN
R520 1 2 @ 0_0402_5% H_CPUSLP#

CPU
1 2 F12 AE27 H_CPUSLP# 4,6
2

LAN_CLK CPUSLP#
B11 AE24 R180 1 2 0_0402_5% H_DPRSTP# H_DPRSTP# 4
PH DD_LED# LAN_RSTSYNC DPRSLP#/TP[4]
DPSLP#/TP[2] AD27 H_DPSLP# 4
E12 LANRXD[0]
E11 AF24 FER R# 1 2 H_FE RR# H_FERR# 4
LANRXD[1] FERR# R573 56_0402_5%
C13 LANRXD[2]
AG25 H_PW RGOOD H_PW RGOOD 4
CPUPWRGD/GPO[49] MAINPW ON 43,44,46
C12 LANTXD[0]
C11 AG26 H_IG NNE# H_IGNNE# 4 R181
LANTXD[1] IGNNE#

1
C224 R207 E13 AE22 @ 330_0402_5% C
@ 10P_0402_50V8J @ 10_0402_5% LANTXD[2] INIT3_3V# H_IN IT# Q22
INIT# AF27 H_INIT# 4 +1.05VS 1 2 2
1 2 2 1 AG24 H_IN TR R188 B @ 2SC2411K_SC59
INTR H_INTR 4
10K_0402_5% E

3
AC97_BITCLK C10 1 2 +3VS
30,35 ICH_AC_BITCLK ACZ_BIT_CLK

AC-97/AZALIA
C
30,35 IC H _AC_SYNC 2 1 AC97_S YNC_R B9 AD23 KB_RST# C
ACZ_SYNC RCIN# EC_KBRST# 34
R215 33_0402_5%
1 2 AC97_RST_R# A10 AF25 H_N MI H_NMI 4 +1.05VS 1 2 2 1 THRMTRIP#
30,35 ICH_AC_RST# ACZ_RST# NMI
R210 33_0402_5% AG27 H_SMI# H_SMI# 4 R182 75_0402_1% R187
AC_S DIN0 SMI# 56_0402_5%
30 ICH_AC_SDIN0 F11 ACZ_SDIN[0]
35 ICH_AC_SDIN1 F10 AE26 H_STPCLK# H_STPCLK# 4
ACZ_SDIN[1] STPCLK# H_THERMTRIP#
B10 ACZ_SDIN[2] H_THERMTRIP# 4,6
AE23 THRMTRIP#
AC97_SDOUT_R THRMTRIP#
30,35 ICH_AC_SDOUT 2 1 C9 ACZ_SDO
R206 33_0402_5% IDE_DA[0..2] 22
AC16 IDE _DA0
PH DD_LED# DA[0] IDE _DA1
34 PHDD_LED# AC19 SATALED# DA[1] AB17
AC17 IDE _DA2
DA[2]

21 SATA_DTX_C_IRX_N0 SATA_DTX_C_IRX_N0 AE3 AD16 IDE _DCS1# IDE_DCS1# 22

SATA_DTX_C_IRX_P0 SATA[0]RXN DCS1# IDE _DCS3#
21 SATA_DTX_C_IRX_P0 AD3 SATA[0]RXP DCS3# AE17 IDE_DCS3# 22
SATA_ITX_DRX_N0 AG2
SATA_ITX_DRX_P0 SATA[0]TXN
AF2 SATA[0]TXP IDE_DD[0..15] 22
AD14 IDE_D D0
DD[0]

SATA
AD7 AF15 IDE_D D1
SATA[2]RXN DD[1]

PIDE
AC7 AF14 IDE_D D2
SATA[2]RXP DD[2] IDE_D D3
AF6 SATA[2]TXN DD[3] AD12
AG6 AE14 IDE_D D4
SATA[2]TXP DD[4] IDE_D D5
DD[5] AC11
CLK_PCIE_SATA# AC2 AD11 IDE_D D6
14 CLK_PCIE_SATA# CLK_PCIE_SATA AC1 SATA_CLKN DD[6] IDE_D D7
14 CLK_PCIE_SATA SATA_CLKP DD[7] AB11
AE13 IDE_D D8
DD[8] IDE_D D9
AG11 SATARBIAS# DD[9] AF13
R209 1 2 24.9_0402_1% SATARBIAS AF11 AB12 IDE_ DD10
B SATARBIAS DD[10] IDE_ DD11 B
DD[11] AB13
AC13 IDE_ DD12
DD[12] IDE_ DD13
DD[13] AE15
R201 1 2 4.7K_0402_5% ID E _ D I ORDY AG15 IDE_ DD14
+3VS DD[14]
ID E _ D I ORDY AF16 AD13 IDE_ DD15
22 ID E _ D IORDY IORDY DD[15]
I DE_IRQ AB16
22 IDE_IRQ IDEIRQ
R203 1 2 8.2K_0402_5% I DE_IRQ IDE_D DACK# AB15
22 IDE_DDACK# DDACK#
IDE_ DIOW # AC14 AB14 IDE_DD REQ
22 IDE_DIOW # DIOW# DDREQ IDE_DDREQ 22
IDE_DIO R# AE16
22 IDE_DIOR# DIOR#

ICH6_BGA609

Place near ICH6 side.

SATA_ITX_DRX_N0 2 1 SATA_ITX_C_DRX_N0
C256 0.01U_0402_16V7K SATA_ITX_C_DRX_N0 21

SATA_ITX_DRX_P0 2 1 SATA_ITX_C_DRX_P0
C257 0.01U_0402_16V7K SATA_ITX_C_DRX_P0 21

A A

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-2492
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401317
D ate: ¬P 期一, 一月 03, 2005 Sheet 18 of 51
5 4 3 2 1
 5 4 3 2 1

+3VALW

1 2 ICH _SMLINK0
R259 10K_0402_5% U17C
1 2 ICH _SMLINK1 EC_SW I# T2 H25 PCIE_PTX_C_IRX_N1
34 EC_SW I# RI# PERn[1] PCIE_PTX_C_IRX_N1 27
R257 10K_0402_5% H24 PCIE_PTX_C_IRX_P1
PERp[1] PCIE_PTX_C_IRX_P1 27
1 2 CK_SCLK GPI26 AF17 G27 PCIE_ITX_PRX_N1 1 2 PCIE_ITX_C_PRX_N1 PCIE_ITX_C_PRX_N1 27
R464 2.2K_0402_5% GPI27 SATA[0]GP/GPI[26] PETn[1] PCIE_ITX_PRX_P1 C198 1
AE18 SATA[1]GP/GPI[29] PETp[1] G26 2 0.1U_0402_16V4Z PCIE_ITX_C_PRX_P1 PCIE_ITX_C_PRX_P1 27
1 2 CK_SDATA GPI28 AF18 C197 0.1U_0402_16V4Z
R465 2.2K_0402_5% GPI29 SATA[2]GP/GPI[30]
AG18 SATA[3]GP/GPI[31] PERn[2] K25
1 2 LINKALERT# K24
R260 10K_0402_5% CK_SCLK PERp[2]
D 14 CK_SCLK Y4 SMBCLK PETn[2] J27 D

PCI-EXPRESS
1 2 EC_LID_OUT# CK_SDATA W5 J26
14 CK_SDATA SMBDATA PETp[2]
R255 @ 10K_0402_5% LINKALERT# Y5
EC_SW I# ICH _SMLINK0 LINKALERT#
1 2 W4 SMLINK[0] PERn[3] M25

GPIO
R256 10K_0402_5% ICH _SMLINK1 U6 M24
PM_BATLOW# MCH_SYN C# SMLINK[1] PERp[3]
1 2 AG21 MCH_SYNC# PETn[3] L27
R249 8.2K_0402_5% SB_SPKR F8 L26
IC H_PCIE_W AKE# 30 SB_SPKR SPKR PETp[3]
1 2
R258 1K_0402_5% W3 P24
36 SUS_STAT# SUS_STAT#/LPCPD# PERn[4]
1 2 S YSRST# P23
R261 10K_0402_5% S YSRST# PERp[4] +3VALW
U2 SYS_RESET# PETn[4] N27
PETp[4] N26
PM_BMBUSY# AD19
+3VS 6 PM_BMBUSY# BM_BUSY#/GPI[6]
T25 DMI_MTX_IRX_N0 RP83
DMI[0]RXN DMI_MTX_IRX_N0 6
ICH_GP I7 AE19 T24 DMI_MTX_IRX_P0 USB_OC#5 4 5
GPI[7] DMI[0]RXP DMI_MTX_IRX_P0 6
1 2 ICH_GP I7 34 EC_SMI# EC_SMI# R1 R27 DMI_ITX_MRX_N0 USB_OC#4 3 6
GPI[8] DMI[0]TXN DMI_ITX_MRX_N0 6
R197 10K_0402_5% R26 DMI_ITX_MRX_P0 USB_OC#6 2 7
DMI[0]TXP DMI_ITX_MRX_P0 6

DIRECT MEDIA INTERFACE

1 2 PM_CLKRUN# A C IN W6 USB_OC#7 1 8
34,38,43 A C IN SMBALERT#/GPI[11]
R196 8.2K_0402_5% V25 DMI_MTX_IRX_N1
DMI[1]RXN DMI_MTX_IRX_N1 6
1 2 ICH_VGATE EC_LID_OUT# M2 V24 DMI_MTX_IRX_P1 10K_1206_8P4R_5%
34 EC_LID_OUT# GPI[12] DMI[1]RXP DMI_MTX_IRX_P1 6
R193 10K_0402_5% EC_ SCI# R6 U27 DMI_ITX_MRX_N1
34 EC_SCI# GPI[13] DMI[1]TXN DMI_ITX_MRX_N1 6
1 2 MCH_SYN C# U26 DMI_ITX_MRX_P1
DMI[1]TXP DMI_ITX_MRX_P1 6
R195 10K_0402_5% PM_STP_PCI# AC21
14 PM_STP_PCI# STP_PCI#/GPO[18]
1 2 SERIRQ Y25 DMI_MTX_IRX_N2 RP82
DMI[2]RXN DMI_MTX_IRX_N2 6
R198 10K_0402_5% AB21 Y24 DMI_MTX_IRX_P2 USB_OC#3 4 5
36 SB_INT_FLASH_SEL# GPO[19] DMI[2]RXP DMI_MTX_IRX_P2 6
W27 DMI_ITX_MRX_N2 USB_OC#0 3 6
DMI[2]TXN DMI_ITX_MRX_N2 6
PM_STP_CPU# AD22 W26 DMI_ITX_MRX_P2 USB_OC#1 2 7
14,49 PM_STP_CPU# STP_CPU#/GPO[20] DMI[2]TXP DMI_ITX_MRX_P2 6
USB_OC#2 1 8
AB24 DMI_MTX_IRX_N3
DMI[3]RXN DMI_MTX_IRX_N3 6
C 1 2 SYS_PW ROK AD20 AB23 DMI_MTX_IRX_P3 10K_1206_8P4R_5% C
GPO[21] DMI[3]RXP DMI_MTX_IRX_P3 6
R248 10K_0402_5% PLTRST_VGA# AD21 AA27 DMI_ITX_MRX_N3
16 PLTRST_VGA# GPO[23] DMI[3]TXN DMI_ITX_MRX_N3 6
1 2 EC_RSMRST# AA26 DMI_ITX_MRX_P3
DMI[3]TXP DMI_ITX_MRX_P3 6
R262 10K_0402_5% IDE_HRESET# V3
21 IDE_HRESET# GPIO[24]
AD25 CLK_P CIE_ICH#
DMI_CLKN CLK_PCIE_ICH# 14
RP85 IDE_MRESET# P5 AC25 CLK_PC IE_ICH
34 IDE_MRESET# GPIO[25] DMI_CLKP CLK_PCIE_ICH 14
4 5 GPI29 R3
GPI28 EC_FLASH# GPIO[27]
3 6 36 EC_FLASH# T3 GPIO[28]
2 7 GPI27 29,33 PM_CLKRUN# PM_CLKRUN# AF19 F24
GPI26 IDE_MPW R CLKRUN#/GPIO[32] DMI_ZCOMP
1 8 22 IDE_MPW R AF20 GPIO[33]
AC18 F23 DMI_IRCOMP R472 1 2 24.9_0402_1% +1.5VS
100_1206_8P4R_5% GPIO[34] DMI_IRCOMP

27 ICH_PCIE_W AKE# IC H_PCIE_W AKE# U5 C23 USB_OC#4

WAKE# OC[4]#/GPI[9] USB_OC#4 38
1 2 PM_DPRSLPVR D23 USB_OC#5
R597 100K_0402_5% SERIRQ OC[5]#/GPI[10] USB_OC#6
24,33,34 SERIRQ AB20 SERIRQ OC[6]#/GPI[14] C25
C24 USB_OC#7
OC[7]#/GPI[15] USB_OC#7 38
EC_THERM# AC20
34 EC_THERM# THRM# USB_OC#0
OC[0]# C27 USB_OC#0 38
6,14,49 VGATE 2 1 ICH_VGATE AF21 VRMPWRGD OC[1]# B27 USB_OC#1
R194 0_0402_5% B26 USB_OC#2
OC[2]# USB_OC#2 38
CLK_14M_ICH E10 C26 USB_OC#3
CLK14 OC[3]#

CLOCK
CLK_48M_ICH A27 C21 USB20_N0
CLK48 USBP[0]N USB20_N0 38
D21 USB20_P0
USBP[0]P USB20_P0 38
RTC_CLK V6 A20
34 RTC_CLK SUSCLK USBP[1]N
USBP[1]P B20
SLP_S3# T4 D19 USB20_N2
34 PM_SLP_S3# SLP_S3# USBP[2]N USB20_N2 38
SLP_S4# T5 C19 USB20_P2
SLP_S4# USBP[2]P USB20_P2 38

USB
SLP_S5# T6 A18
B SLP_S5# USBP[3]N B
USBP[3]P B18
SYS_PW ROK AA1 E17 USB20_N4
40 SYS_PW ROK PWROK USBP[4]N USB20_N4 38

POWER MGT
D17 USB20_P4
USBP[4]P USB20_P4 38
PM_DPRSLPVR AE20 B16 USB20_N5
49 PM_DPRSLPVR DPRSLPVR/TP[1] USBP[5]N USB20_N5 35
A16 USB20_P5
USBP[5]P USB20_P5 35
PM_BATLOW# V2 C15 USB20_N6
BATLOW#/TP[0] USBP[6]N USB20_N6 39
D15 USB20_P6
USBP[6]P USB20_P6 39
PBTN_OUT# U1 A14 USB20_N7
34 PBTN_OUT# PWRBTN# USBP[7]N USB20_N7 38
B14 USB20_P7
USBP[7]P USB20_P7 38
PLT_RST# V5
6,16,17,21,22,24,27,33,34 PLT_RST# LAN_RST# US BRBIAS
USBRBIAS# A22 1 2
EC_RSMRST# Y3 B22 R189 22.6_0402_1%
34 EC_RSMRST# RSMRST# USBRBIAS
ICH6_BGA609

+3VALW C275
0.1U_0402_16V4Z
1 2
5

1 SLP_S4#
CLK_48M_ICH CLK_14M_ICH 4
14 CLK_ICH_48M 14 CLK_ICH_14M 34 PM_SLP_S5#
2 SLP_S5#
1
1

U21
3

A
R218 TC7SH08FU_SSOP5 A
R470 @ 10_0402_5%
@ 10_0402_5%
2
2

1
1
C235
C559
2
@ 10P_0402_50V8J Compal Electronics, Inc.
@ 10P_0402_50V8J Title
2
SCHEMATIC, M/B LA-2492
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401317
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: ¬P 期一, 一月 03, 2005 Sheet 19 of 51
5 4 3 2 1
 5 4 3 2 1

+1.5VS
Near PIN F27(C155), +1.5VS C204
P27(C154), AB27(C157) U17E +RTCVCC 0.1U_0402_16V4Z U17D
1 2 E27 VSS[172] VSS[86] F4
+1.5VS AA22 VCC1_5[1] VCC1_5[98] F9 Y6 VSS[171] VSS[85] F22

220U_D2_4VM_R12

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
1 AA23 U17 0.1U_0402_16V4Z C562 Y27 F19
VCC1_5[2] VCC1_5[97] 0.1U_0402_16V4Z VSS[170] VSS[84]
2 2 2 AA24 VCC1_5[3] VCC1_5[96] U16 Y26 VSS[169] VSS[83] F17

C242
+ AA25 U14 1 2 Y23 E25
VCC1_5[4] VCC1_5[95] 2 2 VSS[168] VSS[82]

C193

C194

C561
AB25 U12 C278 W7 E19
VCC1_5[5] VCC1_5[94] C199 VSS[167] VSS[81]
AB26 VCC1_5[6] VCC1_5[93] U11 W25 VSS[166] VSS[80] E18
2 1 1 1 0.1U_0402_16V4Z
AB27 VCC1_5[7] VCC1_5[92] T17 W24 VSS[165] VSS[79] E15
D F25 T11 C2771 1
1 2 W23 E14 D
VCC1_5[8] VCC1_5[91] VSS[164] VSS[78]
F26 VCC1_5[9] VCC1_5[90] P17 W1 VSS[163] VSS[77] D7
F27 P11 0.1U_0402_16V4Z C564 V4 D22
VCC1_5[10] VCC1_5[89] 0.1U_0402_16V4Z VSS[162] VSS[76]
G22 M17 V27 D20

CORE
VCC1_5[11] VCC1_5[88] VSS[161] VSS[75]
G23 VCC1_5[12] VCC1_5[87] M11 1 2 V26 VSS[160] VSS[74] D18
G24 VCC1_5[13] VCC1_5[86] L17 V23 VSS[159] VSS[73] D14
G25 L16 C201 U25 D13
+5VCD +5VS +3VS VCC1_5[14] VCC1_5[85] 0.1U_0402_16V4Z VSS[158] VSS[72]
H21 VCC1_5[15] VCC1_5[84] L14 U24 VSS[157] VSS[71] D10
H22 VCC1_5[16] VCC1_5[83] L12 1 2 U23 VSS[156] VSS[70] D1
J21 VCC1_5[17] VCC1_5[82] L11 U15 VSS[155] VSS[69] C4
2

2
J22 AA21 C200 U13 C22
R240 R214 D10 VCC1_5[18] VCC1_5[81] 0.1U_0402_16V4Z VSS[154] VSS[68]
K21 VCC1_5[19] VCC1_5[80] AA20 T7 VSS[153] VSS[67] C20
K22 VCC1_5[20] VCC1_5[79] AA19 1 2 T27 VSS[152] VSS[66] C18

PCIE
@ 1K_0402_5% 10_0402_5% RB751V_SOD323 L21 T26 C14
VCC1_5[21] C203 VSS[151] VSS[65]
L22 T23 B25
1

VCC1_5[22] 0.1U_0402_16V4Z +3VS 0.1U_0402_16V4Z VSS[150] VSS[64]

M21 VCC1_5[23] VCC3_3[21] AA10 T16 VSS[149] VSS[63] B24
ICH_V5REF _RUN M22 AG19 1 2 T15 B23
VCC1_5[24] VCC3_3[20] VSS[148] VSS[62]
2 2 2 N21 VCC1_5[25] VCC3_3[19] AG16 T14 VSS[147] VSS[61] B21
N22 AG13 2 2 C202 T13 B19
C243 C233 VCC1_5[26] VCC3_3[18] 0.1U_0402_16V4Z VSS[146] VSS[60]
N23 VCC1_5[27] VCC3_3[17] AD17 T12 VSS[145] VSS[59] B15
1U_0603_10V4Z C237 0.1U_0402_16V4Z N24 AC15 C226 Near PIN 1 2 T1 B13
1 1 1 VCC1_5[28] VCC3_3[16] VSS[144] VSS[58]
N25 AA17 R4 AG7

IDE
0.1U_0402_16V4Z P21
VCC1_5[29] VCC3_3[15]
AA15 C2231 1 AG13, AG16 C567 R25
VSS[143] VSS[57]
AG3
VCC1_5[30] VCC3_3[14] 0.1U_0402_16V4Z VSS[142] VSS[56]
P25 VCC1_5[31] VCC3_3[13] AA14 R24 VSS[141] VSS[55] AG22
P26 VCC1_5[32] VCC3_3[12] AA12 1 2 R23 VSS[140] VSS[54] AG20
P27 0.1U_0402_16V4Z R17 AG17
VCC1_5[33] C565 VSS[139] VSS[53]
R21 VCC1_5[34] R16 VSS[138] VSS[52] AG14
R22 P1 +3VS 0.1U_0402_16V4Z R15 AG12
VCC1_5[35] VCC3_3[11] VSS[137] VSS[51]

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
T21 VCC1_5[36] VCC3_3[10] M7 2 2 2 1 2 R14 VSS[136] VSS[50] AG1
C T22 L7 R13 AF7 C
VCC1_5[37] VCC3_3[9] VSS[135] VSS[49]

C266

C240

C265
U21 L4 C563 R12 AF3
VCC1_5[38] VCC3_3[8] 0.01U_0402_16V7K VSS[134] VSS[48]
U22 VCC1_5[39] VCC3_3[7] J7 R11 VSS[133] VSS[47] AF26
1 1 1
V21 VCC1_5[40] VCC3_3[6] H7 1 2 P22 VSS[132] VSS[46] AF12

GROUND
PCI
V22 VCC1_5[41] VCC3_3[5] H1 P16 VSS[131] VSS[45] AF10
W21 VCC1_5[42] VCC3_3[4] E4 Near PIN A25 P15 VSS[130] VSS[44] AF1
W22 VCC1_5[43] VCC3_3[3] B1 Near PIN P14 VSS[129] VSS[43] AE7
Y21 A6 C566 P13 AE6
Y22
VCC1_5[44] VCC3_3[2] A2-A6, D1-H1 0.01U_0402_16V7K P12
VSS[128] VSS[42]
AE25
VCC1_5[45] VSS[127] VSS[41]
VCCSUS1_5[3] U7 +1.5VALW 1 2 N7 VSS[126] VSS[40] AE21
+1.5VS AA6 VCC1_5[46] VCCSUS1_5[2] R7 N17 VSS[125] VSS[39] AE2
AB4 VCC1_5[47] Near PIN AA19 N16 VSS[124] VSS[38] AE12

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
AB5 VCC1_5[48] 2 2 2 N15 VSS[123] VSS[37] AE11

USB
2 AB6 VCC1_5[49] VCCSUS1_5[1] G19 N14 VSS[122] VSS[36] AE10

C569

C570
C571
AC4 VCC1_5[50] N13 VSS[121] VSS[35] AD6
Near PIN AG5 C232 AD4 G20 N12 AD24
0.1U_0402_16V4Z VCC1_5[51] VCC1_5[78] 1 1 1 VSS[120] VSS[34]
AE4 VCC1_5[52] VCC1_5[77] F20 N11 VSS[119] VSS[33] AD2
1
AE5 VCC1_5[53] VCC1_5[76] E24 N1 VSS[118] VSS[32] AD18

SATA
AF5 VCC1_5[54] VCC1_5[75] E23 M4 VSS[117] VSS[31] AD15

USB CORE
AG5 VCC1_5[55] VCC1_5[74] E22 M27 VSS[116] VSS[30] AD10
VCC1_5[73] E21 +3VALW M26 VSS[115] VSS[29] AD1
+1.5VS AA7 VCC1_5[56] VCC1_5[72] E20 M23 VSS[114] VSS[28] AC6
AA8 D27 C574 M16 AC3
VCC1_5[57] VCC1_5[71] 0.1U_0402_16V4Z VSS[113] VSS[27]
AA9 VCC1_5[58] VCC1_5[70] D26 M15 VSS[112] VSS[26] AC26
2 AB8 VCC1_5[59] VCC1_5[69] D25 1 2 M14 VSS[111] VSS[25] AC24
AC8 VCC1_5[60] VCC1_5[68] D24 +1.5VS M13 VSS[110] VSS[24] AC23
+5VALW +3VALW C234 C573
Near PIN AG9 0.1U_0402_16V4Z
AD8 VCC1_5[61] +2.5VS 0.1U_0402_16V4Z
M12 VSS[109] VSS[23] AC22
AE8 VCC1_5[62] VCC1_5[67] G8 L25 VSS[108] VSS[22] AC12
1
AE9 VCC1_5[63] 1 2 L24 VSS[107] VSS[21] AC10
2

B B
AF9 VCC1_5[64] VCC2_5[4] AB18 L23 VSS[106] VSS[20] AB9
R191 D9 AG9 PCI/IDE RBP P7 C267 L15 AB7
VCC1_5[65] VCC2_5[2] 0.1U_0402_16V4Z VSS[105] VSS[19]
L13 VSS[104] VSS[18] AB2

0.1U_0402_16V4Z
10_0402_5% RB751V_SOD323 ICH6 _VCCPLL AC27 AA18 ICH_V5REF _RUN 2 1 2 K7 AB19
VCCDMIPLL V5REF[2] VSS[103] VSS[17]
+3VS E26 A8 K27 AB10
1

VCC3_3[1] V5REF[1] VSS[102] VSS[16]

C572
ICH_ V5REF_SUS C210 K26 AB1
ICH_ V5REF_SUS 0.1U_0402_16V4Z VSS[101] VSS[15]
2 2 +1.5VS AE1 VCCSATAPLL V5REF_SUS F21 K23 VSS[100] VSS[14] AA4
C213 1
2 +3VS AG10 VCC3_3[22] 1 2 K1 VSS[99] VSS[13] AA16
C568 Near PIN A25 +1.5VS J4 AA13
1U_0603_10V4Z 0.1U_0402_16V4Z VCCUSBPLL VSS[98] VSS[12]
1 1 C560 E26, E27
A13 VCCLAN3_3/VCCSUS3_3[1] VCCSUS3_3[20] A24 +3VALW Near PIN A24 J25 VSS[97] VSS[11] AA11
+3VS F14 VCCLAN3_3/VCCSUS3_3[2] J24 VSS[96] VSS[10] A9
0.1U_0402_16V4Z 1 G13 AB3 +RTCVCC J23 A7
VCCLAN3_3/VCCSUS3_3[3] VCCRTC VSS[95] VSS[9]
G14 VCCLAN3_3/VCCSUS3_3[4] Near PIN AB18 H27 VSS[94] VSS[8] A4
VCCLAN1_5/VCCSUS1_5[2] G11 H26 VSS[93] VSS[7] A26
+3VALW A11 VCCSUS3_3[1] VCCLAN1_5/VCCSUS1_5[1] G10 +1.5VS H23 VSS[92] VSS[6] A23
U4 VCCSUS3_3[2] G9 VSS[91] VSS[5] A21
V1 VCCSUS3_3[3] V_CPU_IO[3] AG23 G7 VSS[90] VSS[4] A19
+3VS
V7 VCCSUS3_3[4] V_CPU_IO[2] AD26 +1.05VS G21 VSS[89] VSS[3] A15
W2 AB22 C228 G12 A12
VCCSUS3_3[5] V_CPU_IO[1] 0.1U_0402_16V4Z VSS[88] VSS[2]
Y7 VCCSUS3_3[6] G1 VSS[87] VSS[1] A1

0.1U_0402_16V4Z
VCCSUS3_3[19] G16 2 1 2
+3VALW A17 VCCSUS3_3[7] VCCSUS3_3[18] G15 C212 Near PIN AG23 ICH6_BGA609
B17 VCCSUS3_3[8] VCCSUS3_3[17] F16
0.1U_0402_16V4Z

0.1U_0402_16V4Z

2 2 C17 VCCSUS3_3[9] VCCSUS3_3[16] F15

L15 R179 1 C230
F18 VCCSUS3_3[10] VCCSUS3_3[15] E16
C221

C229

CHB1608U301_0603 0.5_0603_1% G17 D16 0.1U_0402_16V4Z

VCCSUS3_3[11] VCCSUS3_3[14]
+1.5VS 1 2 ICH6_ VCCDMIPLL1 2 ICH6 _VCCPLL G18 VCCSUS3_3[12] VCCSUS3_3[13] C16 1 2
1 1
A Change to 0 ohm A
2 1 ICH6_BGA609 Near PIN AG10
Near PIN A17
C195
0.1U_0402_16V4Z 1 C205 2
0.01U_0402_16V7K
Compal Electronics, Inc.
Title
SCHEMATIC, M/B LA-2492
Near PIN THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number R ev
AC27 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
401317 B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. D ate: ¬P 期一, 一月 03, 2005 Sheet 20 of 51
5 4 3 2 1
 5 4 3 2 1

+5VS +1.8VS +3VS

SATA Module
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1 2 ATAIOSEL 1 2 T1
Sets maximum transfer rate and UDMA mode
R235 10K_0402_5% R250 10K_0402_5% CNFG2 CNFG1 CNFG0 NOTE
1 1 1 1 1 1 1 1 2 P ID E _HIORDY INT PD INT PD
C375 C357 C591 R499 4.7K_0402_5% 2 1 PIDE_ HDREQ
1 2 PID E_HIOCS16# R492 5.6K_0402_5% * Device Mode 100MB/s
C384 C363 C597 C282 R500 10K_0402_5%
0 0 0
2 2 2 2 2 2 2 T0 PIDE_H INTRQ
1 2 2 1 0 0 1 Device Mode 133MB/s
1000P_0402_50V7K 1U_0603_10V4Z 4.7U_0805_10V4Z 0.1U_0402_16V4Z R245 @ 10K_0402_5% R491 10K_0402_5%
1 2 T2 Device Mode 150MB/s
D R252 @ 10K_0402_5%
0 1 0 D
Pleace near HD CONN Pleace near U178 1 2 T3
1 0 0 Host Mode 100MB/s
R263 10K_0402_5%
1 2 T6 1 0 1 Host Mode 133MB/s
R268 10K_0402_5%
1 1 0 Host Mode 150MB/s
U22 0 1 1 Reserved
PIDE_H DD0 62 32 SATA_DTX_IRX_P0 1 1 1 Reserved
PIDE_H DD1 HDD0 TXP SATA_DTX_IRX_N0
64 HDD1 TXM 31
PIDE_H DD2 2 27 SATA_ITX_C_DRX_P0
PIDE_H DD3 5
HDD2 SATA RXP
28 SATA_ITX_C_DRX_N0 SATA_ITX_C_DRX_P0 18
PIDE_H DD4 HDD3 RXM SATA_ITX_C_DRX_N0 18
7 HDD4
PIDE_H DD5 11 17 SATA_RST# +3VS
PIDE_H DD6 HDD5 RST# T0
13 HDD6 T0 33
PIDE_H DD7 15 34 T1 C250

Config & Debug

PIDE_H DD8 HDD7 T1 T2
14 HDD8 T2 35 1 2 0.1U_0402_16V4Z
PIDE_H DD9 12 36 T3
PIDE_ HDD10 HDD9 T3
10 HDD10 T4 37

5
PIDE_ HDD11 6 38 T5 1 2 U20

Parallel ATA
PIDE_ HDD12 HDD11 T5 T6 R266 10K_0402_5% IDE_HRESET#
3 39 1

P
HDD12 T6 19 IDE_HRESET# B
PIDE_ HDD13 1 40 4 SATA_RST#
PIDE_ HDD14 HDD13 T7 PLT_RST# Y
63 HDD14 CNFG2 20 1 2 2 A

G
PIDE_ HDD15 61 19 CNF G1 1 2 R604 0_0402_5%
HDD15 CNFG1 R237 10K_0402_5% TC7SH08FU_SSOP5
18

3
CNFG0 ATAIOSEL
ATAIOSEL 21
PID E_HDA0 50 +3VS
PID E_HDA1 HDA0 IDE_XTLIN SW DJ@ C643
51 HDA1 XTLIN/OSC 22
C PID E_HDA2 49 23 IDE_XTLOUT 0.1U_0402_16V4Z 2 1 C
PIDE_HCS0# HDA2 XTLOUT
48 HCS0#
PIDE_HCS1# 47 +3VS +1.8VS +3VS
HCS1#
ISET 26 2 1

5
PID E_HIOCS16# 52 44 R232 12.1K_0603_1% U43
PIDE_H INTRQ HIOCS16# VDDIO_0 PLT_RST#
53 4 1

P
HINTRQ VDDIO_1 6,16,17,19,22,24,27,33,34 PLT_RST# B
P IDE_HDMACK# 54 9 4
P ID E _HIORDY HDMACK# VDD_0 Y
55 HIORDY VDD_1 41 30,34 EC_IDERST 2 A

G
PIDE_HDIOR# 58 56
PIDE_ HDIOW # HDIOR# VDD_2 SW DJ@
59 24

3
PIDE_ HDREQ HDIOW# VAA1 0.1U_0402_16V4Z TC7SH08FU_SSOP5
60 HDMARQ VAA2 29 1 2
PIDE_HRESET# 1 2 PIDE_R_HRESET# 16 L31 CHB1608U800_0603
R243 33_0402_5% 46
HRESET# Power 25 Change to 0 ohm
HPDIAG# VSS1
VSS2 30 1 1 1 1
8 C255 C595
GND_0 2.2U_0603_6.3V6K
45 UAO UART GND_1 42
43 UAI GND_2 57
1

2 2 2 2
C258 C590

R275
88SA8040_TQFP64
0.01U_0402_16V7K 1000P_0402_50V7K
P-ATA HDD Conn.
10K_0402_5%
2

JP18 MOLEX_54782-4411
1

PIDE_HRESET#
R230 PIDE_H DD7 44 43 PIDE_H DD8
0_0603_5% PIDE_H DD6 42 41 PIDE_H DD9
PIDE_H DD5 40 39 PIDE_ HDD10
PIDE_H DD4 38 37 PIDE_ HDD11
2

PIDE_H DD3 36 35 PIDE_ HDD12

B PIDE_H DD2 34 33 PIDE_ HDD13 B
+3VS PIDE_H DD1 32 31 PIDE_ HDD14
PIDE_H DD0 30 29 PIDE_ HDD15
Y2 28 27
26 25
1

IDE_XTLIN 1 2 IDE_XTLOUT PIDE_ HDREQ

PIDE_ HDIOW # 24 23
25MHZ_12PF_1BG25000CK1B R513 PIDE_HDIOR# 22 21
20 19
1

+3VS @ 0_0402_5% P ID E _HIORDY SEC_CSEL R503 1 2 470_0402_5%

X3 P IDE_HDMACK# 18 17
2

R236 IDE_XTLIN PIDE_H INTRQ 16 15 R504 1

4 VDD OUT 3 14 13 2 10K_0402_5%
0_0402_5% PID E_HDA1 R322 1 2 10K_0402_5%
PID E_HDA0 12 11 PID E_HDA2
1 1 1
2

PIDE_HCS0# 10 9 PIDE_HCS1#
C293 C287 C294 R344 1 8 7
1 CONT VSS 2 2 @ 10K_0402_5% 6 5
4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z R234 1M_0402_5% 1
2 2 2 +5VS 4 3 +5VS
@ OSC 25MHZ SG645PCG

48
47
C607 2 1
1 1
@ 0.1U_0402_16V4Z

48
47
C259 C249 2
12P_0402_50V8J 12P_0402_50V8J
2 2

25MHz reference clock T[4:3] = 01

A
Place near connector side. A

SATA_DTX_IRX_N0 C251 2 1 0.01U_0402_16V7K SATA_DTX_C_IRX_N0

SATA_DTX_C_IRX_N0 18

SATA_DTX_IRX_P0 C252 2 1 0.01U_0402_16V7K SATA_DTX_C_IRX_P0 Compal Electronics, Inc.

SATA_DTX_C_IRX_P0 18 Title
SCHEMATIC, M/B LA-2492
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
401317 B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: ¬P 期一, 一月 03, 2005 Sheet 21 of 51
5 4 3 2 1
 A B C D E F G H

Placea caps. near ODD CONN.

+5VMOD
18 IDE_DD[0..15]
IDE_DD[0..15] Module Conn.
0.1U_0402_16V4Z 10U_1206_16V4Z IDE_DA[0 ..2]
18 IDE_DA[0..2]
JP31
1 1 1 1 1
C554 C158 71

C551 C155 C552 1

2 2 2 2 2
2
1 CD ROM_R 3 1
30,32 INT_CD_R
1000P_0402_50V7K 1U_0603_10V4Z 10U_1206_16V4Z CDROM_L 4
30,32 INT_CD_L
5
CD_A GND 6
30 CD_AGND
MODULE_RST# 7
+5VMOD 34 MODULE_RST#
8
9
SW _PCI_RST IDE_D D7 10

1
IDE_D D8 11
C170 SW DJ@ R596 IDE_D D6 12
0.1U_0402_16V4Z +3VALW +5VMOD 470_0402_5% IDE_D D9 13
IDE_D D5 14

1
1 2 R165 IDE_ DD10 15

2
16
SW DJ@
14

17
1

U10A 10K_0402_5% IDE_D D4 18

1
D IDE_ DD11 19
OE#
P

18 IDE_DCS1#
IDE _DCS1# 2
I O 3 2 SW _IDE_DCS1# MOD _DISCHARGE 2 Q62 IDE_D D3 20
G 2N7002_SOT23 IDE_ DD12 21
G

S IDE_D D2 22

3
IDE_ DD13 23
7

SW DJ@ +5VMOD 24
SN74LVC125APWLE_TSSOP14 25
IDE_D D1 26
IDE_ DD14 27
IDE_D D0 28
1 2 IDE_ DD15 29
30
R590 0_0402_5% 31
2 IDE_DD REQ 32 2
18 IDE_DDREQ
33
IDE_ DIOW # 34
+5VMOD 18 IDE_DIOW #
35
IDE_DIO R# 36
18 IDE_DIOR#
SW _PCI_RST R166 37
1

+5VMOD 2 1 SH DD_LED# ID E _ D I ORDY 38

18 ID E _ D IORDY
SW DJ@ R514 10K_0402_5% 2 1 SEC_CSEL 39
4

U10B 10K_0402_5% R507 @ 475_0402_1% IDE_D DACK# 40

18 IDE_DDACK#
41
OE#

IDE _DCS3# 5 6 SW _IDE_DCS3# I DE_IRQ 42

18 IDE_DCS3# 18 IDE_IRQ
2

I O M ID2
+3VALW 2 1 MID2 34 43
R446 100K_0402_5% IDE _DA1 44
SW DJ@ 2 1 M ID1 +5VMOD 45
MID1 34
SN74LVC125APWLE_TSSOP14 R443 100K_0402_5% 46
2 1 M ID0 47
MID0 34
R442 100K_0402_5% IDE _DA0 48
1 2 IDE _DA2 49
SW _IDE_DCS1# 50
R591 0_0402_5% SW _IDE_DCS3# 51
34 SHDD_LED# 52
53
M ID2 54
M ID1 55
M ID0 56
57
58
59
60
3 3
61
62
63
64
65
66
67
68
+3VALW 69
70

1
+5VMOD R158 72
Q15
AOS 3401_SOT23 SW DJ@
10K_0402_5%

2
3 1 TYCO_1827293-1
+5VALW
SW _PCI_RST
2 1

1
D
2

1 2 C160 C164 +5VMOD 2 Q60

+5VALW R155 240K_0402_5% 10U_1206_16V4Z 0.1U_0402_16V4Z G SW DJ@
1 2 S 2N7002_SOT23

3
2 1 2 1 MOD _DISCHARGE

1
C166 1U_0805_25V4Z R152 10K_0402_5% SW DJ@ D
R534 1 2 0_0402_5% 2 Q21
17,24,29,33,34 PCI_RST#
G SW DJ@
1

R535 1 2 @ 0_0402_5% S 2N7002_SOT23

6,16,17,19,21,24,27,33,34 PLT_RST#

3
4 4

22K 22K
32,34 CD_PLAY 2 2IDE_MPW R IDE_MPW R 19
22K 22K

Q47 Q48 Compal Electronics, Inc.

3

DTC124EK_SOT23 DTC124EK_SOT23 Title

SCHEMATIC, M/B LA-2492
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
401317 B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: ¬P 期一, 一月 03, 2005 Sheet 22 of 51
A B C D E F G H
 5 4 3 2 1

+S1_VCC +3VS +S2_VCC

S 2_A[0..25]
26 S2_A[0..25]

M10
M12
H10
H11
H12

D19
A11

K12

K19
J12
M7

M9
S 1_A[0..25] S2_ D[0..15]

H8
H9

N7
A5

K8
J8
26 S1_A[0..25] 26 S2_D[0..15]
D U41A D
S1_ D[0..15]

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCA
VCCA

VCCB
VCCB
26 S1_D[0..15]
S1_D10 D1
S1_D9 A_CAD31/A_D10
C1 A_CAD30/A_D9
S1_D1 D3 N1
A_CAD29/A_D1 DATA DATA 26
S1_D8 C2 L6
A_CAD28/A_D8 CLOCK CLOCK 26
S1_D0 B1 N2
A_CAD27/A_D0 LATCH LATCH 26
S1_A0 B4
S1_A1 A_CAD26/A_A0
A4 A_CAD25/A_A1
S1_A2 E6
S1_A3 A_CAD24/A_A2 +3VS
B5 A_CAD23/A_A3
S1_A4 C6 B15 S2_D10
S1_A5 A_CAD22/A_A4 B_CAD31/B_D10 S2_D9 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1U_0603_10V4Z
B6 A_CAD21/A_A5 B_CAD30/B_D9 A16
S1_A6 G9 B16 S2_D1 1 1 1 2 2
S1_A25 A_CAD20/A_A6 B_CAD29/B_D1 S2_D8
C7 A_CAD19/A_A25 B_CAD28/B_D8 A17
S1_A7 B7 C16 S2_D0 C268 C298 C297 C309 C254
S1_A24 A_CAD18/A_A7 B_CAD27/B_D0 S2_A0
A7 A_CAD17/A_A24 B_CAD26/B_A0 D17
S1_A17 S2_A1 2 2 2 1 1
A10 A_CAD16/A_A17 B_CAD25/B_A1 C19
S1_IOW R# E11 D18 S2_A2 0.1U_0402_16V4Z 0.1U_0402_16V4Z
26 S1_IOW R# A_CAD15/A_IOWR# B_CAD24/B_A2
S1_A9 G11 E17 S2_A3
S1 _IORD# A_CAD14/A_A9 B_CAD23/B_A3 S2_A4
26 S1_IORD# C11 A_CAD13/A_IORD# B_CAD22/B_A4 E19
S1_A11 B11 G15 S2_A5 +3VS
S1_OE# A_CAD12/A_A11 B_CAD21/B_A5 S2_A6
26 S1_OE# C12 A_CAD11/A_OE# B_CAD20/B_A6 F18
S1_CE2# B12 H14 S2_A25 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2.2U_0603_6.3V6K
26 S1_CE2# A_CAD10/A_CE2# B_CAD19/B_A25
S1_A10 A12 H15 S2_A7 1 1 1 1 1
S1_D15 A_CAD9/A_A10 B_CAD18/B_A7 S2_A24 C305
E12 A_CAD8/A_D15 B_CAD17/B_A24 G17
S1_D7 C13 K17 S2_A17 C326 C285 C303 C306
S1_D13 A_CAD7/A_D7 B_CAD16/B_A17 S2_IOW R#
F12 A_CAD6/A_D13 B_CAD15/B_IOWR# L13 S2_IOW R# 26
S1_D6 S2_A9 2 2 2 2 2
A13 A_CAD5/A_D6 B_CAD14/B_A9 K18
C S1_D12 C14 L15 S2 _IORD# 0.1U_0402_16V4Z 0.1U_0402_16V4Z C
A_CAD4/A_D12 B_CAD13/B_IORD# S2_IORD# 26
S1_D5 E13 L17 S2_A11
S1_D11 A_CAD3/A_D5 B_CAD12/B_A11 S2_OE#
A14 A_CAD2/A_D11 B_CAD11/B_OE# L18 S2_OE# 26
S1_D4 B14 L19 S2_CE2#
A_CAD1/A_D4 B_CAD10/B_CE2# S2_CE2# 26
S1_D3 E14 M17 S2_A10
A_CAD0/A_D3 B_CAD9/B_A10 S2_D15 +S1_VCC +S2_VCC
M14

S1_REG# C5
PCI 7421 B_CAD8/B_D15
B_CAD7/B_D7 M15
N19
S2_D7
S2_D13
26 S1_REG# A_CC/BE3#/A_REG# B_CAD6/B_D13
S1_A12 F9 N18 S2_D6 1 1 1 1
S1_A8 A_CC/BE2#/A_A12 B_CAD5/B_D6 S2_D12
B10 A_CC/BE1#/A_A8 B_CAD4/B_D12 N15
S1_CE1# G12 M13 S2_D5 C292 C581 C261 C262
26 S1_CE1# A_CC/BE0#/A_CE1# B_CAD3/B_D5 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
P18 S2_D11 0.1U_0402_16V4Z
S1_A13 B_CAD2/B_D11 S2_D4 2 2 2 2
G10 A_CPAR/A_A13 B_CAD1/B_D4 P17
S1_A23 C8 P19 S2_D3
S1_A22 A_CFRAME#/A_A23 B_CAD0/B_D3 S2_REG#
A8 A_CTRDY#/A_A22 B_CC/BE3#/B_REG# F15 S2_REG# 26
S1_A15 B8 G18 S2_A12
S1_A20 A_CIRDY#/A_A15 B_CC/BE2#/B_A12 S2_A8
A9 A_CSTOP#/A_A20 B_CC/BE1#/B_A8 K14
S1_A21 C9 M18 S2_CE1#
A_CDEVSEL#/A_A21 B_CC/BE0#/B_CE1# S2_CE1# 26
S1_A19 E10 K13 S2_A13
S1_A14 A_CBLOCK#/A_A19 B_CPAR/B_A13 S2_A23
F10 A_CPERR#/A_A14 B_CFRAME#/B_A23 G19
S1_WAIT# B3 H17 S2_A22
26 S1_WAIT# A_CSERR#/A_WAIT# B_CTRDY#/B_A22
S1_INPACK# E7 J13 S2_A15
26 S1_INPACK# A_CREQ#/A_INPACK# B_CIRDY#/B_A15
S1_WE# B9 J17 S2_A20
26 S1_WE# A_CGNT#/A_WE# B_CSTOP#/B_A20
S1_BVD1 B2 H19 S2_A21
26 S1_BVD1 A_CSTSCHG/A_BVD1(STSCHG/RI) B_CDEVSEL#/B_A21
S1_WP C3 J19 S2_A19
26 S1_WP A_CCLKRUN#/A_WP(IOIS16) B_CBLOCK#/B_A19
S1_A16 2 1 A16_CLK E9 J18 S2_A14
R273 33_0402_5% A_CCLK/A_A16 B_CPERR#/B_A14 S2_WAIT#
C4 A_CINT#/A_READY(IREQ) B_CSERR#/B_WAIT# B18 S2_WAIT# 26
S1_RD Y# E18 S2_INPACK#
26 S1_RDY# B_CREQ#/B_INPACK# S2_INPACK# 26
S1_RST A6 J15 S2_WE#
B 26 S1_RST A_CRST#/A_RESET B_CGNT#/B_WE# S2_WE# 26 B
F14 S2_BVD1
B_CSTSCHG/B_BVD1(STSCHG/RI) S2_BVD1 26
S1_BVD2 A2 A18 S2_WP
26 S1_BVD2 A_CAUDIO/A_BVD2(SPKR#) B_CCLKRUN#/B_WP(IOIS16) S2_WP 26
H18 2 1 S2_A16
S1_CD1# B_CCLK/B_A16 S2_RD Y# R239 33_0402_5%
26 S1_CD1# C15 A_CCD1#/A_CD1# B_CINT#/B_READY(IREQ) B19 S2_RDY# 26
S1_CD2# E5 F17 S2_RST
26 S1_CD2# A_CCD2#/A_CD2# B_CRST#/B_RESET S2_RST 26
S1_VS1 A3 C17 S2_BVD2
26 S1_VS1 A_CVS1/A_VS1# B_CAUDIO/B_BVD2(SPKR#) S2_BVD2 26
S1_VS2 E8 N13 S2_CD1#
26 S1_VS2 A_CVS2/A_VS2# B_CCD1#/B_CD1# S2_CD1# 26
B17 S2_CD2#
B_CCD2#/B_CD2# S2_CD2# 26
S1_D14 B13 C18 S2_VS1
A_CRSVD/A_D14 B_CVS1/B_VS1# S2_VS1 26
S1_D2 D2 F19 S2_VS2
+3VS A_CRSVD/A_D2 B_CVS2/B_VS2# S2_VS2 26
S1_A18 C10 N17 S2_D14
A_CRSVD/A_A18 B_CRSVD/B_D14 S2_D2
B_CRSVD/B_D2 A15
R305 2 1 10K_0402_5% E2 K15 S2_A18
R304 2 A_USB_EN# B_CRSVD/B_A18
1 10K_0402_5% E1 B_USB_EN#
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

S2_CD1# S2_CD2#
PCI7421GHK_PBGA288
G7
G8
G13
H13
J9
J10
J11
K9
K10
K11
L8
L9
L10
L11
L12
M8

1 1
S1_CD1# S1_CD2# C284 C279
10P_0402_50V8J 10P_0402_50V8J
2 2
1 1
C281 C307
10P_0402_50V8J
2
10P_0402_50V8J
2 Closed to Pin N13 Closed to Pin B17
A A

Closed to Pin C15 Closed to Pin E5

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-2492
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401317
D ate: ¬P 期一, 一月 03, 2005 Sheet 23 of 51
5 4 3 2 1
 5 4 3 2 1

+AVDD_7421 +3VS
+VDPLL_33 +VDPLL_33 +3VS
0.1U_0402_16V4Z AVDD_7421 0.1U_0402_16V4Z 1 2
L30 CHB1608U800_0603
1 1 1 1 1 Change to 0 ohm C260 1 2 1U_0603_25V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
C589 1 1 1 1 1 1 2
C291 C283 C286 C288 C295 C299 C290
C325 1 2 1U_0603_25V4Z
2 2 2 2 2 C310 C300 C302 C273
D D
10U_1206_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 2 2 2 2 2 1
+AVDD_7421 +3VS 10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1U_0603_10V4Z

W10
M19
R13
R14
V17

V19
T18

W3
H1
U41B

VDPLL_33
VDPLL_15
AVDD
AVDD
AVDD

VCCP
VCCP
VR_PORT
VR_PORT
U2 PC I_AD31
AD31 PC I_AD30
AD30 V1
MC_PW R_CTRL_0 F1 V2 PC I_AD29
25 MC_PW R_CTRL_0 MC_PWR_CTRL_0 AD29 PCI_AD[0..31]
1 2 F2 U3 PC I_AD28 PCI_AD[0..31] 17,29
R313 @ 0_0402_5% MC_PWR_CTRL_1 AD28 PC I_AD27
AD27 W2
SDC D# E3 V3 PC I_AD26
25 SDCD# SD_CD# AD26
MSCD# F5 U4 PC I_AD25
25 MSCD# MS_CD# AD25
SMCD# F6 V4 PC I_AD24
25 SMCD# SM_CD# AD24
V5 PC I_AD23
R552 2 AD23
25 MSCLK_SDCLK 1 33_0402_5% AD22 U5 PC I_AD22
R303 2 1 33_0402_5% G5 R6 PC I_AD21
25 SMELWP# MS_CLK/SD_CLK/SM_EL_WP# AD21
MSBS_SDCMD_SMWE2 F3 P6 PC I_AD20
25 MSBS_SDCMD_SMWE2 MS_BS/SD_CMD/SM_WE# AD20
MSDATA3_SDDAT3_SMD3 H5 W6 PC I_AD19
25 MSDATA3_SDDAT3_SMD3 MS_DATA3/SD_DAT3/SM_D3 AD19
MSDATA2_SDDAT2_SMD2 G3 V6 PC I_AD18
25 MSDATA2_SDDAT2_SMD2 MS_DATA2/SD_DAT2/SM_D2 AD18
MSDATA1_SDDAT1_SMD1 G2 U6 PC I_AD17
25 MSDATA1_SDDATA1_SMD1 MS_DATA1/SD_DAT1/SM_D1 AD17
MSDATA0_SDDAT0_SMD0 G1 R7 PC I_AD16
25 MSDATA0_SDDAT0_SMD0 MS_SDIO(DATA0)/SD_DAT0/SM_D0 AD16
V9 PC I_AD15
AD15 PC I_AD14
AD14 U9
R280 1 2 33_0402_5% J5 R9 PC I_AD13
25 SMRE# SD_CLK/SM_RE#/SC_GPIO1 AD13
C SMALE J3 N9 PC I_AD12 C
25 SMALE SD_CMD/SM_ALE/SC_GPIO2 AD12
SMD4 H3 V10 PC I_AD11
25 SMD4 SD_DAT0/SM_D4/SC_GPIO6 AD11
SMD5 J6 U10 PC I_AD10
25 SMD5 SD_DAT1/SM_D5/SC_GPIO5 AD10
SMD6 J1 R10 PCI_AD9
25 SMD6 SD_DAT2/SM_D6/SC_GPIO4 AD9
SMD7 J2 N10 PCI_AD8
25 SMD7 SD_DAT3/SM_D7/SC_GPIO3 AD8
C387 1 2 1U_0603_25V4Z TPBIAS0 SDW P_SMCE# H7 V11 PCI_AD7
25 SDW P_SMCE# SD_WP/SM_CE# AD7
U11 PCI_AD6
AD6 PCI_AD5
AD5 R11
2

SMCLE J7 W12 PCI_AD4

25 SMCLE SM_CLE/SC_GPIO0 AD4
SMRB# K1 V12 PCI_AD3
25 SMRB# SM_R/B AD3
R355 R359 SM_PHYS_WP#2 1 K2 U12 PCI_AD2
56.2_0402_1% 25 SM_PHYS_WP# SM_PHYS_WP#/SC_FCB AD2
56.2_0402_1% N11 PCI_AD1
JP20 R581 AD1 PCI_AD0
W13
1

TPA0+ +3VS @ 0_0402_5% AD0

4 L2 SC_CD#
TPA0- K5
3 TPB0+ SC_CLK
2 K3 SC_RST C/BE3# W4 PCI_C/BE#3 17,29
TPB0- R277 1 2 10K_0402_5% K7 W7
1 SC_VCC_5V C/BE2# PCI_C/BE#2 17,29
L1 W9
SC_DATA
PCI7421 C/BE1# PCI_C/BE#1 17,29
2

L3 SC_OC# C/BE0# W11 PCI_C/BE#0 17,29

AMP_440168-2 L5
R350 R347 SC_PWR_CTRL
PAR P9 PCI_PAR 17,29
56.2_0402_1% 56.2_0402_1% P12 V7
TEST0 FRAME# PCI_FRAME# 17,29
W17 R8 PCI_TRDY# 17,29
1

NC TRDY#
T19 RSVD IRDY# U7 P C I_ IRDY# 17,29
STOP# W8 PCI_STOP# 17,29
2

1 DEVSEL# N8 PCI_DEVSEL# 17,29

+3VS M1 W5 PC M_ID 2 1 PC I_AD20
14 CLK_SD_48M CLK_48 IDSEL
R346 C362 V8 R283 100_0402_5%
5.11K_0402_1% PERR# PCI_PERR# 17,29
220P_0402_50V7K U8
B 2 R238 1 SERR# PCI_SERR# 17,29 B
2 4.7K_0402_5% R17 U1 PCI_REQ#2 17
1

PHY_TEST_MA REQ#
GNT# T2 PCI_GNT#2 17

PCICLK P5 CLK_PCI_PCM 14
R242 1 2 6.34K_0402_1% U18 R3 R562 2 1 0_0402_5%
R0 PCIRST# PCI_RST# 17,22,29,33,34
U19 T1 R563 2 1 @ 0_0402_5%
R1 GRST# PLT_RST# 6,16,17,19,21,22,27,33,34
TPBIAS0 U15 T3
TPA0+ TPBIAS0 RI_OUT#/PME#
V15 TPA0P
TPA0- W15 R2 R311 2 1 4.7K_0402_5% +3VS
TPB0+ TPA0N SUSPEND#
V14 TPB0P
TPB0- W14 L7 PCM_SPK#
TPB0N SPKROUT PCM_SPK# 30
C274 1 2 1U_0603_25V4Z TPBIAS1 TPBIAS1 U17
TPA1+ TPBIAS1 PCI_ PIRQA#
V18 TPA1P MFUNC0 N3 PCI_PIRQA# 17
TPA1- W18 M5 PCI_ PIRQB#
TPA1N MFUNC1 PCI_PIRQB# 17
2

TPB1+ V16 P1 PCI_PIRQC# +3VS

TPB1P MFUNC2 PCI_PIRQC# 17
TPB1- W16 P2 SERIRQ
TPB1N MFUNC3 SERIRQ 19,33,34
R251 R247 AVDD_7421 R276 1 2 1K_0402_5% M11 P3 PCI_PIRQD#
56.2_0402_1% CPS MFUNC4 PCI_PIRQD# 17
56.2_0402_1% R254 2 1 4.7K_0402_5% P15 N5 5 IN1_LED#
CNA MFUNC5 5IN1_LED 25,38
R19 R1 R299 1 2 10K_0402_5%
1

TPA1+ XO MFUNC6
39 TPA1+ R18 XI
TPA1- C587 18P_0402_50V8J R12 M3 R302 1 2 220_0402_5% R300 1 2 @ 10K_0402_5%
39 TPA1- PC0(TEST1) SCL
TPB1+ U13 M2 R301 1 2 220_0402_5%
39 TPB1+ PC1(TEST2) SDA
2

VSSPLL
TPB1- VSSPLL
39 TPB1- V13 PC2(TEST3)
AGND
AGND
AGND

X2 H2
VR_EN#
2

24.576MHz_16P_3XG-24576-43E1

2
1
1

R265 R253 PCI7421GHK_PBGA288 R312 C322 PCM_SPK# R586 1 2 10K_0402_5%

N12
U14
U16

P14
T17

56.2_0402_1% 56.2_0402_1% C588 18P_0402_50V8J 220_0402_5% 0.1U_0402_16V4Z

1

A 2 A

1
2

1
LED R MAY CHANGE TO 150OHM
R264 C280
5.11K_0402_1% 220P_0402_50V7K
2 Compal Electronics, Inc.
1

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-2492
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401317
D ate: ¬P 期一, 一月 03, 2005 Sheet 24 of 51
5 4 3 2 1
 5 4 3 2 1

D D

5 in 1 CardReader Conn.
JP29
MSDATA0_SDDAT0_SMD0 34 11 MSDATA3_SDDAT3_SMD3
24 MSDATA0_SDDAT0_SMD0 SM-D0 SD-DAT3
MSDATA1_SDDAT1_SMD1 33 12 MSDATA2_SDDAT2_SMD2
24 MSDATA1_SDDATA1_SMD1 SM-D1 / XD-D1 SD-DAT2
MSDATA2_SDDAT2_SMD2 32 6 MSDATA1_SDDAT1_SMD1
24 MSDATA2_SDDAT2_SMD2 SM-D2 / XD-D2 SD-DAT1
MSDATA3_SDDAT3_SMD3 31 5 IN 1 CONN SD-DAT0 7 MSDATA0_SDDAT0_SMD0
24 MSDATA3_SDDAT3_SMD3 SM_D3 / XD_D3
SMD4 21 5 SDW P_SMCE#
24 SMD4 SM-D4 / XD-D4 SD-WP-SW
SMD5 22 10 MSBS_SDCMD_SMWE2
+3VS 24 SMD5 SM-D5 / XD-D5 SD-CMD
SMD6 23 8 MSCLK_SDCLK
24 SMD6 SM-D6 / XD-D6 SD_CLK MSCLK_SDCLK 24
SMD7 24 9 +VCC_5IN1
24 SMD7 SM-D7 / XD-D7 SD-VCC
4 R626 2 1 @ 0_0402_5% SDC D#
SD-CD-SW SDCD# 24
R267 2 1 10K_0402_5% SDC D# SMELWP# 35 42 R627 2 1 0_0402_5%
24 SMELWP# SM_WP-IN / XD_WP-IN SD-VCC-SW
SM_PHYS_WP# 43 41
24 SM_PHYS_WP# SM-WP-SW SD-COM-SW
R233 2 1 10K_0402_5% MSCD# MSBS_SDCMD_SMWE2 36
24 MSBS_SDCMD_SMWE2 #SM_-WE / XD_-WE
SMALE 37 15 MSDATA0_SDDAT0_SMD0
24 SMALE #SM-ALE / XD-ALE MS-DATA0
R200 2 1 10K_0402_5% SMCD# 14 MSDATA1_SDDAT1_SMD1
MS-DATA1 MSDATA2_SDDAT2_SMD2
25 SM-LVD MS-DATA2 16
C SMCD# 2 1 3 18 MSDATA3_SDDAT3_SMD3 C
R602 0_0402_5% 29 SM-VCC-SW MS-DATA3 MSCLK_SDCLK
+VCC_5IN1 SM_-VCC / XD_-VCC MS-SCLK 19
+VCC_5IN1 SMRB# 2 1 26 17 MSCD#
24 SMRB# #SM_R/-B / XD_R/-B MS-INS MSCD# 24
SMRE# R582 0_0402_5% 27 13 MSBS_SDCMD_SMWE2
24 SMRE# #SM_-RE / XD_-RE MS-BS
SDW P_SMCE# 28 20 +VCC_5IN1
24 SDW P_SMCE# #SM_-CE / XD_-CE MS-VCC
R583 2 1 2.2K_0402_5% SMRB# SMCD# 2 1 30
24 SMCD# #SM_-CD
R603 0_0402_5% 2 40 +VCC_5IN1
SMCLE SM-COM-SW XD-VCC SMCD#
24 SMCLE 38 SM-CLE / XD-CLE XD-CD 39
R584 2 1 @ 43K_0402_5% SDW P_SMCE# 1
GND
GND 44

SMELWP# R585 2 1 0_0402_5% SM_PHYS_WP# TAITW UN_R007-L30-15-S

TI Workaround need check

+VCC_5IN1

1U_0603_10V4Z 4.7K_0402_5%
SD/XD/MS/SM PWR SWITCH

2
B +3VS B
2 2
+3VS C397 R589
C381
2

C393
R354 +3VS +VCC_5IN1 1 1

1
2
10K_0402_5% U33
R353
1 8 10K_0402_5% 0.1U_0402_16V4Z 4.7U_0805_10V4Z
1

GND OUT
R588 2 IN OUT 7
3 6

1
IN OUT +3VS
24 MC_PW R_CTRL_0 2 1 4 EN# OC# 5

Q30 0.1U_0402_16V4Z
0_0402_5%
1

D TPS2041ADR_SO8
2 C685 2 2
24,38 5IN1_LED
G C382
2

S @ 0.1U_0402_16V4Z C398 C394

3

R286 4.7U_0805_10V4Z 1U_0603_10V4Z

1 1
10K_0402_5% @ 2N7002_SOT23
1

A A

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-2492
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401317
D ate: ¬P 期一, 一月 03, 2005 Sheet 25 of 51
5 4 3 2 1
 5 4 3 2 1

CardBus Socket
JP19
FOX_1CA84122-TC-4F_150P

Power Switch for PCMCIA A1 B1

a68 b68
23 DATA A2 a34 b34 B2
S1_CD2# A3 B3 S2_CD2#
23 CLOCK 23 S1_CD2# a67 b67 S2_CD2# 23
S1_WP A4 B4 S2_WP
23 LATCH +3VS 23 S1_WP a33 b33 S2_WP 23
D S1_D10 A5 B5 S2_D10 D
16,32,34,36,37,41,47,48 SUSP# a66 b66
U39 S1_D2 A6 B6 S2_D2
S1_D9 a32 b32 S2_D9
A7 a65 b65 B7
3 20 S1_D1 A8 B8 S2_D1
DATA 12V a31 b31
4 CLOCK 12V 7 A9 GND GND B9
+3VS 2 1 5 S1_D8 A10 B10 S2_D8
R483 10K_0402_5% LATCH S1_D0 a64 b64 S2_D0
12 RESET# A11 a30 b30 B11
15 14 C244 0.1U_0402_16V4Z S1_BVD1 A12 B12 S2_BVD1
+S1_VPP OC# 3.3V 23 S1_BVD1 a63 b63 S2_BVD1 23
21 13 S1_A0 A13 B13 S2_A0
SHDN# 3.3V C580 4.7U_0805_10V4Z S1_BVD2 a29 b29 S2_BVD2
2 1 23 S1_BVD2 A14 a62 b62 B14 S2_BVD2 23
0.01U_0402_16V7K C582 20mil S1_A1 A15 B15 S2_A1
S1_REG# a28 b28 S2_REG#
2 1 8 AVPP 5V 24 +5VS 23 S1_REG# A16 a61 b61 B16 S2_REG# 23
1U_0402_6.3V4Z C583 19 2 A17 B17
+S1_VCC BVPP 5V C585 0.1U_0402_16V4Z S1_A2 GND GND S2_A2
5V 1 A18 a27 b27 B18
S1_INPACK# A19 B19 S2_INPACK#
23 S1_INPACK# a60 b60 S2_INPACK# 23
2 1 9 11 C586 4.7U_0805_10V4Z S1_A3 A20 B20 S2_A3
10U_1206_16V4Z C579 AVCC GND S1_WAIT# a26 b26 S2_WAIT#
40mil 10 AVCC 23 S1_WAIT# A21 a59 b59 B21 S2_WAIT# 23
S1_A4 A22 B22 S2_A4
S1_RST a25 b25 S2_RST
17 BVCC NC 23 23 S1_RST A23 a58 b58 B23 S2_RST 23
+S2_VPP 18 22 S1_A5 A24 B24 S2_A5
BVCC NC a24 b24
2 1 NC 16 A25 GND GND B25
0.01U_0402_16V7K C247 6 S1_VS2 A26 B26 S2_VS2
NC 23 S1_VS2 a57 b57 S2_VS2 23
2 1 S1_A6 A27 B27 S2_A6
1U_0402_6.3V4Z C246 S1_A25 a23 b23 S2_A25
A28 a56 b56 B28
+S2_VCC TPS2224ADBR_HTSSOP24 S1_A7 A29 B29 S2_A7
S1_A24 a22 b22 S2_A24
A30 a55 b55 B30
2 1 S1_A12 A31 B31 S2_A12
10U_1206_16V4Z C584 S1_A23 a21 b21 S2_A23
A32 a54 b54 B32
A33 GND GND B33
C C276 S1_A15 A34 B34 S2_A15 C272 C
S1_A22 a20 b20 S2_A22
A35 a53 b53 B35
0.1U_0402_16V4Z S1_A16 A36 B36 S2_A16 0.1U_0402_16V4Z
a19 b19
+S1_VPP A37 a52/a18 b52/b18 B37 +S2_VPP
A38 none none B38
+S1_VCC A39 a51/a17 b51/b17 B39 +S2_VCC
S1_RD Y# A40 B40 S2_RD Y#
23 S1_RDY# a16 b16 S2_RDY# 23
S1_A21 A41 B41 S2_A21
C263 S1_WE# a50 b50 S2_WE# C264
23 S1_WE# A42 a15 b15 B42 S2_WE# 23
A43 GND GND B43
0.1U_0402_16V4Z S1_A20 A44 B44 S2_A20 0.1U_0402_16V4Z
S1_A14 a49 b49 S2_A14
A45 a14 b14 B45
S1_A19 A46 B46 S2_A19
S 1_A[0..25] S1_A13 a48 b48 S2_A13
23 S1_A[0..25] A47 a13 b13 B47
S1_A18 A48 B48 S2_A18
S1_ D[0..15] S1_A8 a47 b47 S2_A8
23 S1_D[0..15] A49 a12 b12 B49
S1_A17 A50 B50 S2_A17
a46 b46
A51 GND GND B51
S1_A9 A52 B52 S2_A9
S 2_A[0..25] S1_IOW R# a11 b11 S2_IOW R#
23 S2_A[0..25] 23 S1_IOW R# A53 a45 b45 B53 S2_IOW R# 23
S1_A11 A54 B54 S2_A11
S2_ D[0..15] S1 _IORD# a10 b10 S2 _IORD#
23 S2_D[0..15] 23 S1_IORD# A55 a44 b44 B55 S2_IORD# 23
S1_OE# A56 B56 S2_OE#
23 S1_OE# a9 b9 S2_OE# 23
S1_VS1 A57 B57 S2_VS1
23 S1_VS1 a43 b43 S2_VS1 23
S1_A10 A58 B58 S2_A10
a8 b8
A59 GND GND B59
S1_CE2# A60 B60 S2_CE2#
23 S1_CE2# a42 b42 S2_CE2# 23
S1_CE1# A61 B61 S2_CE1#
23 S1_CE1# a7 b7 S2_CE1# 23
S1_D15 A62 B62 S2_D15
B S1_D7 a41 b41 S2_D7 B
A63 a6 b6 B63
S1_D14 A64 B64 S2_D14
S1_D6 a40 b40 S2_D6
A65 a5 b5 B65
S1_D13 A66 B66 S2_D13
a39 b39
A67 GND GND B67
S1_D5 A68 B68 S2_D5
S1_D12 a4 b4 S2_D12
A69 a38 b38 B69
S1_D4 A70 B70 S2_D4
S1_D11 a3 b3 S2_D11
A71 a37 b37 B71
S1_D3 A72 B72 S2_D3
S1_CD1# a2 b2 S2_CD1#
23 S1_CD1# A73 a36 b36 B73 S2_CD1# 23
A74 a1 b1 B74
A75 a35 b35 B75

GND
GND
GND
GND
3
4
5
6
A A

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-2492
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401317
D ate: ¬P 期一, 一月 03, 2005 Sheet 26 of 51
5 4 3 2 1
 5 4 3 2 1

U36
+3VALW
PCIE_PTX_C_IRX_P1 C507 1 2 0.1U_0402_16V4Z PCIE_PTX_IRX_P1 49 LED 59 LAN _ACTIVITY#
19 PCIE_PTX_C_IRX_P1 TX_P LED_ACTn LAN_ACTIVITY# 38,39
PCIE_PTX_C_IRX_N1 C508 1 2 0.1U_0402_16V4Z PCIE_PTX_IRX_N1 50 PCI-E 60 LED_10/100
19 PCIE_PTX_C_IRX_N1 TX_N LED_LINK10/100n
PCIE_ITX_C_PRX_P1 54 62 LED_1000
19 PCIE_ITX_C_PRX_P1 RX_P LED_LINK1000n
PCIE_ITX_C_PRX_N1 53 63 L AN_LINK#
19 PCIE_ITX_C_PRX_N1 RX_N LED_LINKn LAN_LINK# 38,39

1
19 ICH_PCIE_W AKE# 6 WAKEn
55 46 R77
14 CLK_PCIE_LAN REFCLKP TESTMODE +LAN_AVDD25
56 TEST 29 4.7K_0402_5%
14 CLK_PCIE_LAN# REFCLKN TSTPT

3
D PLT_RST# 5 D
6,16,17,19,21,22,24,33,34 PLT_RST# PERSTn
64 +LAN_AVDD25

2
LAN_MDI0+ VDD25 LAN_CTRL12
28 LAN_MIDI0+ 17 MDIP0 1
28 LAN_MIDI0- LAN_MDI0- 18 POWER 19 +LAN_AVDDL 1 2 Q11
LAN_MDI1+ MDIN0 AVDDL L26 0_0402_5% BCP69_SOT223
28 LAN_MIDI1+ 20 MDIP1 AVDDL 22
28 LAN_MIDI1- LAN_MDI1- 21 Media & 28

2
4
LAN_MDI2+ MDIN1 AVDDL
28 LAN_MIDI2+ 26 MDIP2 AVDDL 32 +LAN_AVDDL
28 LAN_MIDI2- LAN_MDI2- 27 GROUND 51
LAN_MDI3+ MDIN2 AVDDL C467 0.1U_0402_16V4Z
28 LAN_MIDI3+ 30 MDIP3 AVDDL 52 40mil
28 LAN_MIDI3- LAN_MDI3- 31 57 1 2 +LAN_VDD12
MDIN3 AVDDL
1
VPD_CLK 38 23 +LAN_AVDD
VPD_DATA VPD_CLK AVDD C51
+3VALW
41 VPD_DATA EEPROM
1 +3VALW 4.7U_0805_10V4Z
VDDO_TTL 2
34 SPI_DO VDDO_TTL 8
35 SPI_DI FLASH VDDO_TTL 40
R437 2 1 4.7K_0402_5% VPD_CLK 37 MEMORY 45
R438 SPI_CLK VDDO_TTL
2 1 4.7K_0402_5% VPD_DATA 36 SPI_CS VDDO_TTL 61

LAN_X1 15 2 +LAN_VDD12
+3VALW LAN_X2 XTALI VDD
14 XTALO CLOCK VDD 7
VDD 13
R76 2 1 10K_0402_5% 10 33
R74 LOM_DISABLEn VDD
2 1 10K_0402_5% 12 VAUX_AVLBL VDD 39
11 44 +3VALW
R425 2 SWITCH_VCC VDD
1 10K_0402_5% 47 VMAIN_AVLBL VDD 48
9 SWITCH_VAUX VDD 58
24 HSDACP
25 HSDACN EPAD 65

1
C R73 2 1 4.7K_0402_1% 16 Analog C
LAN_CTRL25 RSET R71
4 CTRL25 SMCLK/NC 42
LAN_CTRL12 3 43 4.7K_0402_5%
CTRL12 SMDATA/NC

3
2
R73 -- 2K for 88E8036 88E8053_QFN64 LAN_CTRL25 1
Q10
4.7K for 88E8053 BCP69_SOT223

2
4
+3VALW
40mil
+LAN_AVDD25
1 1
+3VALW
C43 C504
4.7U_0805_10V4Z 0.1U_0402_16V4Z
C521 2 2
1 2 0.1U_0402_16V4Z 1 1 1 1 1
C484 C492 C479 C497 C503

U38 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

2 2 2 2 2
8 VCC A0 1
7 WP A1 2
VPD_CLK 6 3
VPD_DATA SCL A2
5 SDA GND 4

AT24C16N10SC-2.7_SO8

B B
1

+LAN_AVDDL
R436

100K_0402_5%
2

1 1 1 1 1 1
C464 C468 C466 C465 C501 C500
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2 2 2

+LAN_VDD12

Y4
LAN_X1 LAN_X2

25MHZ_20P_1BX25000CK1A 1 1 1 1 1 1
1 1
C493 C502 C480 C491 C477 C499
A
C473 C476 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z A
27P_0402_50V8J 27P_0402_50V8J 2 2 2 2 2 2
2 2

Compal Electronics, Inc.

Title
SCHEMATIC, M/B LA-2492
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
401317 B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: ¬P 期一, 一月 03, 2005 Sheet 27 of 51
5 4 3 2 1
 5 4 3 2 1

unpop when use 88E8036(10/100)

1 1
C35 C36
D D

2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z

+LAN_AVDD25
24ST0023-3(SP050004200) for 88E8036(10/100)

1
R59
49.9_0402_1% 24HST1041A-3(SP050002110) for 88E8053(GbE)
R58 R60 R61
49.9_0402_1% 49.9_0402_1% 49.9_0402_1% T1
1 24

2
TCT1 MCT1
LAN_MDI3- 2 1:1 23 RJ45_MDI3-
27 LAN_MIDI3- TD1+ MX1+ RJ45_MDI3- 38,39

27 LAN_MIDI3+ LAN_MDI3+ 3 22 RJ45_MDI3+

TD1- MX1- RJ45_MDI3+ 38,39
4 TCT2 MCT2 21

LAN_MDI2- 5 1:1 20 RJ45_MDI2-

27 LAN_MIDI2- TD21+ MX2+ RJ45_MDI2- 38,39

27 LAN_MIDI2+ LAN_MDI2+ 6 19 RJ45_MDI2+

TD2- MX2- RJ45_MDI2+ 38,39
C 7 18 C
TCT3 MCT3
LAN_MDI1- 8 1:1 17 RJ45_MDI1-
27 LAN_MIDI1- TD3+ MX3+ RJ45_MDI1- 38,39

27 LAN_MIDI1+ LAN_MDI1+ 9 16 RJ45_MDI1+

TD3- MX3- RJ45_MDI1+ 38,39
10 TCT4 MCT4 15

LAN_MDI0- 11 1:1 14 RJ45_MDI0-

27 LAN_MIDI0- TD4+ MX4+ RJ45_MDI0- 38,39

27 LAN_MIDI0+ LAN_MDI0+ 12 13 RJ45_MDI0+

TD4- MX4- RJ45_MDI0+ 38,39
24HST1041A-3_24P
1

R66 R67 R65 R64

49.9_0402_1% 49.9_0402_1%

1
49.9_0402_1% 49.9_0402_1%
2

R396 R395
75_0402_1% 75_0402_1%
1 1

2
C38 C37
B 0.1U_0402_16V4Z 0.1U_0402_16V4Z B
2 2

RJ45_MDI3- R390 1 2 @ 0_0402_5%

RJ45_MDI3+ R391 1 2 @ 0_0402_5%

RJ45_MDI2- R393 1 2 @ 0_0402_5%

RJ45_MDI2+ R394 1 2 @ 0_0402_5%

1
reseved for 88E8036(10/100) R392 R389
75_0402_1% 75_0402_1%

2
RJ4 5_GND
RJ45_GND 38,39

A A

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-2492
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401317
D ate: ¬P 期一, 一月 03, 2005 Sheet 28 of 51
5 4 3 2 1
 A B C D E

1
+3V 1

C179 1 2 0.1U_0402_16V4Z
PCI_AD[0..31]
PCI_AD[0..31] 17,24

5
U9
1 MINI_PCI SOCKET

P
34 W L_OFF# B
Y 4
34,35,37 KILL_SW# 2 A

G
JP28
TC7SH08FU_SSOP5

3
TIP 1 2 RING
1 2
3 3 4 4
LAN RESERVED 5 6
5 6
7 7 8 8
D6 9 10 LAN RESERVED
RB751V_SOD323 9 10
11 11 12 12
+3VS_MINIPCI 1 2 13 13 14 14
15 15 16 16
L13 PCI_PIRQH# 17 18 W=30mils
W=40mils17 PCI_PIRQH# 17 18 +5VS_MINIPCI
1 2 19 20 PCI_ PIRQG#
+3V 0_0603_5% 19 20 PCI_PIRQG# 17
21 21 22 22 +3VS_MINIPCI
23 24 W=40mils
23 24 +3V
CLK_PC I_MINI 25 26 PCI_RST# L14
14 CLK_PCI_MINI 25 26 PCI_RST# 17,22,24,33,34W=40mils
27 27 28 28 1 2 +3V
29 30 0_0603_5%
17 PCI_REQ#1 29 30 PCI_GNT#1 17
31 31 32 32
PC I_AD31 33 34
2 CLK_PC I_MINI PC I_AD29 33 34 WLANPME# 33,34 2
35 35 36 36
37 38 PC I_AD30
37 38
1

PC I_AD27 39 40
R156 PC I_AD25 39 40 PC I_AD28
41 41 42 42
@ 33_0402_5% 43 44 PC I_AD26
43 44 PC I_AD24
17,24 PCI_C/BE#3 45 45 46 46
PC I_AD23 47 48 MINI_ IDSEL1 2 PC I_AD18 IDSEL : PCI_AD18
2

47 48 R162 100_0402_5%
49 49 50 50
1 PC I_AD21 51 52 PC I_AD22
PC I_AD19 51 52 PC I_AD20
53 53 54 54
C174 55 56
55 56 PCI_PAR 17,24
@ 10P_0402_50V8J PC I_AD17 57 58 PC I_AD18
2 57 58 PC I_AD16
17,24 PCI_C/BE#2 59 59 60 60
17,24 P C I_ IRDY# 61 61 62 62
63 63 64 64 PCI_FRAME# 17,24
19,33 PM_CLKRUN# 65 65 66 66 PCI_TRDY# 17,24
17,24 PCI_SERR# 67 67 68 68 PCI_STOP# 17,24 +5VS_MINIPCI
69 69 70 70
17,24 PCI_PERR# 71 71 72 72 PCI_DEVSEL# 17,24 1 2 2 1
17,24 PCI_C/BE#1 73 73 74 74
PC I_AD14 75 76 PC I_AD15 C178 C181 C173 C175
75 76 PC I_AD13 @ 1000P_0402_50V7K @ 0.1U_0402_16V4Z @ 0.1U_0402_16V4Z @ 10U_1206_16V4Z
77 77 78 78
PC I_AD12 PC I_AD11 2 1 1 2
79 79 80 80
PC I_AD10 81 82
81 82 PCI_AD9
83 83 84 84
PCI_AD8 85 86
PCI_AD7 85 86 PCI_C/BE#0 17,24
87 87 88 88
89 90 PCI_AD6
PCI_AD5 89 90 PCI_AD4
91 91 92 92
3 PCI_AD2 3
93 93 94 94
PCI_AD3 95 96 PCI_AD0
W=30mils 95 96
+5VS_MINIPCI 97 97 98 98
PCI_AD1 99 100
99 100 +3VS_MINIPCI
101 101 102 102
103 103 104 104 2 2 2 2 2 1
105 105 106 106
107 108 C182 C176 C171 C172 C177 C184
107 108 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 10U_1206_16V4Z
109 109 110 110
1 1 1 1 1 2
111 111 112 112
113 113 114 114
115 115 116 116
117 117 118 118
119 119 120 120
121 121 122 122
1 2 W=30mils 123 124 W=20mils
+5VS 123 124 +3V
L12 0_0603_5% 2
0603 QTC_C102A-040B31-4 C183
0.1U_0402_16V4Z
+5VS_MINIPCI 1

4 4

Compal Electronics, Inc.

Title
SCHEMATIC, M/B LA-2492
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
401317 B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: ¬P 期一, 一月 03, 2005 Sheet 29 of 51
A B C D E
 A B C D E F G H

+3V 28.7K for Module Design (VDDA = 4.702)

C296 +VDDA
1 2 0.1U_0402_16V4Z (output = 250 mA)
60mil

1
U24
U25A R501 40mil

14
+5VALW 4 VIN VOUT 5 +VDDA
SN74LVC14APWLE_TSSOP14 10K_0402_5% 1 1

2
C602 C308 C312 2 6 R496 1 4.85V

P
R495 C603 DELAY SENSE or ADJ 30K_0402_1%
34 BEEP# 1 O 2 2 1 1 2

2
I 1U_0402_6.3V4Z 22U_1206_16V4Z_V1 0.1U_0402_16V4Z C313
560_0402_5% 7 ERROR CNOISE 1

G
1U_0402_6.3V4Z 2 2 10U_1206_16V4Z
2 1
2
8 3 1

1
SD GND

1
C599
1 R498 SI9182DH-AD_MSOP8 1

1
10K_0402_5%
2
34,38,40,41,47 S YSON R497

2
+3V C604 0.1U_0402_16V4Z 10K_0402_1%
1 2 MO NO_IN

2
14

1U_0402_6.3V4Z

1
C601 C 1 2 R336 2 1 @ 6.8K_0402_5%
P

R494 Q28
24 PCM_SPK# 3 I O 4 2 1 1 2 2 R502
560_0402_5% B 2SC2411K_SC59 2.4K_0402_5% R349 2 1 @ 6.8K_0402_5%
G

U25B 1U_0402_6.3V4Z E

3
SN74LVC14APWLE_TSSOP14 R342 2 1 6.8K_0402_5% 1 2 C354 LINEL
31 LINE_IN_L
7

1U_0402_6.3V4Z
C600
R493 R345 2
2 1 1 2 31 LINE_IN_R 1 6.8K_0402_5% 1 2 C359 L INER
560_0402_5% 1U_0402_6.3V4Z

1
1U_0402_6.3V4Z 1 1
+3V D12
R279 RB751V_SOD323 C639 C640
10K_0402_5% @ 1U_0402_6.3V4Z @ 1U_0402_6.3V4Z
14

2 2

2
P

5 6 +3V
19 SB_SPKR I O
G

U25C
SN74LVC14APWLE_TSSOP14
AC97 Codec
7

1
2 2
L18 1 2 @FBM-L10-160808-301-T_0603 +3VS R536 R537
@ 1K_0402_5% @ 4.7K_0402_5%
+AVDD_AC97

2 1

2
0.1U_0402_16V4Z +AC97_DVDD L19 1 2 FBM-L10-160808-301-T_0603
L21

G
Change to 0 ohm
1 2 0.1U_0402_16V4Z 1 1 1
+VDDA
FBM-L10-160808-301-T_0603 1 1 1 C317 1 3 SMB_CLK
4,34,39 EC_SMB_CK2
C369 C366 C316 C314

S
C348 10U_1206_16V4Z Q58 @ 2N7002_SOT23
10U_0805_10V4Z 2 2 2

25

38

9
2 2 2
1 2

1
0.1U_0402_16V4Z 0.1U_0402_16V4Z R538 0_0402_5%

AVDD1

AVDD2

DVDD1

DVDD2
R539 R540
@ 1K_0402_5% @ 4.7K_0402_5%
C608 1 2 1U_0603_10V4Z 14 35 AMP_LEFT 32

2 1

2
AUX_L LINE_OUT_L
C609 1U_0603_10V4Z

G
1 2 15 AUX_R LINE_OUT_R 36 AMP_RIGHT 32
16 37 1 3 SMB_DATA
JD2 MONO_OUT/VREFOUT3 4,34,39 EC_SMB_DA2

S
32,38 NBA_PLUG 17 JD1 HP_OUT_L 39 HP_OUT_L 31
Q59 @ 2N7002_SOT23
R309 2 1 6.8K_0402_5% LINEL 23 41 1 2
LINE_IN_L HP_OUT_R HP_OUT_R 31
R542 0_0402_5%
R329 2 1 6.8K_0402_5% L INER 24 LINE_IN_R R289
BIT_CLK 6 1 2 22_0402_5% ICH_AC_BITCLK 18,35
R323 2 1 20K_0402_5% C332 1 2 1U_0402_6.3V4Z 18
3 22,32 INT_CD_L CD_L 3
8 R288 1 2 22_0402_5%
SDATA_IN ICH_AC_SDIN0 18
R328 2 1 20K_0402_5% C339 1 2 1U_0402_6.3V4Z 20
22,32 INT_CD_R CD_R
2 R291 1 2 @ 0_0402_5%
XTL_IN CLK_14M_CODEC 14

2
CD_ GNA C334 1 2 1U_0603_10V4Z 19 CD_GND
1 2 C_M IC 21 R521 X4 1 2
32 MIC MIC1
C344 1U_0603_10V4Z @ 1M_0402_5%
1 2 22 3 1 24.576MHz_16P_3XG-24576-43E1 1

1
R315 20K_0402_5% CD_ GNA C349 1U_0603_10V4Z MIC2 XTL_OUT
22 CD_AGND 2 1
1 2 13 29 C373 1 2 1000P_0402_50V7K C610 C611
C318 0.1U_0402_16V4Z PHONE AFILT1 22P_0402_25V8K 22P_0402_25V8K
1

MO NO_IN C388 1 2 2
12 PC_BEEP AFILT2 30 2 1000P_0402_50V7K
R282 R324
VREFOUT 28 +AUD_VREF
0_0402_5% 6.8K_0402_5% R522 1 2 22_0402_5% 11
18,35 ICH_AC_RST# RESET#
27 1U_0402_6.3V4Z
2

R287 1 VREF
18,35 IC H _AC_SYNC 2 22_0402_5% 10 SYNC
32 C389 1 2 0.01U_0402_16V7K
R290 1 DCVOL
18,35 ICH_AC_SDOUT 2 22_0402_5% 5 SDATA_OUT
C612 1 2 1U_0603_10V4Z
1 1
SMB_DATA 45 31 C641 1 2 1U_0603_10V4Z C368
SDA NC R523 1
46 XTLSEL VREFOUT2 33 2 @ 0_0402_5% C367
34 R524 1 2 @ 0_0603_5% +AVDD_AC97 0.1U_0402_16V4Z
VAUX R525 1 0_0402_5% 2 2
32,34 EAPD 47 SPDIFI/EAPD DISABLE# 43 2 EC_IDERST 21,34
2

44 SMB_CLK
R321 SCK
1 2 48 SPDIFO 1 2 +3VS
R307 0_0603_5% @ 0_0402_5% 40 R526 @ 10K_0402_5%
NC
4 DVSS1 AVSS1 26
7 42
1

4 DVSS2 AVSS2 4
1 2
R306 0_0603_5% U27 ALC250-VD_LQFP48

1
R284
2
0_0603_5%
DGND AGND
Compal Electronics, Inc.
Title
SCHEMATIC, M/B LA-2492
With 14.318Mhz : R321 POP THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
GND GNDA AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
With 24.576Mhz : R321 DEPOP DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401317 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: ¬P 期一, 一月 03, 2005 Sheet 30 of 51
A B C D E F G H
 5 4 3 2 1

1 2 R330 1 2 1K_0402_5% R320 1 2 10K_0402_5% R298 1 2 4.7K_0402_5%

39 LINEIL#
C336 1U_0402_6.3V4Z 1
C337 1000P_0402_50V7K +VDDA
2 C315 1 2
1

4
1U_0402_6.3V4Z
C321 1000P_0402_50V7K 2

V+
-
O 1 LINE_IN_L 30
R297 1 2
1 2 2 1K_0402_5% R292 1 2 10K_0402_5% 3 +VDDA

V-
39 LINEIL +
C320 1U_0402_6.3V4Z U26A
D LMV824MTX_TSSOP14 D

11
+DOCK_AUD_VREF R334 1 2 4.7K_0402_5% +VDDA

4
+DOCK_AUD_VREF
9

V+
R294 - + DOCK_AUD_VREF
O 8
1 2 10

V-
R319 1 +
39 L INEIR# 1 2 2 1K_0402_5% R314 1 2 10K_0402_5% R326 1 2 4.7K_0402_5% 100K_0402_5% U26C

2
C329 1U_0402_6.3V4Z 1 1 LMV824MTX_TSSOP14 1

11
C341
C330 1000P_0402_50V7K +VDDA R308 C331 1U_0402_6.3V4Z
100K_0402_5% 0.1U_0402_16V4Z
2 2 2

1
1

4
C343 1000P_0402_50V7K 6

V+
-
O 7 LINE_IN_R 30
R332 1 2 R333
1 2 2 1K_0402_5% 1 2 10K_0402_5% 5

V-
39 L IN EIR +
C345 1U_0402_6.3V4Z U26B
LMV824MTX_TSSOP14

11
+DOCK_AUD_VREF R335 1 2 4.7K_0402_5%

R358 1 2 22K_0402_5%

1 2
C378 68P_0402_50V8K +VDDA
C C
+VDDA C355 1 2

4
R361 4 1U_0402_6.3V4Z
22K_0402_5% 2

V+
-
1 2 1 2 9 1 1 2
V+

30 HP_OUT_L - O LINEOL 39
C379 1U_0402_6.3V4Z 8 3 C350 1U_0402_6.3V4Z

V-
O + U30A
10
V-

+DOCK_AUD_VREF +

2
2 U30C LMV824MTX_TSSOP14

11
LMV824MTX_TSSOP14
11

C360 R360
0.1U_0402_16V4Z 4.7K_0402_5%
1

1
R357 2 1 4.7K_0402_5%

+VDDA

4
6

V+
-
O 7 1 2 LINEOL# 39
5 C372 1U_0402_6.3V4Z

V-
+DOCK_AUD_VREF +
2 U30B
LMV824MTX_TSSOP14

11
C358
0.1U_0402_16V4Z
1

B B

R372 1 2 22K_0402_5%

1 2
C405 68P_0402_50V8K +VDDA

+VDDA 1 2
C390 1U_0402_6.3V4Z

4
R371
4

22K_0402_5% 2

V+
-
1 2 1 2 9 1 1 2
V+

30 HP_OUT_R - O LINEOR 39
C400 1U_0402_6.3V4Z 8 3 C391 1U_0402_6.3V4Z

V-
O + U31A
10
V-

+DOCK_AUD_VREF +
2

2 U31C 11 LMV824MTX_TSSOP14
LMV824MTX_TSSOP14
11

C406 R369
0.1U_0402_16V4Z 4.7K_0402_5%
1
1

R367 2 1 4.7K_0402_5%

+VDDA
4

6
V+

-
A O 7 1 2 LINEOR# 39 A
5 C392 1U_0402_6.3V4Z
V-

+DOCK_AUD_VREF +
2 U31B
LMV824MTX_TSSOP14
11

C386
0.1U_0402_16V4Z
1
Compal Electronics, Inc.
Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
SCHEMATIC, M/B LA-2492
PROPRIETARY NOTE TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 401317
D ate: ¬P 期一, 一月 03, 2005 Sheet 31 of 51
5 4 3 2 1
 A B C D E

+5VCD

1
R318
100K_0402_5%

+5VCD

2
W=40mil SHUTDOW N#
Q29 Speaker Conn.

1
D 2N7002_SOT23
1 1 1 2 EC_MUTE 34 1
G
C346 C347 S JP8

3
0.1U_0402_16V4Z 4.7U_0805_10V4Z SPKL+ R565 1 2 0_0603_5%
2 2 SPKL- R566 0_0603_5% 4
1 2 3

1
D Q31 SPKR+ R567 0_0603_5%
1 2 2
2 EAPD SPKR- R568 1 2 0_0603_5%
EAPD 30,34 1
G
S @ 2N7002_SOT23 ACES_85204-0400

3
U29

3
7 22 R348 1 2 100K_0402_5% +5VCD
PVDD SHUTDOWN# NBA_PLUG D36 D37
18 PVDD SE/BTL# 15
19 VDD PC-BEEP 14 1 2
11 BYPASS C364 0.1U_0402_16V4Z @ PSOT24C_SOT23
R331 1 BYPASS
2 100K_0402_5% PATH_SEL_1 2 HP/LINE# LOUT- 9 SPKL- @ PSOT24C_SOT23
VOL_AMP 3 16 SPKR-
38 VOL_AMP

1
SPKL+ VOLUME ROUT-
4 LOUT+ LIN 10
SPKR+ 21 8
LINE_OUTL LEFT_2 ROUT+ RIN
30 AMP_LEFT 1 2 5 LLINEIN
C327 1U_0402_6.3V4Z R IGHT_2 23 1
L INE_OUTR RLINEIN GND
30 AMP_RIGHT 1 2 6 LHPIN GND 12
C328 1U_0402_6.3V4Z 20 13 2 2 2
RHPIN GND
GND 24
17 C361 C356
HP_L CLK 1U_0402_6.3V4Z C351 1U_0402_6.3V4Z
22,30 INT_CD_L 1 2
C338 @ 1U_0402_6.3V4Z TPA0232PWP_TSSOP24 1 1 1
1 2 HP _R 1 1U_0402_6.3V4Z
22,30 INT_CD_R
C335 @ 1U_0402_6.3V4Z 1
2 2 2 C353 2
C333 0.047U_0402_16V7K
2
C340 2 0.1U_0402_16V4Z
0.1U_0402_16V4Z 1 1 C342
0.1U_0402_16V4Z

HeadPhone JACK
JP22
5

NBA_PLUG 4
+5VCD 30,38 NBA_PLUG
SPKR+ C352 1 2 150U_4A_10VM L22 1 2 FBM-11-160808-700T_0603

+
1 2 3
R356 0_0402_5% 6
2

SPKL+ C399 1 2 150U_4A_10VM L24 1 2 FBM-11-160808-700T_0603

+
1 2 2
R362 0_0402_5% 1
R337
@ 100K_0402_5% FOX_JA6033L-5S3-TR
C376 C370
1

PATH_SEL_1 330P_0402_50V7K 330P_0402_50V7K

1

D
2 SUSP#
Q33 G
@ 2N7002_SOT23 S
3

3 3

+5VCD
Q39
AOS 3401_SOT23
+AUD_VREF
+5VALW 3 1

2 1 MIC JACK
2

1
1 2 C371 C365 JP21
+5VALW R363 240K_0402_5% 10U_1206_16V4Z 0.1U_0402_16V4Z 5
1 2 R352 R351
4.7K_0402_5% 4.7K_0402_5% 4
2 1 2 1

2
C383 1U_0402_6.3V4Z R343 10K_0402_5% MIC1 3
1 6
2 MIC 1 2 2
30 MIC
1

1 L23 FBM-11-160808-700T_0603 1
W M-64PCY_2P 1
C395 FOX_JA6033L-5S3-TR
220P_0402_50V7K C377
SUSP# 22K 22K CD_PLAY 2 220P_0402_50V7K
16,26,34,36,37,41,47,48 SUSP# 2 2 CD_PLAY 22,34 2
22K 22K

Q36 Q32
3

4 4
DTC124EK_SOT23 DTC124EK_SOT23
SW DJ@

Compal Electronics, Inc.

Title
SCHEMATIC, M/B LA-2492
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401317
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. B
D ate: ¬P 期一, 一月 03, 2005 Sheet 32 of 51
A B C D E
 A B C D E

+3VS

SUPER I/O SMsC LPC47N217 LPC_A D[0..3]

18,34 LPC_AD[0..3]
1 1 1 1
+3VS C220 C236 C216 C227
4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
R224 1 2 2 2 2
2 10K_0402_5% S IO_PD# U18
LPC_AD0 10 62 RXD1
LAD0 RXD1 RXD1 37
R211 1 2 10K_0402_5% SIO_SMI# LPC_AD1 TXD1

SERIAL I/F
12 LAD1 TXD1 63 TXD1 37
LPC_AD2 13 64 D SR#1
LAD2 DSR1# DSR#1 37
1 R222 2 1 100K_0402_5% FIR_DET# LPC_AD3 14 1 RTS#1 1
LAD3 RTS1# RTS#1 37
2 CTS#1
CTS1# CTS#1 37
R223 2 1 100K_0402_5% BT_DET# LPC_FRAME# 15 3 DTR#1
18,34 LPC_FRAME# LFRAME# DTR1# DTR#1 37
LPC_DRQ#1 16 4 RI#1
18 LPC_DRQ#1 LDRQ# RI1# RI#1 37

LPC I/F
R543 2 1 100K_0402_5% LPT_DET# 5 DCD #1
DCD1# DCD#1 37
R545 1 2 0_0402_5% 17
R544 2 17,22,24,29,34 PCI_RST# PCI_RESET#
1 100K_0402_5% SERIAL_DET# R546 1 2 @ 0_0402_5% S IO_PD# 18 LPCPD# IRRX2 37 IRRX
IRRX 37
6,16,17,19,21,22,24,27,34 PLT_RST# FIR 38 IRTXOUT
IRTX2 IRTXOUT 37
R564 2 1 100K_0402_5% L CD_ID PM_CLKRUN# 19 39 IR MODE
19,29 PM_CLKRUN# CLKRUN# IRMODE/IRRX3 IRMODE 37
CLK _PCI_SIO 20 +3VS
14 CLK_PCI_SIO PCI_CLK
SERIRQ 21 41 INIT#
LCD ID : High -- EDID 19,24,34 SERIRQ
SIO_PME# 6
SER_IRQ INIT#
42 S LCTIN#
29,34 SIO_PME# IO_PME# SLCTIN#
44 LPD0
Low -- Panel ID PD0

2
CLK_SIO_14M 9 46 LPD1
14 CLK_14M_SIO CLK14 PD1 LPD2 R216
CLOCK PD2 47
L CD_ID 23 48 LPD3 @ 10K_0402_5%
16,17 L CD_ID GPIO40 PD3

PARALLEL I/F
24 49 LPD4
SIO_IRQ R208 2 GPIO41 PD4
1 10K_0402_5% 25 50 LPD5 Base I/O Address

1
GPIO42 PD5 LPD6
27 GPIO43 PD6 51
IRRX R204 1 2 10K_0402_5% FIR_DET# LPD7 0 *= 02Eh

GPIO
37 FIR_DET# 28 GPIO44 PD7 53
BT_DET# 29 55 LPTSLCT SIO_GPIO11 1 = 04Eh
17,35 BT_DET# LPT_DET# GPIO45 SLCT LPTPE
30 GPIO46 PE 56

2
SERIAL_DET# 31 57 L PTBUSY
38 SERIAL_DET# GPIO47 BUSY LPTACK# R219
32 GPIO10 ACK# 58
SIO_GPIO11 33 59 LPTERR# 1K_0402_5%
SIO_SMI# GPIO11/SYSOPT ERROR# LPTAFD#
34 GPIO12/IO_SMI# ALF# 60
SIO_IRQ 35 61 LPTSTB#

1
GPIO13/IRQIN1 STROBE#
36 GPIO14/IRQIN2
40 GPIO23
2 2
8 VSS VTR 7 +3V
CLK_SIO_14M CLK _PCI_SIO 22 11 1
VSS VCC
43 VSS POWER VCC 26
2

52 45 C222
R202
@ 10K_0402_5% R225
VSS VCC
VCC 54 +3VS 2
0.1U_0402_16V4Z Parallel Port
@ 10_0402_5% LPC47N217_STQFP64
+5V_PRN
1

1 1
C225
@ 15P_0402_50V8J C239 D24
@ 15P_0402_50V8J +5VS 2 1
2 2

1
L: R POP LPT Enable RB420D_SOT23
LPT Module H: R De-POP LPT Disable R37
2.2K_0402_5%

2
C411
LPT_DET# R551 1 2 1K_0402_5% 1 2

220P_0402_50V7K

JP5
R_LPTSTB# 1
AFD#/3M# 14
RP93 F D0 2
39 FD0
+5V_PRN 1 8 LPTSLCT_EMI LPTERR# 15
3 39 LPTERR# 3
2 7 LPTPE_EMI F D1 3
39 FD1
3 6 LPTBUSY_EMI LPTINIT# 16
4 5 LPTACK#_EMI F D2 4
39 FD2
LPTSLCT R610 1 2 33_0402_5% LPT@ LPTSLCT_EMI LPTSLCTIN# 17
LPTPE R611 1 2 33_0402_5% LPT@ LPTPE_EMI 2.7K_1206_8P4R_5% F D3 5
39 FD3
L PTBUSY R612 1 2 33_0402_5% LPT@ LPTBUSY_EMI RP5 18
LPTACK# R613 1 2 33_0402_5% LPT@ LPTACK#_EMI 1 8 AFD#/3M#_EMI F D4 6
39 FD4
2 7 LPTERR#_EMI 19
3 6 LPTINIT#_EMI F D5 7
39 FD5
AFD#/3M# R614 1 2 33_0402_5% LPT@ AFD#/3M#_EMI 4 5 LPTSLCTIN#_EMI 20
LPTERR# R615 1 2 33_0402_5% LPT@ LPTERR#_EMI F D6 8
39 FD6
Close to Docking LPTINIT# R616 1 2 33_0402_5% LPT@ LPTINIT#_EMI 2.7K_1206_8P4R_5% 21
LPTSLCTIN# R617 1 2 33_0402_5% LPT@ LPTSLCTIN#_EMI RP4 F D7 9
39 FD7
1 8 F D0_EMI 22
LPTSTB# R43 1 2 33_0402_5% R_LPTSTB# 2 7 F D1_EMI LPTACK# 10
R_LPTSTB# 39 39 LPTACK#
F D0 R618 1 2 33_0402_5% LPT@ F D0_EMI 3 6 F D2_EMI 23
LPTAFD# R36 1 2 33_0402_5% AFD#/3M# F D1 R619 1 2 33_0402_5% LPT@ F D1_EMI 4 5 F D3_EMI L PTBUSY 11
AFD#/3M# 39 39 LPTBUSY
F D2 R620 1 2 33_0402_5% LPT@ F D2_EMI 24
INIT# R22 1 2 33_0402_5% LPTINIT# F D3 R621 1 2 33_0402_5% LPT@ F D3_EMI 2.7K_1206_8P4R_5% LPTPE 12
LPTINIT# 39 39 LPTPE
RP1 25
S LCTIN# R35 1 2 33_0402_5% LPTSLCTIN# 1 8 F D7_EMI LPTSLCT 13
LPTSLCTIN# 39 39 LPTSLCT
F D7 R622 1 2 33_0402_5% LPT@ F D7_EMI 2 7 F D6_EMI
F D6 R623 1 2 33_0402_5% LPT@ F D6_EMI 3 6 F D5_EMI SUYIN_7313S-25G2T-AA

2
F D5 R624 1 2 33_0402_5% LPT@ F D5_EMI 4 5 F D4_EMI
RP3 F D4 R625 1 2 33_0402_5% LPT@ F D4_EMI L34
LPD0 1 8 F D0 2.7K_1206_8P4R_5% FBM-11-160808-121T_0603
LPD1 2 7 F D1
LPD2 3 6 F D2

1
LPD3 4 5 F D3
4

68_1206_8P4R_5%
EMI Request for LPT ISSUE 4

RP2
LPD7 4 5 F D7
LPD6 3 6 F D6 Compal Electronics, Inc.
LPD5 2 7 F D5 Title
LPD4 1 8 F D4 SCHEMATIC, M/B LA-2492
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
68_1206_8P4R_5% Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
401317 B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: ¬P 期一, 一月 03, 2005 Sheet 33 of 51
A B C D E
 5 4 3 2 1

+RTCVCC +3VALW
+3VALW
For EC Tools

2
KBA[0..19] R469 R199 JP27
KBA[0..19] 36 L29 Change to 0 ohm @ 0_0402_5% 0_0402_5%
1 1 +3VALW
ADB[0..7] 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1 2 2
ADB[0..7] 36 2
1 1 C215 1 1 2 2 FBM-L11-160808-800LMT_0603 3

1
C238 3
1 4 4
C206 C219 C241 C231 5
1000P_0402_50V7K 1000P_0402_50V7K C557 5
1 1 6 6
L16 2 2 2 2 1 1 C218 C217
7 7

ECAGND
ECAGND 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z E51_RXD
1 2 8 8
FBM-L11-160808-800LMT_0603 0.1U_0402_16V4Z 1U_0603_10V4Z 9 E51_TXD
2 2 9
D 10 10 D
KSI[0..7]
KSI[0..7] 35,38
@ 96212-1011S

123
136
157
166

161

159
KSO[0..15]

16
34
45

95

96
KSO[0..15] 35
U15
LPC_AD0 15

VCC
VCC
VCC
VCC
VCC
VCC
VCC

VCCA

AGND

VCCBAT

BATGND
18,33 LPC_AD0 LAD0
C577 LPC_AD1 14 49 KSO0
18,33 LPC_AD1 LAD1 GPOK0/KSO0
@ 22P_0402_50V8J LPC_AD2 13 50 KSO1
18,33 LPC_AD2 LAD2 GPOK1/KSO1
2 1 R482 2 1 @ 33_0402_5% LPC_AD3 10 51 KSO2 Analog Board ID definition,
18,33 LPC_AD3 LAD3 GPOK2/KSO2 KSO3
18,33 LPC_FRAME#
LRST#
9 LFRAME# LPC Interface GPOK3/KSO3 52
KSO4 Please see page 3.
165 LRST#/GPIO2C GPOK4/KSO4 53

ENE-KB910-B4
18 56 KSO5
14 CLK_PCI_LPC LCLK GPOK5/KSO5
7 57 KSO6 +3VALW
19,24,33 SERIRQ SERIRQ GPOK6/KSO6
DOCKIN# 25 58 KSO7
15,39 DOCKIN# CLKRUN#/GPIO0C * GPOK7/KSO7
24 59 KSO8
+3VALW LPCPD#/GPIO0B * GPOK8/KSO8 KSO9
GPOK9/KSO9 60

2
FR D# 150 61 KSO10
36 F RD# RD# GPOK10/KSO10
FW R# KSO11 R170

Internal Keyboard
36 FW R# 151 WR# GPOK11/KSO11 64
2

FSEL# 173 65 KSO12 Ra 100K_0402_5%

36 FSEL# MEMCS# GPOK12/KSO12
R205 SELIO# 152 66 KSO13
10K_0402_5% ADB0 IOCS# GPOK13/KSO13 KSO14
138 67

1
ADB1 D0 GPOK14/KSO14 KSO15 AD_BID0
139 D1 GPOK15/KSO15 68
ADB2 140 153
1

D2 GPOK16/KSO16

2
ADB3 141 154 KSO17 1
29,33 WLANPME# D3 GPOK17/KSO17 KSO17 38
ADB4 144 R168 C186
EC_PME# ADB5 D4 KSI0
29,33 LAN_PME# 145 D5 GPIK0/KSI0 71 EC_PLAYBTN# 35,38 Rb

X-BUS Interface
ADB6 146 72 KSI1 33K_0402_5% 0.1U_0402_16V4Z
D6 GPIK1/KSI1 EC_STOPBTN# 35,38 2
ADB7 147 73 KSI2
EC_REVBTN# 35,38

1
29,33 SIO_PME# KBA0 D7 GPIK2/KSI2 KSI3
124 A0 GPIK3/KSI3 74 EC_FRDBTN# 35,38
KBA1 125 77 KSI4
R478 1 0_0402_5% ENBKL KBA2 A1/XIOP_TP GPIK4/KSI4 KSI5
8,16 GMCH_ENBKL 2 126 A2 GPIK5/KSI5 78
KBA3 127 79 KSI6
C KBA4 A3 GPIK6/KSI6 KSI7 C
128 A4/DMRP_TP GPIK7/KSI7 80
R547 1 2 0_0402_5% LRST# KBA5 131
17,22,24,29,33 PCI_RST# KBA6 A5/EMWB_TP INVT_PWM +3VALW
132 A6 GPOW0/PWM0 32 INVT_PWM 16
R548 1 2 @ 0_0402_5% KBA7 133 33 BEEP#
7,19,21,22,24,27,33 PLT_RST# A7 GPOW1/PWM1 BEEP# 30
KBA8 143 36 PW R_SUSP_LED
A8 FAN2PWM/GPOW2/PWM2 PW R_SUSP_LED 38

2
KBA9 142 37 ACOFF
A9 GPOW3/PWM3 ACOFF 45
KBA10 135 Pulse Width GPOW4/PWM4 38 R479
KBA11 A10 EC_ON 10K_0402_5%
134 A11 GPOW5/PWM5 39 EC_ON 40
+3VALW +3VALW KBA12 130 40 EC_LID_OUT#
A12 GPOW6/PWM6 EC_LID_OUT# 19
SKU ID definition, SKU ID1 definition KBA13 129 43 EC_MUTE
EC_MUTE 32

1
KBA14 A13 FAN1PWM/GPOW7/PWM7 D33
121
Please see page 3. KBA15 120
A14
2 ON/O FF
A15 GPWU0 ON/OFF 40
2

KBA16 113 26 2 1
A16 GPWU1 AC IN 19,38,43
R183 R549 KBA17 112 29 KILL_SW#
A17 GPWU2 KILL_SW# 29,35,37
Rc 100K_0402_5% Re 100K_0402_5% KBA18 104 30 PM_SLP_S3#
A18 GPWU3 PM_SLP_S3# 19
KBA19 103 Wake Up Pin 44 PM_SLP_S5# CH751H-40_SC76
A19 GPWU4 PM_SLP_S5# 19
IE_BTN# 108 76 IDE_MRESET#
1

38 IE_BTN# A20/GPIO23 GPWU5 IDE_MRESET# 19

SKU_ID_CHECK_0 SKU_ID_CHECK_1 +3VALW 2 1 105 172 EC_PME#
R467 100K_0402_5% E51CS#/GPIO20/ISPEN TIN1/GPWU6 M ID2
TIN2/FANFB2/GPWU7 176 MID2 22
2

1 1 KB_CLK 110 2 1 ECAGND

39 KB_CLK PSCLK1
R184 C207 R550 C688 KB_DATA 111 81 BATT_TEMP C209 0.01U_0402_16V7K
39 KB_DATA PSDAT1 GPIAD0/AD0 BATT_TEMPA 44
Rd Rf PS_CLK 114 82 SKU_ID_CHECK_0
39 PS_CLK PSCLK2 GPIAD1/AD1
0_0402_5% 0.1U_0402_16V4Z @ 0_0402_5% 0.1U_0402_16V4Z PS_DATA BATT_AOVP
2 2 39 PS_DATA
TP_CLK
115 PSDAT2PS2 Interface GPIAD2/AD2 83
DPCONF_S5P
BATT_AOVP 45
116 84
1

35 TP_CLK PSCLK3 GPIAD3/AD3 DPCONF_S5P 39

TP_DATA 117 Analog To Digital 87 ALI/MH#
35 TP_DATA PSDAT3 GPIAD4/AD4 ALI/MH# 44
88 SKU_ID_CHECK_1
GPIAD5/AD5 SKU_ID_CHECK_1 38
EC_SMB_CK1 163 89 AD_BID0
In PWR Board 36,44 EC_SMB_CK1 SCL1 GPIAD6/AD6
EC_SMB_DA1 164 90 1 2
36,44 EC_SMB_DA1 SDA1 GPIAD7/AD7 100K_0402_5% ADP_I 45
+5VS EC_SMB_CK2 169 SMBus R169
4,30,39 EC_SMB_CK2 SCL2
RP81 EC_SMB_DA2 170 99 DAC_BRIG 1 2
4,30,39 EC_SMB_DA2 SDA2 GPODA0/DA0 DAC_BRIG 16
1 8 KB_CLK 100 BT_PWR C185 0.22U_0402_10V4Z
GPODA1/DA1 BT_PWR 35
B 2 7 KB_DATA DKN_B+_ON 8 101 IR EF B
45 DKN_B+_ON GPIO04 GPODA2/DA2 IR EF 45
3 6 PS_CLK EC_SCI# 20 102 EN_DFAN1#
19 EC_SCI# GPIO07 GPODA3/DA3 EN_DFAN1 37
4 5 PS_DATA BT_RST# 21 Digital To Analog 1 CD_PLAY
35 BT_RST# GPIO08 GPODA4/DA4 CD_PLAY 22,32
BT_WAKE_UP 22 42 PM_BATLOW# CRY11 R476 2 CRY2
35 BT_WAKE_UP GPIO09 GPODA5/DA5
4.7K_0804_8P4R_5% ENBKL 27 47 EC_IDERST @ 20M_0603_5%
GPIO0D GPODA6/DA6 EC_IDERST 21,30

2
+3VALW BKOFF# 28 174 AUD_SUDMUT_P3#
16 BKOFF# GPIO0E GPODA7/DA7 AUD_SUDMUT_P3# 39
RP84 FSTCHG 48 R475
45 FSTCHG GPIO10
1 8 MODE# EC_SMI# 62 85 PW R_LED#
19 EC_SMI# GPIO13 *GPIO18/XIO8CS# PW R_LED# 38
2 7 FR D# 63 86 W L_BT_LED# 0_0402_5%
22 MODULE_RST# GPIO14 *GPIO19/XIO9CS# W L_BT_LED# 38
3 6 SELIO# 69 91 HDD_LED#
29 W L_OFF# HDD_LED# 38

1
FSEL# GPIO15 *GPIO1A/XIOACS# BATT_LOW_LED#
4 5 19 EC_SW I# 70 GPIO16 GPIO *GPIO1B/XIOBCS# 92 BATT_LOW_LED# 38
75 Expanded I/O * GPIO1C/XIOCCS# 93 BATT_CHGI_LED#
40 S4_LATCH GPIO17 BATT_CHGI_LED# 38
10K_0804_8P4R_5% 109 94 ODD_LED# 1 1
+5VALW 40 S4_SATA GPIO24 *GPIO1D/XIODCS# MODE_LED# 38
LID_SW # 118 97 M ID1 C576 C575
38 LID_SW # GPIO25 *GPIO1E/XIOECS# MID1 22

4
RP86 MODE# 119 98 M ID0
38 MODE# GPIO26 * GPIO1F/XIOFCS# MID0 22

10P_0402_50V8J

10P_0402_50V8J
1 8 EC_SMB_CK1 SYSON 148 X1

IN

OUT
30,38,40,41,47 SYSON GPIO27 2 2
2 7 EC_SMB_DA1 SUSP# 149 171 FAN_SPEED1
16,26,32,36,37,41,47,48 SUSP# GPIO28 GPIO2E/TOUT1/FANFB1 FAN_SPEED1 37
3 6 EC_SMB_CK2 VR_ON 155 12 DPLL_TP
49 VR_ON GPIO29 DPLL_TP/GPIO06/FANFB3 1394_PHYRST_S3P 39
4 5 EC_SMB_DA2 EJCTSW# 156 FANTEST_TP/GPIO05/FAN3PWM 11 TEST_TP
39 EJCTSW# GPIO2A 1394_DILSON_S3P 39
BT_DETACH

NC

NC
35 BT_DETACH 162 GPIO2B
4.7K_0804_8P4R_5% PBTN_OUT# 168 175 EC_THERM#
19 PBTN_OUT# GPIO2D EC_THERM# 19
Timer PinTOUT2/GPIO2F

3
PADS_LED# 55 3
35 PADS_LED# FnLock#/GPIO12* E51IT0/GPIO00 EC_RSMRST# 19
C578 0.1U_0402_16V4Z CAPS_LED# 54 4 SHDD_LED#
+5VS 35 CAPS_LED# CapLock#/GPIO011* E51IT1/GPIO01 SHDD_LED# 22
2 1 NUM_LED# 23 106 E51_RXD 1 2
35 NUM_LED# NumLock#/GPIO0A * E51RXD/GPIO21/ISPCLK EAPD 30,32
41 107 E51_TXD R587 0_0402_5%
18 PHDD_LED# ScrollLock#/GPIO0F * E51TXD/GPIO22/ISPDAT
2 1 TP_CLK +3VALW 2 1 19 ECRST# MISC CRY2 32.768KHZ_12.5P_1TJS125DJ2A073
4.7K_0402_5% R172 R480 47K_0402_5% 5 158 R474 1 2 @ 0_0402_5% RTC_CLK
18 EC_GA20 GA20/GPIO02 XCLKI RTC_CLK 19
2 1 TP_DATA 18 EC_KBRST# 6 KBRST#/GPIO03 XCLKO 160 CRY1
4.7K_0402_5% R171 31
GND
GND
GND
GND
GND
GND

ECSCI#
D38
A A
KB910Q B4_LQFP176 3
17
35
46
122
137
167

1 2 ENBKL 1
+3VALW R481 @ 120K_0402_5% CD_PLAY 2

2 1 KBA1 1 2 DPCONF_S5P
1K_0402_5% R175 R178 470_0402_5% PSOT24C_SOT23
2 1 KBA4
1K_0402_5% R174 1 2 DPLL_TP Compal Electronics, Inc.
2 1 KBA5 R229 1K_0402_5% Title
1K_0402_5% R173 SCHEMATIC, M/B LA-2492
2 1 EJCTSW# 1 2 TEST_TP PROPRIETARY NOTE THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
100K_0402_5% R473 R228 1K_0402_5% TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE 401317 B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: 星期一, 一月 03, 2005 Sheet 34 of 51
5 4 3 2 1
 +3V +3VS_MDC +5VS_MDC
BlueTooth Interface
1 1 1
C253 C248 C593
MDC CONN. 2
1U_0805_25V4Z
2
1U_0805_25V4Z
2
1U_0805_25V4Z
+5VS +3VS
JP30

2
1 MONO_OUT/PC_BEEP AUDIO_PWRDN/DETECH 2
3 4 R116 C142
GND MONO_PHONE 100K_0402_5% 0.1U_0402_16V4Z
5 AUXA_RIGHT RESERVED/BT_ON# 6
7 AUXA_LEFT GND 8 Change to 0 ohm

3
9 10 +5VS_MDC 1 2 +5VS

1
CD_GND +5Vmain L32 CHB1608B121_0603
11 CD_RIGHT RESERVED/USB+ 12 2
R241 13 14 Q12
0_0402_5% CD_LEFT RESERVED/USB- SI2301DS-T1_SOT23
15 GND RESERVED/PRIMARY_DN 16 1 2 +3VS

1
1 2 17 18 R488 10K_0402_5% C151
+3V +3.3Vaux/BT_VCC RESERVED/+5VD/WAKEUP
Change to 0 ohm 19 20

1
GND RESERVED/GND
+3VS 1 2 +3VS_MDC 21 +3.3Vmain AC97_SYNC 22 IC H _AC_SYNC 18,30
0.1U_0402_16V4Z
+BT_VCC
L17 CHB1608B121_0603 23 24 1 2 0_0402_5%
18,30 ICH_AC_SDOUT AC97_SDATA_OUT AC97_SDATA_IN1 22K
18,30 ICH_AC_RST# 25 26 R487 1 2 2
AC97_RESET# AC97_SDATA_IN0 R486 22_0402_5% ICH_AC_SDIN1 18 34 BT_PWR C141
27 GND GND 28
Q13
29 AC97_MSTRCLK AC97_BITCLK 30 1 2 ICH_AC_BITCLK 18,30
R485 22_0402_5% 22K 10U_1206_16V4Z
DTC124EK_SOT23

3
ACES_88018-3010

+12VALW

TP CONN. +5VS
Module ID
Indication for polarity of reset

2
+5VS_TP Reset input High Active --> Low ,
R605 Reset input Low Active --> Open
100K_0402_5%

C168 0.1U_0402_16V4Z

1
0.1U_0402_16V4Z C Q67
2
B
E MMBT3904_SOT23 +3VS

3
1

1
D C C245
JP15

2
2 C690 2 @ 0.1U_0402_16V4Z
41,48 SUSP B
TP_DATA G R606
8 7 TP_DATA 34 E Q68
TP_CLK S
34 TP_CLK

3
6 5

2
S P_GROND S P_Y Q63
4 3

5
SP_X SP_VCC MMBT3904_SOT23 R607 U19

1
2 1 2N7002_SOT23 10_0402_5% 1

P
29,34,37 KILL_SW# B
4 BT_RESET#
ACES_87153-0801-01 +5VS_TP +5VS Y
R608 34 BT_RST# 2

1
A

G
+5VS_TP 2 1 @ TC7SH08FU_SSOP5

3
100K_0402_5% @ 0_0603_5%

JP32
1 2
R226 0_0402_5%
TP_DATA 8 7 TP_DATA C671
TP_CLK 6
4
5
3
TP_CLK 0.1U_0402_16V4Z INT_KBD CONN.
2 1 JP14
ACES_87153-0801-01
37 38
34 JP13
NUM_LED# 34
34 PADS_LED# 33
32 ACES_87153-2008
CAPS_LED# 34
+3VS 2 1 31 20
R140 300_0402_5% 30 KSO15 Module ID
KSO14 Module_Detect 19
29 17,33 BT_DET# 18
28 KSO10
KSI[0..7] KSO11 17
KSI[0..7] 34,38 27 16
26 KSO8
KS O[0..15] KSO9 15
KSO[0..15] 34 25 14
24 KSO13 BT_RESET#
K SI7 BT_WAKE_UP 13
23 34 BT_WAKE_UP 12
22 KSO3
KSO7 C625 100P_0402_25V8K KSO15 C613 100P_0402_25V8K KSO7 11
21 10
20 KSO12
KSO6 C626 100P_0402_25V8K KSO14 C614 100P_0402_25V8K K SI4 9
19 34 BT_DETACH 8
18 K SI6
KSO5 C627 100P_0402_25V8K KSO13 C615 100P_0402_25V8K K SI5 7
17 6
16 KSO6 USB20_P5
19 USB20_P5 5
KSO4 C628 100P_0402_25V8K KSO12 C616 100P_0402_25V8K KSO5 15 USB20_N5
19 USB20_N5 4
14 K SI3
KSO3 C629 100P_0402_25V8K K SI0 C617 100P_0402_25V8K K SI0 3
13 2
12 KSO0 +BT_VCC
K SI4 C630 100P_0402_25V8K KSO11 C618 100P_0402_25V8K KSO1 1
11
10 K SI1 (MAX=200mA)
KSO2 C631 100P_0402_25V8K KSO10 C619 100P_0402_25V8K K SI2 9 C140
8 KSO2 (Top Contact)
KSO1 C632 100P_0402_25V8K K SI1 C620 100P_0402_25V8K KSO4 7 0.1U_0402_16V4Z
6 1 2 +3VS Bluetooth Connector
KSO0 C633 100P_0402_25V8K K SI2 C621 100P_0402_25V8K SP_VCC 5 300_0402_5% R559
4 SP_X
K SI5 C634 100P_0402_25V8K KSO9 C622 100P_0402_25V8K S P_GROND 3 PVT Reverse for FFC change
2 S P_Y
K SI6 C635 100P_0402_25V8K K SI3 C623 100P_0402_25V8K +3VS 2 1 1
R560 300_0402_5% 35 36
K SI7 C636 100P_0402_25V8K PADS_LED# C682 100P_0402_25V8K
ACES_88172-3400
KSO8 C624 100P_0402_25V8K NUM_LED# C683 100P_0402_25V8K

CAPS_LED# C684 100P_0402_25V8K

Compal Electronics, Inc.
Title
SCHEMATIC, M/B LA-2492
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
401317 B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: ¬P 期一, 一月 03, 2005 Sheet 35 of 51
 +3VALW +3VALW
C214
SB_INT_FLASH_SEL# 19

1
1 2 R192
100K_0402_5%

13
SUSP# 16,26,32,34,37,41,47,48
0.1U_0402_16V4Z U10D

2
G

OE#
5
U14 INT_FLASH_SEL 11 12 SUS_STAT# 19

2
O I
2 1 3

P
I0 EC_FLASH# 19
FWE# 4

S
O @ SN74LVC125APWLE_TSSOP14
I1 1

G
Q23
TC7SH32FU_SSOP5 2N7002_SOT23

3
FW R# 34

+3VALW

C644 1 2 @ 0.1U_0402_16V4Z

2
R529
@ 10K_0402_5% INT_FLASH_EN# R527 1 2

@ 100K_0402_5%

10
+5VALW +5VALW U10C

OE#
INT_FSEL# R528 1 2 @ 22_0402_5% 8 9
O I FSEL# 34

1
R164
C187 1 2 0.1U_0402_16V4Z
100K_0402_5% @ SN74LVC125APWLE_TSSOP14
2

1 2
U11
8 1 R592 0_0402_5%
VCC A0
7 WP A1 2
34,44 EC_SMB_CK1 6 SCL A2 3
34,44 EC_SMB_DA1 5 SDA GND 4

AT24C16N10SC-2.7_SO8
1

R167

100K_0402_5%
2

KB A[0..19]
34 KBA[0..19]
ADB[0 ..7]
34 ADB[0..7]

1MB ROM Socket

1MB Flash ROM JP17
+3VALW KBA16 KBA17
KBA15 1 2
U16
KBA14 3 4
KBA0 KBA13 5 6 KBA19
21 A0 VCC0 31 7 8
KBA1 20 30 1 KBA12 KBA10
KBA2 A1 VCC1 C188 KBA11 9 10 ADB7
19 A2 11 12
KBA3 18 KBA9 ADB6
KBA4 A3 ADB0 0.1U_0402_16V4Z KBA8 13 14 ADB5
17 A4 D0 25 15 16
KBA5 ADB1 2 FWE# ADB4
16 A5 D1 26 17 18
KBA6 15 27 ADB2 RESET# +3VALW
KBA7 A6 D2 ADB3 INT_FLASH_EN# 19 20
14 A7 D3 28 21 22
KBA8 8 32 ADB4 INT_FLASH_SEL
KBA9 A8 D4 ADB5 KBA18 23 24 ADB3
7 A9 D5 33 25 26
KBA10 36 34 ADB6 KBA7 ADB2
KBA11 A10 D6 ADB7 KBA6 27 28 ADB1
6 A11 D7 35 29 30
KBA12 5 KBA5 ADB0
KBA13 A12 KBA4 31 32 F RD#
4 A13 33 34
KBA14 3 10 RESET# 1 2 +3VALW KBA3
KBA15 A14 RP# R212 100K_0402_5% KBA2 35 36 FSEL#
2 A15 NC 11 37 38
KBA16 1 12 KBA1 KBA0
KBA17 A16 READY/BUSY# 39 40
40 A17 NC0 29
KBA18 13 38 @ SUYIN_80065AR-040G2T
KBA19 A18 NC1
37 A19
INT_FSEL# 22
F RD# CE#
34 F RD# 24 OE# GND0 23
FWE# 9 39
WE# GND1

SST39VF080-70_TSOP40 Compal Electronics, Inc.

Title
SCHEMATIC, M/B LA-2492
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401317
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: ¬P 期一, 一月 03, 2005 Sheet 36 of 51
 Close to Docking +3V
Kill SWITCH
2
+3V
C153
0.1U_0402_16V4Z
1

26
3

2
U7
+3V 2 28

VCC
D7 C1+
V+ 27 2 1
DAN217_SOT23 C148 C154 0.1U_0402_16V4Z

2
0.1U_0402_16V4Z 24
1 C1-
2 1 3 2 1

1
R160 C2+ V- C146 0.1U_0402_16V4Z
100K_0402_5% C143
0.1U_0402_16V4Z 2

1
1 C2- DTR#
33 DTR#1 14 TIN1 TOUT1 9 DTR# 38,39
KILL_SW# 13 10 RTS#
KILL_SW# 29,34,35 33 RTS#1 TIN2 TOUT2 RTS# 38,39
12 11 TXD
33 TXD1 TIN3 TOUT3 TXD 38,39
1

19 4 CTS#
33 CTS#1 ROUT1 RIN1 CTS# 38,39
18 5 R I#
1

33 RI#1 ROUT2 RIN2 R I# 38,39

17 6 RXD
33 RXD1 ROUT3 RIN3 RXD 38,39
16 7 D CD#
33 DCD#1 ROUT4 RIN4 D C D# 38,39
SW1 1BS003-1211L_3P 15 8 DS R#
33 DSR#1 ROUT5 RIN5 DSR# 38,39
20 ROUTB2
INVLD# 21
16,26,32,34,36,41,47,48 SUSP# 23 FORCEON
GND 25
22 FORCEOFF#
MAX3243CAI_SSOP28

FAN Conn No Docking and Serial Port -----> Del

+12VALW +5VS

1 2
C522
0.1U_0402_16V4Z
8

1
P

1
EN_ DFAN1 3 C Q46 D3 C108
34 EN_DFAN1 +IN
1 E N_FAN1 1 2 2 FMMT619_SOT23 1SS355_SOD323 10U_1206_16V4Z

2
OUT B
2 1 2 -IN R441 2 E
3

2
G

R435 U37A 100_0402_5%

10K_0402_5% LM358A_SO8 C523 FA N1 L: R POP; FIR Enable
FIR Module
4

@ 0.1U_0402_16V4Z JP12 H: R De-POPFIR Disable

1

1
D26 3
1N4148_SOT23 2
1 2 1
R440 8.2K_0402_5%
ACES_85205-0300
2

FIR_DET# R220 1 2 1K_0402_5%

33 FIR_DET#

+3VS R88 1 2 10K_0402_5%

34 FAN_SPEED1 +IR_ANODE
2 2 +3VS

C107 C106 (60mil) R366 @ 4.7_1206_5%

@ 1000P_0402_50V7K @ 1000P_0402_50V7K +3VS 1 2
1 1
1
1 2 (60mil)
C385 R365 4.7_1206_5%

2
1 22U_1206_16V4Z_V1
2
C396 R368 IR 1
@ 10U_0805_10V4Z 0_1206_5% 1
2 IRED_A IRTXOUT
2 3 IRTXOUT 33

1
IRRX IRED_C TXD IR MODE
33 IRRX 4 RXD SD/MODE 5 IRMODE 33
+IR_3VS 6 7
(30mil) VCC MODE
8 GND GND 9
1 1
HSDL-3603-007_9P
C401 C402
10U_1206_16V4Z 0.1U_0402_16V4Z
2 2
SD/MODE: SHUTDOWN MODE, HIGH ACTIVE
MODE: HIGH/LOW SPEED SELECT

Compal Electronics, Inc.

Title
SCHEMATIC, M/B LA-2492
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401317
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: ¬P 期一, 一月 03, 2005 Sheet 37 of 51
 5 4 3 2 1

RJ45 / Serial Board Conn. Power / LED Board Conn.

+3VALW JP4
JP3
1 13 SKU _ID_CHECK_1
34 SKU_ID_CHECK_1 1 13
30 15 LAN _ACTIVITY# 2 14 KSO17 C672 1 2 220P_0402_50V7K
30 15 LAN_ACTIVITY# 27,39 34 KSO17 2 14
USB20_N7 29 14 L AN_LINK# ON /OFFBTN# 3 15 ON /OFFBTN# C673 1 2 220P_0402_50V7K
19 USB20_N7 29 14 LAN_LINK# 27,39 40 ON/OFFBTN# 3 15
USB20_P7 28 13 PW R_LED_1# 4 16 PW R_LED_1# C674 1 2 220P_0402_50V7K
19 USB20_P7 28 13 4 16
DTR# 27 12 RJ4 5_GND PW R_SUSPLED# 5 17 PW R_SUSPLED# C675 1 2 220P_0402_50V7K
37,39 DTR# 27 12 RJ45_GND 28,39 5 17
RTS# 26 11 RJ45_MDI3+ IEBTN# 6 18 IEBTN# C676 1 2 220P_0402_50V7K
37,39 RTS# 26 11 RJ45_MDI3+ 28,39 6 18
TXD 25 10 RJ45_MDI3- MODEBTN# 7 19 MODEBTN# C677 1 2 220P_0402_50V7K
37,39 TXD 25 10 RJ45_MDI3- 28,39 7 19
CTS# 24 9 RJ4 5_GND EC_REVBTN# 8 20 EC_REVBTN# C678 1 2 220P_0402_50V7K
37,39 CTS# 24 9 34,35 EC_REVBTN# 8 20
D R I# 23 8 RJ45_MDI2+ E C_FRDBTN# 9 21 E C_FRDBTN# C679 1 2 220P_0402_50V7K D
37,39 R I# 23 8 RJ45_MDI2+ 28,39 34,35 EC_FRDBTN# 9 21
RXD 22 7 RJ45_MDI2- EC_PLAYBTN# 10 22 EC_PLAYBTN# C680 1 2 220P_0402_50V7K
37,39 RXD 22 7 RJ45_MDI2- 28,39 34,35 EC_PLAYBTN# 10 22
D CD# 21 6 RJ4 5_GND EC_STOPBTN# 11 23 EC_STOPBTN# C681 1 2 220P_0402_50V7K
37,39 D C D# 21 6 34,35 EC_STOPBTN# 11 23
DS R# 20 5 RJ45_MDI1+ 12 24
37,39 DSR# 20 5 RJ45_MDI1+ 28,39 12 24
SYSON# 19 4 RJ45_MDI1-
19 4 RJ45_MDI1- 28,39
+5VALW 18 3 RJ4 5_GND ACES_85203-1202
18 3 RJ45_MDI0+
33 SERIAL_DET# 17 17 2 2 RJ45_MDI0+ 28,39
16 1 RJ45_MDI0-
16 1 RJ45_MDI0- 28,39
1 C693 1 C692
ACES_87216-3002

680P_0402_50V7K
2 2
680P_0402_50V7K PW R_LED_0#
D17 POWER/ON LED
2 1

HT-191NB_BLUE_0603
+3VALW
2 MODE# 34
MODEBTN# 1
3 51ON# D35
51ON# 40,43
S Y SON PW R_SUSPLED_1# 2 1
POWER/SUSP LED
3

D31
2

47K DAN202U_SC70 HT-191UD_AMBER_0603

G

2 1 3 PW R_SUSP_LED
10K PW R_SUSP_LED 34
D

Q66
2N7002_SOT23
Q52 +3VALW +5VALW
C DTA114YKA_SC59 AC IN LED C
1

D18

2
1 2 2 1
R530 1 2 300_0402_5% PW R_SUSPLED# R531 R364 120_0402_5%
100K_0402_5% HT-191NB_BLUE_0603

1
D
2N7002_SOT23
19,34,43 A C IN 2

1
R609 1 2 300_0402_5% PW R_SUSPLED_1# G Q40
2 IE_BTN# 34 S

3
IEBTN# 1
3 51ON#
+5VALW
D16
D30
USB Board Conn. DAN202U_SC70
1 2 2 1 BATT_LOWLED# BATTERY CHG
+5VALW R374 120_0402_5%

JP16 1 2 3 4 BATT_CHGILED#
1 16 R561 120_0402_5%
1 16 USB20_N0 19
2 2 17 17 USB20_P0 19
3 3 18 18 HT-297UD/NB_BLUE/AMB_0603
4 4 19 19 USB20_N2 19
5 20 100K_0402_5% 1 2 R185 +3VALW
5 20 USB20_P2 19
SYSON# 6 21
41
19
SYSON#
USB_OC#0 7
6
7
21
22 22 USB20_N4 19
+5VS
D20
HDD LED
19 USB_OC#2 8 8 23 23 USB20_P4 19
9 24 2 LID_SW # 1 2 2 1
19 USB_OC#4 9 24 LID_SW # 34 HDD_LED# 34
10 25 L ID 1 R375 120_0402_5%
NBA_PLUG 10 25 HT-191NB_BLUE_0603
30,32 NBA_PLUG 11 11 26 26 3 S4_LID_SW# 40
B VOL_AMP B
32 VOL_AMP 12 12 27 27 RTCVREF
13 28 D8
14
13
14
28
29 29
+5VCD
DAN202U_SC70 +5VS
D19
MODE LED
15 15 30 30
1 2 2 1 MODE_LED# 34
ACES_87216-3002 R376 120_0402_5%
HT-191NB_BLUE_0603

+3VALW
D15
WL LED
+5VS 1 2 2 1 WL_BT_LED# 34
R370 300_0402_5%
BATTERY CHGI/LOW LED HT-110UD_1204

S Y SON
S YSON 30,34,40,41,47
BATT_CHGILED# BATT_LOWLED#
3

+5VS
2

47K D34
G
1

1 2 2 1
200_0402_5% 200_0402_5%
10K
2 1 3 PW R_LED# PW R_LED# 34
R293 120_0402_5%
HT-110UD_1204
5IN1 LED
D

1
R163 R471 Q65 D
2N7002_SOT23 2N7002_SOT23
24,25 5IN1_LED 2
1 2

1 2

Q57 G Q55
DTA114YKA_SC59 S
1

3
A A
100K 100K
34 BATT_CHGI_LED# BATT_CHGI_LED# 2 2 BATT_LOW_LED# BATT_LOW_LED# 34 R532 1 2 300_0402_5% PW R_LED_0#

DTC115EKA_SOT23 100K 100K DTC115EKA_SOT23 R533 1 2 300_0402_5% PW R_LED_1#

Q20 Q51
Compal Electronics, Inc.
3

Title
SCHEMATIC, M/B LA-2492
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401317
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: ¬P 期一, 一月 03, 2005 Sheet 38 of 51
5 4 3 2 1
 A B C D E

+3VALW +3VALW +3VALW

1
C11 2 1 0.1U_0402_16V4Z R574
D @ 100K_0402_5%

5
U2
R13 2 1 10K_0402_5% DCOCT1# 2

2
I0 DOCKIN#
4
Docking Conn. R17 1 2 10K_0402_5% DCOCT2# 1 I1
O DOCKIN# 15,34

G
JP23A TC7SH32FU_SSOP5 JP23B

3
1 245 GND GND 247 249 GND GND 251 1
246 GND GND 248 250 GND GND 252

+DC_IN_S1 241 VCC VCC 242 +DC_IN_S1 243 VCC VCC 244

DKN_B+ 1 S1 S61 61 DKN_B+ DKN_B+ 121 S121 S181 181 DNK_B+

2 S2 S62 62 122 S122 S182 182
DCOCT1# 3 63 EJCTSW# D_EC_SMB_CK2 123 183 D_EC_SMB_DA2
S3 S63 EJCTSW# 34 S123 S183
+5VS 4 S4 S64 64 +5VS +5VS 124 S124 S184 184 +5VS
PS_CLK 5 65 PS_DATA +5VALW 125 185
34 PS_CLK S5 S65 PS_DATA 34 S125 S185
KB_CLK 6 66 KB_DATA KB_DATA 34 TPA1+ 126 186 TPA1-
34 KB_CLK S6 S66 24 TPA1+ S126 S186 TPA1- 24
7 S7 S67 67 127 S127 S187 187
1394_PHYRST_S3P 8 68 TPB1+ 128 188 TPB1-
34 1394_PHYRST_S3P S8 S68 24 TPB1+ S128 S188 TPB1- 24
D PCONF_S5P 9 69 1394_DILSON_S3P 129 189 USBDP1-S3P
34 DPCONF_S5P S9 S69 1394_DILSON_S3P 34 S129 S189 USB20_P6 19
10 70 130 190 USBDP1-S3N
S10 S70 S130 S190 USB20_N6 19
11 S11 S71 71 131 S131 S191 191
CRT_CRTSC-P3P 12 72 CRT_CRTSD-P3P 132 192
15 D_DDC_CLK S12 S72 D_DDC_DATA 15 S132 S192
CRT_CRE D-PYP 13 73 133 193
15 D_CRT_R S13 S73 S133 S193
CRT_C GREEN-PYP 14 74 Pin 73, 74 and 75 for VGA GND AUD_SUDMUT_P3# 134 194 LINE OR
15 D_CRT_G S14 S74 34 AUD_SUDMUT_P3# S134 S194 LINEOR 31
CRT _CBLUE-PYP 15 75 135 195 LIN EOR#
15 D_CRT_B S15 S75 S135 S195 LINEOR# 31
CRT_C VSYNC-P5P 16 76 CRT_CHS YNC-P5P LINEOL 136 196 L INEOL#
15 D_CRT_VSYNC S16 S76 D_CRT_HSYNC 15 31 LINEOL S136 S196 LINEOL# 31
DV I_SCLK 17 77 DVI_SDATA LINEIL 137 197 LINE IL#
16 DVI_SCLK S17 S77 DVI_SDATA 16 31 LINEIL S137 S197 LINEIL# 31
18 78 LINEIR# 138 198 L I NEIR
S18 S78 31 L INEIR# S138 S198 L INEIR 31
19 S19 S79 79 139 S139 S199 199
20 80 DVI_TXD5+ DO CK_ON/OFFBTN# 140 200 RXD
S20 S80 DVI_TXD5+ 40 DOCK_ON/OFFBTN# S140 S200 RXD 37,38
21 81 DVI_TXD5- D CD# 141 201 RTS#
S21 S81 DVI_TXD5- 37,38 D CD# S141 S201 RTS# 37,38
DVI_TXD2+ 22 82 DVI_TXD4+ DS R# 142 202 CTS#
16 DVI_TXD2+ S22 S82 DVI_TXD4+ 37,38 DSR# S142 S202 CTS# 37,38
DVI_TXD2- 23 83 DVI_TXD4- TXD 143 203 DTR#
16 DVI_TXD2- S23 S83 DVI_TXD4- 37,38 TXD S143 S203 DTR# 37,38
2 DVI_TXD1+ 24 84 DVI_TXD3+ R I# 144 204 LPTSLCT 2
16 DVI_TXD1+ S24 S84 DVI_TXD3+ 37,38 R I# S144 S204 LPTSLCT 33
DVI_TXD1- 25 85 DVI_TXD3- LPTPE 145 205 L PTBUSY
16 DVI_TXD1- S25 S85 DVI_TXD3- 33 LPTPE S145 S205 LPTBUSY 33
DVI_TXD0+ 26 86 F D7 146 206 LPTACK#
16 DVI_TXD0+ S26 S86 33 F D7 S146 S206 LPTACK# 33
DVI_TXD0- 27 87 F D6 147 207 F D5
16 DVI_TXD0- S27 S87 33 F D6 S147 S207 FD5 33
28 S28 S88 88 148 S148 S208 208
29 S29 S89 89 149 S149 S209 209
DVI_TXC+ 30 90 F D4 150 210 F D3
16 DVI_TXC+ S30 S90 33 F D4 S150 S210 FD3 33
DVI_TXC- 31 91 F D1 151 211 LPTSLCTIN#
16 DVI_TXC- S31 S91 33 F D1 S151 S211 LPTSLCTIN# 33
D VI_DET 32 92 F D2 152 212 LPTINIT#
16 DVI_DET S32 S92 33 F D2 S152 S212 LPTINIT# 33
33 93 F D0 153 213 LPTERR#
S33 S93 33 F D0 S153 S213 LPTERR# 33
34 94 R_LPTSTB# 154 214 AFD#/3M#
S34 S94 33 R_LPTSTB# S154 S214 AFD#/3M# 33
35 S35 S95 95 155 S155 S215 215
36 S36 S96 96 156 S156 S216 216
37 S37 S97 97 157 S157 S217 217
38 S38 S98 98 158 S158 S218 218
39 S39 S99 99 159 S159 S219 219
40 S40 S100 100 160 S160 S220 220
41 S41 S101 101 161 S161 S221 221
42 S42 S102 102 162 S162 S222 222
43 S43 S103 103 163 S163 S223 223
44 S44 S104 104 164 S164 S224 224
45 S45 S105 105 165 S165 S225 225
46 S46 S106 106 166 S166 S226 226
47 S47 S107 107 167 S167 S227 227
48 S48 S108 108 168 S168 S228 228
49 S49 S109 109 169 S169 S229 229
50 S50 S110 110 170 S170 S230 230
51 S51 S111 111 171 S171 S231 231
52 S52 S112 112 172 S172 S232 232
3 3
173 S173 S233 233
234 LAN _ACTIVITY#
S234 LAN_ACTIVITY# 27,38
RJ45_MDI3+ 55 115 RJ45_MDI2- +3VALW 175 235 L AN_LINK#
28,38 RJ45_MDI3+ S55 S115 RJ45_MDI2- 28,38 S175 S235 LAN_LINK# 27,38
RJ45_MDI3- 56 236 DCOCT2#
28,38 RJ45_MDI3- S56 S236
117 RJ45_MDI2+
S117 RJ45_MDI2+ 28,38 LAN
RJ4 5_GND 178
28,38 RJ45_GND L178
MDC1 _RING 59 RJ45_MDI0+ 179 239 RJ45_MDI1+
M59 MODEM 28,38 RJ45_MDI0+ L179 L239 RJ45_MDI1+ 28,38
MDC2_TIP 60 RJ45_MDI0- 180 240 RJ45_MDI1-
M60 28,38 RJ45_MDI0- L180 L240 RJ45_MDI1- 28,38

253 GND GND 254

+5VALW +3VALW
2

TYCO_1674036 TYCO_1674036
R15
100K_0402_5%
2
G
1

1 3 Q3 1394_DILSON_S3P
2N7002_SOT23
D

MDC to Docking Conn. 1 2 +5VALW

2
G

R16 4.7K_0402_5%

JP2 3 1 D_EC_SMB_CK2
4,30,34 EC_SMB_CK2
S

1 1
2 Q5
MDC1 _RING 2 2N7002_SOT23
4 3 3 1 2 +5VALW 4
2
G

MDC2_TIP 4 R14 4.7K_0402_5%

4
ACES_85205-0400 3 1 D_EC_SMB_DA2
4,30,34 EC_SMB_DA2
S

Q4
2N7002_SOT23
Compal Electronics, Inc.
Title
SCHEMATIC, M/B LA-2492
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401317
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: ¬P 期一, 一月 03, 2005 Sheet 39 of 51
A B C D E
 A B C D E

TOP Side +3VALW

J2
2 1
JOPEN Power Button RTC Battery

2
J3
2 1
JOPEN
R468 - BATT1 + +RTCBATT

Button Side 100K_0402_5% 2 1 +RTCBATT

1 1

1
D29
2 O N/OFF 34
ON /OFFBTN# 1 RTCBATT
38 ON/OFFBTN#

1
3 51ON#
51ON# 38,43
D28
RTCVREF DAN202U_SC70
BAS40-04_SOT23
+RTCVCC

2
2

2
R593 R594
+CHGRTC
1
D@ 100K_0402_5% D@ 100K_0402_5%
C558
1

2 1
0.1U_0402_16V4Z
G 2

39 DOCK_ON/OFFBTN# 3 1
Q61
S

D @ 2N7002_SOT23

1 2

R595 0_0402_5%

1
2 D27
2 2
C556
1000P_0402_50V7K
+3VALW 1 RLZ20A_LL34

2
RTCVREF RTCVREF RTCVREF RTCVREF
2

R466
4.7K_0402_5%

1
D13 C301 0.1U_0402_16V4Z
R270 R278 R281 1 2 ON /OFFBTN#
1

E C_ON 1 2 2
34 EC_ON
R463 100K_0402_5% 100K_0402_5% 680K_0402_5% 1N4148_SOT23
33K_0402_5%

1
Q49 D

P
3

DTC124EK_SC59 1 2 2 4 1 2 2 Q24
A Y
1

D C304 1U_0805_16V7K R272 G 2N7002_SOT23

G
Q50 2 10K_0402_5% S

3
G U23

3
1
2N7002_SOT23 S D NC7SZ14M5X_SOT23-5
3

2 Q25
38 S4_LID_SW#
G 2N7002_SOT23
S

1
D

30,34,38,41,47 S YSON 2
G
Q26 S

3
2N7002_SOT23
3 3

RTCVREF 1 2 1 2
R325 C324 1U_0805_16V7K
10K_0402_5%
RTCVREF
U28 C323 0.1U_0402_16V4Z
1 14 1 2
Power ON Circuit 2
CD1# VCC
13
D1 CD2#
34 S4_LATCH 3 CP1 D2 12
+3VS 1 2 4 11
RTCVREF SD1# CP2
2

R317 1 5 10
+3V +3V R569 10K_0402_5% C319 Q1 SD2#
6 Q1# Q2 09
10K_0402_5% 7 GND Q2# 08
1

@ 1U_0805_16V7K
U25D U25E 2 74LCX74MTC_TSSOP14
1

R269 SN74LVC14APWLE_TSSOP14 SN74LVC14APWLE_TSSOP14

14

14

180K_0402_5% +3VALW 1 2
R285 D14
P

P
2

1
10K_0402_5% D
9 I O 8 11 I O 10 SYS_PW ROK 19
2 1 D_SET_S4 2 Q27
34 S4_SATA
G

2 +3V POWER +3V POWER G 2N7002_SOT23

S
7

3
C289 RB751V_SOD323
R271
1U_0805_25V4Z
1 100K_0402_5%

4 4

Compal Electronics, Inc.

Title
SCHEMATIC, M/B LA-2492
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
401317 B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: ¬P 期一, 一月 03, 2005 Sheet 40 of 51
A B C D E
 A B C D E

+3V +25VS_18VS
+3VALW TO +3V +5VALW TO +5VS
+3V

2
+5VALW +5VS R161 R431
U32 @ 470_0402_5% @ 470_0402_5%
1 1 8 D S 1
C196 C190 7 2

1
D S
6 D S 3 1 1
10U_1206_16V4Z 1U_0805_25V4Z 5 4 C404 C403
D G

1
+3VALW 2 2 D D
1 U12 1 SI4800DY_SO8 4.7U_0805_10V4Z 1U_0805_25V4Z 2 SYSON# 2 SUSP 1
2 2 G G
8 D S 1
7 2 R157 C380 S Q18 S Q45

3
D S 100K_0402_5% 4.7U_0805_10V4Z @ 2N7002_SOT23 @ 2N7002_SOT23
6 D S 3
SYSON_ALW 2
5 D G 4 1 2 +12VALW

1
SI4800DY_SO8 2

1
C180 R159 D 5VS_GATE
1
C189 2 SYSON#
0.1U_0402_16V4Z @ 1M_0402_5% G
10U_1206_16V4Z 1 S Q19
2

3
2 2N7002_SOT23

+3VS +5VS
+1.5VALW TO +1.5VS

2
R340 R341
+1.5VALW +1.5VS @ 470_0402_5% @ 470_0402_5%
U13
8 1

1
D S
7 D S 2
6 D S 3 1 1

1
C211 C208 D D
5 4
+3VALW TO +3VS D G
2 SUSP 2 SUSP
1 SI4800DY_SO8 4.7U_0805_10V4Z 1U_0805_25V4Z G G
+3VS 2 2 S Q37 S Q38

3
C191 @ 2N7002_SOT23 @ 2N7002_SOT23
4.7U_0805_10V4Z
2 2 2
1 1
+3VALW C596 C592

U40 10U_1206_16V4Z 1U_0805_25V4Z 5VS_GATE

2 2
8 D S 1
7 2 R490
D S 100K_0402_5%
6 D S 3
5 4 5VS_GATE 1 2 +12VALW
D G +1.5VS
SI4800DY_SO8
1

2
1 2 +2.5V TO +2.5VS (DDR1)
1

C598 C594 R484 D +DDRVCC +25VS_18VS R489

2 SUSP R80 1 2 0_0805_5% +2.5VS @ 470_0402_5%
10U_1206_16V4Z 0.1U_0402_16V4Z @ 1M_0402_5% G U6
2 1 Q53 R81
S 8 1 1 2 @ 0_0805_5% +1.8VS
2

1
2N7002_SOT23 D S
7 D S 2
6 3
D S +1.8V TO +1.8VS (DDR2)

1
D
5 D G 4 1 1
C61 C72 2 SUSP
SI4800DY_SO8 G
1 4.7U_0805_10V4Z 1U_0805_25V4Z S Q54

3
2 2 @ 2N7002_SOT23
C90
4.7U_0805_10V4Z
2
+3VALW +3VALW
+3V
5VS_GATE
3 3

2
1

C642
R553
0.1U_0402_16V4Z
14

14

0_0402_5% U42A 1 U42B

+5VALW +5VALW
P

P
2

1 I O 2 3 I O 4 V_ON 47
2 +5VS
G

2
C645 +3VALW POWER +3VALW POWER
SN74LVC14APWLE_TSSOP14 SN74LVC14APWLE_TSSOP14 R338 R339
7

@ 0.1U_0402_16V4Z C687 10K_0402_5% 10K_0402_5%

1 10U_0805_6.3V6M

1
1 1 SUSP SYSON#
35,48 SUSP 38 SYSON#

1
+3VALW POWER 2 2
+3VS
100K 100K
2 S Y SON 2
+3VALW +3VALW 16,26,32,34,36,37,47,48 SUSP# 30,34,38,40,47 S YSON
C686
10U_0805_6.3V6M
DTC115EKA_SOT23 DTC115EKA_SOT23
1

100K 100K
R554 Q35 Q34
In CUP side

3
14

14

0_0402_5% U42C U42D

P

P
2

4 5 I O 6 9 I O 8 VS_ON 47,48 4
2
G

C646 +3VALW POWER +3VALW POWER

SN74LVC14APWLE_TSSOP14 SN74LVC14APWLE_TSSOP14
7

@ 0.1U_0402_16V4Z
1

Compal Electronics, Inc.

Title

PROPRIETARY NOTE THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND SCHEMATIC, M/B LA-2492
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE B B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 401317
D ate: ¬P 期一, 一月 03, 2005 Sheet 41 of 51
A B C D E
 5 4 3 2 1

C F9 C F4 CF10 CF14 +3V

SMD40M80 SMD40M80 SMD40M80 SMD40M80

+VDDA

14
1

1
U25F

4
CF11 C F7 C F2 C F1 CF15 CF16

P
SMD40M80 SMD40M80 SMD40M80 SMD40M80 SMD40M80 SMD40M80 13 13 12

V+
- I O
D
O 14 D

G
12

V-
+ U26D SN74LVC14APWLE_TSSOP14
1

7
LMV824MTX_TSSOP14

11
F D6 F D3 F D5 F D4 F D1 F D2
F IDUCAL F IDUCAL F IDUCAL F IDUCAL F IDUCAL F IDUCAL

+3VALW
1

1
+VDDA

14
U42F

4
13 I O 12
13 +12VALW

V+
-

G
O 14
SN74LVC14APWLE_TSSOP14 12

V-
7
+ U31D U37B
LMV824MTX_TSSOP14 5 +IN

11
H1 H2 H3 H4 H5 7
SCREW 8.5X2.8 SCREW 8.5X2.8 SCREW 8.5X2.8 SCREW 8.5X2.8 SCREW 8.5X2.8 OUT
6 -IN

LM358A_SO8

+3VALW
1

1
C +VDDA C

14

4
U42E
13

V+
H6 H7 H8 H9 H10 -
11 I O 10 O 14
SCREW 8.5X2.8 SCREW 8.5X2.8 SCREW 8.5X2.8 SCREW 8.5X2.8 SCREW 8.5X2.8 12

V-
+

G
U30D
SN74LVC14APWLE_TSSOP14 LMV824MTX_TSSOP14

11
1

H11 H12 H13 H14 H15

SCREW 8.5X2.8 SCREW 8.5X2.8 SCREW 8.5X2.8 SCREW 8.5X2.8 SCREW 8.5X2.8
1

B B
H16 H17 H18 H19 H20
SCREW 8.5X2.8 SCREW 8.5X2.8 SCREW 8.5X2.8 SCREW 8.5X2.8 SCREW 8.5X2.8
1

H21 H22 H23

SCREW 8.5X2.8 EMI2_7X2 EMI2_7X2
1

M1 M2 M3 M4
SCREW 8.5X2.8 SCREW 8.5X2.8 SCREW 8.5X2.8 SCREW 8.5X2.8

A A
1

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND SCHEMATIC, M/B LA-2492
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 401317
D ate: ¬P 期一, 一月 03, 2005 Sheet 42 of 51
5 4 3 2 1
 A B C D

+DC_IN_S1 V IN
PL1 PF1
FBM-L18-453215-900LMA90T_1812
DC_IN_S2 1 2 DC_IN_S1 1 2
PJP1
1 12A_65VDC_451012
1 PC4
2 100P_0402_50V8J
2

1
3 PC1 PC2 PC3
1
3 1000P_0402_50V7K 100P_0402_50V8J 1000P_0402_50V7K 1

2
4 4

JST_S4B-EH

VS

V IN
1 2
PR1 1M_0402_1%

1
1
VS PR2
V IN PR3
5.6K_0402_5%
61.9K_0402_1% 1 2

2
A C IN 19,34,38

2
PD1 PR4

8
2 1 PD2 PU1A 1K_0402_5%
BATT_A
1 2 3

P
1N4148_SOD80 1N4148_SOD80 PR5 15.4K_0402_1% + P ACIN
O 1 P ACIN 45,46
2

1
-

G
1
1

1
PR6 LM393M_SO8 PD4

4
1
PC5 PC6 PR7
PR8 1000P_0402_50V7K 20K_0402_1% 0.1U_0402_16V7K 10K_0402_5%

2
1538VCC VS RLZ4.3B_LL34

2
33_1206_5%

2
PR9
Vin Detector

2
2 1 RTCVREF
2 CH GRTCP 1 2 3 1 2

PR10 PQ1 10K_0402_5%

200_0603_5% TP0610T_SOT23 3.3V High 14.57 14.01 13.46
1

2
1

1
PR11
PC7 PC8
Low 14.06 13.51 12.98
0.22U_1206_25V7M 0.1U_0603_25V7K PR28
100K_0402_5%
2

1 2
2

1 2 1K_1206_5%
38,40 51ON#
PR12 22K_0402_5% PD3
VIN 2 1 1 PR29 2
B+
1N4148_SOD80 1K_1206_5%
RTCVREF
1 PR32 2
PU2
S-812C33AUA-C2N-T2_SOT89 1K_1206_5%

PR13 PR14 3.3V

1
+CHGRTC 1 2 1 2 3 OUT IN 2
PR34
1

200_0603_5% 200_0603_5% 499K_0402_1%

1

GND PC9
PC10 1U_0805_25V4Z
2

2
10U_0805_10V4Z 1
PR67 PR60
2

1 2 1 2
VL
3 10K_0402_5% 2.2M_0402_5% 3

1
8
PD24 PU1B PC17
2 5 PR57 1000P_0402_50V7K

2
PJ1 PJ2 18,44,46 MAINPWON +
1 7

2
O
+3VALWP 2 2 1 1 +3VALW +1.8VSP 2 2 1 1 +1.8VS 3 - 6 1 PR63 2 VL 499K_0402_1%

G
45 ACON

1
JUMP_43X118 JUMP_43X79 RB715F_SOT323 34K_0402_1%

4
1

1
(5A,200mils ,Via NO.= 10) (1A,40mils ,Via NO.= 2) PR68

1
PC39 PR64 237K_0402_1%
PJ3 PC3766.5K_0402_1%

2
2 1 PJ4 LM393M_SO8 1000P_0402_50V7K
+5VALWP +5VALW

2
2 1
+1.5VALWP 2 1 +1.5VALW

2
JUMP_43X118 2 1
PR69

1
JUMP_43X118 D
(5A,200mils ,Via NO.= 10)
(3.5A,140mils ,Via NO.= 7) 1000P_0402_50V7K PQ16 2 1 2 P ACIN
PJ5
G
+12VALWP 2 1 +12VALW S

3
2 1

1
2N7002_SOT23 47K_0402_5%
PJ6
JUMP_43X39
+DDRVTTP 2 2 1 1 +DDRVTT
Precharge detector
(120mA,40mils ,Via NO.= 2)
JUMP_43X118 PQ17 2
PJ7 (2A,80mils ,Via NO.= 4) 14.3V/13.18V for adapter +5VALWP

+DDRVCCP 2 2 1 1 +DDRVCC
DTC115EUA_SC70
JUMP_43X118

3
PJ8 PJ9
4 2 2 1 1 +2.5VSP 2 2 1 1 +2.5VS 4

JUMP_43X118 JUMP_43X118
(8A,320mils ,Via NO.= 16) (2A,80mils ,Via NO.= 4)

PJ10
+1.05VSP 2 2 1 1 +1.05VS THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY Compal Electronics, Inc.
OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE Title
JUMP_43X118 SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE SCHEMATIC, M/B LA-2492
(3.5A,140mils ,Via NO.= 7) CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS
AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR Size Document Number R ev
THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY 401317 B
THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS,
IN C . D ate: ¬P 期一, 一月 03, 2005 Sheet 43 of 51
A B C D
 A B C D

PH1 under CPU botten side :

CPU thermal protection at 84 degree C
Recovery at 45 degree C

1 1

VMB_A PL2 VL VS VL
PJP2 PF2 12A_65VDC_451012 FBM-L18-453215-900LMA90T_1812
1 BATT_A_S1 1 2 1 2
BATT+ BATT_A

2
1K_0402_5% PR15

1
2 ALI/N IMH# 1 PR16 2
ID A B/I PR17 2 PH1 PC11 47K_0402_1%
B/I 3 1 +3VALWP MAINPW ON 18,43,46

1
4 TS_A 47K_0402_5% 0.1U_0603_25V7K

1
TS EC_SMDA PC12 PC13 PR18
SMD 5

1
6 EC_SMCA 1000P_0402_50V7K 0.01U_0402_25V7Z 10KB_0603_1%_TH11-3H103FT 1 2

2
SMC PR19 47K_0402_1% PQ2
GND 7

8
1K_0402_5% PR20 DTC115EUA_SC70
TYCO_1747602-1_7P 1 2 3 PU3A PD5

P
+
2

16.9K_0402_1% 1 2 1 2

2
2
TM_REF1 O
2 -

G
PR21 PR22 1SS355_SOD323
100_0402_5% 100_0402_5% LM393M_SO8
ALI/MH# 34

4
1

3
PR23
1

2 1 +3VALWP

1
PC14
PR24 PR25
6.49K_0402_1%
1

PR26 0.22U_0805_16V7K_V2 3.32K_0402_1% 2 1 VL

1
100K_0402_1%
1K_0402_5% PC15

2
1000P_0402_50V7K

2
2

1
2 2
BATT_TEMPA 34
PR27

100K_0402_1%
EC_SMB_DA1 34,36

2
EC_SMB_CK1 34,36

PH2 near main Battery CONN :

BAT. thermal protection at 79 degree C
Recovery at 45 degree C

VL VL

2
3 PH2 PR30 3

47K_0402_1%
10KB_0603_1%_TH11-3H103FT
PR31

1
1 2
47K_0402_1%
PR33

8
14.7K_0402_1% PU3B
1 2 5 PD6

P
+
O 7 2 1
TM_REF1 6 -

G
1
1SS355_SOD323

1
PC18 PR35 LM393M_SO8

4
0.22U_0805_16V7K_V2 3.48K_0402_1%

4 4

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY Compal Electronics, Inc.
OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE Title
SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE SCHEMATIC, M/B LA-2492
CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS
AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR Size Document Number R ev
THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY 401317 B
THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS,
IN C . D ate: ¬P 期一, 一月 03, 2005 Sheet 44 of 51
A B C D
 A B C D

Iadp=0~4.7A
P2 P3 B+
PQ3
PQ4 PQ5 AO4407_SO8
AO4407_SO8 AO4407_SO8 PR36 PJ11 1 8
V IN 8 1 1 8 2 1 2 2 1 1 B++ 2 7
7 2 2 7 3 6

1
6 3 3 6 0.015_2512_1% JUMP_43X118 PC19 PC20 PC21 5
5 5
4.7U_1206_25V6K 4.7U_1206_25V6K 4.7U_1206_25V6K

4
4

4
1 1

1
PR37
1

3
PR38 PQ6 200K_0402_1%
47K_0402_5% DTA144EUA_SC70 PR39

2
47K

1
1 2 V IN
2 PC22 PU4 47K_0402_5%
47K

1
0.1U_0603_25V7K 1 -INC2 24
34 ADP_I
2

2
+INC2

3
2
1
PR40 PD7
PQ7 1K_0402_5%
2 1 2 23 AO4407_SO8 RLZ18B_LL34
OUTC2 GND
1

PR41 100K_0402_5% PC23 N18 4 AC OFF#

1

22
0.022U_0402_16V7K
3 22 CS 1 2 PD8
+INE2 CS

1
PQ8 1SS355_SOD323
2 PC24

1
DTC115EUA_SC70 4 21 1 2

1
-INE2 VCC(o)

1
0.1U_0402_16V7K PR42

5
6
7
8
1
PC26 PR44 0.1U_0603_25V7K 2 1 2 ACOFF 34
1

D PC25 PR43 25.5K_0402_1% PD9

1 2 1 2 5 20
3

PR45 10K_0402_1% 10K_0402_5% FB2 OUT PQ9

2

2
G PQ10 100K_0402_1% 4700P_0402_25V7K 1SS355_SOD323

2
S 6 19 1 2 LXCHRG DTC115EUA_SC70
3

3
SN7002N_SOT23 VREF VH PC27
2

1
PC28 PC29 PR46 0.1U_0603_25V7K
PD10 0.1U_0402_16V7K 1 2 1 2 7 18 1 2
AC OFF#1 1K_0402_5% FB1 VCC PC30
2
CC=0.5~3.3A
2
2 1000P_0402_50V7K 0.1U_0603_25V7K 2

1SS355_SOD323 8 17 1 2
-INE1 RT PR47 CV=12.6V(9 CELLS LI-ION)
143K_0402_1% 68K_0402_5%
1

D
34 IR E F 1 2 9 +INE1 -INE3 16
P ACIN 1 2 2 PR48 PL4 PR50
43,46 P ACIN
PR49 G PQ11 PR52 PC31 1 2 1 2 BATT_A
3K_0402_1% S SN7002N_SOT23 2 1 10 15 1 2 1 2 10UH_D104C-919AS-100M_4.5A_20%
3

OUTC1 FB3
1

1 PR51 10K_0402_5% 47K_0402_5% 0.02_2512_1%

PR53 1500P_0402_50V7K 4.7U_1206_25V6K
PC32 11 14 AC ON
43 ACON OUTD CTL

1
100K_0402_1% PD11 PD12 PC33 PC34 PC35
2
2

0.1U_0402_16V7K 12 13 EC31QS04 EC31QS04 4.7U_1206_25V6K 4.7U_1206_25V6K

2
-INC1 +INC1
IREF=1.31*Icharge

2
MB3887_SSOP24
IREF=0.6V~3.21V

+3VALWP
CS
PR54 PR55
4.2V
1

2 1 2 1
1

PR56
47K_0402_5% PQ12 150K_0603_0.1% 300K_0603_0.1%
DTC115EUA_SC70
2

3 2 3

PQ14
1

DKN_B+ B+
PQ13 AO4407_SO8
DTC115EUA_SC70 8 1
3

7 2
34 FSTCHG 2 6 3
VMB_A 5

4
PR59
3

27K_0402_1%
PR58 B+ 1 2
340K_0402_1%

2
1 2 PR61
2

10K_0402_1%
OVP voltage : LI PC36
1

3S3P : 13.5V--> BATT_OVP= 1.5V +12VALWP 1U_1206_25V7K

1
PR62
499K_0402_1%
(BAT_OVP=0.1111 *VMB)

1
2
8

PU5A
LM358A_SO8 3 PU5B
P

+ LM358A_SO8
1 0 5 2
34 BATT_AOVP 2 7 0
+ 34 DKN_B+_ON
-
G

6 PQ15
-
4

4 DTC115EUA_SC70 4

3
1

PR65
1

PR66 PC38

2.2K_0402_5% 0.01U_0402_25V7Z
2

105K_0402_1%
Compal Electronics, Inc.
2

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY

OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE Title
SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE SCHEMATIC, M/B LA-2492
CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS
AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR Size Document Number R ev
THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY 401317 B
THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS,
IN C . D ate: ¬P 期一, 一月 03, 2005 Sheet 45 of 51
A B C D
 5 4 3 2 1

PC44
N4 1 2

1
PD13
4.7U_1206_25V6K

2
PC45
B+++ 470P_0805_100V7K EC11FS2_SOD106

1
D PJ12 1 2 PC46 BST31 BST51 D

2
2 1 0.1U_0603_25V7K S NB 2 1 FLYBACK
B+ 2 1 PR74 22_1206_5%

2
JUMP_43X118 PT1

8
7
6
5
1

1 PC48 PQ18

D
D
D
D

2
PC47 SI4800DY-T1_SO8 PD14
4.7U_1206_25V6K VS
2

4.7U_1206_25V6K DAP202U_SOT323 1 2 PC49 10uH_SDT-1205P-100-118_5A_20%

3
G
S
S
S
0.1U_0603_25V7K B+++

1
2
3
4

1
VL
PLX3 PD15

5
6
7
8
1SS355_SOD323 +12VALWP PQ19

8
7
6
5

D
D
D
D
1

1
PQ20 SI4800DY-T1_SO8

D
D
D
D

1
SI4810DY_SO8 PC50 PC51

1
PC52 4.7U_1206_25V6K 4.7U_1206_25V6K

G
1

S
S
S
4.7U_0805_6.3V6K PR75

2
G

1
S
S
S
PC53

4
3
2
1
0.1U_0603_25V7K PC54 1.54K_0402_1%
1
2
3
4

2
1

PC55 4.7U_1206_25V6K

2
PDH3
1

47P_0402_50V8J PDL3
PL5 PD H5

5
6
7
8

1
10UH_D104C-919AS-100M_4.5A_20% PR76
2

2 1 PC56

D
D
D
D
1.27K_0402_1% 47P_0402_50V8J
2

2
22

21
2

1
C PC57 PU7 PQ21 C

1
S
S
S
PR77 25 4 SI4810DY_SO8

VL
V+
1.27K_0402_1% 0.47U_0603_16V7K BST3 12OUT PR78
5
2

4
3
2
1
VDD
2

PR80 27 DH3 BST5 18

16 2M_0402_1%
1

1M_0402_1% DH5 PLX5

2 1 26 17

2
LX3 LX5 PDL5
24 DL3 DL5 19
+3VALWP PR79 20
1

0_0402_5% PGND
CSH5 14
PR81 CS H3 1 13 CS H5
CSH3 CSL5
2 620_0402_5%
1 CSL3 2 CSL3 FB5 12

1
3 FB3 SEQ 15

1
1 3.32K_0402_1% 1 2 10 9 2.5VREF PC58 PR83
43,45 PACIN SKIP# REF
1

220U_6.3V_M PD16 PR82 23 6 698_0402_1%

SHDN# SYNC
1

1
+ PR84 10K_0402_5% 11 0.47U_0603_16V7K

2
PC60 RST# PC61
7

2
PC59 SKUL30-02AT_SMA 100P_0402_50V8J TIME/ON5 4.7U_0805_6.3V6K
2

2
2
28

GND
+5VALWP
2

RUN/ON3
POK 47
PR85
1

1
8

1
VS 1 2 PC62 MAX1902EAI_SSOP28 PR86 1
1

1
PC64 1000P_0402_50V7K PC63 220U_6.3V_M PD17
2

@ 100P_0402_50V8J PR87 47K_0402_5% 10.2K_0402_1% 100P_0402_50V8J +

2
2

2
1

10K_0402_1% PC65 SKUL30-02AT_SMA

PC66 2
1

2
1

1
@ 0.047U_0603_25V7M
2

PR88 PC67
B @ 100P_0402_50V8J B

2
2 1 VL
PR89 10K_0402_1%

2
220K_0402_5%

MAINPW ON 18,43,44
1

PC68
0.47U_0603_16V7K
2

A A

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY Compal Electronics, Inc.
OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE Title
SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE SCHEMATIC, M/B LA-2492
CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS
AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR Size Document Number R ev
THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY 401317 B
THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS,
IN C . D ate: ¬P 期一, 一月 03, 2005 Sheet 46 of 51
5 4 3 2 1
 A B C D

PL6
FBM-L18-453215-900LMA90T_1812
1 2 B+

1
PC70

1
4.7U_1206_25V6K PC69 PR90

1
1 4.7U_1206_25V6K 1

2
0_1206_5% PC71

2
+5VALWP
4.7U_1206_25V6K

2
PC16 PD18

1
4.7U_0805_6.3V6K DAP202U_SOT323 PC72 PR91 PC73

2
2.2U_0805_10V6K

2
0.1U_0603_25V7K 2.2_0603_5%

1
2

3
8
7
6
5
2.5V/1.8V

D
D
D
D
PQ22
SI4800DY-T1_SO8

14

28
G
S
S
S
+DDRVCCP PL7 PC74 PU8 PC75

5
6
7
8
1.8UH_D104C-919AS-1R8N_9.5A_20% 2 1 12 17 2 1

VIN

VCC
1
2
3
4
0.01U_0402_25V7K SOFT1 SOFT2 0.01U_0402_25V7K

D
D
D
D
1 2
PR92 PQ23
1 2 1 1 2 6 23 1 2 2 1 SI4800DY-T1_SO8
BOOT1 BOOT2

G
8
7
6
5

S
S
S
220U_6.3V_M PR93
+ PQ24 PC76 0_0603_5% 0_0603_5% PC77
+1.5V
D
D
D
D

4
3
2
1
2 0.1U_0402_16V7K
SI4810DY_SO8 0.1U_0402_16V7K PL8 2

PC78 0.01U_0402_16V7Z 5 24 4.7UH_D104C-919AS-100M_5.2A_20% +1.5VALWP

2 UGATE1 UGATE2

G
1

S
S
S
PC79 4 25 1 2
1 PHASE1 PHASE2
2
3
4
PR94 PR96
2

5
6
7
8
18.2K_0402_1% PR95 2.4K_0402_1%
1 2 7 22 1 2 0.01U_0402_16V7Z

D
D
D
D
2

ISEN1 ISEN2 PQ25 PC81 1

1.87K_0402_1% 2 27 SI4810DY_SO8 220U_6.3V_M
LGATE1 LGATE2

1
+

1
S
S
S
PC80

4
3
2
1

2
PR97 2
3 PGND1 PGND2 26
6.81K_0402_1%

2
9 VOUT1 VOUT2 20
10 VSEN1 VSEN2 19
8 EN1 EN2 21 1 2 POK 46

1
1 PR98 2 15 PG1 PG2/REF 16 PR99 0_0402_5%
1

1
30,34,38,40,41 S YSON @ 0_0402_5% PR100

GND

DDR
PR101 1 2 11 18 PC83
41 V_ON OCSET1 OCSET2 @ 0.1U_0402_16V7K 10K_0402_1%

2
1
10K_0402_1% PR70 0_0402_5% ISL6225BCA-T_SSOP28 PR102

13

2
1

1
2

PR103 200K_0402_1%
PC82 107K_0402_1%
2

2
@ 0.1U_0402_16V7K
2

3 3

PJ13 PU9 +2.5VSP

+3VS 2 2 1 1 2 VIN VO 3

1
2

2
JUMP_43X118 PC84 1 4 PC85
EN ADJ PR104 10U_1206_6.3V6M
PR94 UNPOP 4.7U_0805_6.3V6K 5 7 22K_0402_1% @

1
GND GND
@ @

2
6 GND GND 8
DDRI 18.2K_0402_1% (2.5V) PU9,PC84,PR105,PR104,PR106,PC85
G965-18P1U_SO8

1
1 2 @
16,26,32,34,36,37,41,48 SUSP#
PR105 PR106
0_0402_5% 20K_0402_1% @
10K_0402_1% (1.8V) PU12,PC95,PR114,PC96 @
DDRII

2
1 2
41,48 VS_ON
PR72
0_0402_5%
@

1
4 4

PC86
@ 0.1U_0402_16V7K

2
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY Compal Electronics, Inc.
OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE Title
SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE SCHEMATIC, M/B LA-2492
CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS
AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR Size Document Number R ev
THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY 401317 B
THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS,
IN C . D ate: ¬P 期一, 一月 03, 2005 Sheet 47 of 51
A B C D
 5 4 3 2 1

PR107
PJ14
1 2 2 2 1 1 +5VALW

2
10_0603_5% JUMP_43X118

1
PC87
PD19 PC88 PC89
1U_0603_6.3V6M 1N4148_SOD80 22U_1206_6.3V 22U_1206_6.3V

2
2

1
1
PR108 PC90

5
6
7
8
470P_0603_50V7K

5
5.1K_0402_1% PU10 PC91 PQ26

D
D
D
D
2
D 0.1U_0402_16V7K SI4800DY-T1_SO8 D

VCC
1

1
BOOT 1

G
S
S
S
7

2
OCSET

4
3
2
1
PL9
UGATE 2
PR109 3UH_SPC-07040-3R0_5A_30%

1
100K_0402_5% D
6 FB 2 1 +1.05VSP
VL 2 1 2 PQ27
G SN7002N_SOT23 8
PHASE

5
6
7
8
S 1

3
VS_ON 1 2 PQ28

D
D
D
D
SI4800DY-T1_SO8 + PC92
PR143 3 4 220U_6.3V_M
0_0402_5% GND LGATE

G
1

D 2

S
S
S
1 2 2 PQ29 APW 7057KC-TR_SOP8
6,26,32,34,36,37,41,47 SUSP#

4
3
2
1
G SN7002N_SOT23
PR110 S
3

@ 0_0402_5% PR111
2

2.26K_0402_1%
PC93 1 2
1

@ 0.1U_0402_16V7K

2
PR112 1 2
7.5K_0402_1%
PC94
C 0.1U_0402_16V7K C

1
PC122 @ 1U_0603_10V4Z
2 1
PU14
PC123

+1.8VS 1 VOUT BP 5 1 2

2 @ +DDRVCC
GND 0.1U_0402_16V4Z

+3V 3 4 1.8VS_ON
VIN SHDN#
1

1
@ 1U_0603_10V4Z PC124 APL5301-18BC-TR_SOT23-5
@ PJ15

1
2
JUMP_43X118

22
PU11
PJ16 PU12 +1.8VSP 1 6 +3VALWP
VIN VCNTL
+DDRVCCP 2 2 1 1 2 VIN VO 3
2 GND NC 5
2

1
B JUMP_43X118 PC95 PC96 B
1 EN ADJ 4

1
10U_1206_6.3V6M PC97 3 7 PC98
4.7U_0805_6.3V6K 10U_1206_6.3V7K VREF NC 1U_0603_6.3V6M
5 7
1

2
GND GND PR113 4 VOUT NC 8
6 8 1K_0402_1%
GND GND
9

2
G965-18P1U_SO8 TP
SUSP# 1 2 1.8VS_ON APL5331KAC-TR_SO8
PR115
PR114 +DDRVTTP

1
@ 0_0402_5% 0_0402_5% D

1
SUSP 1 2 2

1
VS_ON 1 2 35,41 SUSP G PR116 PC100
41,47 VS_ON PQ30 S 1K_0402_1% 0.1U_0402_16V7K PC101

2
1
PR710_0402_5% SN7002N_SOT23 10U_1206_6.3V7K

2
PC102
1

@ 0.1U_0402_16V7K

2
PC99
@ 0.1U_0402_16V7K
2

A A

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY Compal Electronics, Inc.
OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE Title
SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE SCHEMATIC, M/B LA-2492
CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS
AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR Size Document Number R ev
THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY 401317 B
THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS,
IN C . D ate: ¬P 期一, 一月 03, 2005 Sheet 48 of 51
5 4 3 2 1
 CPU_B+ B+
+5VS
PL3
1 2

4.7U_1206_25V6K

4.7U_1206_25V6K
PD20 FBM-L18-453215-900LMA90T_1812

1
EP10QY03

1
PR117
10_0402_5% 1

PC104

PC105
2 1

2
+ PC103

2
220U_25V_M
2
2
PC106

0.01U_0402_25V7Z
PC107

2
1U_0603_16V6K 2.2U_0603_6.3V6K

5
6
7
8
1

PC108

0.22U_0603_16V7K
PQ31

D
D
D
D
1

1
AO4408_SO8

PC109
V CC 10 30
VCC VDD

G
S
S
S
5 CPU_VID0 24 D0 V+ 36

4
3
2
1
5 CPU_VID1 23 D1 BSTM 26 2 PR118 1
PR146 3.3_0603_5% +CPU_CORE
22 28 2 1 PL10
5 CPU_VID2 D2 DHM 0.56UH_ETQP4LR56WFC_21A_20% PR119
21 27 0_0603_5% 1 2 1 2
5 CPU_VID3 D3 LXM

1
20 PU13 29 0.001_2512_5%
5 CPU_VID4 D4 DLM

5
6
7
8
PR144

AO4410_SO8
19 31 4.7_1206_5% CPU VCC SENSE

D
D
D
D
5 CPU_VID5 D5 PGND

PQ32

909_0402_1%
1
6,14,19 VGATE PR140 0_0402_5% 25 MAX1532 37

2
VROK CMP

499_0402_1%

499_0402_1%
1 2

1
S
S
S
4 S0 CMN 38

1000P_0402_50V7K
V CC PR141 @1 0_0402_5%
2

4
3
2
1

2
3K_0402_1%
V CC 5 17 PC40

2
S1 OAIN+

PR123

PC110
R EF PR142 @1 0_0402_5%
2 680P_0603_50V8J PC111

PR120
34 VR_ON 1 2 6 16 1 2

1
PR124 0_0402_5% PR125 30.1K_0402_1% SHDN# OAIN-

PR121

PR122
2 1 1 15 FB 0.47U_0603_16V7K

1
TIME FB PR126 909_0402_1%
PC112 1 2 12 14 1 2 1 2
CCV CCI PC113 470P_0402_50V8J @
1 2 270P_0402_50V7K 2 35
TON BSTS
PR127 200K_0402_1% 1 2 R EF 8 33 2 PR147 1
PR129 REF DHS 0_0603_5% 1 2
1 2 PC114 0.22U_0603_16V7K 9 34 PR128
66.5K_0402_1% ILIM LXS 3K_0402_1%
+5VS
FB 1 2 7 32 1 2 1 2
OFS DLS
10.7K_0402_1%

100P_0402_50V8J

PR130 100K_0402_1% 3 40 PC115 PR131

SUS CSP
2

1 2 0.022U_0402_16V7K 0_0402_5%
PR132

PC116

RHU002N06_SOT323 18 39
SKIP CSN
2
1

2
D CPU_B+

3.3_0603_5%
27P_0402_50V8J

PQ33 11 13 PD22
GND GNDS
1

PR133
2 EP10QY03
14,19 PM_STP_CPU#
1

PC117
RHU002N06_SOT323

G 2
S G
3

4.7U_1206_25V6K

4.7U_1206_25V6K
S
3

D 5
D 6
D 7
D 8

1
AO4408_SO8
PQ34

PR134

PC118

PC119
PQ35
0_0402_5%

2
0.22U_0603_16V7K
19 PM_DPRSLPVR 1 2

G
S
S
S
PC120
+5VS 1 2

4
3
2
1
PR135 PL11
2

20K_0402_1%
2

PR136 0.56UH_ETQP4LR56WFC_21A_20%
PR137 10K_0402_1% 1 2
100K_0402_1%

909_0402_1%
1 1

5
6
7
8

1
1

D
RHU002N06_SOT323

AO4410_SO8
PR145

D
D
D
D
PQ36
2 4.7_1206_5%
G
S
3

1 2

2
G
1

S
S
S
PQ37

C
5 PSI# 2

4
3
2
1

PR138
B PC41 1 2
E PQ38 680P_0603_50V8J
3

2
HMBT2222A_SOT23 PC121
0.47U_0603_16V7K

909_0402_1%
1 2

PR139

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY Compal Electronics, Inc.
OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE Title
SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE SCHEMATIC, M/B LA-2492
CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS
AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR Size Document Number R ev
THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY 401317 B
THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS,INC.
D ate: ¬P 期一, 一月 03, 2005 Sheet 49 of 51
 5 4 3 2 1

EAT10 PIR List

********** Rev:0.2 PIR List 2004/10/26 Writer by Sam Tsai **********
P04:Add @ in R28 Intel Recommend

P06:Add @ in C441, C427

D C472 & C460 Change Value from 220U to 330U
Del JP9 Power Team testing OK D

P12:+3VS change from JP25.196 to JP25.194 Intel Recommend

P15:New add R570, R571 & R572 RGB without Docking

New add L33 EMI
Del D2 & D25 EMI

P16:Change U44 from 7404 to 74125 LCDVDD Soft-Start

P18:New add R573 Intel Recommend

R439 Change Value from 180K to 20K Intel Recommend
C271 Change Value from 0.1U to 1U Intel Recommend

P20:R214 Change Value from 1K to 10ohm Intel Recommend

P22:New add @R , @R& Q SWDJ testing

P24:New add R586 TI Recommend

New add @R581

P25:New add R582, R583, @R584, R585, R588, R589 & @C685 TI Recommend

P27:R73 Change Value from 4.99K to 4.7K Marvwll Recommend

P31:R361 & R371 Change Value from 47K to 22K Design Change
P33:New add R543, R544
P32:Modify C399 Net to SPKL+ Design Change

C P33:New add L34 EMI C

add@ in C647 ~ C662

P34:New add R587 Design Change

P35:New add JP32 & C671 Design Change

New add C682 ~ C684 EMI
JP13 reverse Design Change

P36:New add SWDJ testing

P37:SW1 change to 1BS003-1211L_3P Design Change

P38:Q52.3 change from +3VALW to +3V Design Change

Q57.3 change from +5VALW to +5VS
Lid Switch IC Power change from JP16.26 +3VALW to JP16.27 RTCVREF
New add C672 ~ C681 EMI

P39:New add R574 Design Change

P40:Del D11 Design Change

B B

A A

Compal Electronics, Inc.

Title
SCHEMATIC, M/B LA-2492
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
401317 B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: ¬P 期一, 一月 03, 2005 Sheet 50 of 51
5 4 3 2 1
 5 4 3 2 1

Version Change List ( P. I. R. List ) for Power Circuit

Request
Item Page# Title Date Owner Description Rev.
D D
0.1
1 45 Design change 07/06/2004 Compal Change PD7 from RLZ22B to RLZ18B for 15V adapter OVP

2 43 Design change 08/20/2004 Compal Add precharge function for MAX1902 UVP when adapter pull out /in right away 0.2

3 49 Design change 08/20/2004 Compal Add PL3 fo speed step function,change PC103 from 100U_25V_M to 220U_25V_M 0.2

4 43 Design change 08/20/2004 Compal Change PF1 from 7A to 12A for customer review fuse current rating too margin 0.2

0.2
5 43 Design change 08/20/2004 Compal Change PQ1 from TP0610T to TP0610T for EOL

0.2
6 47 48 Design change 08/20/2004 Compal Change control sign for HW request
C C

7 49 Design change 08/20/2004 Compal Change PC115 from 0.022U to 2200P for improve transient 0.2

8 47 Design change 08/20/2004 Compal Change PL7 from 4.7UH_5.2A to 9.5A for design margin 0.2

9 48 Design change 10/04/2004 Compal Change control sign for HW request

10 48 Design change 12/20/2004 Compal Change PR118.PR133 from 0_0603_5% to 3.3_0603_5% and add 4.7_1206_5% on PR144,PR145,680p_0603_50V on PC40 PC41.
for EMI fail

B B

A A

Compal Electronics, Inc.

Title
SCHEMATIC, M/B LA-2492
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401317
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: 星期一, 一月 03, 2005 Sheet 51 of 51
5 4 3 2 1