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Let’s talk about MemoryBIST!

Raghu Aratlakota · Follow
10 min read · Aug 18, 2023

562 5

Design for testability (DFT) is a technique that adds extra logic to a circuit to
improve its testability (Controllability & Observability). This means that we can
control the inputs and observe the outputs of the circuit more easily. It will
make testing easier!

Controllability means the ability to place a value on a node or cell.

One way to achieve controllability is by writing a value in a memory cell. This

operation changes the content of the cell to the desired value, regardless of its
previous value in that cell. To write a value, we need to access it through an
address. By using the address, we can reach the memory cell and write value in
it.

W0 - Writes value 0 in a memory cell.

W1 - Writes value 1 in a memory cell.

Observability means the ability to observe a value from a node or cell.

One way to achieve observability is by reading a value from a memory cell.

There is already an existing value in the memory cell, we have to read that
value. To read that value, we need to access it through an address. By using the
address, we can reach the memory cell and read its value.

R0- Reads value 0 from a memory cell.

R1- Reads value 1 from a memory cell.

Why don’t we perform scan insertion for Memories?

The design will contain both logic part and memory part. In the case of logic,
we add some additional test points & insert SCAN to gain controllability and
observability. How would we achieve controllability and observability in
memory modules?

Before knowing that, we should understand the architecture of memories. For

example, let us consider the following architecture.
By using the address line, we can access any memory cell. Then, by using
read/write signal, we can perform read or write operation on that particular
cell. This gives us flexibility when working with memories.

Memories have a built-in architecture that allows us to write (controllability)

and read (observability) on any cell. So, we don’t need to perform scan for
memories.

Why don’t we perform ATPG for Memories?

1. Both have different set of faults for each i.e., ATPG Faults and Memory
Faults.

2. Pattern length will increase, which will further increase the test time.

3. It will be complex to test the memory faults with D-Algorithm (ATPG).

We proceed further in 3 steps: Problem, Analysis, and Solution.

What is the problem? How to analyze that problem? Finding the solution to that
problem!

PROBLEM: Faulty memories due to presence of memory faults!

ANALYSIS: How can we detect memory faults.

SOLUTION: Design an algorithm that detects all faults in memories.

PROBLEM
“MEMORY FAULTS”

Fault

Logic level representation of a Manufacturing Defect

Types of Memory Fault Models

Stuck-at Fault

Stuck-open Fault.

Transition Fault

Coupling Fault

Address Decoder Fault

Retention Fault

Neighborhood Fault

Memory cell behavior

A memory cell that can perform write operation (W) and read operation (R)
with two possible values: 0 and 1. If the memory cell is normal, it should behave
as follows:
W0, R0: write 0 and read 0.
W1, R1: write 1 and read 1.
W0, R1: write 0 and read 1.
W1, R0: write 1 and read 0.

STUCK-AT FAULT (SAF)

Memory cell is fixed to a logic value 0 or 1.

Stuck-at 0 (SA0):

A memory cell is fixed to a logic value 0. Even if you perform {WO, RO} & {W1,
R1}, It results in output as 0 always.

If the memory cell has SA0 fault, it will behave as follows:

W0, R0: write 0 and read 0.

W1, R1: write 1 and read 0.
W0, R1: write 0 and read 0.
W1, R0: write 1 and read 0.

Stuck-at 1 (SA1):

Memory cell is fixed to a logic value 1. Even if you perform {WO, RO} & {W1,
R1}, It results in output as 1 always.
If the memory cell has SA1 fault, it will behave as follows:

W0, R0: write 0 and read 1.

W1, R1: write 1 and read 1.
W0, R1: write 0 and read 1.
W1, R0: write 1 and read 1.

STUCK-OPEN FAULT (SOF)

Memory fault that occurs due to broken wires. So, we are unable to access that
memory cell which causes data loss.

TRANSITION FAULT (TF)

A Transition fault occurs when a cell fails to change from logic value 0 to 1 or 1
to 0 within a specified time.

There are two types of Transition faults. They are:

1. Slow to rise.

2. Slow to fall.

SLOW TO RISE:

A memory cell unable to rise from logic value 0 to 1 on time.

Slow to rise transition can be detected by performing write 0 (W0) and then
write 1 (W1) in the next cycle. If it is slow to rise, then the read operation will
detect 0 instead of 1.

SLOW TO FALL:

A memory cell unable to fall from logic value 1 to 0 on time.

Slow to fall transition can be detected by performing write 1 (W1) and then
write 0 (W0) in the next cycle. If it is slow to fall, then the read operation will
detect 1 instead of 0.
COUPLING FAULT (CF)

CFs occur when reading or writing in one cell impacts the adjacent cell.

Victim cell: The cell that affected is called victim cell.

Aggressor cell: The cell that is affects is called Aggressor cell.

There are 3 types of Coupling faults. They are:

1. State coupling fault.

2. Idempotent coupling fault.

3. Inversion coupling fault.

STATE COUPLING FAULT:

Read or write in one cell forces the other cell to a logic value of 0 or 1.

W0 or W1 or R0 or R1 operation in one cell may force logic 0 or 1 in another

cell.

INVERSE COUPLING FAULT:

When the transition happens in one cell complements the value in another cell.

Rising {W0 -> W1} or Falling {W1 -> W0} transition in one cell may change A to
A’ in another cell.

IDEMPOTENT COUPLING FAULT:

When transition happens in one memory cell forces a value in another cell.
Rising {W0 -> W1}, Falling {W1 -> W0} transition in one cell may force logic
value 0 or 1 in another cell.

ADDRESS DECODER FAUTLS (ADF)

In our memories, we have one address for one cell. That means a memory cell
can be accessed by only one particular address. If this does not happen in your
memories, then ADF will occur.
a. one address, multiple cells are accessed.

It happens when the address decoder logic mistakenly activates more than one-
word line for a given address, causing multiple memory cells to be accessed
simultaneously. Finally, the data from different cells may interfere with each
other.

b. one address, no cell is accessed.

It is when the address decoder logic fails to activate any word line for a given
address, causing no memory cell to be accessed. Finally, the system cannot read
or write the data from the intended cell.
c. Multiple addresses, no cell is accessed.

It happens when the address decoder logic generates invalid addresses that do
not correspond to any memory cell, causing no memory cell to be accessed. It
will lead to a waste of time by trying to access non-existent cells.

d. Multiple addresses, one cell is accessed.

It happens when the address decoder logic maps more than one address to the
same memory cell, causing the same memory cell to be accessed by multiple
addresses. Finally, the system may read or write different data from the same
cell depending on the address used.
DATA RETENTION FAULTS (DRF)

Unable to retain data in the memory. The logic value will change after some
time. i.e., a memory cell will lose its data over time.

NEIGHBOURHOOD PATTERN SENSITIVE FAULTS (NPSF)

The value of the cell is impacted by the cells around it.

ANALYSIS

MemoryBIST Architecture
MemoryBIST consists of 4 main components:

1. Memory Interface

2. MemoryBIST Controller

3. Memories

4. Comparator

Memory Interface
The memory interface is responsible for connecting the MemoryBIST controller
to the memories.

Each memory has its own memory interface. Memory Interface Logic consists of
Multiplexer logic that selects either the system path or test mode path by
enabling or disabling BIST_EN.

MemoryBIST Controller
The memory BIST controller consists of an FSM (Finite state Machine), Data
generator (DG), Address generator (AG), Control signal generator (CG) &
Comparator logic.

The FSM controls the operation of the MemoryBIST controller according to a

predefined memory algorithm. It controls all data, addresses, and control
signals.

The data generator produces the test data input that is sent to the memories
through the memory interface. The address generator generates the addresses
for accessing the memories. The control signal generator generates the write and
read signals for writing and reading the memories.

Comparator

The comparator logic compares the test response from the memories with the
expected output from the data generator.
How testing will happen with the help of MemoryBIST Controller?

It selects an address from the address generator and sends it to the memory
interface.

It enables the write signal from the control signal generator and sends it to
the memory interface.

It sends a data pattern (0 or 1) from the data generator to the memory

interface, which writes it to the selected address in the memory.

It repeats these steps for different addresses and data patterns until all the
memory locations are written.

Later,

It selects an address from the address generator and sends it to the memory
interface.

It enables the read signal from the control signal generator and sends it to
the memory interface.

It reads back the data from the selected address in the memory through the
memory interface and sends it to the comparator logic.

It repeats these steps for different addresses until all the memory locations
are read and compared.

It compares the read data with the expected output from the data generator
using the comparator logic. If they match, then it indicates that the memory
location is working correctly. If they do not match, then it indicates that there is
a fault in the memory location.

Comparator logic locations:

It has two possible locations. They are:

MBIST Controller location:

Comparator logic can be shared among multiple memories that are tested by the
same controller. The advantage of this location is that it can reduce the area
overhead of the MBIST system, since the gate count of the comparator logic is
minimized.

Memory Interface location:

Each memory has its own dedicated comparator logic. The advantage of this
location is that it can increase the parallelism and speed of the MBIST system,
since multiple memories can be compared simultaneously.
If area is a critical factor, then the MBIST controller location may be preferred.
If performance is a critical factor, then the memory interface location may be
preferred.

SOLUTION
For logic, we generate patterns using ATPG. ATPG uses the D-algorithm to
detect faults and generate patterns. For Memories, how are we able to do this?

We will first learn how to generate patterns for fault models. Later, we build an
algorithm.

Detection of stuck-at:

Place the opposite value on the cell and then read it back to detect the stuck-at.

Stuck at 0: {W1, R1}

Write 1 and then read it back. If the read value is 0, then we have detected a
stuck-at 0 fault.
Stuck at 1: {W0, R0}

Write 0 and then read it back. If the read value is 1, then we have detected a
stuck-at 1 fault.

Detection of the Transition fault:

Slow to Rise: {W0, R0}; {W1, R1}

Detected by the transiting value from 0 to 1. It shows a value of 0 instead of 1 at

the output because it has slowly changed to a logic value of 1.

Slow to Fall: {W1, R1}; {W0, R0}

Detected by transiting a value from 1 to 0. It shows value 1 instead of 0 at the

output because it slowly changes to logic value 0.

Building algorithm

By using this algorithm, it should generate patterns that detect all faults in the
memory.

Stuck at 1: {W0, R0}

Stuck at 0: {W1, R1}

Slow to Rise: {W0, R0}; {W1, R1}

Slow to Fall: {W1, R1}; {W0, R0}

Merging all the detection patterns we get

{W0, R0}; {W1 R1}; {W0 R0}

This pattern will detect all the Stuck-at, and Transition faults.
In this way, algorithms are built to ensure the reliability and quality of memory
devices.

Checkout:

Let’s talk about SCAN!

Let’s talk about Testability!

Scan chain formation

Let’s talk about Clock gaters

References

VLSI Testing and Testability

VLSI test principles and architectures: design for testability, Book by: Cheng-
Wen Wu

Programming Vlsi Dft Tech Technology

Written by Raghu Aratlakota Follow

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