BASIC CONCEPTS

The maximum size of the memory that can be used in any computer is determined
by the addressing scheme.

Address Memory Locations

16 Bit 216 = 64 K
32 Bit 232 = 4G (Giga)
40 Bit 240 = IT (Tera)

Fig: Connection of Memory to Processor:

If MAR is k bits long and MDR is n bits long, then the memory may contain upto
2K addressable locations and the n-bits of data are transferred between the
memory and processor.
This transfer takes place over the processor bus.
The processor bus has,

Address Line
Data Line
Control Line (R/W, MFC Memory Function Completed)

The control line is used for co-ordinating data transfer.

The processor reads the data from the memory by loading the address of the
required memory location into MAR and setting the R/W line to 1.
The memory responds by placing the data from the addressed location onto the
data lines and confirms this action by asserting MFC signal.
Upon receipt of MFC signal, the processor loads the data onto the data lines into
MDR register.
The processor writes the data into the memory location by loading the address of
this location into MAR and loading the data into MDR sets the R/W line to 0.

Memory Access Time It is the time that elapses between the intiation of an
 Operation and the completion of that operation.
Memory Cycle Time It is the minimum time delay that required between the
initiation of the two successive memory operations.

RAM (Random Access Memory):

In RAM, if any location that can be accessed for a Read/Write operation in fixed

Cache Memory:

It is a small, fast memory that is inserted between the larger slower main memory
and the processor.
It holds the currently active segments of a pgm and their data.

Virtual memory:

The address generated by the processor does not directly specify the physical
locations in the memory.
The address generated by the processor is referred to as a virtual / logical address.
The virtual address space is mapped onto the physical memory where data are
actually stored.
The mapping function is implemented by a special memory control circuit is often
called the memory management unit.
Only the active portion of the address space is mapped into locations in the
physical memory.
The remaining virtual addresses are mapped onto the bulk storage devices used,
which are usually magnetic disk.
As the active portion of the virtual address space changes during program
execution, the memory management unit changes the mapping function and
transfers the data between disk and memory.
Thus, during every memory cycle, an address processing mechanism determines
whether the addressed in function is in the physical memory unit.
If it is, then the proper word is accessed and execution proceeds.
If it is not, a page of words containing the desired word is transferred from disk to
memory.
This page displaces some page in the memory that is currently inactive.

SEMI CONDUCTOR RAM MEMORIES:

Semi-Conductor memories are available is a wide range of speeds.
Their cycle time ranges from 100ns to 10ns
INTERNAL ORGANIZATION OF MEMORY CHIPS:

Memory cells are usually organized in the form of array, in which each cell is
capable of storing one bit of in formation.
Each row of cells constitute a memory word and all cells of a row are connected
to a common line called as word line.
The cells in each column are connected to Sense / Write circuit by two bit lines.
The Sense / Write circuits are connected to data input or output lines of the chip.
During a write operation, the sense / write circuit receive input information and
store it in the cells of the selected word.

Fig: Organization of bit cells in a memory chip

The data input and data output of each senses / write ckt are connected to a single
bidirectional data line that can be connected to a data bus of the cptr.

R/W Specifies the required operation.

CS Chip Select input selects a given chip in the multi-chip memory system

Requirement of external
Bit Organization connection for address, data and
control lines
128 (16x8) 14
(1024) 128x8(1k) 19
Static Memories:

Memories that consists of circuits capable of retaining their state as long as power is
applied are known as static memory.

Fig:Static RAM cell

Two inverters are cross connected to form a batch

The batch is connected to two bit lines by transistors T1 and T2.
These transistors act as switches that can be opened / closed under the control of
the word line.
When the wordline is at ground level, the transistors are turned off and the latch
retain its state.

Read Operation:

In order to read the state of the SRAM cell, the word line is activated to close
switches T1 and T2.
If the cell is in state 1, the signal on bit line b is high and the signal on the bit line
b is low.Thus b and b are complement of each other.
Sense / write circuit at the end o
the output accordingly.
Write Operation:

The state of the cell is set by placing the appropriate value on bit line b and its
complement on b and then activating the word line. This forces the cell into the
corresponding state.
The required signal on the bit lines are generated by Sense / Write circuit.
Fig:CMOS cell (Complementary Metal oxide Semi Conductor):
 Transistor pairs (T3, T5) and (T4, T6) form the inverters in the latch.
In state 1, the voltage at point X is high by having T5, T6 on and T4, T5 are OFF.
Thus T1, and T2 returned ON (Closed), bit line b and b will have high and low
signals respectively.
The CMOS requires 5V (in older version) or 3.3.V (in new version) of power
supply voltage.
The continuous power is needed for the cell to retain its state
Merit :

It has low power consumption because the current flows in the cell only when the
cell is being activated accessed.
econds.

Demerit:

power is interrupted.

Asynchronous DRAMS:-

cannot retain their state indefinitely. Hence they are called

(DRAM).
The information stored in a dynamic memory cell in the form of a charge on a
capacitor and this charge can be maintained only for tens of Milliseconds.
The contents must be periodically refreshed by restoring by restoring this
capacitor charge to its full value.

Fig:A single transistor dynamic Memory cell

appropriate voltage is applied to the bit line, which charges the capacitor.
After the transistor is turned off, the capacitor begins to discharge which is caused

Hence the information stored in the cell can be retrieved correctly before the
threshold value of the capacitor drops down.
 connected to the bit line detects whether the charge on the capacitor is above the
threshold value.

If charge on capacitor > threshold value -> Bit line will have log
If charge on capacitor < threshold value -

Fig:Internal organization of a 2M X 8 dynamic Memory chip.

DESCRIPTION:

The 4 bit cells in each row are divided into 512 groups of 8.
21 bit address is needed to access a byte in the memory(12 bit To select a row,9
bit Specify the group of 8 bits in the selected row).

A8-0 Row address of a byte.

A20-9 Column address of a byte.

During Read/ Write operation ,the row address is applied first. It is loaded into the
row address latch in response to a signal pulse on Row Address Strobe(RAS)
input of the chip.
When a Read operation is initiated, all cells on the selected row are read and
refreshed.
Shortly after the row address is loaded,the column address is applied to the
address pins & loaded into Column Address Strobe(CAS).
The information in this latch is decoded and the appropriate group of 8
Sense/Write circuits are selected.
R/W =1(read operation) The output values of the selected circuits are
transferred to the data lines D0 - D7.
R/W =0(write operation) The information on D0 - D7 are transferred to the
selected circuits.
 RAS and CAS are active low so that they cause the latching of address when they
change from high to low. This is because they are indicated by RAS & CAS.

be accessed periodically.
Refresh operation usually perform this function automatically.
A specialized memory controller circuit provides the necessary control signals
RAS & CAS, that govern the timing.
The processor must take into account the delay in the response of the memory.
Such memories are referred to as

Fast Page Mode:

Transferring the bytes in sequential order is achieved by applying the consecutive

sequence of column address under the control of successive CAS signals.
This scheme allows transferring a block of data at a faster rate. The block of
transfer capability is called as Fast Page Mode.
Synchronous DRAM:

Here the operations e directly synchronized with clock signal.

The address and data connections are buffered by means of registers.
The output of each sense amplifier is connected to a latch.
A Read operation causes the contents of all cells in the selected row to be loaded
in these latches.
Fig:Synchronous DRAM
 Data held in the latches that correspond to the selected columns are transferred
into the data output register, thus becoming available on the data output pins.

Fig:Timing Diagram Burst Read of Length 4 in an SDRAM

First ,the row address is latched under control of RAS signal.

The memory typically takes 2 or 3 clock cycles to activate the selected row.
Then the column address is latched under the control of CAS signal.
After a delay of one clock cycle,the first set of data bits is placed on the data lines.
The SDRAM automatically increments the column address to access the next 3
sets of bits in the selected row, which are placed on the data lines in the next 3
clock cycles.

Latency & Bandwidth:

A good indication of performance is given by two parameters.They are,

Latency
Bandwidth
Latency:

It refers to the amount of time it takes to transfer a word of data to or from the
memory.
For a transfer of single word,the latency provides the complete indication of
memory performance.
For a block transfer,the latency denote the time it takes to transfer the first word
of data.
Bandwidth:

It is defined as the number of bits or bytes that can be transferred in one second.
 Bandwidth mainly depends upon the speed of access to the stored data & on the
number of bits that can be accessed in parallel.

Double Data Rate SDRAM(DDR-SDRAM):

The standard SDRAM performs all actions on the rising edge of the clock signal.
The double data rate SDRAM transfer data on both the edges(loading edge,
trailing edge).
The Bandwidth of DDR-SDRAM is doubled for long burst transfer.
To make it possible to access the data at high rate , the cell array is organized into
two banks.
Each bank can be accessed separately.
Consecutive words of a given block are stored in different banks.
Such interleaving of words allows simultaneous access to two words that are
transferred on successive edge of the clock.

Larger Memories:

Dynamic Memory System:

The physical implementation is done in the form of Memory Modules.

If a large memory is built by placing DRAM chips directly on the main system
printed circuit board that contains the processor ,often referred to as
Motherboard;it will occupy large amount of space on the board.
These packaging consideration have led to the development of larger memory

SIMM-Single Inline memory Module

DIMM-Dual Inline memory Module

SIMM & DIMM consists of several memory chips on a separate small board that
plugs vertically into single socket on the motherboard.

MEMORY SYSTEM CONSIDERATION:

To reduce the number of pins, the dynamic memory chips use multiplexed
address inputs.
The address is divided into two parts.They are,

High Order Address Bit(Select a row in cell array & it is provided first
and latched into memory chips under the control of RAS signal).
Low Order Address Bit(Selects a column and they are provided on same
address pins and latched using CAS signals).

The Multiplexing of address bit is usually done by Memory Controller Circuit.

 Fig:Use of Memory Controller

The Controller accepts a complete address & R/W signal from the processor,
under the control of a Request signal which indicates that a memory access
operation is needed.
The Controller then forwards the row & column portions of the address to the
memory and generates RAS &CAS signals.
It also sends R/W &CS signals to the memory.
The CS signal is usually active low, hence it is shown as CS.

Refresh Overhead:

All dynamic memories have to be refreshed.

In DRAM ,the period for refreshing all rows is 16ms whereas 64ms in SDRAM.

Eg:Given a cell array of 8K(8192).

Clock cycle=4
Clock Rate=133MHZ
No of cycles to refresh all rows =8192*4
=32,768
Time needed to refresh all rows=32768/133*106
=246*10-6 sec
=0.246sec
Refresh Overhead =0.246/64
Refresh Overhead =0.0038

Rambus Memory:

The usage of wide bus is expensive.

Rambus developed the implementation of narrow bus.
Rambus technology is a fast signaling method used to transfer information
between chips.
 Instead of using signals that have voltage levels of either 0 or Vsupply to represent
the logical values, the signals consists of much smaller voltage swings around a
reference voltage Vref.
.The reference Voltage is about 2V and the two logical values are represented by
0.3V swings above and below Vref..
This type of signaling is generally is known as Differential Signalling.
Rambus provides a complete specification for the design of communication
links(Special Interface circuits) called as Rambus Channel.
Rambus memory has a clock frequency of 400MHZ.
The data are transmitted on both the edges of the clock so that the effective data
transfer rate is 800MHZ.
The circuitry needed to interface to the Rambus channel is included on the
RAM).
Rambus channel has,

9 Data lines(1-8 Transfer the data,9th line Parity checking).

Control line
Power line

A two channel rambus has 18 data lines which has no separate address lines.It is
also called as
Communication between processor or some other device that can serves as a
master and RDRAM modules are serves as slaves ,is carried out by means of
packets transmitted on the data lines.
There are 3 types of packets.They are,

Request
Acknowledge
Data

READ ONLY MEMORY:

Both SRAM and DRAM chips are volatile,which means that they lose the stored
information if power is turned off.
Many application requires Non-volatile memory (which retain the stored
information if power is turned off).
Eg:Operating System software has to be loaded from disk to memory which
requires the program that boots the Operating System ie. It requires non-volatile
memory.
Non-volatile memory is used in embedded system.
Since the normal operation involves only reading of stored data ,a memory of this
type is called ROM.
Fig:ROM cell

Transistor(T) is connected to the ground point(P).

Transistor switch is closed & voltage on bitline nearly drops to zero.
Transistor switch is open.
The bitline remains at high voltage.

To read the state of the cell,the word line is activated.

A Sense circuit at the end of the bitline generates the proper output value.

Types of ROM:

Different types of non-volatile memory are,

PROM
EPROM
EEPROM
Flash Memory

PROM:-Programmable ROM:

PROM allows the data to be loaded by the user.

The u
locations using high-current pulse.
This process is irreversible.

Merit:
It provides flexibility.
It is faster.
It is less expensive because they can be programmed directly by the user.

EPROM:-Erasable reprogrammable ROM:

EPROM allows the stored data to be erased and new data to be loaded.
 transistor is used, which has the ability to function either as a normal transistor or

This transistor can be programmed to behave as a permanently open switch, by

injecting charge into it that becomes trapped inside.
Erasure requires dissipating the charges trapped in the transistor of memory cells.
This can be done by exposing the chip to ultra-violet light, so that EPROM chips
are mounted in packages that have transparent windows.
Merits:
It provides flexibility during the development phase of digital system.
It is capable of retaining the stored information for a long time.

Demerits:
The chip must be physically removed from the circuit for reprogramming and its
entire contents are erased by UV light.

EEPROM:-Electrically Erasable ROM:

Merits:
It can be both programmed and erased electrically.
It allows the erasing of all cell contents selectively.
Demerits:
It requires different voltage for erasing ,writing and reading the stored data.

Flash Memory:

In EEPROM, it is possible to read & write the contents of a single cell.

In Flash device, it is possible to read the contents of a single cell but it is only
possible to write the entire contents of a block.
Prior to writing,the previous contents of the block are erased.
Eg.In MP3 player,the flash memory stores the data that represents sound.
Single flash chips cannot provide sufficient storage capacity for embedded system
application.
There are 2 methods for implementing larger memory modules consisting of
number of chips.They are,
Flash Cards
Flash Drives.
Merits:
Flash drives have greater density which leads to higher capacity & low cost per
bit.
It requires single power supply voltage & consumes less power in their operation.

Flash Cards:
One way of constructing larger module is to mount flash chips on a small card.
Such flash card have standard interface.
 The card is simply plugged into a conveniently accessible slot.
Its memory size are of 8,32,64MB.
Eg:A minute of music can be stored in 1MB of memory. Hence 64MB flash cards
can store an hour of music.

Flash Drives:

Larger flash memory module can be developed by replacing the hard disk drive.
The flash drives are designed to fully emulate the hard disk.
The flash drives are solid state electronic devices that have no movable parts.
Merits:
They have shorter seek and access time which results in faster response.
They have low power consumption which makes them attractive for battery
driven application.
They are insensitive to vibration.
Demerit:
The capacity of flash drive (<1GB) is less than hard disk(>1GB).
It leads to higher cost perbit.
Flash memory will deteriorate after it has been written a number of
times(typically atleast 1 million times.)

SPEED,SIZE COST:
Characteristics SRAM DRAM Magnetis Disk
Speed Very Fast Slower Much slower than
DRAM
Size Large Small Small
Cost Expensive Less Expensive Low price

Magnetic Disk:
A huge amount of cost effective storage can be provided by magnetic disk;The

smaller units where speed is of essence.

Memory Speed Size Cost

Registers Very high Lower Very Lower
Primary cache High Lower Low
Secondary cache Low Low Low
Main memory Lower than High High
Seconadry cache
Secondary Very low Very High Very High
Memory
Fig:Memory Hierarchy

Types of Cache Memory:

The Cache memory is of 2 types.They are,

Primary /Processor Cache(Level1 or L1 cache)
Secondary Cache(Level2 or L2 cache)

Primary Cache It is always located on the processor chip.

Secondary Cache It is placed between the primary cache and the rest of the memory.

The main memory is implemented using the dynamic

components(SIMM,RIMM,DIMM).
The access time for main memory is about 10 times longer than the access time
for L1 cache.

CACHE MEMORIES
The effectiveness of cache mechanism is ba Locality of

Locality of Reference:
Many instructions in the localized areas of the program are executed repeatedly
during some time period and remainder of the program is accessed relatively
infrequently.
It manifests itself in 2 ways.They are,
Temporal(The recently executed instruction are likely to be executed again
very soon.)
Spatial(The instructions in close proximity to recently executed instruction
are also likely to be executed soon.)
If the active segment of the program is placed in cache memory, then the total
execution time can be reduced significantly.
 The term Block refers to the set of contiguous address locations of some size.
The cache line is used to refer to the cache block.
Fig:Use of Cache Memory

The Cache memory stores a reasonable number of blocks at a given time but this
number is small compared to the total number of blocks available in Main
Memory.
The correspondence between main memory block and the block in cache memory
is specified by a mapping function.
The Cache control hardware decide that which block should be removed to create
space for the new block that contains the referenced word.
The collection of rule for making this decision is called the replacement
algorithm.
The cache control circuit determines whether the requested word currently exists
in the cache.
If it exists, then Read/Write operation will take place on appropriate cache
location. In this case Read/Write hit will occur.
In a Read operation, the memory will not involve.
The write operation is proceed in 2 ways.They are,

Write-through protocol
Write-back protocol
Write-through protocol:

Here the cache location and the main memory locations are updated
simultaneously.

Write-back protocol:

This technique is to update only the cache location and to mark it as with
associated flag bit called dirty/modified bit.
The word in the main memory will be updated later,when the block containing
this marked word is to be removed from the cache to make room for a new block.
If the requested word currently not exists in the cache during read operation,then
read miss will occur.
To overcome the read miss Load through / Early restart protocol is used.
Read Miss:
The block of words that contains the requested word is copied from the main memory
into cache.
Load through:
After the entire block is loaded into cache,the particular word requested is
forwarded to the processor.
If the requested word not exists in the cache during write operation,then Write
Miss will occur.
If Write through protocol is used,the information is written directly into main
memory.
If Write back protocol is used then block containing the addressed word is first
brought intothe cache and then the desired word in the cache is over-written with
the new information.

Mapping Function:
Direct Mapping:
It is the simplest technique in which block j of the main memory maps onto block

Thus whenever one of the main memory blocks 0,128,256 is loaded in the cache,it
is stored in block 0.
Block 1,129,257 are stored in cache block 1 and so on.
The contention may arise when,
When the cache is full
When more than one memory block is mapped onto a given cache block
position.
The contention is resolved by allowing the new blocks to overwrite the currently
resident block.
Placement of block in the cache is determined from memory address.
Fig: Direct Mapped Cache
 The memory address is divided into 3 fields.They are,

Low Order 4 bit field(word) Selects one of 16 words in a block.

7 bit cache block field When new block enters cache,7 bit determines the cache
position in which this block must be stored.
5 bit Tag field The high order 5 bits of the memory address of the block is
stored in 5 tag bits associated with its location in the cache.
As execution proceeds, the high order 5 bits of the address is compared with tag
bits associated with that cache location.
If they match,then the desired word is in that block of the cache.
If there is no match,then the block containing the required word must be first read
from the main memory and loaded into the cache.
Merit:
It is easy to implement.
Demerit:
It is not very flexible.

Associative Mapping:
In this method, the main memory block can be placed into any cache block position.

Fig:Associative Mapped Cache.

12 tag bits will identify a memory block when it is resolved in the cache.
The tag bits of an address received from the processor are compared to the tag bits
of each block of the cache to see if the desired block is persent.This is called
associative mapping.
It gives complete freedom in choosing the cache location.
A new block that has to be brought into the cache has to replace(eject)an existing
block if the cache is full.
 In this method,the memory has to determine whether a given block is in the cache.
A search of this kind is called an associative Search.
Merit:
It is more flexible than direct mapping technique.
Demerit:
Its cost is high.

Set-Associative Mapping:
It is the combination of direct and associative mapping.
The blocks of the cache are grouped into sets and the mapping allows a block of
the main memory to reside in any block of the specified set.
In this case,the cache has two blocks per set,so the memory blocks

block position within the set.

6 bit set field Determines which set of cache contains the desired block .
6 bit tag field The tag field of the address is compared to the tags of the two blocks of
the set to clock if the desired block is present.

Fig: Set-Associative Mapping:

No of blocks per set no of set field

2 6
3 5
8 4
128 no set field
 The cache which contains 1 block per set is called direct Mapping.
k-way set associative cache
Each block contains a control bit called a valid bit.
The Valid bit indicates that whether the block contains valid data.
The dirty bit indicates that whether the block has been modified during its cache
residency.
Valid bit=0 When power is initially applied to system
Valid bit =1 When the block is loaded from main memory at first time.
If the main memory block is updated by a source & if the block in the source is

If Processor & DMA uses the same copies of data then it is called as the Cache
Coherence Problem.
Merit:
The Contention problem of direct mapping is solved by having few choices for
block placement.
The hardware cost is decreased by reducing the size of associative search.

Replacement Algorithm:
In direct mapping, the position of each block is pre-determined and there is no
need of replacement strategy.
In associative & set associative method,the block position is not pre-
determined;ie..when the cache is full and if new blocks are brought into the cache,
then the cache controller must decide which of the old blocks has to be replaced.
Therefore,when a block is to be over-written,it is sensible to over-write the one
that has gone the longest time without being referenced.This block is called Least
recently Used(LRU) block & the technique is called LRU algorithm.
The cache controller track the references to all blocks with the help of block
counter.
Eg:

Consider 4 blocks/set in set associative cache,

2 bit counter can be used for each block.
When a occurs,then block counter=0;The counter with values originally
lower than the referenced one are incremented by 1 & all others remain
unchanged.
When a occurs & if the set is full,the blocks with the counter value 3 is

block counters are incremented by 1.

Merit:
The performance of LRU algorithm is improved by randomness in deciding
which block is to be over-written.
PERFORMANCE CONSIDERATION:
Two Key factors in the commercial success are the performance & cost ie the best
possible performance at low cost.
A common measure of success is called the Pricel Performance ratio.
Performance depends on how fast the machine instruction are brought to the
processor and how fast they are executed.
To achieve parallelism(ie. Both the slow and fast units are accessed in the same
manner),interleaving is used.

Interleaving:
Fig:Consecutive words in a Module

VIRTUAL MEMORY:
Techniques that automatically move program and data blocks into the physical
main memory when they are required for execution is called the Virtual
Memory.
The binary address that the processor issues either for instruction or data are
called the virtual / Logical address.
The virtual address is translated into physical address by a combination of
hardware and software components.This kind of address translation is done by
MMU(Memory Management Unit).
When the desired data are in the main memory ,these data are fetched /accessed
immediately.
If the data are not in the main memory,the MMU causes the Operating system to
bring the data into memory from the disk.
 Transfer of data between disk and main memory is performed using DMA
scheme.

Fig:Virtual Memory Organisation

Address Translation:

In address translation,all programs and data are composed of fixed length units
called Pages.
The Page consists of a block of words that occupy contiguous locations in the
main memory.
The pages are commonly range from 2K to 16K bytes in length.
The cache bridge speed up the gap between main memory and secondary storage
and it is implemented in software techniques.
Each virtual address generated by the processor contains virtual Page
number(Low order bit) and offset(High order bit)
Virtual Page number+ Offset Specifies the location of a particular byte (or word) within
a page.
Page Table:

It contains the information about the main memory address where the page is
stored & the current status of the page.
Page Frame:

An area in the main memory that holds one page is called the page frame.
Page Table Base Register:
 It contains the starting address of the page table.

Virtual Page Number+Page Table Base register Gives the address of the
corresponding entry in the page table.ie)it gives the starting address of the page if that
page currently resides in memory.

Control Bits in Page Table:

The Control bits specifies the status of the page while it is in main memory.
Function:

The control bit indicates the validity of the page ie)it checks whether the page is
actually loaded in the main memory.
It also indicates that whether the page has been modified during its residency in
the memory;this information is needed to determine whether the page should be
written back to the disk before it is removed from the main memory to make room
for another page.

Fig:Virtual Memory Address Translation

The Page table information is used by MMU for every read & write access.
The Page table is placed in the main memory but a copy of the small portion of
the page table is located within MMU.
This small portion or small cache is called Translation LookAside Buffer(TLB).
This portion consists of the page table enteries that corresponds to the most
recently accessed pages and also contains the virtual address of the entry.
Fig:Use of Associative Mapped TLB

When the operating system changes the contents of page table ,the control bit in
TLB will invalidate the corresponding entry in the TLB.
Given a virtual address,the MMU looks in TLB for the referenced page.
If the page table entry for this page is found in TLB,the physical address is
obtained immediately.
If there is a miss in TLB,then the required entry is obtained from the page table in
the main memory & TLB is updated.
When a program generates an access request to a page that is not in the main
memory ,then Page Fault will occur.
The whole page must be broght from disk into memry before an access can
proceed.
When it detects a page fault,the MMU asks the operating system to generate an
interrupt.
The operating System suspend the execution of the task that caused the page fault
and begin execution of another task whose pages are in main memory because the
long delay occurs while page transfer takes place.
When the task resumes,either the interrupted instruction must continue from the
point of interruption or the instruction must be restarted.
If a new page is brought from the disk when the main memory is full,it must
replace one of the resident pages.In that case,it uses LRU algorithm which
removes the least referenced Page.
 A modified page has to be written back to the disk before it is removed from the
main memory. In that case,write through protocol is used.

MEMORY MANAGEMENT REQUIREMENTS:

Management routines are part of the Operating system.
System Space
The virtual space in which the use User
.
Each user space has a separate page table.
The MMU uses the page table to determine the address of the table to be used in
the translation process.
Hence by changing the contents of this register, the OS can switch from one space
to another.
The process has two stages. They are,
User State
Supervisor state.
User State:
In this state,the processor executes the user program.
Supervisor State:
When the processor executes the operating system routines,the processor will be
in supervisor state.
Privileged Instruction:
In user state,the machine instructions cannot be executed.Hence a user program is
prevented from accessing the page table of other user spaces or system spaces.
The control bits in each entry can be set to control the access privileges granted to
each program.
Ie)One program may be allowed to read/write a given page,while the other
programs may be given only red access.

SECONDARY STORAGE:
The Semi-conductor memories donot provide all the storage capability.
The Secondary storage devices provide larger storage requirements.
Some of the Secondary Storage devices are,
Magnetic Disk
Optical Disk
Magnetic Tapes.

Magnetic Disk:
Magnetic Disk system consists o one or more disk mounted on a common spindle.
A thin magnetic film is deposited on each disk, usually on both sides.
ACCESSING I/O DEVICES
A simple arrangement to connect I/O devices to a computer is to use a single bus
structure. It consists of three sets of lines to carry
Address
Data
Control Signals.
When the processor places a particular address on address lines, the devices that
recognize this address responds to the command issued on the control lines.
The processor request either a read or write operation and the requested data are
transferred over the data lines.
When I/O devices & memory share the same address space, the arrangement is called
memory mapped I/O.

Single Bus Structure

Processor Memory

Bus

I/O device 1 I/O device n

Eg:-

Move DATAIN, Ro Reads the data from DATAIN then into processor register Ro.
Move Ro, DATAOUT Send the contents of register Ro to location DATAOUT.
DATAIN Input buffer associated with keyboard.
DATAOUT Output data buffer of a display unit / printer.

Fig: I/O Interface for an Input Device

Address line
Data line
Control line

Address Control Data & status I/O interface

decoder circuits register

Input device.
Address Decoder:

It enables the device to recognize its address when the address appears on address
lines.

Data register It holds the data being transferred to or from the processor.
Status register It contains infn/. Relevant to the operation of the I/O devices.

The address decoder, data & status registers and the control circuitry required to
co-
For an input device, SIN status flag in used SIN = 1, when a character is entered
at the keyboard.
For an output device, SOUT status flag is used SIN = 0, once the char is read by
processor.

Eg

DIR Q Interrupt Request for display.

KIR Q Interrupt Request for keyboard.
KEN keyboard enable.
DEN Display Enable.
SIN, SOUT status flags.

The data from the keyboard are made available in the DATAIN register & the data sent to
the display are stored in DATAOUT register.

Program:
WAIT K Move # Line, Ro
Test Bit #0, STATUS
Branch = 0 WAIT K
Move DATAIN, R1
WAIT D Test Bit #1, STATUS
Branch = 0 WAIT D
Move R1, DATAOUT
Move R1, (Ro)+
Compare #OD, R1
Branch = 0 WAIT K
Move #DOA, DATAOUT
Call PROCESS
EXPLANATION:
This program, reads a line of characters from the keyboard & stores it in a
memory buffer starting at locations LINE.

As each character is read, it is echoed back to the display.

Register Ro is used as a updated using Auto increment mode so that successive
characters are stored in successive memory location.
Each character is checked to see if there is carriage return (CR), char, which has
the ASCII code 0D(hex).
If it is, a line feed character (on) is sent to more the cursor one line down on the
display & subroutine PROCESS is called. Otherwise, the program loops back to
wait for another character from the keyboard.

PROGRAM CONTROLLED I/O

Here the processor repeatedly checks a status flag to achieve the required
synchronization between Processor & I/O device.(ie) the processor polls the device.

There are 2 mechanisms to handle I/o operations. They are,

Interrupt, -
DMA (Synchronization is achieved by having I/O device send special over
the bus where is ready for data transfer operation)

DMA:

Synchronization is achieved by having I/O device send special over the bus where
is ready for data transfer operation)
It is a technique used for high speed I/O device.
Here, the input device transfer data directly to or from the memory without
continuous involvement by the processor.
INTERRUPTS
When a program enters a wait loop, it will repeatedly check the device status.
During this period, the processor will not perform any function.
The Interrupt request line will send a hardware signal called the interrupt signal to
the processor.
On receiving this signal, the processor will perform the useful function during the
waiting period.
The routine executed in response to an interrupt request is called Interrupt
Service Routine.
The interrupt resembles the subroutine calls.

Fig:Transfer of control through the use of interrupts

The processor first completes the execution of instruction i Then it loads the
PC(Program Counter) with the address of the first instruction of the ISR.
After the execution of ISR, the processor has to come back to instruction i + 1.
Therefore, when an interrupt occurs, the current contents of PC which point to i
+1 is put in temporary storage in a known location.
A return from interrupt instruction at the end of ISR reloads the PC from that
temporary storage location, causing the execution to resume at instruction i+1.
When the processor is handling the interrupts, it must inform the device that its
request has been recognized so that it remove its interrupt requests signal.
This may be accomplished by a special control signal called the interrupt
acknowledge signal.
The task of saving and restoring the information can be done automatically by the
processor.
The processor saves only the contents of program counter & status register (ie)
it saves only the minimal amount of information to maintain the integrity of the
program execution.
 Saving registers also increases the delay between the time an interrupt request is
received and the start of the execution of the ISR. This delay is called the
Interrupt Latency.
Generally, the long interrupt latency in unacceptable.
The concept of interrupts is used in Operating System and in Control
Applications, where processing of certain routines must be accurately timed
relative to external events. This application is also called as real-time processing.

Interrupt Hardware:

Fig:An equivalent circuit for an open drain bus used to implement a common
interrupt request line

connected to the line via switches to ground.

To request an interrupt, a device closes its associated switch, the voltage on INTR
line drops to 0(zero).
If all the interrupt request signals (INTR1 to INTRn) are inactive, all switches are
open and the voltage on INTR line is equal to Vdd.
When a device requests an interrupts, the value of INTR is the logical OR of the
requests from individual devices.

(ie)

INTR It is used to name the INTR signal on common line it is active in the low
voltage state.

Open collector (bipolar ckt) or Open drain (MOS circuits) is used to drive INTR
line.
The Output of the Open collector (or) Open drain control is equal to a switch to
the ground that is open wh

pull-up resistor because it pulls the line voltage upto the

high voltage state when the switches are open.
Enabling and Disabling Interrupts:

The arrival of an interrupt request from an external device causes the processor to
suspend the execution of one program & start the execution of another because
the interrupt may alter the sequence of events to be executed.
INTR is active during the execution of Interrupt Service Routine.
There are 3 mechanisms to solve the problem of infinite loop which occurs due to
successive interruptions of active INTR signals.
The following are the typical scenario.

The device raises an interrupt request.

The processor interrupts the program currently being executed.
Interrupts are disabled by changing the control bits is PS (Processor Status
register)
The device is informed that its request has been recognized & in response, it
deactivates the INTR signal.
The actions are enabled & execution of the interrupted program is resumed.
Edge-triggered:

The processor has a special interrupt request line for which the interrupt handling
circuit responds only to the leading edge of the signal. Such a line said to be edge-
triggered.

Handling Multiple Devices:

When several devices requests interrupt at the same time, it raises some questions.
They are.

How can the processor recognize the device requesting an interrupt?

Given that the different devices are likely to require different ISR, how
can the processor obtain the starting address of the appropriate routines in
each case?
Should a device be allowed to interrupt the processor while another
interrupt is being serviced?
How should two or more simultaneous interrupt requests be handled?

Polling Scheme:

If two devices have activated the interrupt request line, the ISR for the selected
device (first device) will be completed & then the second request can be serviced.
The simplest way to identify the interrupting device is to have the ISR polls all
the encountered with the IRQ bit set is the device to be serviced
IRQ (Interrupt Request) -> when a device raises an interrupt requests, the status
register IRQ is set to 1.
Merit:
 It is easy to implement.
Demerit:
The time spent for interrogating the IRQ bits of all the devices that may not be
requesting any service.

Vectored Interrupt:

Here the device requesting an interrupt may identify itself to the processor by
sending a special code over the bus & then the processor start executing the ISR.
The code supplied by the processor indicates the starting address of the ISR for
the device.
The code length ranges from 4 to 8 bits.
The location pointed to by the interrupting device is used to store the staring
address to ISR.
The processor reads this address, called the interrupt vector & loads into PC.
The interrupt vector also includes a new value for the Processor Status Register.
When the processor is ready to receive the interrupt vector code, it activate the
interrupt acknowledge (INTA) line.

Interrupt Nesting:
Multiple Priority Scheme:

In multiple level priority scheme, we assign a priority level to the processor that
can be changed under program control.
The priority level of the processor is the priority of the program that is currently
being executed.
The processor accepts interrupts only from devices that have priorities higher than
its own.
At the time the execution of an ISR for some device is started, the priority of the
processor is raised to that of the device.
The action disables interrupts from devices at the same level of priority or lower.

Privileged Instruction:

The processor priority is usually encoded in a few bits of the Processor Status
word. It can also be changed by program instruction & then it is write into PS.
These instructions are called privileged instruction. This can be executed only
when the processor is in supervisor mode.
The processor is in supervisor mode only when executing OS routines.
It switches to the user mode before beginning to execute application program.

Privileged Exception:

User program cannot accidently or intentionally change the priority of the

processor & disrupts the system operation.
 An attempt to execute a privileged instruction while in user mode, leads to a
special type of interrupt called the privileged exception.

Fig: Implementation of Interrupt Priority using individual Interrupt request

acknowledge lines

Each of the interrupt request line is assigned a different priority level.

Interrupt request received over these lines are sent to a priority arbitration circuit
in the processor.
A request is accepted only if it has a higher priority level than that currently
assigned to the processor,

Simultaneous Requests:
Daisy Chain:

The interrupt request line INTR is common to all devices. The interrupt
acknowledge line INTA is connected in a daisy chain fashion such that INTA
signal propagates serially through the devices.
When several devices raise an interrupt request, the INTR is activated & the
processor responds by setting INTA line to 1. this signal is received by device.
 Device1 passes the signal on to device2 only if it does not require any service.
If devices1 has a pending request for interrupt blocks that INTA signal &
proceeds to put its identification code on the data lines.
Therefore, the device that is electrically closest to the processor has the highest
priority.

Merits:
It requires fewer wires than the individual connections.

Arrangement of Priority Groups:

Here the devices are organized in groups & each group is connected at a different
priority level.
Within a group, devices are connected in a daisy chain.

Controlling Device Requests:

KEN Keyboard Interrupt Enable

DEN Display Interrupt Enable
KIRQ / DIRQ Keyboard / Display unit requesting an interrupt.

There are two mechanism for controlling interrupt requests.

At the devices end, an interrupt enable bit in a control register determines whether
the device is allowed to generate an interrupt requests.
At the processor end, either an interrupt enable bit in the PS (Processor Status) or
a priority structure determines whether a given interrupt requests will be accepted.

Initiating the Interrupt Process:

Load the starting address of ISR in location INTVEC (vectored interrupt).

Load the address LINE in a memory location PNTR. The ISR will use this
location as a pointer to store the i/p characters in the memory.
Enable the keyboard interrupts by setting bit 2 in register CONTROL to 1.
Enable interrupts in the processor by setting to 1, the IE bit in the processor status
register PS.

Exception of ISR:

Read the input characters from the keyboard input data register. This will cause
the interface circuits to remove its interrupt requests.
Store the characters in a memory location pointed to by PNTR & increment
PNTR.
When the end of line is reached, disable keyboard interrupt & inform program
main.
Return from interrupt.
Exceptions:

An interrupt is an event that causes the execution of one program to be suspended

and the execution of another program to begin.
The Exception is used to refer to any event that causes an interruption.

Kinds of exception:

Recovery from errors

Debugging
Privileged Exception

Recovery From Errors:

Computers have error-checking code in Main Memory , which allows detection of
errors in the stored data.
If an error occurs, the control hardware detects it informs the processor by raising
an interrupt.
The processor also interrupts the program, if it detects an error or an unusual
condition while executing the instance (ie) it suspends the program being
executed and starts an execution service routine.
This routine takes appropriate action to recover from the error.

Debugging:

System software has a program called debugger, which helps to find errors in a
program.
The debugger uses exceptions to provide two important facilities
They are
Trace
Breakpoint

Trace Mode:

When processor is in trace mode , an exception occurs after execution of every

instance using the debugging program as the exception service routine.
The debugging program examine the contents of registers, memory location etc.
On return from the debugging program the next instance in the program being
debugged is executed
The trace exception is disabled during the execution of the debugging program.

Break point:

Here the program being debugged is interrupted only at specific points selected by
the user.
 An instance called the Trap (or) software interrupt is usually provided for this
purpose.
While debugging the user may interrup
When the program is executed and reaches that point it examine the memory and
register contents.

Privileged Exception:

To protect the OS of a computer from being corrupted by user program certain

instance can be executed only when the processor is in supervisor mode. These
are called privileged exceptions.
When the processor is in user mode, it will not execute instance (ie) when the
processor is in supervisor mode , it will execute instance.
DIRECT MEMORY ACCESS
A special control unit may be provided to allow the transfer of large block of data
at high speed directly between the external device and main memory , without
continous intervention by the processor. This approach is called DMA.
DMA transfers are performed by a control circuit called the DMA Controller.
To initiate the transfer of a block of words , the processor sends,

Starting address
Number of words in the block
Direction of transfer.
When a block of data is transferred , the DMA controller increment the memory
address for successive words and keep track of number of words and it also informs
the processor by raising an interrupt signal.
While DMA control is taking place, the program requested the transfer cannot
continue and the processor can be used to execute another program.
After DMA transfer is completed, the processor returns to the program that requested
the transfer.
Fig:Registes in a DMA Interface

31 30 1 0
Status &
Control Flag

IRQ Done

IE

Starting Address

Word Count
R/W Determines the direction of transfer .
When
R/W =1, DMA controller read data from memory to I/O device.
R/W =0, DMA controller perform write operation.
Done Flag=1, the controller has completed transferring a block of data and is
ready to receive another command.
IE=1, it causes the controller to raise an interrupt (interrupt Enabled) after it has
completed transferring the block of data.
IRQ=1, it indicates that the controller has requested an interrupt.

Fig: Use of DMA controllers in a computer system

A DMA controller connects a high speed network to the computer bus . The disk
controller two disks, also has DMA capability and it provides two DMA channels.
To start a DMA transfer of a block of data from main memory to one of the disks,
the program write s the address and the word count inf. Into the registers of the
corresponding channel of the disk controller.
When DMA transfer is completed, it will be recorded in status and control
registers of the DMA channel (ie) Done bit=IRQ=IE=1.

Cycle Stealing:

Requests by DMA devices for using the bus are having higher priority than
processor requests .
Top priority is given to high speed peripherals such as ,
Disk
High speed Network Interface and Graphics display device.

Since the processor originates most memory access cycles, the DMA controller
can be said to steal the memory cycles from the processor.
This interviewing technique is called Cycle stealing.
Burst Mode:
The DMA controller may be given exclusive access to the main memory to
transfer a block of data without interruption. This is known as Burst/Block Mode

Bus Master:
The device that is allowed to initiate data transfers on the bus at any given time is
called the bus master.

Bus Arbitration:

It is the process by which the next device to become the bus master is selected and
the bus mastership is transferred to it.
Types:
There are 2 approaches to bus arbitration. They are,

Centralized arbitration ( A single bus arbiter performs arbitration)

Distributed arbitration (all devices participate in the selection of next bus
master).

Centralized Arbitration:

Here the processor is the bus master and it may grants bus mastership to one of its
DMA controller.
A DMA controller indicates that it needs to become the bus master by activating
the Bus Request line (BR) which is an open drain line.
The signal on BR is the logical OR of the bus request from all devices connected
to it.
When BR is activated the processor activates the Bus Grant Signal (BGI) and
indicated the DMA controller that they may use the bus when it becomes free.
This signal is connected to all devices using a daisy chain arrangement.
If DMA requests the bus, it blocks the propagation of Grant Signal to other
devices and it indicates to all devices that it is using the bus by activating open
collector line, Bus Busy (BBSY).

Fig:A simple arrangement for bus arbitration using a daisy chain

Fig: Sequence of signals during transfer of bus mastership for the devices

The timing diagram shows the sequence of events for the devices connected to the
processor is shown.
DMA controller 2 requests and acquires bus mastership and later releases the bus.
During its tenture as bus master, it may perform one or more data transfer.
After it releases the bus, the processor resources bus mastership

Distributed Arbitration:
It means that all devices waiting to use the bus have equal responsibility in carrying out
the arbitration process.

Fig:A distributed arbitration scheme

Each device on the bus is assigned a 4 bit id.

When one or more devices request the bus, they assert the Start-Arbitration signal
& place their 4 bit ID number on four open collector lines, ARB0 to ARB3.
A winner is selected as a result of the interaction among the signals transmitted
over these lines.
 The net outcome is that the code on the four lines represents the request that has
the highest ID number.
The drivers are of open collector type. Hence, if the i/p to one driver is equal to 1,

is in low-voltage state).
Eg:
Assume two devices A & B have their ID 5 (0101), 6(0110) and their code is
0111.
Each devices compares the pattern on the arbitration line to its own ID starting
from MSB.
If it detects a difference at any bit position, it disables the drivers at that bit
posi

lines ARB1 & ARB0.

This causes the pattern on the arbitration line to change to 0110 which means that
won the contention.
Buses
A bus protocol is the set of rules that govern the behavior of various devices
connected to the bus ie, when to place information in the bus, assert control
signals etc.
The bus lines used for transferring data is grouped into 3 types. They are,
Address line
Data line
Control line.

Control signals Specifies that whether read / write operation has to performed.
It also carries timing infn/. (ie) they specify the time at which the
processor & I/O devices place the data on the bus & receive the data
from the bus.

Master
Master device initiates the data transfer by issuing read / write command on the
Initiator
The device addressed by the master is called as Slave / Target.

Types of Buses:
There are 2 types of buses. They are,
Synchronous Bus
Asynchronous Bus.
Synchronous Bus:-

In synchronous bus, all devices derive timing information from a common clock
line.
Equally spaced pulses on this line define equal time.
 bus cycle
crossing points
in an indeterminate / high impedance state is represented by an
intermediate half way between the low to high signal levels.

Fig:Timing of an input transfer of a synchronous bus.

At time to, the master places the device address on the address lines & sends an
appropriate command on the control lines.
In this case, the command will indicate an input operation & specify the length of
the operand to be read.
The clock pulse width t1 t0 must be longer than the maximum delay between
devices connected to the bus.
The clock pulse width should be long to allow the devices to decode the address
& control signals so that the addressed device can respond at time t1.
The slaves take no action or place any data on the bus before t1.

Fig:A detailed timing diagram for the input transfer

The picture shows two views of the signal except the clock.
One view shows the signal seen by the master & the other is seen by the salve.
The master sends the address & command signals on the rising edge at the
beginning of clock period (t0). These signals do not actually appear on the bus
until tam.
 Some times later, at tAS the signals reach the slave.
The slave decodes the address & at t1, it sends the requested data.
At t2, the master loads the data into its i/p buffer.
Hence the period t2, tDM is the setup time for the masters i/p buffer.
The data must be continued to be valid after t2, for a period equal to the hold time
of that buffers.
Demerits:
The device does not respond.
The error will not be detected.

Multiple Cycle Transfer:-

During, clock cycle1, the master

The slave receives this information & decodes it.

At the active edge of the clock (ie) the beginning of clock cycel2, it makes
accession to respond immediately.
The data become ready & are placed in the bus at clock cycle3.
slave-ready
The master which has been waiting for this signal, strobes, the data to its i/p
buffer at the end of clock cycle3.
The bus transfer operation is now complete & the master sends a new address to
start a new transfer in clock cycle4.
slave-ready
confirming that valid data has been sent.

Fig:An input transfer using multiple clock cycles

Asynchronous Bus:-

An alternate scheme for controlling data transfer on. The bus is based on the use
handshake Master & the Slave. The common clock is replaced by
two timing control lines.
They are
 Master ready
Slave ready.

Fig:Handshake control of data transfer during an input operation

The handshake protocol proceed as follows :

At t0 The master places the address and command information on the bus and
all devices on the bus begin to decode the information
At t1 The master sets the Master ready line to 1 to inform the I/O devices that
the address and command information is ready.

The delay t1 t0 is intended to allow for any skew that may occurs on the bus.
The skew occurs when two signals simultaneously transmitted from one source
arrive at the destination at different time.
Thus to guarantee that the Master ready signal does not arrive at any device a
head of the address and command information the delay t1 t0 should be larger
than the maximum possible bus skew.

At t2 The selected slave having decoded the address and command information
performs the required i/p operation by placing the data from its data
register on the data lines. At the same time, it sets t
signal to 1.
At t3 The slave ready signal arrives at the master indicating that the i/p data are
available on the bus.
At t4 The master removes the address and command information on the bus.
The delay between t3 and t4 is again intended to allow for bus skew.
Errorneous addressing may take place if the address, as seen by some
device on the bus, starts to change while the master ready signal is still
equal to 1.
At t5 When the device interface receives the 1 to 0 tranitions of the Master
ready signal. It removes the data and the slave ready signal from the bus.
This completes the i/p transfer.
 In this diagram, the master place the output data on the data lines and at the same
time it transmits the address and command information.
The selected slave strobes the data to its o/p buffer when it receives the Master-
ready signal and it indicates this by setting the slave ready signal to 1.
At time t0 to t1 and from t3 to t4, the Master compensates for bus.
A change of state is one signal is followed by a change is the other signal. Hence
this scheme is called as Full Handshake.
It provides the higher degree of flexibility and reliability.

INTERFACE CIRCUITS:
The interface circuits are of two types.They are

Parallel Port
Serial Port

Parallel Port:

The output of the encoder consists of the bits that represent the encoded character
and one signal called valid,which indicates the key is pressed.
The information is sent to the interface circuits,which contains a data
register,DATAIN and a status flag SIN.
When a key is pressed, the Valid signal changes from 0 to1,causing the ASCII
code to be loaded into DATAIN and SIN set to 1.
The status flag SIN set to 0 when the processor reads the contents of the DATAIN
register.
The interface circuit is connected to the asynchronous bus on which transfers are
controlled using the Handshake signals Master ready and Slave-ready.
Serial Port:

A serial port used to connect the processor to I/O device that requires transmission one
bit at a time.
It is capable of communicating in a bit serial fashion on the device side and in a bit
parallel fashion on the bus side.

STANDARD I/O INTERFACE

A standard I/O Interface is required to fit the I/O device with an Interface circuit.
The processor bus is the bus defined by the signals on the processor chip itself.
The devices that require a very high speed connection to the processor such as the
main memory, may be connected directly to this bus.
The bridge connects two buses, which translates the signals and protocols of one
bus into another.
The bridge circuit introduces a small delay in data transfer between processor and
the devices.

Fig:Example of a Computer System using different Interface Standards

Processor Main Memory

Bridge
 Processor Bus

Additional SCS / Ethernet i/f USB ISA i/f

Memory Controller Controller

SCSI Bus

Disk CD ROM Video IDE Disk

Controller Controller

DISK 1 DISK 2 CD ROM Key Board GAME

We have 3 Bus standards.They are,

PCI (Peripheral Component Inter Connect)

SCSI (Small Computer System Interface)
USB (Universal Serial Bus)

PCI defines an expansion bus on the motherboard.

SCSI and USB are used for connecting additional devices both inside and outside
the computer box.
SCSI bus is a high speed parallel bus intended for devices such as disk and video
display.
USB uses a serial transmission to suit the needs of equipment ranging from
keyboard keyboard to game control to internal connection.
IDE (Integrated Device Electronics) disk is compatible with ISA which shows
the connection to an Ethernet.
PCI:
PCI is developed as a low cost bus that is truly processor independent.
It supports high speed disk, graphics and video devices.
PCI has plug and play capability for connecting I/O devices.
To connect new devices, the user simply connects the device interface board to
the bus.
Data Transfer:

The data are transferred between cache and main memory is the bursts of several
words and they are stored in successive memory locations.
from
memory, the memory responds by sending a sequence of data words starting at
that address.
During write operation, the processor sends the address followed by sequence of
data words to be written in successive memory locations.
PCI supports read and write operation.
A read / write operation involving a single word is treated as a burst of length one.
PCI has three address spaces. They are

Memory address space

I/O address space
Configuration address space

I/O address space

Configuration space
capability.
PCI Bridge provides a separate physical connection to main memory.
The master maintains the address information on the bus until data transfer is
completed.
At any time, only one device acts as bus master.
DMA.
The addressed device that responds to read and write commands is called a
target.
A complete transfer operation on the bus, involving an address and bust of data is

Fig:Use of a PCI bus in a Computer system

HOST

PCI Bridge Main Memory

PCI
BUS

DISK PRINTER Ethernet i/f

Data Transfer Signals on PCI Bus:

Name Function

CLK 33 MHZ / 66 MHZ clock

FRAME # Sent by the indicator to indicate the duration of transaction
AD 32 address / data line
C/BE # 4 command / byte Enable Lines
IRDY, TRDYA Initiator Ready, Target Ready Signals
DEVSEL # A response from the device indicating that it has
recognized its address and is ready for data transfer
transaction.
IDSEL # Initialization Device Select

Fig :Read operation an PCI Bus

In Clock cycle1, the processor asserts FRAME # to indicate the beginning of a

transaction ; it sends the address on AD lines and command on C/BE # Lines.
Clock cycle2 is used to turn the AD Bus lines around ; the processor ; The
processor removes the address and disconnects its drives from AD lines.
The selected target enable its drivers on AD lines and fetches the requested data to
be placed on the bus.
It asserts DEVSEL # and maintains it in asserted state until the end of the
transaction.
C/BE # is used to send a bus command in clock cycle and it is used for different
purpose during the rest of the transaction.
 During clock cycle 3, the initiator asserts IRDY #, to indicate that it is ready to
receive data.
If the target has data ready to send then it asserts TRDY #. In our eg, the target
sends 3 more words of data in clock cycle 4 to 6.
The indicator uses FRAME # to indicate the duration of the burst, since it read 4
words, the initiator negates FRAME # during clock cycle 5.
After sending the 4th word, the target disconnects its drivers and negates DEVSEL
# during clockcycle 7.

Fig: A read operation showing the role of IRDY# / TRY#

It indicates the pause in the middle of the transaction.

The first and words are transferred and the target sends the 3rd word in cycle 5.
But the indicator is not able to receive it. Hence it negates IRDY#.
In response the target maintains 3rd data on AD line until IRDY is asserted again.
In cycle 6, the indicator asserts IRDY. But the target is not ready to transfer the
fourth word immediately, hence it negates TRDY in cycle 7. Hence it sends the
4th word and asserts TRDY# at cycle 8.
Device Configuration:

The PCI has a configuration ROM memory that stores information about that
device.
ccessible in the configuration
address space.

In each case, it determines whether the device is a printer, keyboard, Ethernet

interface or disk controller.
Devices are assigned address during initialization process and each device has an
w/p signal called IDSEL # (Initialization device select) which has 21 address lines
(AD) (AD to AD31).
During configuration operation, the address is applied to AD i/p of the device and
the corresponding AD line is set to and all other lines are set to 0.
 AD11 - AD31 Upper address line
A00 - A10 Lower address line
access the content of device configuration
ROM.
The configuration software scans all 21 locations.
PCI bus has interrupt request lines.
Each device may requests an address in the I/O space or memory space
Electrical Characteristics:

The connectors can be plugged only in compatible motherboards PCI bus can
operate with either 5 33V power supply.
The motherboard can operate with signaling system.

SCSI Bus:- (Small Computer System Interface)

SCSI refers to the standard bus which is defined by ANSI (American National
Standard Institute).
SCSI bus the several options. It may be,

Narrow bus It has 8 data lines & transfers 1 byte at a time.

Wide bus It has 16 data lines & transfer 2 byte at a time.
Single-Ended Transmission Each signal uses separate wire.
HVD (High Voltage Differential) It was 5v (TTL cells)
LVD (Low Voltage Differential) It uses 3.3v

Because of these various options, SCSI connector may have 50, 68 or 80 pins.
The data transfer rate ranges from 5MB/s to 160MB/s 320Mb/s, 640MB/s.
The transfer rate depends on,
Length of the cable
Number of devices connected.
To achieve high transfer rat, the bus length should be 1.6m for SE signaling and
12m for LVD signaling.
The SCSI bus us connected to the processor bus through the SCSI controller.
The data are stored on a disk in blocks called sectors.
Each sector contains several hundreds of bytes. These data will not be stored in
contiguous memory location.
SCSI protocol is designed to retrieve the data in the first sector or any other
selected sectors.
Using SCSI protocol, the burst of data are transferred at high speed.
The controller connected to SCSI bus is of 2 types. They are,
Initiator
Target
Initiator:
 It has the ability to select a particular target & to send commands specifying the
operation to be performed.
They are the controllers on the processor side.
Target:
The disk controller operates as a target.
It carries out the commands it receive from the initiator. The initiator establishes a
logical connection with the intended target.
Steps:

Consider the disk read operation, it has the following sequence of events.

The SCSI controller acting as initiator, contends process, it selects the target
controller & hands over control of the bus to it.
The target starts an output operation, in response to this the initiator sends a
command specifying the required read operation.
The target that it needs to perform a disk seek operation, sends a message to the
initiator indicating that it will temporarily suspends the connection between them.
Then it releases the bus.
The target controller sends a command to disk drive to move the read head to the
first sector involved in the requested read in a data buffer. When it is ready to
begin transferring data to initiator, the target requests control of the bus. After it
wins arbitration, it reselects the initiator controller, thus restoring the suspended
connection.
The target transfers the controls of the data buffer to the initiator & then suspends
the connection again. Data are transferred either 8 (or) 16 bits in parallel
depending on the width of the bus.
The target controller sends a command to the disk drive to perform another seek
operation. Then it transfers the contents of second disk sector to the initiator. At
the end of this transfer, the logical connection b/w the two controller is
terminated.
As the initiator controller receives the data, if stores them into main memory
using DMA approach.
The SCSI controller sends an interrupt to the processor to inform it that the
requested operation has been completed.

Bus Signals:-
The bus has no address lines.
Instead, it has data lines to identify the bus controllers involved in the selection /
reselection / arbitration process.
For narrow bus, there are 8 possible controllers numbered from 0 to 7.
For a wide bus, there are 16 controllers.
Once a connection is established b/w two controllers, these is no further need for
addressing & the datalines are used to carry the data.
SCSI bus signals:

Category Name Function

Data - DB (0) to DB (7) Datalines
- DB(P) Parity bit for data bus.
Phases - BSY Busy
- SEL Selection
Information type - C/D Control / Data
- MSG Message
Handshake - REQ Request
- ACK Acknowledge
Direction of transfer I/O Input / Output
Other - ATN Attention
- RST Reset.

All signal names are proceeded by minus sign.

This indicates that the signals are active or that the dataline is equal to 1, when
they are in the low voltage state.

Phases in SCSI Bus:-

The phases in SCSI bus operation are,
Arbitration
Selection
Information transfer
Reselection
Arbitration:-
When the BSY signal is in inactive state, the bus will he free & any controller
can request the use of the bus.
Since each controller may generate requests at the same time, SCSI uses
distributed arbitration scheme.
Each controller on the bus is assigned a fixed priority with controller 7 having the
highest priority.
When BSY becomes active, all controllers that are requesting the bus examines
the data lines & determine whether the highest priority device is requesting the
bus at the same time.
The controller using the highest numbered line realizes that it has won the
arbitration process.
At that time, all other controllers disconnect from the bus & wait for BSY to
become inactive again.
Fig:Arbitration and selection on the SCSI bus.Device 6 wins arbitration and select
device 2

Selection:

Here Device wons arbitration and it asserts BSY and DB6 signals.
The Select Target Controller responds by asserting BSY.
This informs that the connection that it requested is established.

Reselection:

The connection between the two controllers has been reestablished,with the target
in control the bus as required for data transfer to proceed.

USB Universal Serial Bus

USB supports 3 speed of operation. They are,

Low speed (1.5Mb/s)
Full speed (12mb/s)
High speed ( 480mb/s)
The USB has been designed to meet the key objectives. They are,

It provide a simple, low cost & easy to use interconnection s/m that overcomes
the difficulties due to the limited number of I/O ports available on a computer.
It accommodate a wide range of data transfer characteristics for I/O devices
including telephone & Internet connections.
Enhance user convenience through mode of operation.
Port Limitation:-
Normally the system has a few limited ports.
To add new ports, the user must open the computer box to gain access to the
internal expansion bus & install a new interface card.
The user may also need to know to configure the device & the s/w.

Merits of USB:-

USB helps to add many devices to a computer system at any time without opening the
computer box.

Device Characteristics:-
The kinds of devices that may be connected to a cptr cover a wide range of
functionality.
The speed, volume & timing constrains associated with data transfer to & from
devices varies significantly.

Eg:1 Keyboard Since the event of pressing a key is not synchronized to any other
event in a computer system, the data generated by keyboard are called asynchronous.
The data generated from keyboard depends upon the speed of the human operator which
is about 100bytes/sec.

Eg:2 Microphone attached in a cptr s/m internally / externally

The sound picked up by the microphone produces an analog electric signal, which
must be converted into digital form before it can be handled by the cptr.
This is accomplished by sampling the analog signal periodically.
The sampling process yields a continuous stream of digitized samples that arrive
at regular intervals, synchronized with the sampling clock. Such a stream is called
isochronous (ie) successive events are separated by equal period of time.

sampling process is s/2.

A standard rate for digital sound is 44.1 KHz.
Requirements for sampled Voice:-
It is important to maintain precise time (delay) in the sampling & replay process.
A high degree of jitter (Variability in sampling time) is unacceptable.

Eg-3:Data transfer for Image & Video:-

The transfer of images & video require higher bandwidth.

The bandwidth is the total data transfer capacity of a communication channel.
To maintain high picture quality, The image should be represented by about
160kb, & it is transmitted 30 times per second for a total bandwidth if 44MB/s.
Plug & Play:-

The main objective of USB is that it provides a plug & play capability.
The plug & play feature enhances the connection of new device at any time, while
the system is operation.
The system should,
Detect the existence of the new device automatically.
Identify the appropriate device driver s/w.
Establish the appropriate addresses.
Establish the logical connection for communication.

USB Architecture:-

USB has a serial bus format which satisfies the low-cost & flexibility
requirements.
Clock & data information are encoded together & transmitted as a single signal.
There are no limitations on clock frequency or distance arising form data skew, &
hence it is possible to provide a high data transfer bandwidth by using a high
clock frequency.
To accommodate a large no/. of devices that can be added / removed at any time,
the USB has the tree structure.

Fig:USB Tree Structure

Each hub
control point b/w host & I/O devices.
At the root of
The leaves of the tree are the I/O devices being served.