SN54AHC138, SN74AHC138

SCLS258M – DECEMBER 1995 – REVISED APRIL 2024

SNx4AHC138 3-Line to 8-Line Decoders/Demultiplexers

1 Features 2 Description
• Operating range 2V to 5.5V VCC The SNx4AHC138 decoders/demultiplexers are
• Designed specifically for high-speed memory designed for high-performance memory-decoding
decoders and data-transmission systems and data-routing applications that require very
• Incorporate three enable inputs to simplify short propagation-delay times. In high-performance
cascading and/or data reception memory systems, these decoders can be used to
• Latch-up performance exceeds 250mA per JESD minimize the effects of system decoding. When
17 employed with high-speed memories utilizing a fast
• ESD protection exceeds JESD 22: enable circuit, the delay times of these decoders and
– 2000V Human-Body Model (A114-A) the enable time of the memory usually are less than
– 1000V Charged-Device Model (C101) the typical access time of the memory. This means
that the effective system delay introduced by the
decoders is negligible.
Device Information
PART NUMBER PACKAGE (1) PACKAGE SIZE (2) BODY SIZE (3)
RGY (VQFN, 16) 4mm x 3.5mm 4mm x 3.5mm
N (PDIP, 16) 19.3 mm × 9.4 mm 19.32 mm x 6.35 mm
D (SOIC, 16) 9.9 mm × 6 mm 9.90 mm x 3.90 mm
SN74AHC138 NS (SOP, 16) 10.2mm x 7.8mm 10.20 mm x 5.30 mm
DB (SSOP, 16) 6.2 mm × 7.8 mm 6.20 mm x 5.30 mm
PW (TSSOP , 16) 5 mm × 6.4 mm 5.00 mm x 4.40 mm
DGV (TVSOP, 16) 3.6mm x 6.4mm 3.6mm x 4.4mm

(1) For more information, see Section 10.

(2) The package size (length × width) is a nominal value and
includes pins, where applicable.
(3) The body size (length × width) is a nominal value and does
not include pins.

Logic Diagram (Positive Logic)

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features............................................................................1 6.3 Function Table.............................................................9
2 Description.......................................................................1 7 Application and Implementation.................................. 10
3 Pin Configuration and Functions...................................3 7.1 Application Information............................................. 10
4 Specifications.................................................................. 5 7.2 Power Supply Recommendations............................. 11
4.1 Absolute Maximum Ratings........................................ 5 7.3 Layout....................................................................... 12
4.2 Recommended Operating Conditions.........................5 8 Device and Documentation Support............................13
4.3 Thermal Information....................................................6 8.1 Documentation Support (Analog)..............................13
4.4 Electrical Characteristics.............................................6 8.2 Receiving Notification of Documentation Updates....13
4.5 Switching Characteristics: VCC = 3.3V ± 0.3V.............6 8.3 Support Resources................................................... 13
4.6 Switching Characteristics: VCC = 5V ± 0.5V................7 8.4 Trademarks............................................................... 13
4.7 Operating Characteristics........................................... 7 8.5 Electrostatic Discharge Caution................................13
5 Parameter Measurement Information............................ 8 8.6 Glossary....................................................................13
6 Detailed Description........................................................9 9 Revision History............................................................ 13
6.1 Overview..................................................................... 9 10 Mechanical, Packaging, and Orderable
6.2 Functional Block Diagram........................................... 9 Information.................................................................... 14

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3 Pin Configuration and Functions

Figure 3-1. D, DB, DGV , N, NS , or PW Package, 16-Pin SOIC, SSOP, TVSOP, PDIP, SOP, or TSSOP
(Top View)

Figure 3-2. RGY Package,

16-Pin VQFN
(Top View)

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NC: No internal connection

FK Package,
20-Pin LCCC
(Top View)

Table 3-1. Pin Functions

PIN
TYPE(1) DESCRIPTION
NAME NO.
A0 1 I Address select 0
A1 2 I Address select 1
A2 3 I Address select 2
G0 4 I Output strobe 0, active low
G1 5 I Output strobe 1, active low
G2 6 I Output strobe 2
Y7 7 O Output 7
GND 8 G Ground
Y6 9 O Output 6
Y5 10 O Output 5
Y4 11 O Output 4
Y3 12 O Output 3
Y2 13 O Output 2
Y1 14 O Output 1
Y0 15 O Output 0
VCC 16 P Positive supply
The thermal pad can be connected to GND or left floating. Do not connect to any other signal or
Thermal pad(2)
supply.

(1) Signal Types: I = Input, O = Output, I/O = Input or Output, P = Power, G = Ground.
(2) WBQB package only.

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4 Specifications
4.1 Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VCC Supply voltage range −0.5 7 V
VI (2) Input voltage range −0.5 7 V
VO (2) Output voltage range −0.5 VCC + 0.5 V
IIK Input clamp current (VI < 0) −20 mA
IOK Output clamp current (VO < 0 or VO > VCC) ±20 mA
IO Continuous output current (VO = 0 to VCC) ±25 mA
Continuous current through VCC or GND ±75 mA
Tstg Storage temperature range −65 150 °C

(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

4.2 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)(1)
SN54AHC138 SN74AHC138
UNIT
MIN MAX MIN MAX
VCC Supply voltage 2 5.5 2 5.5 V
VCC = 2 V 1.5 1.5
VIH High-level input voltage VCC = 3 V 2.1 2.1 V
VCC = 5.5 V 3.85 3.85
VCC = 2 V 0.5 0.5
VIL Low-level input voltage VCC = 3 V 0.9 0.9 V
VCC = 5.5 V 1.65 1.65
VI Input voltage 0 5.5 0 5.5 V
VO Output voltage 0 VCC 0 VCC V
VCC = 2 V −50 −50 mA
IOH High-level output current VCC = 3.3 V ± 0.3 V −4 −4
mA
VCC = 5 V ± 0.5 V −8 −8
VCC = 2 V 50 50 mA
IOL Low-level output current VCC = 3.3 V ± 0.3 V 4 4
mA
VCC = 5 V ± 0.5 V 8 8
VCC = 3.3 V ± 0.3 V 100 100
Δt/Δv Input transition rise or fall rate ns/V
VCC = 5 V ± 0.5 V 20 20
TA Operating free-air temperature −55 125 −40 85 °C

(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

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4.3 Thermal Information

SN74AHC138
THERMAL METRIC(1) D DB DGV N NS PW RGY UNIT
16
R θJA Junction-to-ambient 120 135.9
73 (SOIC) 82 (SSOP) 67 (PDIP) 64 (SOP) 39 (VQFN) °C/W
thermal resistance (TVSOP) (TSSOP )

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application
report.

4.4 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
TA = 25°C SN54AHC138 SN74AHC138
PARAMETER TEST CONDITIONS VCC UNIT
MIN TYP MAX MIN MAX MIN MAX
2V 1.9 2 1.9 1.9
IOH = −50μA 3V 2.9 3 2.9 2.9
VOH 4.5 V 4.4 4.5 4.4 4.4 V
IOH = −4 mA 3V 2.58 2.48 2.48
IOH = −8 mA 4.5 V 3.94 3.8 3.8
2V 0.1 0.1 0.1
IOL = 50μA 3V 0.1 0.1 0.1
VOL 4.5 V 0.1 0.1 0.1 V
IOL = 4 mA 3V 0.36 0.5 0.44
IOL = 8 mA 4.5 V 0.36 0.5 0.44
II VI = 5.5 V or GND 0 V to 5.5 V ±0.1 ±1(1) ±1 μA
ICC VI = VCC or GND, IO = 0 5.5 V 4 40 40 μA
Ci VI = VCC or GND 5V 2 10 10 pF

(1) On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V.

4.5 Switching Characteristics: VCC = 3.3V ± 0.3V

over recommended operating free-air temperature range, VCC = 3.3V ± 0.3V (unless otherwise noted) (see Load Circuit and
Voltage Waveforms)
FROM TO LOAD TA = 25°C SN54AHC138 SN74AHC138
PARAMETER UNIT
(INPUT) (OUTPUT) CAPACITANCE MIN TYP MAX MIN MAX MIN MAX
tPLH 8.2(1) 11.4(1) 1(1) 13(1) 1 13
A, B, C Any Y CL = 15pF ns
tPHL 8.2(1) 11.4(1) 1(1) 13(1) 1 13
tPLH 8.1(1) 12.8(1) 1(1) 15(1) 1 15
G1 Any Y CL = 15pF ns
tPHL 8.1(1) 12.8(1) 1(1) 15(1) 1 15
tPLH 8.2(1) 11.4(1) 1(1) 13.5(1) 1 13.5
G2A, G2B Any Y CL = 15pF ns
tPHL 8.2(1) 11.4(1) 1(1) 13.5(1) 1 13.5
tPLH 10 15.8 1 18 1 18
A, B, C Any Y CL = 50pF ns
tPHL 10 15.8 1 18 1 18
tPLH 10.6 16.3 1 18.5 1 18.5
G1 Any Y CL = 50pF ns
tPHL 10.6 16.3 1 18.5 1 18.5
tPLH 10.7 14.9 1 17 1 17
G2A, G2B Any Y CL = 50pF ns
tPHL 10.7 14.9 1 17 1 17

(1) On products compliant to MIL-PRF-38535, this parameter is not production tested.

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4.6 Switching Characteristics: VCC = 5V ± 0.5V

over recommended operating free-air temperature range, VCC = 5V ± 0.5V (unless otherwise noted) (see Load Circuit and
Voltage Waveforms)
LOAD TA= 25°C SN54AHC138 SN74AHC138
FROM TO
PARAMETER CAPACITAN UNIT
(INPUT) (OUTPUT) MIN TYP MAX MIN MAX MIN MAX
CE
tPLH 5.7(1) 8.1(1) 1(1) 9.5(1) 1 9.5
A, B, C Any Y CL = 15pF ns
tPHL 5.7(1) 8.1(1) 1(1) 9.5(1) 1 9.5
tPLH 5.6(1) 8.1(1) 1(1) 9.5(1) 1 9.5
G1 Any Y CL = 15pF ns
tPHL 5.6(1) 8.1(1) 1(1) 9.5(1) 1 9.5
tPLH 5.8(1) 8.1(1) 1(1) 9.5(1) 1 9.5
G2A, G2B Any Y CL = 15pF ns
tPHL 5.8(1) 8.1(1) 1(1) 9.5(1) 1 9.5
tPLH 7.2 10.1 1 11.5 1 11.5
A, B, C Any Y CL = 50pF ns
tPHL 7.2 10.1 1 11.5 1 11.5
tPLH 7.1 10.1 1 11.5 1 11.5
G1 Any Y CL = 50pF ns
tPHL 7.1 10.1 1 11.5 1 11.5
tPLH 7.3 10.1 1 11.5 1 11.5
G2A, G2B Any Y CL = 50pF ns
tPHL 7.3 10.1 1 11.5 1 11.5

(1) On products compliant to MIL-PRF-38535, this parameter is not production tested.

4.7 Operating Characteristics

VCC = 5 V, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
Cpd Power dissipation capacitance No load, f = 1 MHz 13 pF

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5 Parameter Measurement Information

A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2
is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
E. All parameters and waveforms are not applicable to all devices.

Figure 5-1. Load Circuit and Voltage Waveforms

TEST S1
tPLH/tPHL Open
tPLZ/tPZL VCC
tPHZ/tPZH GND
Open Drain VCC

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6 Detailed Description
6.1 Overview
The conditions at the binary-select inputs and the three enable inputs select one of eight output lines. Two
active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding. A
24-line decoder can be implemented without external inverters, and a 32-line decoder requires only one inverter.
An enable input can be used as a data input for demultiplexing applications.
6.2 Functional Block Diagram

Pin numbers shown are for the D, DB, DGV, J, N, NS, PW, RGY, and W packages.
6.3 Function Table
ENABLE INPUTS SELECT INPUTS OUTPUTS
G1 G2A G2B C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
X H X X X X H H H H H H H H
X X H X X X H H H H H H H H
L X X X X X H H H H H H H H
H L L L L L L H H H H H H H
H L L L L H H L H H H H H H
H L L L H L H H L H H H H H
H L L L H H H H H L H H H H
H L L H L L H H H H L H H H
H L L H L H H H H H H L H H
H L L H H L H H H H H H L H
H L L H H H H H H H H H H L

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7 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.

7.1 Application Information

Figure 7-1. 24-Bit Decoding Scheme

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Figure 7-2. 32-Bit Decoding Scheme

7.2 Power Supply Recommendations

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7.3 Layout
7.3.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices, inputs must never be left floating. In many cases,
functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a
triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left
unconnected because the undefined voltages at the outside connections result in undefined operational states.
All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the
input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular
unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever
makes more sense for the logic function or is more convenient.
7.3.2 Layout Example

Figure 7-3. Example Layout for the SN74AHC138

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8 Device and Documentation Support

TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
8.1 Documentation Support (Analog)
8.1.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 8-1. Related Links
TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER SAMPLE & BUY
DOCUMENTS SOFTWARE COMMUNITY
SN54AHC138 Click here Click here Click here Click here Click here
SN74AHC138 Click here Click here Click here Click here Click here

8.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Notifications to register and receive a weekly digest of any product information that has changed. For change
details, review the revision history included in any revised document.
8.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
8.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
8.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

8.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

9 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision L (July 2003) to Revision M (April 2024) Page
• Added Package Information table, Pin Functions table, ESD Ratings table, Thermal Information table, Device
Functional Modes,Application and Implementation section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ............................................................................. 1
• Removed references to machine model.............................................................................................................1
• Updated thermal values for PW package from RθJA = 108 to 135.9, all values in °C/W ................................. 6

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10 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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 PACKAGE OPTION ADDENDUM

www.ti.com 15-Apr-2024

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

5962-9851601Q2A ACTIVE LCCC FK 20 55 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962- Samples
& Green 9851601Q2A
SNJ54AHC
138FK
5962-9851601QEA ACTIVE CDIP J 16 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-9851601QE Samples
& Green A
SNJ54AHC138J
5962-9851601QFA ACTIVE CFP W 16 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-9851601QF Samples
& Green A
SNJ54AHC138W
SN74AHC138DBR ACTIVE SSOP DB 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HA138 Samples

SN74AHC138DGVR ACTIVE TVSOP DGV 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HA138 Samples

SN74AHC138DR ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AHC138 Samples

SN74AHC138N ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 SN74AHC138N Samples

SN74AHC138NSR ACTIVE SO NS 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AHC138 Samples

SN74AHC138PWR ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HA138 Samples

SN74AHC138RGYR ACTIVE VQFN RGY 16 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 HA138 Samples

SNJ54AHC138FK ACTIVE LCCC FK 20 55 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962- Samples
& Green 9851601Q2A
SNJ54AHC
138FK
SNJ54AHC138J ACTIVE CDIP J 16 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-9851601QE Samples
& Green A
SNJ54AHC138J
SNJ54AHC138W ACTIVE CFP W 16 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-9851601QF Samples
& Green A
SNJ54AHC138W

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

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NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN54AHC138, SN74AHC138 :

• Catalog : SN74AHC138
• Automotive : SN74AHC138-Q1, SN74AHC138-Q1
• Military : SN54AHC138

NOTE: Qualified Version Definitions:

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 PACKAGE OPTION ADDENDUM

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• Catalog - TI's standard catalog product

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
• Military - QML certified for Military and Defense Applications

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 PACKAGE MATERIALS INFORMATION

www.ti.com 9-Apr-2024

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74AHC138DBR SSOP DB 16 2000 330.0 16.4 8.35 6.6 2.4 12.0 16.0 Q1
SN74AHC138DGVR TVSOP DGV 16 2000 330.0 12.4 6.8 4.0 1.6 8.0 12.0 Q1
SN74AHC138DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
SN74AHC138NSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
SN74AHC138PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74AHC138RGYR VQFN RGY 16 3000 330.0 12.4 3.8 4.3 1.5 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 9-Apr-2024

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74AHC138DBR SSOP DB 16 2000 356.0 356.0 35.0
SN74AHC138DGVR TVSOP DGV 16 2000 356.0 356.0 35.0
SN74AHC138DR SOIC D 16 2500 340.5 336.1 32.0
SN74AHC138NSR SO NS 16 2000 356.0 356.0 35.0
SN74AHC138PWR TSSOP PW 16 2000 356.0 356.0 35.0
SN74AHC138RGYR VQFN RGY 16 3000 356.0 356.0 35.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 9-Apr-2024

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
5962-9851601Q2A FK LCCC 20 55 506.98 12.06 2030 NA
5962-9851601QFA W CFP 16 25 506.98 26.16 6220 NA
SN74AHC138N N PDIP 16 25 506 13.97 11230 4.32
SN74AHC138N N PDIP 16 25 506 13.97 11230 4.32
SNJ54AHC138FK FK LCCC 20 55 506.98 12.06 2030 NA
SNJ54AHC138W W CFP 16 25 506.98 26.16 6220 NA

Pack Materials-Page 3
 PACKAGE OUTLINE
NS0016A SCALE 1.500
SOP - 2.00 mm max height
SOP

8.2 SEATING PLANE

TYP
7.4
A PIN 1 ID 0.1 C
AREA
14X 1.27
16
1

10.4 2X
10.0 8.89
NOTE 3

8
9
0.51
16X
5.4 0.35
B 0.25 C A B 2.00 MAX
5.2
NOTE 4

0.15 TYP

SEE DETAIL A
0.25 0.3
GAGE PLANE 0.1

0 - 10
1.05
0.55 DETAIL A
TYPICAL
(1.25)

4220735/A 12/2021

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.

www.ti.com
 EXAMPLE BOARD LAYOUT
NS0016A SOP - 2.00 mm max height
SOP

16X (1.85) SEE

SYMM DETAILS

1 16

16X (0.6)

SYMM

14X (1.27)

8 9

(R0.05) TYP

(7)

LAND PATTERN EXAMPLE

SCALE:7X

SOLDER MASK SOLDER MASK METAL

METAL OPENING OPENING

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4220735/A 12/2021

NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
NS0016A SOP - 2.00 mm max height
SOP

16X (1.85) SYMM

1 16

16X (0.6)

SYMM

14X (1.27)

8 9

(R0.05) TYP (7)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:7X

4220735/A 12/2021

NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.

www.ti.com
 PACKAGE OUTLINE
PW0016A SCALE 2.500
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

SEATING
PLANE
6.6 C
TYP
A 6.2
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1

2X
5.1 4.55
4.9
NOTE 3

8
9
0.30
4.5 16X 1.2 MAX
B 0.19
4.3
NOTE 4 0.1 C A B

(0.15) TYP
SEE DETAIL A

0.25
GAGE PLANE
0.15
0.05

0.75
0.50
0 -8
DETAIL A
A 20

TYPICAL

4220204/A 02/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.

www.ti.com
 EXAMPLE BOARD LAYOUT
PW0016A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

16X (1.5) SYMM

(R0.05) TYP
1
16X (0.45) 16

SYMM

14X (0.65)

8 9

(5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 10X

SOLDER MASK METAL UNDER SOLDER MASK

METAL SOLDER MASK OPENING
OPENING

EXPOSED METAL EXPOSED METAL

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED) SOLDER MASK DETAILS
15.000

4220204/A 02/2017
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
PW0016A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

16X (1.5) SYMM

(R0.05) TYP
1
16X (0.45) 16

SYMM

14X (0.65)

8 9

(5.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 10X

4220204/A 02/2017
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
 PACKAGE OUTLINE
DB0016A SCALE 1.500
SSOP - 2 mm max height
SMALL OUTLINE PACKAGE

C
8.2
TYP
A 7.4
0.1 C SEATING
PIN 1 INDEX AREA
PLANE
14X 0.65
16
1

2X
6.5
4.55
5.9
NOTE 3

8
9
0.38
16X
0.22
5.6
B 0.1 C A B
5.0
NOTE 4

0.25
0.09

SEE DETAIL A
2 MAX
0.25
GAGE PLANE

0.95 0.05 MIN

0 -8 0.55

DETAIL A
A 15

TYPICAL

4220763/A 05/2022

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-150.

www.ti.com
 EXAMPLE BOARD LAYOUT
DB0016A SSOP - 2 mm max height
SMALL OUTLINE PACKAGE

16X (1.85) SYMM

1 (R0.05) TYP

16X (0.45) 16

SYMM

14X (0.65)

8 9

(7)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 10X

SOLDER MASK METAL UNDER SOLDER MASK

METAL
OPENING SOLDER MASK OPENING

EXPOSED METAL EXPOSED METAL

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS
15.000

4220763/A 05/2022
NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DB0016A SSOP - 2 mm max height
SMALL OUTLINE PACKAGE

16X (1.85) SYMM

(R0.05) TYP
1
16X (0.45) 16

SYMM

14X (0.65)

8 9

(7)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 10X

4220763/A 05/2022
NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.

www.ti.com
 MECHANICAL DATA

MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000

DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE

24 PINS SHOWN

0,23
0,40 0,07 M
0,13
24 13

0,16 NOM
4,50 6,60
4,30 6,20

Gage Plane

0,25

0°–
8°
0,75
1 12
0,50
A

Seating Plane

0,15
1,20 MAX 0,08
0,05

PINS **
14 16 20 24 38 48 56
DIM

A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40

A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20

4073251/E 08/00

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 GENERIC PACKAGE VIEW
FK 20 LCCC - 2.03 mm max height
8.89 x 8.89, 1.27 mm pitch LEADLESS CERAMIC CHIP CARRIER

This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4229370\/A\

www.ti.com
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