2013 IEEE 11th International Conference on Dependable, Autonomic and Secure Computing

A Radiation Hardened SRAM in 180-nm RHBD

Technology

CHEN Nan, WEI Tingcun, WEI Xiaomin and Chen Xiao

School of Computer Science and Technology, Northwestern Polytechnical University
Xi’an, China
[email protected]

Abstract—A 24 kB radiation hardened static random access Co mmercial CM OS process in 180-nm and RHBD
memory using 180-nm commercial CMOS process appropriate technology are adopted to realize radiation-hardened design in
for embedded system on a chip integrated circuits is presented. the system, circuit and layout in this paper. The proto chips of
Radiation-hardened design is realized in the system, circuit and SRAM are fabricated and tested, and the electrical properties of
layout design to improve tolerance of radiation effects. The proto SRAM chips are measured. On that basis, TID experiment with
chips of S RAM are fabricated and tested, not only the electrical using a Co-60 gamma radiation source is made on it, and the
properties of S RAM chips are measured, but also the total result is analyzed.
ionizing dose effects experiments are finished using a Co-60
gamma radiation source. The experimental results show that, the This paper is organized as follows: Sect. II describes the
TID(total ionizing dose effect) tolerance of S RAM chips is larger design of SRAM for radiation hardness improvement, Sect. III
than 300 krad (Si) in which the electrical functions of S RAM are present the electrical properties test results, Sect. IV presents
correct, but with the increase of TID rate, the static and the experimental TID and analyzes the results, and conclusion
dynamic current of S RAM increase seriously, and the write and is given in Sect. V.
read time increase slowly. Furthermore, it is verified by our
research that, CMOS transistor layout design with ring-gate and
P-type guard ring can enhance the TID tolerance of S RAM II. THE DESIGN OF RADIAT ION-HARDENED SRAM CHIP
greatly. SRAM’s system, circuit and layout are anti-radiation
improvement by RHBD technologies , mainly targeting TID
Keywords—SRAM; Radiation Hardened by Design; Total and SEU and SEL.
Ionizing Dose Effect; Ring-gate; Guard Ring

I. INT RODUCT ION

SRAM with CMOS process is widely used in space 24Kb×8bit Radiation Hard SRAM
exp loration and high-energy physics experiments. Since a large
number of cosmic rays and charged particles (α particle, high
Replication Array
energy proton, neutron and so on) existing in these application
Repli-
environment, SRAM is especially sensitive to the ionizing Pre-
charge and cation
radiation that they create, which easily cause storage data bits SRAM Memory Array
Amplifier Array
Control
upset, the decrease of data access rate, temporal disorder, Signal
tremendous parameters change and power consumption [1]. Sequential Address
Control Decoding
The life and stability of SRAM is seriously declined because of SRAM
Driver
radiation effect [2]. Therefore, the research and design of Address
radiation hardened SRAM is very necessary. Line 24Kb×13bit SRAM
Writing Data 5HDGLQJ
According to the damage, the ionizing radiation is divided and
/ 13 bits EDAC Test
Circuit
'DWDDQG
/UHGXQGDQF\
into SEE (Single Event Effect) and TID (Total Ionizing Dose) Redundancy ELWV
%LWV
Bits
[3]. SEU (Single Event Upset) and SEL (Single Event Latch-up) EDAC Writing EDAC Reading
are the most important SEE damage in SRAM. TID’s Circuit Circuit
mechanism is to create trapped charges in silica, which leads to ˄Encode˅ ˄Decode˅

the threshold voltage shift, mobility reduce and leak / 8 bits / 2 bits
current increase of CMOS so as to change SRAM’s time / 8 bits
sequence and noise margin, and to increase power consumption,
or even permanent damage [4]. The damage caused by TID
Writing EE_T Reading Error Flag
Data Data
could accumulate over time. Therefore, TID immunity is one
of the most important parameter to SRAM’s life and reliability Fig. 1. T he system block diagram of Rad-Hard SRAM
[5].

T his work is supported by the National Key Scientific Instrument and

Equipment Development Project number 2011YQ040082

978-1-4799-3381-5/13 $31.00 © 2013 IEEE 159

DOI 10.1109/DASC.2013.55
Authorized licensed use limited to: Indian Institute of Technology Indore. Downloaded on March 22,2024 at 08:09:23 UTC from IEEE Xplore. Restrictions apply.
 B. Circuit And Layout Design
The 180-n m co mmercial CM OS process is applied to
design and realize the radiation-hardened proto chips of SRAM
in this paper. Gate o xide thickness is less than 4nm, and then
WL
the threshold voltage offset led by radiation effect is basically
PM1 PM2 eliminated [7]. Ho wever, the leakage flow path around the
edge of MOS, generated by using self-registered technology
when making grid with commercial CMOS proces s, which
becomes the main failure reason of TID in deep-submicron
PM3 PM4
technology [8].
Storage cell is the most important part in SRAM, accounts
NM1 NM2 for about 70% of the area. Therefore, the design of the storage
9'' %/ *1' %/1 9'' cell is especially important. But the anti-radiation design
BL BLN
usually increases the chip area, for examp le, the classic DICE
(a) Schematic (b) Layout with ring-gate NMOS cell structure increases the chip area more than four times. To
Fig. 2. 6-bit cell design of SRAM
save area, this paper puts forward a radiation-hardened
optimu m design of the classic 6 cell. As Figure 2 shows, it
consists of 4 PMOS transistors and 2 NMOS transistors. Since
A. System Design positive charges accumulated between the gate and the
The system structure of the designed radiation-hardened insulating layer of the PMOS, the leakage flow path can’t be
SRAM proto chip is showed in Figure 1. To make up for the formed, so the transfer transistors, NMOS tubes in the classic 6
deficiency of commercial CMOS process’s anti-SEU ability, cell are taken place by PMOS tubes to reduce the impact of
EDAC (Error Detection and Correction) is integrated in SRAM leakage so as to improve the circuit’s ability of anti-TID effect.
to realize real-time processing for storage data. The encoding In the layout design, ring-gate layout structure is adopted in the
algorithm of module EDAC is the (13, 8) hamming code, 2 NMOS transfer transistors to eliminate the leakage flow path
which is 8 bits of data and 5 redundancy codes (13 b its in total). around the edge of the active area and field area and reduce the
When data is written, 5 bits of redundancy codes are created by edge parasitic effect.
EDAC writing circuits, stored in SRAM together with data.
In the layout design of digital standard cell library, two
When the data is read, the data and the 5 redundancy codes in
anti-radiation methods of adding the guard ring and distancing
SRAM co me into EDA C decoding error correction circuits
PMOS tube from NMOS tube are adopted to improve SRAM’s
together. First, decide whether the data is right or not. If it’s
tolerance of SEE. Radiation-induced charge in storage node is
right, output it directly. If one bit is wrong, correct it and then
absorbed by guard ring, which raise the noise margin and
output it. If two are wrong, report the error to the system
improve the ability of anti-SEU. On the other hand, guard ring
through error flag. Error flag is made up by two bits; one
can guide the transient current, reduce the voltage pulse of the
shows whether to correct the error, the other shows whether the
base of parasitic transistor and improve the ability of anti-SEL.
data is effective. When the error bits are greater than or equal
What’s more, the leakage current transmission path between
to 2 bits, the data is useless. Therefore, built-in module EDAC
the trap and the diffusion zone can be cut by adding the guard
can correct or monitor the upset of the storage data, and
ring, so that improve the tolerance of TID.
improve SRAM’s ability to tolerate SEU.
Distancing tube from NM OS increases the base region of
Meanwhile, the storage array of SRAM is arranged
parasitic transistor, decreases the current amplification factor
according to Bit-Interleaving, which reduces the rate of
so as to reduce the probability of SEL. It can be proven that the
mu ltibit upsets and improve SRAM’s ability to anti-SEU.
circuit has higher tolerance of anti-SEL, if the distance between
Besides, a low-power consumption design strategy is applied to
PMOS and NMOS is wider. When the distance is 5um, the
divide modules for the storage array of SRAM.
circuit is basically immune to SEL [9]. In this design,
The common time sequence control method of SRAM is considering the compro mise between silicon cost and anti-SEL
based on clock signal and the sequence signal[6]. Delay unit is ability, 2u m is distanced from PM OS tube and NMOS tube so
used to produce sequence signal that controls the input and that the circuit’s anti-SEL ability can reach above
output data, word line and bit line. However, transistor’s gate 40MeV ·cm2 /mg [9].
capacitance increasing in radiation environment, lead to the
device’s speed changes, and the accuracy of delay unit gets III. THE REALIZAT ION AND VERIFICAT ION OF RADIAT ION-
worse, which easily result in d isoperation. Instead of delay unit, HARDENED SRAM PROT O CHIP
dedicated radiation-hardened sequential circuits are used to
produce timing sequence signals in the designed radiation- In this paper, a 24kB radiation-hardened SRAM proto chip
hardened SRAM in this paper. It adds a row and a colu mn of is researched and designed using 180-n m co mmercial CM OS
the replication unit of storage array in storage array to track the process. To verify and co mpare the result of the above
key signal lines of storage and feed back to the s equential radiation-hardened design methods, 4 different versions of
control unit so that it can control the writing and reading of SRAM chips are designed, named Chip A, Ch ip B, Chip C and
data according to the feedback signal. Chip D respectively. The radiation-hardened measure each

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version adopted is listed in Table І, micrographs of SRAM TABLE II. T HE MEASURED ELECTRICAL P ROP ERTIES OF SRAM CHIP S
chips are shown in Figure 3.
Electrical Chips versions
In the SRAM chip test, PXI-1033 fro m NI is adopted to properties Chip A Chip B Chip C Chip D
generate and collect data. Labview is used for software Chip Area 5.24mm2 5.24mm2 5.24mm2 1.86mm2
programming. In normal conditions (VDD=1.8 V,
temperature=25°C), the most importance electrical properties Frequency 50M Hz 50M Hz 50M Hz 50M Hz
of 4 versions of SRAM chip are tested and compared T ime 7.6ns 7.6ns 7.6ns 3.9ns
respectively. The result is summarized in table П. Static Power 0.49uW 0.49uW 0.49uW 0.41uW
As is shown in Table П, RHDB technology is used in Chip Dynamic Power 7.38mW 7.38mW 7.38mW 5.40mW
A, Chip B and Chip C, including adding EDAC module and a.
Time means the write and read time
redundant storage cell, storage cell NMOS is replaced by ring-
gate in layout design, 2um is distanced from PMOS tube and
NMOS tube in digital standard cell library, the area of the chips IV. TID EXPERIMENT AND RESULT A NALYSIS
increased 2.8 times as big as the original, compared with the The Co-60 gamma radiation source with 4000-curie is used
ordinary Chip D. The reading and writing time has doubled as our irrad iation source. The radiation dose rate is 50 rad(Si)/s
because of the delay of EDA C module. Besides, as EDAC and calibrated by UNIDOS dosimeter. When performing the
redundant storage cell are adopted, storage array is increased, experiment, SRAM chip to be tested is powered, but it is in
dynamic power consumption of the chip increases 1.4 t imes. a stationary working position (no storing data), VDD=1.8 V.
Thus it can be seen that as RHBD technology is adopted, The experiment main ly analyzes SRAM’s static current,
radiation toleration of the chip gets improved while the other dynamic current and read and writes time with total ionizing
properties degrade. Electrical properties of Chip A, B, C are doses increasing. The chosen total ionizing doses are 65ࠊ
the same, which shows that the type of the guard ring has no 125ࠊ162ࠊ200ࠊ300 krad(Si). When testing dynamic current
impact to the normal electrical properties of SRAM.
and reading and writing time, the radiation source is cut
temporarily, and then continuing the irradiation after the
PP PP measure. The average of the 6 chip samples is considered as
the final result so as to reduce the individual difference of the
E F G chips.
PP
PP ) LOOHU
&KLS' Figure 4 shows the tendency that the static current increases
&KLS$ with the total ionizing dose. As the total dose rate accumulates
continually, static power consumption increases rapidly. That’s
) LOOHU
because TID effect causes the significant increase of the
leakage current of CMOS devices. While the total dose is 65
krad(Si), SRAM static current has no noticeable change, which
proves that the process itself could stand the TID effect in this
PP G &KLS% &KLS& G
PP
scope.
F F

E E
When the total dose is 300 krad(Si), co mpared with Chip D,
the static power consumption of Chip A reduces by 97%,
PP PP
which is the consequence of the adoption of the ring-gate in
XP XP XP NMOS in the storage cell of Chip A. Thus it can be seen that
XP XP XP the ring-gate layout effectively suppresses the increase of the
(('$&:ULWLQJ&LUFXLW )('$&5HDGLQJ&LUFXLW *('$&7HVW&LUFXLW
leakage current and reduces the damage of TID. The curve of
Fig.3. Micrographs of Rad-Hard SRAM chips Chip A is almost coincided with that of Chip B, which proves
that the adding of N-type guard ring has no obvious effect on
suppressing leakage current. However, compared with Chip D,
TABLE I. T HE RAD -HARD METHODS OF SRAM CHIP S the static current of Chip C reduces by 99%, it’s
RHBD Chips versions a dual outcome of the adoption of the ring-gate and P-type
Method Chip A Chip B Chip C Chip D
guard ring. Co mpared with Chip A, the static current of Chip C
reduces by 51%, showing that P-type guard ring has a
EDAC YES YES YES YES remarkable function in suppressing TID effect.
T ime Replication Replication Replication Replication
Control Array Array Array Array Figure 5 shows the curve that the dynamic current increases
Store Cell Ring- Ring- Ring- with the total ionizing dose, which has almost the same
(NMOS) Bar gate changing trend as that of the static current. Co mpared with
gate gate gate
Guard Chip D, the dynamic current of Chip C reduces by 24%,
No N-type P-type No
Ring showing that ring-gate layout and P-type guard ring effectively
Distance 2um 2um 2um 0um suppress the effect TID has on dynamic power consumption.
a. And the dynamic current of Chip B only reduces by 14%,
Distance means distancing PMOS tube from NMOS tube
which shows that N-type guard ring has a weak role in

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suppressing TID effect. Besides, different fro m leakage current,
data bits upset makes dynamic current itself b ig, the leakage
current caused by radiation has a small proportion in
dynamic current, therefore, TID has a smaller effect on
dynamic current.
Figure 6 shows the curve that the read and write time of
SRAM increases with the total ionizing dose. As the dose
accumulates, SRAM reading and writing speed slows down,
because the decrease of the mobility slows the speed of SRAM
down. But since the gate oxide is too thin, the mobility doesn’t
change much, 4 chips all have timing protection circuits, read
and write time basically fo llows the same trend with small
increment.
Fig.6. T he write and read time increases the total ionizing dose
V. CONCLUSION
In this paper, a 24kB radiation-hardened SRAM proto chip
is researched and designed using 180-n m co mmercial CM OS
process. The TID effects experiments are fin ished using a Co- REFERENCES
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Fig.5. T he dynamic current increases with the total ionizing dose

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