Calibre DRC, LVS and DFM

overview
Martin Niehoff
Application Engineer Calibre Manufacturing Solutions

January 2019
 Your Presenter – Martin Niehoff
 Graduation from Friedrich-Alexander University (Erlangen-Nürnberg,
Germany):
— Major: Physics - diploma thesis in experimental Optics
— Minor: Computer Science
 1998 – 2004: Siemens Semiconductor / Infineon Technologies
— Metrology process engineering
— Lithography process engineering
— Lithography R&D (65nm & 45nm nodes)
 2004 – 2010: Mentor Graphics
— European Product Specialist OPC & MDP
 2010 – 2014: ASML/Brion
— Senior Application Engineer Fab Tools & OPC
 2014 – now: Mentor Graphics / Siemens
— European Application Engineer – Calibre Manufacturing Solutions
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 Agenda

 Introduction
 DRC, LVS, xRC:
— Calibre in the EDA Ecosystem
— Advanced Nodes
— Established Nodes
— Productivity
— Foundry Status
 DFM:
— LFD
— YieldAnalyzer
— YieldEnhancer
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 Agenda

 Introduction
 DRC, LVS, xRC:
— Calibre in the EDA Ecosystem
— Advanced Nodes
— Established Nodes
— Productivity
— Foundry Status
 DFM:
— LFD
— YieldAnalyzer
— YieldEnhancer
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 Siemens Investing in Increasing R&D Headcount
Functional Simulation Physical Verification
(Excluding Solido)

+25% +15%
Hardware Based Verification Design for Test and Yield

+33% +21%
High Level Synthesis All Increases over 20 months
January 31, 2017 through
+33% September 30, 2018

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 DESIGN TO SILICON
Abstraction Physics

GDSII Silicon
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 Agenda

 Introduction
 DRC, LVS, xRC:
— Calibre in the EDA Ecosystem
— Advanced Nodes
— Established Nodes
— Productivity
— Foundry Status
 DFM:
— LFD
— YieldAnalyzer
— YieldEnhancer
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 Calibre Design Solutions Portfolio

ACCURACY
&
PERFORMANCE

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 Agenda

 Introduction
 DRC, LVS, xRC:
— Calibre in the EDA Ecosystem
— Advanced Nodes
— Established Nodes
— Productivity
— Foundry Status
 DFM:
— LFD
— YieldAnalyzer
— YieldEnhancer
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 Advanced Physical Verification
nmDRC/eqDRC

Functionality Complexity Performance

Context Sensitivity

28/22nm

FinFET Delta-V

16/14nm

CutOD DFM DV

10/7/5nm

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 Agenda

 Introduction
 DRC, LVS, xRC:
— Calibre in the EDA Ecosystem
— Advanced Nodes
— Established Nodes
— Productivity
— Foundry Status
 DFM:
— LFD
— YieldAnalyzer
— YieldEnhancer
Restricted © 2019 Mentor Graphics Corporation

11 MN, Calibre Design Tools @ MIET, January 2019

 Traditional IC Verification
 DRC, LVS, ERC
— Provide limited context, rules applied to entire design
— Often leverage “marker” / CAD layers to refine checking area
 Increased design complexity requires focused verification

DRC LVS ERC

I/O Pad

Compare

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 TSMC ESD/Latch-up Rules – From Their DRM

 “Un-checkable” with traditional EDA tools

 Includes reliability focused applications
— Topology, P2P, CD, layout based latch-up
 Decks available for N28 and below
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 Analog Constraint Checking - RESCAR
 Focused effort to improve reliability of automotive designs
— Developed through customer collaboration with
Mentor for RESCAR project
 Includes checks for
— Alignment, Symmetry, Matched Orientation
— Parameter Match, Cluster, Others
 Simple constraint entry greatly
simplifies adoption
 Jointly presented at DAC 2014 and
ASP-DAC 2015

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 Agenda

 Introduction
 DRC, LVS, xRC:
— Calibre in the EDA Ecosystem
— Advanced Nodes
— Established Nodes
— Productivity
— Foundry Status
 DFM:
— LFD
— YieldAnalyzer
— YieldEnhancer
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 Calibre RealTime Platform: Accelerating DRC Closure

Custom Digital
 Interactive checking during design creation  Manually fix “Last Few” errors after P&R

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 Calibre RealTime Digital
Customer Results at Block Level
Time to Reach DRC Clean Block Time to Reach DRC Clean Block

Block 2
Block 3 40%
Reduction Block 5
85%
Block 2 Block 4
Reduction

Block 3
Block 1

Block 1
0 1 2 3 4 5 6 7 8 9

With RealTime Without RealTime 0 2 4 6 8 10 12

WITH RealTime Without RealTime

“40% reduction in DRC closure “85% reduction in DRC fixing time

time for each block @ GF 22nm for every block for every ECO for
can save us 2 weeks to Tape-out our 16nm design”
– Invecas - Customer B
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 Agenda

 Introduction
 DRC, LVS, xRC:
— Calibre in the EDA Ecosystem
— Advanced Nodes
— Established Nodes
— Productivity
— Foundry Status
 DFM:
— LFD
— YieldAnalyzer
— YieldEnhancer
Restricted © 2019 Mentor Graphics Corporation

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 Calibre Process Support for Established Nodes
DRC LVS xRC/xACT
130 nm P P P
90 nm P P P
65/55 nm P P P
40 nm P P P
180
BCD/MCU/7HV/W
P P P
L/7RF/SW

130
BCD/MCU/7HV/W P P P
L/7RF/SW
90nm/9SF/9HP P P P
65/55LPe/LPx
10SF/65PKG P P P

45/40nm
45RFSOI/40LP P P P

180 nm P P P
130 nm P P P
110 nm P P P
65 nm P P P
45 nm P P P
HCMOS9gpSOI P P P
65 nm RF P P P

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 Summary: Calibre is The Low Risk Choice
 TSMC Tech Symposium
All Node DRC Market Share
— N7: Will tape out ≥50 chips in CY18
— Using Calibre: 49 2016
Micro Magis
Silvaco
Synopsys
0%
1%
10%
 Calibre dominant at: Samsung, GF, UMC, SMIC, etc.
Cadence
 Integrated everywhere 17%

— Ecosystem
— Best in class EDA solutions

 Full solutions, others missing key tools:

Mentor
— PERC 72%
— SRAM/Pattern Matching
Mentor Cadence Synopsys Silvaco Micro Magis

Source: Gary Smith EDA (December 2017)

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 Agenda

 Introduction
 DRC, LVS, xRC:
— Calibre in the EDA Ecosystem
— Advanced Nodes
— Established Nodes
— Productivity
— Foundry Status
 DFM:
— LFD
— YieldAnalyzer
— YieldEnhancer
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 DFM Methodology
Identify
Determine Source, Cause and Impact of Yield Limiters

Yield
Enhance Analyze
Make Design/Process Locate, Prioritize and
Changes to Improve Yield Score the Yield Limiters

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 Agenda

 Introduction
 DRC, LVS, xRC:
— Calibre in the EDA Ecosystem
— Advanced Nodes
— Established Nodes
— Productivity
— Foundry Status
 DFM:
— LFD
— YieldAnalyzer
— YieldEnhancer
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 LFD vs DRC
 DRC-clean ≠ printable

Courtesy of Luigi Capodieci, Ph.D. at AMD - SPIE Microlithography 2006

Layout context in halo Variation in process

(~2μm around feature) window (n dose/focus)

Layout Targeted Printed

Mask Litho
dimension dimension dimension
at nominal dose/focus at actual dose/focus

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 Calibre® LFD:
based on production RET/OPC recipes
Manufacturing Environment
RET/OPC Recipes Optical Models
LFD Kit
Check Rules Resist/Etch Models

Input Layout
Contours
Calibre LFD Hotspots
Fixing Hints
Design Environment

Process Variability LFD Checks LFD Hint

RET/OPC
Simulation

Fixing Hint

MWC
M1_E1_ORG M1_E2_ORG M1_E1 OPC M1_E2 OPC Restricted © 2019 Mentor Graphics Corporation

25 MN, Calibre Design Tools @ MIET, January 2019

 Agenda

 Introduction
 DRC, LVS, xRC:
— Calibre in the EDA Ecosystem
— Advanced Nodes
— Established Nodes
— Productivity
— Foundry Status
 DFM:
— LFD
— YieldAnalyzer
— YieldEnhancer
Restricted © 2019 Mentor Graphics Corporation

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 YieldAnalyzer Visualization

YRC Rule Summary Table

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 Agenda

 Introduction
 DRC, LVS, xRC:
— Calibre in the EDA Ecosystem
— Advanced Nodes
— Established Nodes
— Productivity
— Foundry Status
 DFM:
— LFD
— YieldAnalyzer
— YieldEnhancer
Restricted © 2019 Mentor Graphics Corporation

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 A toolbox for layout modification
 Automatic or user-selected
 DRC-clean and DFM-aware
 Embedded and Programmable features

Programmable Edge
SmartFill Via enhancement
Movement
Original DFM Shift
location polygon
by X & Y
DFM SHIFT

DFM SHIFT EDGE DFM EXPAND EDGE

ORIGINAL LAYER ORIGINAL LAYER

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 Screenshot before via insertion

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 Screenshot after via insertion

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 Additional YieldEnhancer Commands:
Programmable Edge Movement (PEM)
 Requires deck development
— Users determine the required movement by analysis
— Manufacturing companies know from silicon results what changes are needed and by how much to
improve Yield
DFM EXPAND EDGE FIX
 Released Property Based Edits ORIGINAL LAYER WITH ISSUES

— DFM EXPAND EDGE, DFM GROW

— DFM SHIFT EDGE, DFM SIZE
— DFM SHIFT
DFM SHIFT EDGE REGION
ORIGINAL LAYER
Original DFM Shift
location polygon
by X & Y

DFM SIZE LAYER PROP = 0.2

ORIGINAL LAYER

PROP = 0.1
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