ES8311

Low Power Mono Audio CODEC

FEATURES DAC

• 24-bit, 8 to 96 kHz sampling frequency

System
• 110 dB signal to noise ratio, -80 dB
• High performance and low power multi- THD+N
bit delta-sigma audio ADC and DAC • One pair of analog output with
• I2S/PCM master or slave serial data port headphone driver and differential
• 256/384Fs, USB 12/24 MHz and other output option
non standard audio system clocks • Dynamic range compression
• I2C interface • Pop and click noise suppression

ADC Low Power

• 24-bit, 8 to 96 kHz sampling frequency • 1.8V to 3.3V operation

• 100 dB signal to noise ratio, -93 dB • 14 mW playback and record
THD+N • Low standby current
• One pair of analog input with
differential input option
• Low noise pre-amplifier APPLICATIONS
• Noise reduction filters
• Auto level control (ALC) and noise gate • Automotive
• Support analog and digital microphone • Phone
• Toy
• 2-way radio
• Dash cam
• IP Camera
• DVR, NVR
• Surveillance

ORDERING INFORMATION
ES8311 -40°C ~ +85°C
QFN-20

1
 Everest Semiconductor Confidential ES8311

1. BLOCK DIAGRAM

ASDOUT
CDATA

DSDIN
MCLK

LRCK
CCLK

SCLK
CE
Clock Mgr I2C I2S/PCM

OUTP
MIC1P ADC ALC
Mono Mono HP Driver
PGA DAC DRC OUTN
ADC DAC
MIC1N Noise Filter

Analog Reference Power Supply

VMID
DACVREF
ADCVREF

AGND
AVDD
DGND
PVDD
DVDD

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2. PIN OUT AND DESCRIPTION

MIC1P/DMIC_SDA
CDATA

MIC1N
VMID
20 CE
19
18
17
16
CCLK 1 15 ADCVREF
MCLK 2 14 DACVREF
PVDD 3 ES8311 13 OUTN
DVDD 4 12 OUTP
DGND 5 11 AVDD

10
6
7
8
9
SCLK/DMIC_SCL
ASDOUT
LRCK
DSDIN
AGND

Pin Name Pin number Input or Output Pin Description

CCLK, CDATA, CE 1, 19, 20 I, I/O, I I2C clock, data, address
MCLK 2 I Master clock
SCLK/DMIC_SCL 6 I/O Serial data bit clock/DMIC bit clock
LRCK 8 I/O Serial data left and right channel frame clock
ASDOUT 7 O ADC serial data output
DSDIN 9 I DAC serial data input
MIC1P/DMIC_SDA 18
I Mic input
MIC1N 17
OUTP, OUTN 12, 13 O Differential analog output
PVDD 3 Analog Power supply for the digital input and output
DVDD, DGND 4, 5 Analog Digital power supply
AVDD, AGND 11, 10 Analog Analog power supply
VMID 16 Analog Filtering capacitor connection
ADCVREF, DACVREF 15, 14 Analog Filtering capacitor connection

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3. TYPICAL APPLICATION CIRCUIT

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4. CLOCK MODES AND SAMPLING FREQUENCIES

The device supports standard audio clocks (64Fs, 128Fs, 256Fs, 384Fs, 512Fs, etc), USB clocks
(12/24 MHz), and some common non standard audio clocks (16 MHz, 25 MHz, 26 MHz, etc).

According to the serial audio data sampling frequency (Fs), ADC can work in two speed modes:
single speed mode or double speed mode. In single speed mode, Fs normally ranges from 8 kHz
to 48 kHz, and in double speed mode, Fs normally range from 64 kHz to 96 kHz.

The device can work either in master clock mode or slave clock mode. In slave mode, LRCK and
SCLK are supplied externally, and LRCK and SCLK must be synchronously derived from the
system clock with specific rates. In master mode, LRCK and SCLK are derived internally from
device master clock.

5. MICRO-CONTROLLER CONFIGURATION INTERFACE

The device supports standard I2C micro-controller configuration interface. External micro-
controller can completely configure the device through writing to internal configuration
registers.

I2C interface is a bi-directional serial bus that uses a serial data line (CDATA) and a serial clock
line (CCLK) for data transfer. The timing diagram for data transfer of this interface is given in
Figure 1a and Figure 1b. Data are transmitted synchronously to CCLK clock on the CDATA line on
a byte-by-byte basis. Each bit in a byte is sampled during CCLK high with MSB bit being
transmitted firstly. Each transferred byte is followed by an acknowledge bit from receiver to pull
the CDATA low. The transfer rate of this interface can be up to 400 kbps.

A master controller initiates the transmission by sending a “start” signal, which is defined as a
high-to-low transition at CDATA while CCLK is high. The first byte transferred is the slave address.
It is a seven-bit chip address followed by a RW bit. The chip address must be 0011 00x, where x
equals CE. The RW bit indicates the slave data transfer direction. Once an acknowledge bit is
received, the data transfer starts to proceed on a byte-by-byte basis in the direction specified by
the RW bit. The master can terminate the communication by generating a “stop” signal, which is
defined as a low-to-high transition at CDATA while CCLK is high.

In I2C interface mode, the registers can be written and read. The formats of “write” and “read”
instructions are shown in Table 1 and Table 2. Please note that, to read data from a register, you
must set R/W bit to 0 to access the register address and then set R/W to 1 to read data from the
register.

Table 1 Write Data to Register in I2C Interface Mode

Chip Address R/W Register Address Data to be written

start 0011 00 CE 0 ACK RAM ACK DATA ACK Stop

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Chip Addr Write ACK Reg Addr ACK Write Data ACK

CDATA bit 1 to 7 bit 1 to 8 bit 1 to 8

CCLK

START STOP

Figure 1a I2C Write Timing

Table 2 Read Data from Register in I2C Interface Mode

Chip Address R/W Register Address

Start 0011 00 CE 0 ACK RAM ACK
Chip Address R/W Data to be read
Start 0011 00 CE 1 ACK Data NACK Stop

Chip Addr Write ACK Reg Addr ACK Chip Addr Read ACK Read Data NO ACK

CDATA bit 1 to 7 bit 1 to 8 bit 1 to 7 bit 1 to 8

CCLK

START START STOP

Figure 1b I2C Read Timing

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6. DIGITAL AUDIO INTERFACE

The device provides many formats of serial audio data interface to the input of the DAC or
output from the ADC through LRCK, SCLK and DSDIN or ASDOUT pins. These formats are I2S, left
justified, right justified and DSP/PCM. DAC input DSDIN is sampled by the device on the rising
edge of SCLK. ADC data is out at ASDOUT on the falling edge of SCLK. The relationship of SDATA
(DSIN/ASDOUT), SCLK and LRCK with these formats are shown through Figure 2a to Figure 2d.
1 SCLK 1 SCLK

LRCK L Channel R Channel

SCLK

SDATA

MSB LSB MSB LSB

Figure 2a I2S Serial Audio Data Format

LRCK L Channel R Channel

SCLK

SDATA

MSB LSB MSB LSB

Figure 2b Left Justified Serial Audio Data Format

1 SCLK

LRCK L Channel R Channel

SCLK

SDATA

MSB LSB MSB LSB

Figure 2c DSP/PCM Mode A Serial Audio Data Format

LRCK L Channel R Channel

SCLK

SDATA

MSB LSB MSB LSB

Figure 2d DSP/PCM Mode B Serial Audio Data Format

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7. ELECTRICAL CHARACTERISTICS

ABSOLUTE MAXIMUM RATINGS

Continuous operation at or beyond these conditions may permanently damage the device.

PARAMETER MIN MAX

Analog Supply Voltage Level -0.3V +3.6V
Digital Supply Voltage Level -0.3V +3.6V
Analog Input Voltage Range AGND-0.3V AVDD+0.3V
Digital Input Voltage Range DGND-0.3V PVDD+0.3V
Operating Temperature Range -40°C +85°C
Storage Temperature -65°C +150°C

RECOMMENDED OPERATING CONDITIONS

PARAMETER MIN TYP MAX UNIT
DVDD 1.6 1.8/3.3 3.6 V
PVDD 1.6 1.8/3.3 3.6 V
AVDD 1.7 1.8/3.3 3.6 V
Note 1: for 96 kHz sampling frequency, DVDD must be 3.3V (±10%).

Note 2: The internal clock source can be MCLK or SCLK. When this internal clock source is
multiplied by 4 or 8, its frequency must be greater than 1 MHz for 3.3V DVDD or 500 kHz for
1.8V DVDD.

Note 3: recommend VDDP and VDDD power supply turn on or off within 10 ms of each other;
VDDD must be on when VDDA is on.

Note 4: recommend all power supply on, entering low power through control register setting,
then stopping input clock.

Note 5: recommend to provide MCLK, LRCK and SCLK before control register setting, otherwise
reset after MCLK, LRCK and SCLK are provided.

ADC ANALOG AND FILTER CHARACTERISTICS AND SPECIFICATIONS

Test conditions are as the following unless otherwise specify: AVDD=3.3V, DVDD=3.3V,
AGND=0V, DGND=0V, Ambient temperature=25°C, Fs=48 KHz, MCLK/LRCK=256.

PARAMETER MIN TYP MAX UNIT

ADC Performance
Signal to Noise ratio (A-weigh) 95 100 102 dB
THD+N -95 -93 -85 dB
Gain Error ±5 %
Filter Frequency Response – Single Speed
Passband 0 0.4535 Fs
Stopband 0.5465 Fs
Passband Ripple ±0.05 dB

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Stopband Attenuation 70 dB
Filter Frequency Response – Double Speed
Passband 0 0.0417 Fs
Stopband 0.0792 Fs
Passband Ripple ±0.005 dB
Stopband Attenuation 70 dB
Analog Input
Full Scale Input (differential P and N) 2*AVDD/3.3 Vrms
Input Impedance 6 KΩ

DAC ANALOG AND FILTER CHARACTERISTICS AND SPECIFICATIONS

Test conditions are as the following unless otherwise specify: AVDD=3.3V, DVDD=3.3V,
AGND=0V, DGND=0V, Ambient temperature=25°C, Fs=48 KHz, MCLK/LRCK=256.

PARAMETER MIN TYP MAX UNIT

DAC Performance
Signal to Noise ratio (A-weigh) 105 110 115 dB
THD+N -85 -80 -75 dB
Gain Error ±5 %
Filter Frequency Response – Single Speed
Passband 0 0.4535 Fs
Stopband 0.5465 Fs
Passband Ripple ±0.05 dB
Stopband Attenuation 53 dB
Analog Output
Full Scale Output (differential P and N) 1.71*AVDD/3.3 2*0.9*AVDD/3.3 1.89*AVDD/3.3 Vrms

DC CHARACTERISTICS
PARAMETER MIN TYP MAX UNIT
Normal Operation Mode
DVDD=1.8V, PVDD=1.8V, AVDD=3.3V 8 mA
Power Down Mode
DVDD=1.8V, PVDD=1.8V, AVDD=3.3V 0 uA
Digital Voltage Level
Input High-level Voltage 0.7*PVDD V
Input Low-level Voltage 0.5 V
Output High-level Voltage PVDD V
Output Low-level Voltage 0 V

SERIAL AUDIO PORT SWITCHING SPECIFICATIONS

PARAMETER Symbol MIN MAX UNIT
MCLK frequency 49.2 MHz
MCLK duty cycle 40 60 %
LRCK frequency 100 KHz
LRCK duty cycle (Note 6) 40 60 %
SCLK frequency 26 MHz

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SCLK pulse width low TSLKL 16 ns

SCLK Pulse width high TSCLKH 16 ns
SCLK falling to LRCK edge (master mode only) TSLR 10 ns
LRCK edge to SCLK rising (slave mode only) TLSR 10 ns
SCLK falling to SDOUT valid VDDD=3.3V 16 ns
TSDO
VDDD=1.8V 39
LRCK edge to SDOUT valid (Note 7) VDDD=3.3V 11 ns
TLDO
VDDD=1.8V 25
SDIN valid to SCLK rising setup time TSDIS 10 ns
SCLK rising to SDIN hold time TSDIH 10 ns
Note 6: one SCLK period of high time in DSP/PCM modes.

Note 7: only apply to MSB of Left Justified or DSP/PCM mode B.

LRCK

TSLR TLSR TSCLKH TSCLKL

SCLK

TSDO TLDO
SDOUT

TSDIS TSDIH

SDIN

Figure 3 Serial Audio Port Timing

I2C SWITCHING SPECIFICATIONS (SLOW SPEED MODE/HIGH SPEED MODE)

PARAMETER Symbol MIN MAX UNIT
CCLK Clock Frequency FCCLK 100/400 KHz
Bus Free Time Between Transmissions TTWID 4.7/1.3 us
Start Condition Hold Time TTWSTH 4.0/0.6 us
Clock Low time TTWCL 4.7/1.3 us
Clock High Time TTWCH 4.0/0.6 us
Setup Time for Repeated Start Condition TTWSTS 4.7/0.6 us
CDATA Hold Time from CCLK Falling TTWDH 3.45/0.9 us
CDATA Setup time to CCLK Rising TTWDS 0.25/0.1 us
Rise Time of CCLK TTWR 1.0/0.3 us
Fall Time CCLK TTWF 1.0/0.3 us

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Figure 4 I2C Timing

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8. PACKAGE (UNIT: MM)

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9. CORPORATE INFORMATION

Everest Semiconductor Co., Ltd.

No. 1355 Jinjihu Drive, Suzhou Industrial Park, Jiangsu, P.R. China, Zip Code 215021

苏州工业园区金鸡湖大道 1355 号国际科技园, 邮编 215021

Email: [email protected]

10.IMPORTANT NOTICE AND DISCLAIMER

Everest Semiconductor publishes reliable technical information about its products. Information
contained herein is subject to change without notice. It may be used by a party at their own
discretion and risk. Everest Semiconductor disclaims responsibility for any claims, damages,
costs, losses, and liabilities arising out of your use of the information. This publication is not to
be taken as a license to operate under any existing patents and intellectual properties.

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