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PHASE LOCK LOOP
MODEL: PLA
OBJECTIVE:
Q. inthis experiment you will be constructing the phase lock loop and
there by finding the locking range frequencies.
MATERIALS REQUIRED:
Q. OHM PHASELOCK LOOP TRAINER KIT,
2 pum
Q oscintoscore
Q aro
Q. ser or patcu Tips
THEORY:
As illustrated in the block diagram of figure 1, the phase locked loop is
basically an electronic feedback loop system constructing of
A) Phase detector or comparator
B) Low pass filter
©) Voltage controlled oscillator
From the study of feedback and control systems, these three components are said to
be in the forward and control path of the loop. While the single connection between
the VCO and the phase detector is the feedback path. The Veo
cee r:azaing oscillator, the frequency of which is normally
determined by an external resistor ~ capacitor oF an inductor ~ capacitor network.
‘The VCO frequency (FO) Is fed back to the phase detector where tis compared with
the frequency ofthe input signal (f1). The output ofthe phase detector isthe error
voltage. This isan average DC voltage that is proportional to the difference inthe
frequency (fi-f0) and the phase (A®) of the input and VCO.
PROCEDURE:
1. Switch on the trainer kitand check the power supply to be +5V
2, Patch the circuit as shown in the wiring diagram
3. Connect the audio input (square) at the input terminal.
4. Connect the dual channel CR.O, one channel to the input terminal and the
other channel to the output terminal.
5. Vary the audio frequency from 20 HZ to the maximum frequency.
[At some frequency the output of the PLL using 4046 IC follows the input, this,
frequency range is called as phase lock loop.
7. The frequency range depends upon the capacitor value you have selected, For
example if you select 0.4mF the frequency ranges from 170HZ (appx) to
1.7KHZ(appx).
For 0.01mf the locking ranging will vary form 1.7KHz to 17KHz appx.
Likewise the lock in range frequency depends upon the value of the capacitor
selected at the pin of 6 & 7 of 1C 4046.
