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Verilog Lab RDD

Guided lab file for verilog intro lab

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OjaseeDuble
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21 views

Verilog Lab RDD

Guided lab file for verilog intro lab

Uploaded by

OjaseeDuble
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Verilog Lab

Aims:
1. Understanding HDLs: Not your average C++ Code
2. Introduction to Verilog: Verilog 2005 & SystemVerilog
3. Toolchains: Editor, Icarus Verilog & GTK Wave
4. Basic Designs:
a. Adder
b. Mux
c. Flip Flops
5. Final Design: 8 Bit ALU

Understanding HDLs: Not your average C++ Code


Hardware Description Languages describe the circuit you wish to digitize and
build, which sounds very similar to standard programming.
Key Aspect of HDLs: Every Module executes at the same time, in Parallel;
unlike standard programming, where every instruction is sequentially
executed.
This aspect requires a different design philosophy, which requires you to be
mindful while writing HDL code & take extra steps to produce a working
design.
As Data Structures are key to programming, understanding of digital
combinational & sequential circuits is key to mastering HDLs.
While standard programs run on a computing device producing certain output,
HDL programs run to produce the digital logic to be synthesized which is the
actual computing device itself.
Introduction to Verilog: Verilog 2005 & SystemVerilog
● Verilog IEEE 1364-2005 the last standalone version of Verilog, before
merging into SystemVerilog IEEE 1800-2009. Verilog and SystemVerilog
share a C to C++ type of transition.
● These HDLs model Digital, Analog, Mixed Signal Circuits.
● Only certain subset of Verilog keywords can be synthesized, ie, put on
Silicon.
● SystemVerilog adds further capabilities for Simulation, Testing &
Verification of the Module that is designed.
● VHDL is the older HDL, which has a lot of syntax to be written while
Verilog is simpler to read and write, making it a more productive
language.
● Verilog & SystemVerilog are Data Flow languages, since all the modules
execute simultaneously.

Toolchains: Editor, Icarus Verilog & GTK Wave


● Editor: Any text based editor can work, from as simple as Notepad to
Microsoft Visual Studio Code. Just note that all Verilog files are saved as
“file_name.v”.
● Icarus Verilog: A free compiler implementation for the IEEE-1364
Verilog HDL, maintained by Stephen Williams, under the GNU GPL
license.
● GTK Wave: The primary way to understand and test your designs is by
looking at the Timing Diagrams generated by your Testbenches (More on
that later). GTK Wave is a fully featured GTK+ based wave viewer for
Unix, Win32, and Mac OSX which reads LXT, LXT2, VZT, FST, and GHW
files as well as standard Verilog VCD/EVCD files and allows their viewing.

Iverilog & GTK Wave together form a very simple, functional & light weight CLI
based method to write, simulate & test all your designs in Verilog.
Basic Designs:
The Methodology:
1. Create a simple block diagram based on the circuit you wish to design.
It should be the pseudocode of your circuit and should define what
inputs and outputs you require.
2. Creating the Design File:
The Design file will contain the implementation of the function you wish
to synthesize. It will follow a standard template of Verilog programming
constructs.
This single design file is called a Module.
For complex designs: eg, CPU, a hierarchy of Modules will create a Tree
structure, with the Top File being the root node.
Following the rules of Abstraction helps to keep the implementation and
the I/O separate, making the overall hierarchy cleaner and easier to work
on.
Remember to keep certain test outputs in your design file so that you
have the ability to probe the important signals inside the
implementation itself.
3. Creating the Testbench:
Having designed the module itself, it is super important to test your
module.
Note: Testbenches are not supposed to be synthesizable. They are merely
there for verification and simulation purposes (for now).
A Testbench firstly instantiates the Module under Test. This process is
similar to creating an object of your self defined class.
The Testbench should ideally test all the conditions that the Module
under test may be exposed to.
Exhaustive Testing is the key to designs which work reliably.
4. Testing & Simulation:
Using Iverilog & GTK Wave, testbench outputs can be observed and
verified.
Completing this process yields a verified reliable design module!
Adder:
A basic Combinational circuit that can add/subtract multiple inputs to
provide one output. Can be made to accommodate a variety of signal
widths.

Mux:
The Multiplexer/Demultiplexer combo provides you with the ability to
utilize conditional statements inside your design, allowing you to create
if/else control structures as well as switch case statements.

Flip Flops:
The very basic element of all Sequential Circuits, understanding and
creating working flip flop designs helps out for a variety of bugs, such as
button debouncing and input /output delays.

Adding clocks to purely combinational circuits helps to organize and


systematically create input output systems with discrete visible timing
for use in projects requiring an hierarchy of modules.

Final Design: 8 Bit ALU


The final task is to create an 8 bit ALU using the concepts seen above.
You may refer to the datasheet of 74181 TTL IC, and adapt your design
accordingly.
Alternatively, you may also design your own set of functions that your ALU will
perform.
Your ALU design module should be synthesizable (refer and utilize only
synthesizable keywords) and your testbench should test all the possible
functions of the ALU with positive and negative inputs.
Finally, the output of the testbench as the “dump.vcd” file should verify
correctness of operation via observation under GTK Wave.

Bonus:
The Datasheet states the presence of carry look ahead adders to improve the
addition/subtraction operation times.
Try if you can implement the Carry Look Ahead Adder and integrate it into this
design.
Tip:
4 Bit Carry Look Ahead Adder logic analysis are available online.
You may Daisy Chain two of them together to create the required design.
Create a separate module for Carry Look Ahead Adder and integrate it into the
ALU design along the other functions.

References:
1. Icarus Verilog Setup: It’s just an exe setup for windows. Linux & MacOS
users can use the terminal to directly install the required tools.
https://bleyer.org/icarus/

2. GTK Wave:
https://gtkwave.sourceforge.net/
Linux & MacOS users can again simply use the terminal to get the tools
installed easily.

3. HDLBits: A website that hosts Verilog circuit design problems with


solutions along with the ability to see the waveforms of your design and
the desired output. Similar to Leetcode/Hackerrank/etc.
https://hdlbits.01xz.net/wiki/Main_Page

4. Wikipedia: The Wiki Article for Verilog does a great job introducing the
language, its semantics & certain common beginner fallacies while also
providing methods to alleviate such problems.
https://en.wikipedia.org/wiki/Verilog
It also contains a lot of stuff that is nice to know for even advanced
projects, so that is up to the curiosity of the reader.

5. A List of Synthesizable & Non Synthesizable keywords in Verilog


https://asic-soc.blogspot.com/2013/06/synthesizable-and-non-synthe
sizable.html

6. Datasheet for 74181 4 Bit Slice ALU:


https://www.ti.com/lit/ds/symlink/sn54ls181.pdf?ts=1722498729013
Refer to the Table which lists all the functions available within the
datasheet.

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