Week 1 Day 2

Lesson 2: Quantization
Learning outcome: On completion of this lesson the students must be able to describe the
quantization process, perform Digital-to-analog conversion and Analog-to-digital conversion

Outline
• Quantisation process
• Digital-to-analog conversion
• Analog-to-digital conversion

The signal processing system

x(t) x(n) Digital

Input y(n) Output y(t)
ADC Signal DAC
Filter Processor Filter

Quantization process
Refer to Chapter 2 of the recommended book and Module 1 of the notes

The analog to digital conversion consists of two parts:

• Sampling the analog value
• Quantizing of the sample

Sampling and quantization are the necessary prerequisites for any digital signal processing on
any analog signals.

Figure
3:

Analog to digital conversion [2]

• The sample and hold capacitor holds each measured sample x(nT ) for T seconds
• The AD converter converts the signal to quantised sample xq (nT ) represented by a finite
number of bits B
• The B-bit word is sent to the DSP

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• The sample/hold and ADC may be separate modules or be on the same chip
• The full-scale range R is divided into 2 B quantisation levels
R
• The space between levels, Q, is given by Q = B (quantisation width or resolution)
2
• Typical values of R lie within the range 1-10 volts
R R
• For bipolar ADC possible quantised values lie within the range −  xQ (nT ) 
2 2
• For unipolar ADC possible quantised values lie within the range 0  xQ (nT )  R
• The analog input signal, x(t ) , must be preconditioned to lie within the full-scale range [2]

Figure 4: Signal quantisation for B = 3 [2]

• Quantisation was done by rounding off, replacing each value of x(t ) by the nearest value
of the quantisation level (Define rounding off, truncation, advantage)
• In truncation each value of x(t ) is replaced by the value of the quantisation level below it
• The quantisation error results from using the quantised signal xQ (nT ) instead of the true
signal x(nT )
e(nT ) = xQ (nT ) − x(nT ) or e = xQ − x
Q Q
• The error lies within the range − e
2 2
Q
• The maximum error is given by emax = in magnitude
2
Q
• The root-mean-square (rms) error is given by erms =
12
R
• The quantisation width = 2 B is the signal to noise ratio and can be represented as:
Q

R
( )
SNR = 20 log10   = 20 log10 2 B SNR = 6 B dB
Q
SNR is the dynamic range of the quantizer, known as the 6dB rule [2]

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Example 1:
In digital speech processing the typical sampling rate is 8 kHz . The quantizer has the word
length of 8 bits. An 8-bit ADC has the full-scale range of 10 volts. Determine:
(i) The number of quantisation levels
(ii) An rms noise error
(iii) The bit rate

Solution:
(i) The number of levels 2 B = 2 8 = 256
Q R 2 − B 10  2 − 8
(ii) erms = = = = 11 mV
12 12 12
(iii) Bit rate is B  f s = 8  8 kHz = 64 kbits / sec

Digital to analog conversion

• The DAC is the building block of the successive approximation ADC

Figure 5: B-bit DAC

• The DAC outputs an analog value xQ that lies on one 2 B quantisation levels within the
range R
• If the DAC is unipolar xQ falls in the range [0, R]
 R R
• If the DAC is bipolar xQ falls in the range − , 
 2 2
• The widely used types of DACs are unipolar natural binary, bipolar offset binary and
bipolar two’s complement
• The output of the unipolar DAC is given by :

xQ = R(b1 2 −1 + b2 2 −2 + b3 2 −3 +  + bB 2 − B )
Also
xQ = Qm
where m is an integer value: m = b1 2 B −1 + b2 2 B − 2 +  + bB

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• The output of the bipolar offset DAC is given by shifting by half scale:

xQ = R(b1 2 −1 + b2 2 −2 +  + bB 2 − B − 0.5)
Also
xQ = Qm'
where m ' is the integer m shifted by half the maximum scale

• The two’s complement DAC is obtained by complementing the MSB of the bipolar offset
DAC
xQ = R(b1 2 −1 + b2 2 −2 +  + bB 2 − B − 0.5)

Table1: Summary of the DAC types

Table 2: Converter codes for B = 4 and R = 10 volts

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Analog to digital conversion
The ADC quantizes the value x until it is represented by B bits

Figure 6: The B − bit ADC [2]

• Initially B bits are cleared to zero in the successive approximation register (SAR)
• Starting with the MSB, each bit is turned on in sequence
• The test is performed to determine if the bit should be left on or turned off
• The control logic puts the correct value of the bit in the correct slot in the SAR
• The next bit is turned on and the process is repeated
• After B tests the SAR will hold the correct bit vector which can be sent to the output

Figure 7: Successive approximation ADC [2]

• At each test the SAR vector is applied to the DAC
• The DAC produces the analog quantised value xQ
• When the bit is turned on, xQ is compared with x
• If x  xQ the bit is left on, else the bit is turned off

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Example 2:
Convert the analog value x = 3.5 volts to the offset binary representation. Assume B = 4 and
R = 10 volts

Solution:
Refer to Table 2

• b1 passes the test

• b2 passes the test
• b3 fails the test
• b4 passes the test
• The last row gives the final content of the SAR and the quantised value xQ = 3.125
• The C column gives the serial representation of the final answer
• This is the example for truncation
Example 3:
Perform conversion in Example 2 using rounding off method

Solution:
x is shifted by half the spacing between levels: y = x + 12 Q
3.5 + 0.625
2 = 3.8125

Refer to Table 2.

The SAR ADC is limited to B  12 bits

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Student Activity
• Tutorial 1

• Make use of Table 2 to convert 7.48V to the natural binary representation. Assume that the
system is 4-bits with a range of 10V .

• When a signal is converted to digital an error is introduced when rounding off or truncating.
Demonstrate your knowledge of ADC by calculating an RMS error introduced in a typical
8-bit ADC with a full-scale range of 10 volts.

Preparation for next class

Read Module 2 in the notes

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