Operating Systems-8-Main Memory
Operating Systems-8-Main Memory
Main Memory
Background
❏ Program must be brought (from disk) into memory and placed within a process for it to be run
❏ Main memory and registers are only storage CPU can access directly
❏ Memory unit only sees a stream of addresses + read requests, or address + data and write
requests
❏ Register access in one CPU clock (or less)
❏ Main memory can take many cycles, causing a stall, since it does not have the data required to
complete the instruction that it is executing
❏ Cache sits between main memory and CPU registers for fast access
❏ Protection of memory required to ensure correct operation
Base and Limit Registers
● A pair of base and limit registers define the logical address space
● CPU must check every memory access generated in user mode to be sure it is between base and limit for that
user
Hardware Address Protection
Operating Systems
Address Space
Logical vs. Physical Address Space
● The concept of a logical address space that is bound to a separate
physical address space is central to proper memory
management
○ Logical address – generated by the CPU; also referred to
as virtual address
○ Physical address – address seen by the memory unit
● Logical and physical addresses are the same in compile-time and
load-time address-binding schemes; logical (virtual) and physical
addresses differ in execution-time address-binding scheme
● Logical address space is the set of all logical addresses
generated by a program
● Physical address space is the set of all physical addresses
generated by a program
Memory-Management Unit (MMU)
● MMU - Hardware device that at run time maps virtual to
physical address
● consider simple scheme where the value in the relocation register
is added to every address generated by a user process at the time
it is sent to memory
○ Base register now called relocation register
○ MS-DOS on Intel 80x86 used 4 relocation registers
● The user program deals with logical addresses; it never sees the
real physical addresses
○ Execution-time binding occurs when reference is made to
location in memory
○ Logical address bound to physical addresses
Dynamic Loading
● Routine is not loaded until it is called
● Better memory-space utilization; unused routine is
never loaded
● All routines kept on disk in relocatable load format
● Useful when large amounts of code are needed to
handle infrequently occurring cases
● No special support from the operating system is
required
○ Implemented through program design
○ OS can help by providing libraries to implement
dynamic loading
Dynamic Linking
● Static linking – system libraries and program code combined by the loader into the binary program image
● Small piece of code, stub, used to locate the appropriate memory-resident library routine
● Stub replaces itself with the address of the routine, and executes the routine
● Worst-fit: Allocate the largest hole; must also search entire list
○ Produces the largest leftover hole
Fragmentation
● External Fragmentation – total memory space exists to satisfy a
request, but it is not contiguous
● Internal Fragmentation – allocated memory may be slightly larger
than requested memory; this size difference is memory internal to a
partition, but not being used
● For First fit, statistical analysis reveals that given N blocks allocated,
another 0.5 N blocks lost to fragmentation
○ 1/3 may be unusable -> 50-percent rule
● Reduce external fragmentation by compaction
○ Shuffle memory contents to place all free memory together in
one large block
○ Compaction is possible only if relocation is dynamic, and is done
at execution time
Operating Systems
Segmentation
Segmentation
● Memory-management scheme that supports user view of
memory
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4
3
● Segment table – maps two-dimensional physical addresses; each table entry has:
○ base – contains the starting physical address where the segments reside in memory
○ limit – specifies the length of the segment
● Segment-table base register (STBR) points to the segment table’s location in memory
● To run a program of size N pages, need to find N free frames and load
program
● Set up a page table to translate logical to physical addresses
● The two memory access problem can be solved by the use of a special
fast-lookup hardware cache called associative memory or translation
look-aside buffers (TLBs)
Associative Memory
● Associative memory – parallel search
● Hit ratio = α
○ Hit ratio – percentage of times that a page number is found in the
associative registers;
● Consider α = 80%, ε = 20ns for TLB search, 100ns for memory access
● Consider α = 80%, ε = 20ns for TLB search, 100ns for memory access
○ EAT = 0.80 x 120 + 0.20 x 200 = 136ns
● Consider more realistic hit ratio -> α = 99%, ε = 20ns for TLB search, 100ns for
memory access
○ EAT = 0.99 x 120 + 0.01 x 200 = 120.8ns
Operating Systems
Shared Pages
Shared Pages
● Shared code
○ One copy of read-only (reentrant) code shared among processes (i.e., text
editors, compilers, window systems)
○ Similar to multiple threads sharing the same process space
○ Also useful for inter-process communication if sharing of read-write pages is
allowed