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IASSim: A programmable emulator for the princeton IAS/Von Neumann

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DOI: 10.1145/1953163.1953271

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 IASSim: A Programmable Emulator for the Princeton
IAS/Von Neumann Machine
Barry Fagin Dale Skrien
Dept. of Computer Science, US Air Force Academy Dept. of Computer Science, Colby College
2354 Fairchild Drive 5851 Mayflower Hill
USAFA, CO 80840 Waterville, ME 04901-8858
1-719-333-7377 1-207-859-5851
[email protected] [email protected]

ABSTRACT For block (3), the obvious choice for reading material was Burks,
In this paper, we describe a programmable emulator for the Goldstine and Von Neumann’s technical report [4]. So for the
Princeton IAS/Von Neumann machine. The emulator is corresponding assignment a close encounter with the Princeton
historically accurate, preserving the quirks and eccentricities of Institute for Advanced Study (IAS) computer seemed appropriate.
the machine. It is also user-friendly and robust, suitable for Preliminary inquiries, however, indicated no emulators or
undergraduate architecture and programming classes as a teaching comparable tools existed. Fortunately, the second author had
tool. Users can write non-trivial programs in IAS assembly code developed an extendible microprogrammed simulator “CPU Sim”
or machine code. We present some examples here, and discuss [10] that could implement a wide variety of architectures and
assignments from its first use in two undergraduate classes. instruction sets. This led to collaborative development of
IASSim is a Java application publicly available at no cost. IASSim, a “frozen” offshoot of CPU Sim that faithfully models
assembly language programming on the original IAS machine.
Categories and Subject Descriptors This tool is described here.
C.0 [Computer Systems Organization]: General – instruction
set design, modeling of computer architecture. 2. PREVIOUS WORK
A large variety of computer simulators have been developed for
General Terms educational purposes [6,7,11,14]. Such simulators have value in
Measurement, Design, Standardization, Languages, Verification. environments where resources are limited and the actual
computers are not available for study. They are also valuable in
Keywords introductory courses, in which the study and programming of real
Emulation, IAS Machine, Von Neumann Architecture, architectures would be too complex and time consuming.
Courseware, Computer Architecture. Most simulators imitate a specific architecture. Some simulate
very simple ones [9] that give beginning students a feel for how
1. INTRODUCTION CPUs work. Others simulate real modern architectures, such as
In 2009, the first author began development of a “Great Ideas in the MIPS machine [13]. Many such simulators are discussed in
Computer Science” course, designed for a special academic two issues of JERIC [1,2]. Simulators allow you to study the
program at the US Air Force Academy. Courses in this program architecture of and write programs for computers that no longer
were intended to engage students directly with the fundamental physically exist, except possibly in museums. For example, there
ideas and fundamental figures in the discipline under study. The are simulators for the PDP-8 [2] and the EDSAC [5].
“Great Ideas” chosen by the author, presented in historical order, Unfortunately, no simple simulator could be found by the authors
were 1) Computation as calculation, 2) Computation and its limits for the IAS architecture. This led to the creation of IASSim.
as articulated by Turing, 3) Computation as a physically realizable
idea, 4) Programming languages and software, 5) Computational 3. THE IAS MACHINE
complexity, 6) Cryptography, and 7) The future of computing. The IAS machine is named after the Princeton Institute for
Reading materials chosen included Babbage’s work on the Advanced Study, where it was developed by a team headed by the
Difference Engine [3], Turing’s original paper on computation mathematician John Von Neumann. Von Neumann had met Alan
[12], Rivest, Shamir and Adelman’s paper on public key Turing during the latter’s short stay at Princeton, and was very
cryptosystems [8] and so forth. All students read and discuss the interested in bringing Turing’s ideas to life by building an actual
original papers, and do “hands-on” assignments intended to computer. While there will always be controversy regarding who
acquaint them with the associated ideas as directly as possible. built the “first” computer, the technical report [4] describing the
Copyright 2011 Association for Computing Machinery. ACM acknowledges IAS machine is generally regarded as the first and most
that this contribution was authored or co-authored by an employee, authoritative publication of the general ideas used in computers
contractor or affiliate of the U.S. Government. As such, the Government today. We therefore chose it and the machine it describes as the
retains a nonexclusive, royalty-free right to publish or reproduce this article, “Great Idea” that would best illustrate humanity’s attempts to
or to allow others to do so, for Government purposes only.
SIGCSE’11, March 9–12, 2011, Dallas, Texas, USA.
Copyright 2011 ACM 978-1-4503- 0500-6/11/03...$10.00.

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 Table 1: The IAS Instruction Set
inst name opcode description
S(x)->Ac+ 1 copy the number in Selectron location x into AC AC: Accumulator
S(x)->Ac- 2 same as #1 but copy the negative of the number AR: Arithmetic Register
S(x)->AcM 3 same as #1 but copy the absolute value
S(x)->Ac-M 4 same as #1 but subtract the absolute value
S(x)->Ah+ 5 add the number in Selectron location x into AC
S(x)->Ah- 6 subtract the number in Selectron location x from AC
S(x)->AhM 7 same as #5, but add the absolute value
S(x)->Ah-M 8 same as #7, but subtract the absolute value
S(x)->R 9 copy the number in Selectron location x into AR
R->A 10 copy the number in AR to AC
Multiply the number in Selectron location x by the number in AR.
S(x)*R->A 11 Place the left half of the result in AC and the right half in AR.
Divide the number in AC by the number in Selectron location x.
A/S(x)->R 12 Place the quotient in AR and the remainder in AC.
Cu->S(x) 13 Continue execution at the left-hand instruction of the pair at Selectron location x
Cu`->S(x) 14 Continue execution at the right-hand instruction of the pair at Selectron location x
Cc->S(x) 15 If the number in AC is >= 0, continue as in #13. Otherwise, continue normally.
Cc`->S(x) 16 If the number in AC is >= 0, continue as in #14. Otherwise, continue normally.
At->S(x) 17 Copy the number in AC to Selectron location x
Replace the right-hand 12 bits of the left-hand instruction at Selectron location x
Ap->S(x) 18 by the right-hand 12 bits of AC
Ap`->S(x) 19 Same as above, but modifies right-hand instruction
L 20 Shift the number in AC to the left 1 bit (new bit on the right is 0)
R 21 Shift the number in AC to the right 1 bit (leftmost bit is copied)
halt 0 Halt the program (see paragraph 6.8.5 of IAS report)

first realize computation with actual machines. We used it as the Instructions use 20 bits and so two instructions fit in one word.
guideline in designing IASSim. Halfwords that are used as instructions store the opcode in the left
8 bits, and use the remaining 12 as an address or instruction
Table 1 shows the instruction set of the IAS machine, as originally operand. Instructions and data are co-resident in memory, one of
described in [4]. This is also the instruction set of IASSim. To the fundamental contributions of this machine to computer
recreate the “look and feel” of the original, and to emphasize the science. Instructions are fetched one pair at a time, and executed
origins of programming in mathematics, IASSim preserves the from left to right within the word and from lower addresses to
opcode notation as described by the original authors. Original higher, unless branching interrupts the normal flow.
terminology is also preserved, for example, in the description of a
memory cell as a “Selectron location”. Opcodes are identical to The IAS machine has two programmer-visible registers: The
those originally described in [4]. Contrary to present practice, the Accumulator (AC or A in the table) and the Arithmetic Register
source of an instruction is on the left, destination on the right. (AR or R in the table). Both are 40 bits wide. The AR is set only
by a special load instruction or one of two arithmetic instructions;
The IAS machine organizes memory into 4K words of 40 bits the AC is the more common target. Instructions 13 and 14 are
each. In a quote worth pointing out to students, the authors of the unconditional branches, while 15 and 16 provide conditional
IAS architecture noted "this memory capacity exceeds the branching. Instructions 18 and 19 are used for indexing, which
capacities required for most problems that one deals with at the IAS machine achieves through self-modifying code.
present by a factor of about 10" [4]. They chose a 40-bit word
size since it gave about 12 decimal places of accuracy, "higher The IAS machine does not include any instructions for handling
than what is required for the great majority of present day I/O and so all data must be loaded into memory directly (either
problems" [4]. In this machine, 40-bit integers are stored in 2's manually or via assembly pseudoinstructions) before the program
complement notation. is executed. IASSim includes an option for the programmer to
specify the target load address.
Floating point numbers were not supported in the IAS machine. It
is worth pointing out and discussing Von Neumann’s views on The original IAS report does not specify a halt instruction.
this topic [4] in the classroom. In a nutshell, Von Neumann However, paragraph 6.8.5 states “There is one further order that
believed that the costs were not worth the benefits. If you could the control needs to execute … which will tell the computer to
not keep track of where the binary point belonged during your stop and to flash a light or ring a bell.” In that spirit, we have
calculations, you had no business using a computer. provided a HALT instruction with a zero opcode that will stop
computation and ring a bell. Mercifully, the auditory component
of this instruction can be disabled by the user.

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 ; adds up the values n+...+3+2+1(+0) in a loop and stores
; the sum in memory at the location labeled “sum”

loop:
S(x)->Ac+ n ;load n into AC
Cc->S(x) pos ;if AC >= 0, jump to pos
halt ;otherwise done
.empty ;a 20-bit 0
pos: S(x)->Ah+ sum ;add n to the sum
At->S(x) sum ;put total back at sum
S(x)->Ac+ n ;load n into AC
S(x)->Ah- one ;decrement n
At->S(x) n ;store decremented n
Cu->S(x) loop ;go back and do it again

n: .data 5 ;will loop 6 times total

one: .data 1 ;constant for decrementing n
sum: .data 0 ;where the running/final total is kept

Figure 1: Summing numbers from 1 to n on the IAS Machine

4. A SAMPLE IAS PROGRAM .empty pseudoinstruction stores a 20-bit zero at the indicated
The IAS machine had no assembly language or assembler, and so halfword. Because all instruction fetches are 40 bits at a time, and
coding needed to be done in machine language. However, to because alignment errors are difficult for beginning students to
simplify programming and to make it more useful as a teaching catch and debug, the IASSim assembler enforces labels and
tool, we have provided a basic assembly language and assembler branch targets to align with word boundaries. The .empty
as part of IASSim. pseudoinstruction enables programs to comply with this
requirement.
Figure 1 shows how the IAS machine could be programmed to
sum the numbers from 1 to n, where n is stored in a memory 5. RUNNING PROGRAMS WITH IASSim
location. IASSim supports labeling of memory locations. Labels The opening screen of IASSim is shown in Figure 2. Memory
are terminated with a colon. Each instruction and operand contents appear in the large window on the left. Only a small
corresponds to a 20-bit halfword. Comments are indicated with a number of 40-bit words are shown below, but the size of memory
semicolon. is user-configurable.
The .data pseudoinstruction converts its operand to a 40-bit
binary number and stores it at the current memory location. The

Figure 2: Opening Screen of IASSim

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 Figure 3: After Executing the First Two Instructions

In addition to the previously mentioned AC and AR registers, the next instruction to be executed is always highlighted in the
the Registers window also permits students to view some program window and the Rams Selectron Window
internals of the machine, as an aid to understanding and Programs may be executed to completion at any time by
debugging. Consistent with our emphasis on historical pressing “Go”. At the end of execution, 15 (the sum of the
accuracy, we employ the authors’ original terminology. The numbers from 1 to 5) is stored in the memory location
Control Counter is what we now call the Program Counter. The corresponding to the label “sum:”, the Control Counter holds the
Control Register holds the currently executing instruction. The address of the halt instruction, and the simulator highlights the
Function Table Register holds the current opcode, the Memory empty halfword after it.
Address Register the current memory address, and the Selectron
Register the current data value being read from or written to 6. IASSim TECHNICAL DETAILS
memory. IASSim is based on CPU Sim [10], a Java application that the
Assembly language programs like that of Figure 1 can be second author created for use in introductory computer
created using either the built-in text editor or an external editor organization classes. It was modeled on the STARTLE
and stored as text files. The built-in editor has syntax simulator developed by J. Kerridge and N. Willis [7]. CPU Sim
highlighting specifically designed for IAS assembly language. was designed to simulate many different CPU architectures,
including simple accumulator-based architectures, RISC
Program windows can be opened from the “File” menu, and
architectures, and stack-based architectures such as the JVM.
then assembled and loaded from the “Execute” menu. The
RAM Selectrons window shows each instruction halfword When using CPU Sim, the user can specify a previously saved
loaded into memory, with the upper eight bits of opcode visually architecture or can create a new one. In the latter case, the user
separated as an aid to learning. specifies the CPU features such as the number and width of
registers, the size of main memory, the instruction set, and the
Placing the simulator into “Debug” mode enables setting break
layout and implementation of the instruction set using
points and allows single step execution of the program forward
microinstructions. Once a CPU architecture has been specified,
or backward. After two instructions are executed, the resulting
the user can write and run assembly language and machine
screen is shown in Figure 3. Note that the value of n (5) is now
language programs for that architecture within the CPU Sim
loaded into the accumulator. Since the contents of the
environment.
accumulator are positive, execution will continue at the
instruction labeled “pos:” This can be verified by examining the CPU Sim provides standard debugging tools such as break
value of the Control Counter. The instruction at the branch points and stepping forward and backward through the code to
target has not yet been fetched, so the Control Register still inspect and optionally change the values in registers or memory
holds the previous instruction executed. When in debug mode, at any point.

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IASSim was created by modifying CPU Sim to simulate only perform so well in writing assembly language programs for a
the IAS architecture. Quite a few modifications were necessary 60-year-old computer suggests that IASSim is a useful and
because of the IAS's non-standard features, such as 40-bit words effective teaching tool.
containing either a 40-bit data value or two 20-bit instructions.
To keep IASSim as simple as possible, many menus and menu 7.2 Using IASSim in a CS Course
items used in CPU Sim to allow the user to modify the The second author used IASSim in his computer organization
architecture were removed from IASSim. class in the spring of 2010. The 23 students had already been
using CPU Sim for a month before the IASSim assignment was
7. TEACHING INSIGHTS given, and so they felt very comfortable with the IASSim
package. A brief (6 paragraph) introduction to the IAS
7.1 Using IASSim in a “Great Ideas” Course architecture was given and a sample program was provided that
As mentioned previously, the first author used IASSim in a found the larger of two integers. Then the students were given
“Great Ideas” computer science course, taught to freshman assignments to find the largest of 3 integers, evaluate a cubic
cadets at the US Air Force Academy. Although most of these polynomial, and copy a value into a series of consecutive
students had some computer programming in high school, the locations in memory.
course had no formal prerequisites other than admission into the
USAFA Scholars Program, a program designed to identify the Scores on this assignment are shown below:
top forty or so cadets in each class based on their academic
potential. The course is not required for the computer science IAS  programming  assignment  scores  
major, and although any student enrolled may declare the CS (max=30,  upperclass  CS  majors)  
major in their sophomore year (the typical time for cadets to
declare), it is expected that most will not. 20  
#   15  
Students in this course read the original IAS tech report [4], and
then used IASSim as a vehicle to explore humanity’s first students   10  
attempts to build actual prototypes of Turing’s Universal scoring  in   5  
Computing Machine [12]. Students had written their own range   0  
Turing machines using a tool developed at USAFA, designed to 27+   24+   21+   18+   15+  
follow Turing’s notation and style as much as possible.
Although many students had taken some computer programming Score  range  
in high school, for some their construction of Turing Machines
was their only programming background prior to tackling this
assignment. The students were asked to keep track of the amount of time it
took them to complete these assignments. The average was
Nonetheless, all students successfully completed ten IAS about 4 hours for all three assignments, with the times ranging
assembly language programming assignments. These included from 1.5 hours to 7 hours. These numbers were not significantly
summing two or three numbers, finding the maximum of two or out of line with previous and later CPU Sim assignments. It
three numbers, polynomial evaluation, adding a scalar to a appears that, because of previous exposure to the CPU Sim
vector, multiplying a vector by a scalar, primality testing, and package, simple accumulator based architectures, and self-
using Von Neumann’s algorithm in [4] to calculate reciprocals. modifying code, the students took the IASSim assignments in
Students reported a range of 3 to 15 hours of effort to complete stride with no complaints and no significant difficulties.
all 10 problems, with an average of around 7 hours. The class
average was 95%, with three perfect submissions. A histogram
7.3 Educational Impact
of their performance on the IAS programming task is shown Although the tool is still fairly new and has only been used in
below. two courses at two institutions, we have some evidence of its
educational utility.

IAS  programming  assignment  scores   We have, for example, performance data from IASSim’s use on
(max=100,  freshmen,  non-­‐CS  majors)   graded tasks. The results clearly show that students (albeit in
some cases very bright and highly motivated ones) can use a 60-
15   year-old instruction set architecture to accomplish programming
#   tasks, and can do so with a reasonable amount of effort.
students   10   Qualitatively, we have also seen some evidence of pedagogical
scoring   5   value in using IASSim. Students who work with a “real”
in  range   0   architecture that is nonetheless limited to 12-bit addresses gain
an immediate and practical insight into the relationship between
95+   90+   85+   80+   75+   address space and computational power. The awkwardness of
the “left” and “right” instructions in the IAS also helps students
Score  range   appreciate modern architectures and provides an appreciation for
simplicity and regularity in engineering design.
These results should be interpreted with caution. Students in the One particularly unconventional feature warrants special
Academy Scholars program are an extremely bright and mention. Memory addresses in the IAS architecture can only
motivated group. Nonetheless, the fact that a group of college come from instruction fields (it has no index register). Since
freshmen with a wide variety of academic interests were able to addresses for array accesses are not normally known at compile

363
 time, array indexing requires the address fields of instructions to Speaking from experience, the authors can attest that they will
change while the program runs. Hence if you are working with learn in dramatic fashion the impact of architectural decisions on
vectors on the IAS machine (as the original designers did), you compiler design!
must employ self-modifying code.
IASSim is available for download at http://www.cs.colby.edu/
We believe challenging students with a programming problem djskrien/IASSim/. Source code will be freely provided to anyone
for which the only answer is self-modifying code provides a interested in inspecting or improving it. We hope a user
very useful historical and technical perspective. The historical community will develop that will find bugs, report experiences,
perspective illustrates that even towering intellectual figures develop assignments, and suggest features for future releases.
don’t always get the right answer the first time around.
Sometimes, only the experience of working with a system will 9. ACKNOWLEDGMENTS
show a better way to solve a problem. The authors wish to thank our students in "Computer
The technical perspective is relevant today. Self-modifying Organization" (Colby) and “Introduction to Computing,
code is so frowned-upon as a programming practice that it is Scholars Section” (USAFA) for their service as beta testers.
seldom, if ever taught, and never to beginning programmers.
However, virtually all of the most sophisticated viruses work by
10. REFERENCES
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