Siemens Digital Industries Software

Tessent SiliconInsight
with ATE-Connect
Simplify silicon bring-up and debug
on Automatic Test Equipment

Executive summary
Tessent SiliconInsight with ATE-Connect technology significantly improves
the silicon bring-up, debug, and IP evaluation flow. It enables very efficient
IP debug by DFT engineers on their familiar Tcl-based environment and
provides remote ATE access with light- weight network transaction with
incremental protocols. This connection between the DFT environment and
the ATE eliminates communication barriers between proprietary tester-spe-
cific software and DFT platforms, which accelerates debug of IJTAG devices,
speeds product ramps, and reduces time-to-market for products in 5G wire-
less communications, autonomous driving, and artificial intelligence.

Matthew Knowles, Siemens EDA

siemens.com/eda
 White paper | Tessent SiliconInsight with ATE-Connect — Simplify silicon bring-up and debug on Automatic Test Equipment

Introduction

The complexity of modern System on a Chips (SoC) SoC design technology trends
continues to increase as chip makers strive to deliver Designers have been increasing the amount of IP used
more capabilities to their customers. This complexity in each design for years, and the trend is increasing as
typically involves adding new hardware functionality, shown in figure 1. For 5G wireless communication,
which requires the integration of new and diverse semi- autonomous driving, and artificial intelligence applica-
conductor IPs (intellectual property). The growing num- tions, the amount of IP, and the cost of that IP, is
ber of semiconductor IP blocks implemented in SoCs increasing steadily. According to Semico Research, IP
poses some challenges to the entire design flow that reuse accounts for more than 60% of design starts.
can affect cost and time-to-market. Improving the pro- The increase in IP use is spurred by the need to control design
cess of silicon bring-up for test pattern evaluation and complexity. Standardized blocks save time and money over
debug has become an important element of rapid yield designing new circuitry in house. However, the complexity still
ramp-up and improved time-to-market. increases as the number of transistors increases. In 2015, the
Designers have been rapidly adopting new design flows average SoC had about 34M gates, according to Semico
and methods to improve DFT and yield of large SoCs, Research. By 2020, the average is predicted to be about 78M
such as using IJTAG (IEEE 1687) for a plug-and-play gates. Today, designs for artificial intelligence application can
style integration, but what’s available for improving IP contain 20+ billion transistors. The complexity of SoCs overall
is only going up, constantly stressing design schedules, tools,
evaluation and debug post-silicon?
and knowledge.
The traditional silicon bring-up and debug flow is inef-
IP, while helping to control complexity, creates new challenges
ficient and ripe for improvement. In some cases, design
throughout the design and test of the SoC. For example, how
engineers specify test descriptions in documents and in do you more effectively access all the diverse on-chip IP for
others tests can be generated by simulations. When DFT test? The answer to that has recently emerged in the form of
engineers (or designers) generate tests they send test IEEE standard 1687, also called IJTAG. It enables access and
pattern files to test engineers, who convert the file control of all on-chip ‘instruments’. Adoption of IJTAG is
formats for the ATE who then validate the patterns on quickly increasing.
the silicon. The test engineers send the results back to
the DFT engineers, who have to translate the results 20.0% 300.0
that design tools understand. This long process is 18.0%
250.0
repeated multiple times and in some cases can take 16.0%
several days or weeks for fully debugged tests. There is 14.0% 200.0
12.0%
now a system that directly connects the DFT engineers
10.0% 150.0
with the ATE tester, removing the iterations and stream- 8.0%
lining the silicon bring-up, IP evaluation, and pattern 6.0%
100.0
debug process significantly. 4.0% 50.0
2.0%
Tessent SiliconInsight with ATE-Connect™ technology 0.0
0.0%
coupled with Teradyne’s PortBridge for UltraFLEX,
20 *
20 *
20 *

*
*
07
08
09
10
11
12
13

20 4
15

18
19
16

20
17
1

allows DFT engineers to directly control and observe IPs

20
20
20
20
20
20
20
20

20
20

in the SoC under test on the ATE. The communication Avg. number of IP blocks Percent of silicon cost
works through industry-standard IJTAG commands,
eliminating the burden of dealing with several different Figure 1: Semico Research Corporation, “Licensing, Royalty, and Service
protocol interfaces for different ATEs. Revenues For 3rd Party SIP: A Market Analysis and Forecast for 2018.”

Siemens Digital Industries Software 2

 White paper | Tessent SiliconInsight with ATE-Connect — Simplify silicon bring-up and debug on Automatic Test Equipment

Difficulties in 3rd-party ip evaluation and debug • A DFT engineer generates patterns in a standard
Many of the challenges of integrating IP from either format and sign them off to a test engineer (possibly
internal design groups or from 3rd-party providers can along with indication about analog stimulus / mea-
be automated by using IJTAG networks and test descrip- surement depending on IP).
tions. Even though IJTAG streamlines IP integration
• The test engineer converts those patterns to ATE
during the design phase, problems have persisted dur-
native patterns, runs them on ATE, and then send
ing IP evaluation and debug during silicon bring-up,
back the pattern results (along with analog measure-
particularly for 3rd-party IP. In-house IP, however, can
ment results depending on IPs).
be thoroughly evaluated in the IP development phase
on TEG (Test Element Group) chips and are considered • This big loop is repeated multiple times.
“trusted” IP. There is more uncertainty and risk with Unlike logic evaluation, analog evaluation is very sensi-
3rd-party IP, so IP evaluation and debug in silicon bring- tive to slight differences of environmental conditions,
up becomes an important factor for quick production access sequences, waiting time and etc. So the back-
yield ramp-up. and-force processes in this big loop could become more
IP from 3rd-party vendors often describe tests that are frequent with analog IP evaluations. Since evaluation
agnostic to tester capabilities. When tests don’t work as testers (ATEs) are normally shared among multiple
intended, design engineers expect the combination of groups and tester time-slots must be reserved, it could
ATE instruments (digital, analog, serdes and RF) to be as happen that the next time slots would not be available
flexible as they are in simulation or at the bench. Given until the next day or the day after, and it could result in
that the IP design knowledge resides in the IP vendors critically long time just to try slightly different
or in the chip integrators design group, the DFT engi- conditions.
neers define the design of experiments to the test Even if the DFT engineer could be involved in 3rd-party
under debug. There are differences in how the tester IP evaluation and debug in real-time with the device on
implements a test and how it is described by the DFT ATE, it is common for the DFT engineer to be located far
engineer. The gulf between the two roles introduces from the test engineer’s site where the ATEs are placed.
inefficient iterations, as shown in figure 2. It’s impracti- Using a graphical online meeting tool to share ATE
cal for a DFT engineer (or a designer) to operate ATE, graphical tools is better than nothing, but it isn’t a great
and impossible for a test engineer to debug a device solution.
without design information. The traditional flow goes
something like this:
Translate
Retarget

Test
STIL / WGL program

ATE
Translate
Reverse

Pin/cycle
map

STDF
fail data

Figure 2: IP evaluation requires significant learning and is prone to errors causing increased cycle time.

Siemens Digital Industries Software 3

 White paper | Tessent SiliconInsight with ATE-Connect — Simplify silicon bring-up and debug on Automatic Test Equipment

The Tessent Siliconinsight ATE-Connect solution along with Tessent commands and Tcl commands and
Tessent SiliconInsight with ATE-Connect technology procedures. IJTAG commands such as iRead and iWrite
solves the key problems of IJTAG-based IP evaluation are cumulatively kept on the Shell, and IJTAG com-
and debug. Some of the key features include: mands such as iApply, iReset and iCall incrementally
send IJTAG protocols to the ATE. The Shell environment
• It can be run by the DFT engineers and designers in a
reports the execution results as ICL network register
protocol-based flow instead of a pattern-based flow by
values, and the Tcl program can process these register
using IJTAG commands.
values as variables.
• It allows DFT engineers and designers to use their
This IP debug flow requires only a chip-level ICL file and
familiar Tcl-based Tessent Shell interface.
PDL files (along with related Tcl procedures if needed).
• It allows DFT engineers and designers to access ATE Although a firewall normally exists between the design
remotely with incremental and light-weight communi- servers and the tester controllers, users can put just ICL
cation through TCP. and PDL files on a server in the same security level as
that of the tester controllers. Also, because only a single
Figure 3 illustrates conceptual view of the Tessent
TCP port needs to be opened, the IT department may
SiliconInsight ATE-Connect usage in a protocol-based
allow opening a TCP port on the firewall.
flow with IJTAG commands. It is linked with a Teradyne
UltraFLEX tester using the PortBridge communication
library developed by Teradyne. The DFT engineer can
specify IJTAG commands in Tcl-based Tessent Shell Secure VPN

ATE-Connect

Control ATE through

“ATECommand”

Figure 3: IJTAG-based IP evaluation and debug with ATE-Connect. DFT engineers access a remote ATE through commands in the Tessent Shell environment.

Siemens Digital Industries Software 4

 White paper | Tessent SiliconInsight with ATE-Connect — Simplify silicon bring-up and debug on Automatic Test Equipment

As illustrated in figure 4, Tessent SiliconInsight provides a help with some level of understanding, but the transla-
consistent environment across DFT (with simulation), IP tion from the high-level design language to intermedi-
debug (on ATE), and field-return analysis (on system ate pattern format (WGL, STIL, etc.) to ATE native for-
board). In the pre-silicon stage, Tessent SiliconInsight mat ultimately obfuscates the intent as well as the
offers a capability called SimDUT to allow users to debug mechanism of test execution.
and validate the PDL procedures and related Tcl proce-
Accelerating debug on ATE requires the reduction or
dures if they have appropriate simulation models of
elimination of steps which add complexity and no value.
“target” IPs. When the silicon comes back from the
As shown in Figure 4, the Tessent Silicon Insight tools
foundry, users can start evaluation and debug of those IP
facilitate the simulation of tests with the SimDUT step.
blocks on ATE using Tessent SiliconInsight with ATE-
The addition of the ATE-Connect interface allows con-
Connect. To help analyze issues on a system board envi-
trol of real-world hardware. The Teradyne PortBridge
ronment without using ATE at all, as in the case of field
API was designed to allow high-level commands to be
returns, users can employ Tessent SiliconInsight Desktop.
delivered to the test program with on-the-fly translation
to the lower-level digital protocols or analog instrument
Accelerating ATE debug on Teradyne Ultraflex
control. The connection of the two interfaces results in
The debug process illustrated in figure 2 can be slow
a flow which allows design engineers to debug by exe-
and requires multiple people to interface across unfa-
cuting their tests written in high-level languages in their
miliar domains. The design side has access to complete
native environment. When assistance is required with
system operation and works in high-level languages to
ATE specific issues, the test engineers are able to use
design simulations and tests. The test side rarely has
the tools they understand and are proficient with.
access to the overall device knowledge and intent of the
Communication issues are minimized, each engineer
tests delivered to them. Patterns have historically been
operates in their native domain, and no inefficient
the bridge between the two worlds. While patterns are
patterns or non-standard feedback loops are required.
somewhat of a necessarily evil for production efficiency,
they serve neither side well. Embedded comments may

SimDUT
Design
Simulator

ATE-Connect™

Automated Test Equipment

ICL/PDL
TEDB
USB/
GPIB
Desktop
USB/
1149.1
Lab Test Equipment

Figure 4: Consistent platform from DFT through field-return analysis with Tessent SiliconInsight.

Siemens Digital Industries Software 5

 White paper | Tessent SiliconInsight with ATE-Connect — Simplify silicon bring-up and debug on Automatic Test Equipment

A simple example case is shown below in Figure 5. The

Tessent tools can utilize IJTAG to access and control the
MBIST engines shown in the upper right portion of the
DUT section. However, a more interesting case may be the
debug of the DAC and ADC IP blocks. The test engineer is
going to be interested in a fast and reliable test to opti-
mize yield and test cost. The designers will be interested in
functionality and characterization of critical parameters.
The Silicon Insight tools can assist with both goals.
To begin with, the test engineer can set up the test
program with a signal generator connected to the ADC
and a digitizer connected to the DAC. Once the ATE is
properly configured, the test engineer passes control to
the design engineer who begins running the previously
designed tests. The design engineer can debug those Figure 5: IJTAG-based design on ATE.
tests interactively if necessary. Once both IP blocks are
independently verified, the external ATE resources can The test engineer and design engineer now have confi-
be replaced with a loopback connection. This sort of dence that the tests are able to execute properly—ATE
test is potentially more economical and repeatable than and simulation are aligned. At this point, pattern gen-
one using external instrumentation. eration can proceed. Patterns are now no longer the
bottleneck and can be used for efficient production test.
However, the designer now finds that running the test In parallel, ATE-Connect can be used to target a bench
results in an issue. Assume the clocking in the two IP setup with the debugged tests. This can further acceler-
blocks was adequate for testing individually, but when ate correlation between the three environments which
put together, there is an issue. The designer now has the ultimately helps accelerate the time to market.
ability to look at the system level, adjust the necessary Optimizing the design to test loop is a key factor in
PLLs, and re-run the tests. Now they pass. A test engi- reducing the ultimate time to market.
neer would never have been able to control the system
in this manner using patterns and would have required
multiple iterations with design to try and find the issue.

Siemens Digital Industries Software 6

 White paper | Tessent SiliconInsight with ATE-Connect — Simplify silicon bring-up and debug on Automatic Test Equipment

Summary

Tessent SiliconInsight with ATE-Connect technology

significantly improves the silicon bring-up, debug, and
IP evaluation flow. It enables very efficient IP debug by
DFT engineers on their familiar Tcl-based environment
and provides remote ATE access with light-weight net-
work transaction with incremental protocols. This con-
nection between the DFT environment and the ATE
eliminates communication barriers between proprietary
tester-specific software and DFT platforms, which accel-
erates debug of IJTAG devices, speeds product ramps,
and reduces time-to-market for products in 5G wireless
communications, autonomous driving, and artificial
intelligence.

Siemens Digital Industries Software 7

Siemens Digital Industries Software About Siemens Digital Industries Software
Siemens Digital Industries Software is driving
Headquarters transformation to enable a digital enterprise where
Granite Park One engineering, manufacturing and electronics design
5800 Granite Parkway meet tomorrow. Our solutions help companies of all
Suite 600 sizes create and leverage digital twins that provide
Plano, TX 75024 organizations with new insights, opportunities and
USA levels of automation to drive innovation. For more
+1 972 987 3000 information on Siemens Digital Industries Software
products and services, visit siemens.com/software
Americas or follow us on LinkedIn, Twitter, Facebook and
Granite Park One Instagram. Siemens Digital Industries Software –
5800 Granite Parkway Where today meets tomorrow.
Suite 600
Plano, TX 75024
USA
+1 314 264 8499

Europe
Stephenson House
Sir William Siemens Square
Frimley, Camberley
Surrey, GU16 8QD
+44 (0) 1276 413200

Asia-Pacific
Unit 901-902, 9/F
Tower B, Manulife Financial Centre
223-231 Wai Yip Street, Kwun Tong
Kowloon, Hong Kong
+852 2230 3333

siemens.com/eda
© 2019 Siemens. A list of relevant Siemens trademarks can be found here. Other trademarks
belong to their respective owners.
81109-C2 12/18 BM