UNIVERSITY OF KWAZULU-NATAL
SCHOOL OF ELECTRICAL, ELECTRONIC AND COMPUTER
ENGINEERING
SUBJECT: EMBEDDED SYSTEMS
CODE: ENEL4ES
TEST ASSIGNMENT
DUE DATE: 30/09/2010 BEFORE LECTURE
TOTAL MARKS: 50
NO. PAGES: 2 PAGES
EXAMINERS
EXAMINER: DR T. WALINGO
INSTRUCTIONS
ANSWER ALL QUESTIONS
DO NOT WRITE IN PENCIL
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1. A system has a small cache of eight 32-bit words and a main memory of 1KB (256 words). Data are
transferred to cache 4 consecutive bytes at a time on a proper word boundary. The following
sequence of main memory addresses (in hexadecimal) are required by the CPU
54, 58, 104, 5C, 108, 60, F0, 64, 54, 58, 10C, 5C, 110, 60, F0, 64.
Initially the cache is empty. Determine:
a) For Direct Mapping:
i) The address components (Tag, Index, offset),
ii) The contents of the cache and the hit rate after execution.
b) For two-way set associative using the LRU algorithm:
i) The address components (Tag, Index, offset),
ii) The contents of the cache and the hit rate after execution.
2. You have a computer with two levels of cache memory and the following specifications:
CPU Clock: 200 MHz Bus speed: 50 MHz
Processor: 32-bit RISC scalar CPU, single data address maximum per instruction
L1 cache on-chip, 1 CPU cycle access
block size = 32 bytes, 1 block/sector, split I & D cache
each single-ported with one block available for access, non-blocking
L2 cache off-chip, 3 CPU cycles transport time
block size = 32 bytes, 1 block/sector, unified single-ported cache, blocking, non-pipelined
Main memory has 12+4+4+4 CPU cycles transport time for 32 bytes
Figure 2. shows the results of a simulation for the L1 cache:
Determine:
a) The available (as opposed to used) sustained bandwidth between:
i) L1 cache bandwidth available to CPU (assuming 0% L1 misses)?
ii) L2 cache bandwidth available to L1 cache (assuming 0% L2 misses)?
iii) Main memory bandwidth available to L2 cache?
b) How long does an instruction (all type of instructions) take to execute (in ns), assuming 1 clock cycle
per instruction in the absence of memory hierarchy stalls, no write buffering at the L1 cache level,
and 0% L2 miss rate.
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Figure 2. Simulation Results
