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Adders

Adders

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mohanapriya2210021
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6 views

Adders

Adders

Uploaded by

mohanapriya2210021
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Name: Mella Likitha

Register No: 3122223002075

Exp.No: 01 Date:02-08-2024

Design and Implementation of Full-adder


AIM:

To design and implement the adders using structural/behavioural model and verify their
functionality using Xilinx FPGA Trainer Kit

 To design and model a 1-bit Full adder using structural/dataflow/behavioural modelling.


 To compile, simulate and plot the results using Xilinx Tools.
 To implement the proposed systems using Xilinx Tools and generate the synthesis report.
 To demonstrate the working of the proposed systems using Xilinx FPGA Trainer Board.

EQUIPMENT/SOFTWARE REQUIRED:

Hardware: Nexys-A7 with device type Artix-7 based trainer kit

Software: Xilinx vivado

THEORY:

A full-adder is a combinational logic circuit that performs the arithmetic sum of three input bits:
two significant bits (A and B) and a carry bit (Cin) from a previous lower significant position. It is
an essential component in digital electronics, particularly in the design of arithmetic circuits like
adders and subtractors.

FUNCTIONAL DESCRIPTION:
FULL ADDER:
TRUTH TABLE
A B Carry-in Sum Carry-out
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1

UEC 2512 VLSI Design Lab


Name: Mella Likitha
Register No: 3122223002075

1 1 0 0 1
1 1 1 1 1

BOOLEAN EQUATION:
Inputs: A, B &Cin:
Outputs: Sum: A ^ B ^ Cin
Carry: (A & B)||(B &Cin)||(Cin& A)

BLOCK DIAGRAM:

FULL ADDER:

LOGIC DIAGRAM:
FULL ADDER:

VERILOG HDL PROGRAM:

a) 1 BIT FULL ADDER

module fulladd(sum,cout,a,b,c);
output sum,cout;

UEC 2512 VLSI Design Lab


Name: Mella Likitha
Register No: 3122223002075

input a,b,c;
wire s1,c1,c2,c3;
xor(s1,a,b);
xor(sum,s1,c);
and(c1,a,b);
and(c2,b,c);
and(c3,a,c);
or(cout,c1,c2,c3);
endmodule
STIMULUS FILE:
module fulladdstim;
reg a,b,c;
wire sum,cout;
fulladder fa(sum,cout,a,b,c);
initial
begin
$monitor($time, "a=%b, b=%b, c=%b,sum=%b, cout=%b",a, b, c, sum, cout);
end
initial
begin
a=1'b0;b=1'b0;c=1'b0;
#5 a=1'b0;b=1'b0;c=1'b1;
#5 a=1'b0;b=1'b1;c=1'b0;
#5 a=1'b0;b=1'b1;c=1'b1;
#5 a=1'b1;b=1'b0;c=1'b0;
#5 a=1'b1;b=1'b0;c=1'b1;
#5 a=1'b1;b=1'b1;c=1'b0;
#5 a=1'b1;b=1'b1;c=1'b1;
end
endmodule

SIMULATION RESULTS:

OUTPUT WAVEFORMS:

a) 1 BIT FULL ADDER:

UEC 2512 VLSI Design Lab


Name: Mella Likitha
Register No: 3122223002075

CONSOLE WINDOW :

UEC 2512 VLSI Design Lab


Name: Mella Likitha
Register No: 3122223002075

UTILITY REPORT:

RESULT:

Thus, Full-adder is designed and implemented using structural/behavioural model and their
functionality is verified using Xilinx FPGA Trainer Kit.

UEC 2512 VLSI Design Lab


Name: Mella Likitha
Register No: 3122223002075

UEC 2512 VLSI Design Lab

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