School of Electronics Engineering (SENSE)

B. Tech – Electronics & Computer Engineering

BECE406E - FPGA BASED SYSTEM DESIGN

LAB RECORD
(L33+L34)

Submitted By
21BLC1374 – Pranav Pratap Patil

Submitted To
Dr. Sahthivel S M
DATE: 02/09/2024
[21BLC1374] Lab 6 – Serial and Parallel Multiplier 02/09/2024

Slot: L33+L34

LAB - 6
Serial and Parallel Multiplier
AIM: To Design implement, and verify both a parallel and a serial multiplier for 4-bit inputs
using Quartus in Verilog. Verify their functionality by simulating them in ModelSim and
analyzing the resulting waveforms.

Software Required: Quartus Prime, ModelSim

Hardware Required: Altera Cyclone IV E DE2-115 Kit, USB Cable, Power Supply

Procedure:
1. Start Quartus Prime Lite Edition.
2. Go To : File → New Project Wizard.
3. Set The Working Directory and Name of the Project and Create an Empty Project.
4. Set Family to “Cyclone IV E”, Package to “FBGA”, Pin Count to “780” , Core Speed
Grade to “7” and Set Device as “EP4CE115F29C7”.
5. Set Simulation Tool to “ModelSim” and Format to “Verilog HDL”.
6. Verify all details in Summary are Acurate then click Finish.
7. Go To : File → New → “Verilog HDL File”, To create a New File.
8. Code the Apropriate Verilog Program in the File and Save It.
9. Once Done, Go To : Processing → Start Compilation, To compile the Verilog Code.
10. To Perform RTL Simulation Go To : Tools → Run Simulation Tool → RTL Simulation.
11. Perform The Necessary Simulations in ModelSim and Verify The Output.

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[21BLC1374] Lab 6 – Serial and Parallel Multiplier 02/09/2024

Serial Multiplier (Sequential):

Code:
module serialMultiplier (
input clk, // Clock signal
input reset, // Reset signal
input start, // Start signal (to begin multiplication)
input [3:0] A, // 4-bit input A (multiplicand)
input [3:0] B, // 4-bit input B (multiplier)
output reg [7:0] P, // 8-bit product
output reg done // Done signal (indicates multiplication is complete)
);
reg [3:0] count; // Counter to track the number of iterations
reg [3:0] multiplicand; // Store the multiplicand (A)
reg [7:0] product; // Store the partial product
reg [3:0] multiplier; // Store the multiplier (B)

always @(posedge clk or posedge reset) begin

if (reset) begin
P <= 0;
product <= 0;
multiplicand <= 0;
multiplier <= 0;
count <= 0;
done <= 0;
end
else if (start) begin
if (count == 0) begin
multiplicand <= A;
multiplier <= B;
product <= 0;
count <= 4;
done <= 0;
end
else if (count > 0) begin
if (multiplier[0] == 1) begin
product = product + (multiplicand << (4 - count));
end
multiplier = multiplier >> 1;
count = count - 1;
if (count == 1) begin
P <= product;
done <= 1;
end
end
end
end
endmodule

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[21BLC1374] Lab 6 – Serial and Parallel Multiplier 02/09/2024

Output:
Case 1: A = 4’b0011, B = 4’0101, Product = 8’00001111

Case 2: A = 4’b1101, B = 4’1011, Product = 8’10001111

Case 3: A = 4’b1001, B = 4’0011, Product = 8’00011011

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[21BLC1374] Lab 6 – Serial and Parallel Multiplier 02/09/2024

Resource Utilization:

Technology Map:

Parallel Multiplier:
Top Level Code:
module arrayMultiplier(
A,
B,
P
);
input wire [3:0] A;
input wire [3:0] B;
output wire [7:0] P;

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[21BLC1374] Lab 6 – Serial and Parallel Multiplier 02/09/2024

wire SYNTHESIZED_WIRE_0;
wire SYNTHESIZED_WIRE_1;
wire SYNTHESIZED_WIRE_2;
wire SYNTHESIZED_WIRE_3;
wire SYNTHESIZED_WIRE_4;
wire SYNTHESIZED_WIRE_5;
wire SYNTHESIZED_WIRE_6;
wire SYNTHESIZED_WIRE_7;
wire SYNTHESIZED_WIRE_8;
wire SYNTHESIZED_WIRE_9;
wire SYNTHESIZED_WIRE_10;
wire SYNTHESIZED_WIRE_11;
wire SYNTHESIZED_WIRE_12;
wire SYNTHESIZED_WIRE_13;
wire SYNTHESIZED_WIRE_14;
wire SYNTHESIZED_WIRE_15;
wire SYNTHESIZED_WIRE_16;
wire SYNTHESIZED_WIRE_17;
wire SYNTHESIZED_WIRE_18;
wire SYNTHESIZED_WIRE_19;
wire SYNTHESIZED_WIRE_20;
wire SYNTHESIZED_WIRE_21;
wire SYNTHESIZED_WIRE_22;
wire SYNTHESIZED_WIRE_23;
wire SYNTHESIZED_WIRE_24;
wire SYNTHESIZED_WIRE_25;
wire SYNTHESIZED_WIRE_26;
wire SYNTHESIZED_WIRE_27;
wire SYNTHESIZED_WIRE_28;
wire SYNTHESIZED_WIRE_29;
wire SYNTHESIZED_WIRE_30;
wire SYNTHESIZED_WIRE_31;

assign SYNTHESIZED_WIRE_30 = B[0] & A[1];

fullAdder b2v_inst10(
.A(SYNTHESIZED_WIRE_0),
.B(SYNTHESIZED_WIRE_1),
.CIN(SYNTHESIZED_WIRE_2),
.SUM(SYNTHESIZED_WIRE_7),
.COUT(SYNTHESIZED_WIRE_5));

fullAdder b2v_inst11(
.A(SYNTHESIZED_WIRE_3),
.B(SYNTHESIZED_WIRE_4),
.CIN(SYNTHESIZED_WIRE_5),
.SUM(SYNTHESIZED_WIRE_9),
.COUT(SYNTHESIZED_WIRE_12));

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[21BLC1374] Lab 6 – Serial and Parallel Multiplier 02/09/2024

halfAdder b2v_inst12(
.A(SYNTHESIZED_WIRE_6),
.B(SYNTHESIZED_WIRE_7),
.SUM(P[2]),
.CARRY(SYNTHESIZED_WIRE_10));

fullAdder b2v_inst13(
.A(SYNTHESIZED_WIRE_8),
.B(SYNTHESIZED_WIRE_9),
.CIN(SYNTHESIZED_WIRE_10),
.SUM(SYNTHESIZED_WIRE_15),
.COUT(SYNTHESIZED_WIRE_13));

fullAdder b2v_inst14(
.A(SYNTHESIZED_WIRE_11),
.B(SYNTHESIZED_WIRE_12),
.CIN(SYNTHESIZED_WIRE_13),
.SUM(SYNTHESIZED_WIRE_17),
.COUT(SYNTHESIZED_WIRE_20));

halfAdder b2v_inst15(
.A(SYNTHESIZED_WIRE_14),
.B(SYNTHESIZED_WIRE_15),
.SUM(P[3]),
.CARRY(SYNTHESIZED_WIRE_18));

fullAdder b2v_inst16(
.A(SYNTHESIZED_WIRE_16),
.B(SYNTHESIZED_WIRE_17),
.CIN(SYNTHESIZED_WIRE_18),
.SUM(SYNTHESIZED_WIRE_23),
.COUT(SYNTHESIZED_WIRE_21));

fullAdder b2v_inst17(
.A(SYNTHESIZED_WIRE_19),
.B(SYNTHESIZED_WIRE_20),
.CIN(SYNTHESIZED_WIRE_21),
.SUM(SYNTHESIZED_WIRE_25),
.COUT(SYNTHESIZED_WIRE_28));

halfAdder b2v_inst18(
.A(SYNTHESIZED_WIRE_22),
.B(SYNTHESIZED_WIRE_23),
.SUM(P[4]),
.CARRY(SYNTHESIZED_WIRE_26));

fullAdder b2v_inst19(
.A(SYNTHESIZED_WIRE_24),

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[21BLC1374] Lab 6 – Serial and Parallel Multiplier 02/09/2024

.B(SYNTHESIZED_WIRE_25),
.CIN(SYNTHESIZED_WIRE_26),
.SUM(P[5]),
.COUT(SYNTHESIZED_WIRE_29));

fullAdder b2v_inst20(
.A(SYNTHESIZED_WIRE_27),
.B(SYNTHESIZED_WIRE_28),
.CIN(SYNTHESIZED_WIRE_29),
.SUM(P[6]),
.COUT(P[7]));

assign SYNTHESIZED_WIRE_6 = B[2] & A[0];

assign SYNTHESIZED_WIRE_8 = B[2] & A[1];
assign SYNTHESIZED_WIRE_11 = B[1] & A[3];
assign SYNTHESIZED_WIRE_14 = B[3] & A[0];
assign SYNTHESIZED_WIRE_16 = B[2] & A[2];
assign SYNTHESIZED_WIRE_19 = B[2] & A[3];
assign SYNTHESIZED_WIRE_22 = B[3] & A[0];
assign SYNTHESIZED_WIRE_24 = B[3] & A[2];
assign SYNTHESIZED_WIRE_27 = B[3] & A[3];
assign SYNTHESIZED_WIRE_31 = B[1] & A[0];
assign SYNTHESIZED_WIRE_0 = B[1] & A[1];
assign P[0] = B[0] & A[0];
assign SYNTHESIZED_WIRE_1 = B[0] & A[2];
assign SYNTHESIZED_WIRE_3 = B[0] & A[3];
assign SYNTHESIZED_WIRE_4 = B[1] & A[2];

halfAdder b2v_inst9(
.A(SYNTHESIZED_WIRE_30),
.B(SYNTHESIZED_WIRE_31),
.SUM(P[1]),
.CARRY(SYNTHESIZED_WIRE_2));
endmodule

Logic Design Modules:

Half Adder:

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[21BLC1374] Lab 6 – Serial and Parallel Multiplier 02/09/2024

Full Adder:

Parallel Multiplier:

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[21BLC1374] Lab 6 – Serial and Parallel Multiplier 02/09/2024

Output:

Case 1: A = 4’b0011, B = 4’0101, Product = 8’00001111

Case 2: A = 4’b1101, B = 4’1011, Product = 8’10001111
Case 3: A = 4’b1001, B = 4’0011, Product = 8’00011011

Resource Utilization:

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[21BLC1374] Lab 6 – Serial and Parallel Multiplier 02/09/2024

Technology Map:

Inference:
We have understood how to design a Serial and Parallel Multiplier and using various design
techniques and inferred that the Parallel Multiplier requires less Logical Elements as compared
to a Serial Multiplier and hence is much faster and takes less area.

Result:
Thus, we have successfully designed, implemented and verified both a parallel and a serial
multiplier for 4-bit inputs using Quartus in Verilog. We have succesfuly verified their
functionality by simulating them in ModelSim and analyzing the resulting waveforms.

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