LT3501

Monolithic Dual Tracking

3A Step-Down Switching
Regulator
Features Description
n Wide Input Range: 3.1V to 25V The LT®3501 is a dual-current mode PWM step-down
n Two Switching Regulators with 3A Output Capability DC/DC converter with two internal 3.5A switches. Inde-
n Independent Supply to Each Regulator pendent input voltage, feedback, soft-start and power
n Adjustable/Synchronizable Fixed Frequency good pins for each channel simplify complex power
Operation from 250kHz to 1.5MHz supply tracking/sequencing requirements.
n Antiphase Switching Both converters are synchronized to either a common
n Outputs Can be Paralleled
external clock input or a resistor programmable fixed
n Independent, Sequential, Ratiometric or Absolute
250kHz to 1.5MHz internal oscillator. At all frequencies, a
Tracking Between Outputs
180° phase relationship between channels is maintained,
n Independent Soft-Start and Power Good Pins
reducing voltage ripple and component size. Programmable
n Enhanced Short-Circuit Protection
frequency allows for optimization between efficiency and
n Low Dropout: 95% Maximum Duty Cycle
external component size.
n Low Shutdown Current: <10µA
n 20-Lead TSSOP Package with Exposed Leadframe Minimum input-to-output voltage ratios are improved
by allowing the switch to stay on through multiple clock
Applications cycles, only switching off when the boost capacitor needs
n DSP Power Supplies recharging, resulting in ~95% maximum duty cycle.
n Disc Drives Each output can be independently disabled using its own
n DSL/Cable Modems soft-start pin, or by using the SHDN pin the entire part can
n Wall Transformer Regulation be placed in a low quiescent current shutdown mode.
n Distributed Power Regulation
The LT3501 is available in a 20-lead TSSOP package with
L, LT, LTC, LTM, Linear Technology, Burst Mode and the Linear logo are registered trademarks
and ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the exposed leadframe for low thermal resistance.
property of their respective owners.

Typical Application
3.3V and 1.8V Dual 3A Step-Down Converter with Output Tracking Efficiency
VIN, 12V 100
VOUT1 = 5V VOUT1 = 3.3V
4.7µF 90
VIN1 VIN2 61.9k 80
SHDN RT/SYNC
70 VOUT1 = 1.8V
BST1 BST2 VOUT1 = 2.5V
EFFICIENCY (%)

4.7µH 0.47µF 0.47µF 3.3µH 60

SW1 SW2
50
PMEG4005 PMEG4005 B360A B360A 40
LT3501
VOUT2 30
IND1 IND2
1.8V, 3A
VOUT1 VOUT2 20 VIN = 12V
VOUT1
3.3V, 3A 24.9k 10k 100µF 10 IOUT2 = 0A
PG1 PG2 FREQUENCY = 500kHz
47µF FB1 FB2 0
VC1 VC2 0 0.5 1 1.5 2 2.5 3
470pF SS/TRACK1 SS/TRACK2 470pF LOAD CURRENT (A)
8.06k 8.06k
GND 3501 TA01b

10pF 40.2k 40.2k 47pF

0.1µF
3501 TA01a

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 LT3501
Absolute Maximum Ratings Pin Configuration
(Note 1)
VIN1/2, SHDN, PG1/2....................................... 25V/–0.3V TOP VIEW

SW1/2.....................................................................VIN1/2 VIN1 1 20 BST1

BST1/2............................................................ 35V/–0.3V SW1 2 19 SS/TRACK1

BST1/2 Pins Above SW1/2.........................................25V IND1 3 18 VC1

IND1/2 .......................................................................±5A VOUT1 4 17 FB1

PG1 5 16 RT/SYNC
VOUT1/2......................................................... VIN1/2 /–0.3V 21
PG2 6 15 SHDN
FB1/2, SS1/2, RT/SYNC.............................................5.5V
VOUT2 7 14 FB2
VC1/2....................................................................... ±1mA IND2 8 13 VC2
Operating Junction Temperature Range SW2 9 12 SS/TRACK2
LT3501EFE (Notes 2, 8)...................... –40°C to 125°C VIN2 10 11 BST2
LT3501IFE (Notes 2, 8)....................... –40°C to 125°C
FE PACKAGE
Storage Temperature Range................... –65°C to 150°C 20-LEAD PLASTIC TSSOP
Lead Temperature (Soldering, 10 sec).................... 300°C TJMAX = 125°C, θJA = 45°C/W, θJC(PAD) = 10°C/W
EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB

Order Information
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LT3501EFE#PBF LT3501EFE#TRPBF LT3501 20-Lead Plastic TSSOP –40°C to 125°C
LT3501IFE#PBF LT3501IFE#TRPBF LT3501 20-Lead Plastic TSSOP –40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

Electrical Characteristics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TJ = 25°C. VVIN1/2 = 15V, VBST1/2 = open, VRT/SYNC = 2V, VVOUT1/2 = open,
unless otherwise specified.
PARAMETER CONDITIONS MIN TYP MAX UNITS
SHDN Threshold VOUT1/2 = 0V, RT/SYNC = 133k l 1.23 1.28 1.37 V
SHDN Input Current VSHDN = 1.375V 7 10 13 µA
VSHDN = 1.225V 2 3 5 µA
Minimum Input Voltage Ch 1 (Note 3) VFB1/2 = 0V, VVOUT1/2 = 0V, VIND1/2 = 0V, RT/SYNC = 133k 2.8 3 V
Minimum Input Voltage Ch 2 VFB1/2 = 0V, VVOUT1/2 = 0V, VIND1/2 = 0V 2.8 3 V
Supply Shutdown Current Ch 1 VSHDN = 0V l 9 30 µA
Supply Shutdown Current Ch 2 VSHDN = 0V 0 5 µA
Supply Quiescent Current Ch 1 VFB1/2 = 0.9V 3.5 5 mA
Supply Quiescent Current Ch 2 VFB1/2 = 0.9V 200 500 µA
Feedback Voltage Ch 1/Ch 2 VVC1/2 = 1V l 0.784 0.8 0.816 V
Feedback Voltage Line Regulation VVIN1/2 = 3V to 25V l –1 0 1 %
Feedback Voltage Offset Ch 1 to Ch 2 VVC1/2 = 1V l –16 0 16 mV
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 LT3501
Electrical Characteristics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TJ = 25°C. VVIN1/2 = 15V, VBST1/2 = open, VRT/SYNC = 2V, VVOUT1/2 = open,
unless otherwise specified.
PARAMETER CONDITIONS MIN TYP MAX UNITS
Feedback Bias Current Ch 1/Ch 2 VFB1/2 = 0.8V, VVC1/2 = 1V l –250 75 250 nA
Error Amplifier gm Ch 1/Ch 2 VVC1/2 = 1V, IVC1/2 = ±5µA l 150 275 450 µmho
Error Amplifier Gain Ch 1/Ch 2 1000 V/V
Error Amplifier to Switch Gain Ch 1/Ch 2 3.3 A/V
Error Amplifier Source Current Ch 1/Ch 2 VFB1/2 = 0.6V, VVC1/2 = 1V 10 15 25 µA
Error Amplifier Sink Current Ch 1/Ch 2 VFB1/2 = 1V, VVC1/2 = 1V 15 20 30 µA
Error Amplifier High Clamp Ch 1/Ch 2 VFB1/2 = 0.7V 1.75 2.0 2.25 V
Error Amplifier Switching Threshold Ch 1/Ch 2 VOUT1/2 = 5V, RT/SYNC = 133k 0.5 0.7 1 V
Soft-Start Source Current Ch 1/Ch 2 VFB1/2 = 0.6V, VSS1/2 = 0.4V l 2 3 4.2 µA
Soft-Start VOH Ch 1/Ch 2 VFB1/2 = 0.9V 1.9 2 2.4 V
Soft-Start Sink Current Ch 1/Ch 2 VFB1/2 = 0.6V, VSS1/2 = 1V 200 600 1000 µA
Soft-Start VOL Ch 1/Ch 2 VFB1/2 = 0V 50 80 125 mV
Soft-Start to Feedback Offset Ch 1/Ch 2 VVC1/2 = 1V, VSS1/2 = 0.4V l –16 0 16 mV
Soft-Start Sink Current Ch 1/Ch 2 POR VSS1/2 = 0.4V (Note 4), VVC = 1V 0.5 1.5 2 mA
Soft-Start POR Threshold Ch 1/Ch 2 VFB1/2 = 0V (Note 4) 55 80 105 mV
Soft-Start Switching Threshold Ch 1/Ch 2 VFB1/2 = 0V 30 50 70 mV
Power Good Leakage Ch 1/Ch 2 VFB1/2 = 0.9V, VPG1/2 = 25V, VVIN1/2 = 25V 0 1 µA
Power Good Threshold Ch 1/Ch 2 VFB1/2 Rising, PG1/2 = 20k to 5V l 87 90 93 %
Power Good Hysteresis Ch 1/Ch 2 VFB1/2 Falling, PG1/2 = 20k to 5V 20 30 50 mV
Power Good Sink Current Ch 1/Ch 2 VFB1/2 = 0.65V, VPG1/2 = 0.4V 400 800 1200 µA
Power Good Shutdown Sink Current Ch 1/Ch 2 VVIN1/2 = 2V, VFB1/2 = 0V, VPG1/2 = 0.4V 10 50 100 µA
RT/SYNC Reference Voltage VFB1/2 = 0.9V, IRT/SYNC = –40µA 0.93 0.975 1 V
Switching Frequency RT/SYNC = 133k, VFB1/2 = 0.6V, VBST1/2 = VSW + 3V 200 250 300 kHz
RT/SYNC = 15.4k, VFB1/2 = 0.6V, VBST1/2 = VSW + 3V 1.2 1.5 1.8 MHz
Switching Phase Angle Ch A to Ch B RT/SYNC = 133k, VFB1/2 = 0.6V, VBST1/2 = VSW + 3V 120 180 210 Deg
Minimum Boost for 100% Duty Cycle Ch 1/Ch 2 VFB1/2 = 0.7V, IRT/SYNC = –35µA (Note 5), VOUT = 0V 1.7 2 V
SYNC Frequency Range VBST1/2 = VSW + 3V 250 1500 kHz
SYNC Switching Phase Angle Ch A to Ch B SYNC Frequency = 250kHz, VBST1/2 = VSW + 3V 120 180 210 Deg
IND + VOUT Current Ch 1/Ch 2 VVOUT1/2 = 0V, VFB1/2 = 0.9V 40 70 100 µA
VVOUT1/2 = 5V 0 1 µA
IND to VOUT Maximum Current Ch 1/Ch 2 VVOUT1/2 = 0.5V (Note 6), VFB1/2 = 0.7V, VBST1/2 = 20V 3.25 4 5 A
VVOUT1/2 = 5V (Note 6), RT/SYNC = 133k, VBST1/2 = 20V 3.5 4 5 A
Switch Leakage Current Ch 1/Ch 2 VSW1/2 = 0V, VVIN1/2 = 25V l 0 50 µA
Switch Saturation Voltage Ch 1/Ch 2 ISW1/2 = 3A, VBST1/2 = 20V, VFB1/2 = 0.7V l 250 600 mV
Boost Current Ch 1/Ch 2 ISW1/2 = 3A, VBST1/2 = 20V, VFB1/2 = 0.7V 25 60 100 mA
Minimum Boost Voltage Ch 1/Ch 2 ISW1/2 = 3A, VBST1/2 = 20V, VFB1/2 = 0.7V 1.4 2.5 V
Note 1: Stresses beyond those listed under Absolute Maximum Ratings characterization and correlation with statistical process controls. The
may cause permanent damage to the device. Exposure to any Absolute LT3501IFE is guaranteed and tested over the full –40°C to 125°C operating
Maximum Rating condition for extended periods may affect device junction temperature range.
reliability and lifetime. Note 3: Minimum input voltage is defined as the voltage where internal
Note 2: The LT3501EFE is guaranteed to meet performance specifications bias lines are regulated so that the reference voltage and oscillator remain
from 0°C to 125°C junction temperature. Specifications over the –40°C constant. Actual minimum input voltage to maintain a regulated output will
to 125°C operating junction temperature range are assured by design, depend upon output voltage and load current. See Applications Information.
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 LT3501
Electrical Characteristics
Note 4: An internal power-on reset (POR) latch is set on the positive current flowing from the IND pin to the VOUT pin which resets the switch
transition of the SHDN pin through its threshold. The output of the latch latch when the VC pin is at its high clamp.
activates current sources on each SS pin which typically sink 1.5mA, Note 7: This is the minimum voltage across the boost capacitor needed to
discharging the SS capacitor. The latch is reset when both SS pins are guarantee full saturation of the internal power switch.
driven below the soft-start POR threshold or the SHDN pin is taken below Note 8: This IC includes overtemperature protection that is intended
its threshold. to protect the device during momentary overload conditions. Junction
Note 5: To enhance dropout operation, the output switch will be turned off temperature will exceed 125°C when overtemperature protection is active.
for the minimum off-time only when the voltage across the boost capacitor Continuous operation above the specified maximum operating junction
drops below the minimum boost for 100% duty cycle threshold. temperature may impair device reliability.
Note 6: The IND to VOUT maximum current is defined as the value of

Typical Performance Characteristics

Shutdown Threshold and Minimum
Feedback Voltage vs Temperature RT/SYNC Voltage vs Temperature Input Voltage vs Temperature
0.816 1.05 3.0

0.811 2.5 MINIMUM INPUT

1.03 VOLTAGE

0.806 2.0
SHUTDOWN

VOLTAGE (V)
VOLTAGE (V)
VOLTAGE (V)

1.01
THRESHOLD
0.801 1.5 VOLTAGE
0.99
0.796 1.0

0.97
0.791 0.5

0.786 0.95 0
–50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125
TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C)
3501 G02 3501 G03 3501 G04

Shutdown Quiescent Current Soft-Start Source Current IND to VOUT Maximum Current
vs Temperature vs Temperature vs Temperature
16 4.0 5.0
3.8 4.8
14
VVIN1 3.6 4.6
12
3.4 4.4
CURRENT (µA)

10
CURRENT (µA)

CURRENT (A)

3.2 4.2
VOUT = 5V
8 3.0 4.0

2.8 3.8 VOUT = 0V

6
2.6 3.6
4
2.4 3.4
2 3.2
VVIN2 2.2
0 2.0 3.0
–50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125
TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C)
3501 G05 3501 G06 3501 G07

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 LT3501
Typical Performance Characteristics
Soft-Start to Feedback Offset VC Switching Threshold Voltage Power Good Threshold Voltage
Voltage vs Temperature vs Temperature vs Temperature
4 1000 800
780
3
900
760
2
740
800 RISING
VOLTAGE (mV)

1 VOUT = 5V

VOLTAGE (V)

VOLTAGE (V)
720
0 700 700 FALLING
VOUT = 0V 680
–1
600
660
–2
640
500
–3 620
–4 400 600
–50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125
TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C)
3501 G08 3501 G09 3501 G10

Power Good Sink Current Minimum Switching Times Switching Frequency and Channel
vs Temperature vs Temperature Phase vs Temperature
1000 250 300 200
RT/SYNC = 133kΩ
950 230 290 190
900 210 280 180
MINIMUM ON-TIME PHASE
850 190 FREQUENCY (kHz) 270 170
CURRENT (µA)

PHASE (DEG)
800 170 260 160
TIME (ns)

750 150 250 150

700 130 240 FREQUENCY 140
MINIMUM OFF-TIME
650 110 230 130
600 90 220 120
550 70 210 110
500 50 200 100
–50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125
TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C)
3501 G11 3501 G12 3501 G13

Switching Frequency and Channel Synchronization Clock Frequency Channel Phase vs Temperature
Phase vs Temperature Range vs Temperature with External Synchronization
1650 200 2500 188
RRT/SYNC = 15.4k
195 186
1600 164
PHASE 190 2000
185 MAXIMUM 182
1550
FREQUENCY (kHz)

FREQUENCY (kHz)

SYNCHRONIZATION SYNCHRONIZATION
PHASE (DEG)
PHASE (DEG)

180 1500 180 FREQUENCY = 250kHz

FREQUENCY FREQUENCY
1500 175 178
170 1000 176
1450 174
165
160 500 MINIMUM 172
1400 SYNCHRONIZATION SYNCHRONIZATION
155 FREQUENCY 170 FREQUENCY = 1500kHz
1350 150 0 168
–50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125
TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C)
3501 G14 3501 G15 3501 G16

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 LT3501
Typical Performance Characteristics
External Sync Duty Cycle Range Frequency and Phase vs RT/SYNC Switch Saturation Voltage
vs External Sync Frequency Pin Resistance vs Switch Current
100 1600 190 450
90 400
1400 185
MAXIMUM CLOCK FREQUENCY 125°C
80 350
DUTY CYCLE 1200 180
70 25°C

FREQUENCY (kHz)
300
DUTY CYCLE (%)

VOLTAGE (mV)
1000 175

PHASE (DEG)
60
250
50 800 170 –50°C
PHASE 200
40
600 165
150
30
MINIMUM CLOCK 400 160
20 100
DUTY CYCLE
10 200 155 50

0 100 150 0
250 500 750 1000 1250 1500 0 20 40 60 80 100 120 140 0.5 1 1.5 2 2.5 3 3.5
FREQUENCY (kHz) RESISTANCE (kΩ) CURRENT (A)
3501 G17 1344 G18 3501 G19

Minimum Boost Voltage VOUT + IND Current VOUT + IND Current

vs Temperature vs Temperature vs Voltage
2.5 100 100
95 90
2.0 90 80
85 70

CURRENT (µA)
CURRENT (µA)
VOLTAGE (V)

1.5 80 60
75 50
1.0 70 40
65 30
0.5 60 20
55 10
0 50 0
–50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
TEMPERATURE (°C) TEMPERATURE (°C) VOLTAGE (V)
3501 G21 3501 G22 3501 G23

Minimum Input Voltage Minimum Input Voltage Minimum Input Voltage

vs Load Current vs Load Current vs Load Current
5.0 6.0 7.5
VOUT = 2.5V VOUT = 3.3V VOUT = 5V

4.5 5.5 7.0

4.0 5.0 6.5

VOLTAGE (V)

VOLTAGE (V)
VOLTAGE (V)

3.5 4.5 6.0

3.0 4.0 5.5

RUNNING RUNNING
RUNNING
2.5 3.5 5.0

2.0 3.0 4.5

1 10 100 1000 10000 1 10 100 1000 10000 1 10 100 1000 10000
CURRENT (mA) CURRENT (mA) CURRENT (mA)
3501 G24 3501 G25 3501 G26

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 LT3501
Typical Performance Characteristics
Inductor Value vs Frequency for Inductor Value vs Frequency for
Dropout Operation 3A Maximum Load Current 3A Maximum Load Current
6 1500 1500
LOAD = 1A VOUT = 3.3V VOUT = 5V
IRIPPLE = 1A L = 2.2µH IRIPPLE = 1A
5
1250 1250
VOUT = 5V L = 2.2µH
OUTPUT VOLTAGE (V)

4 L = 3.3µH

FREQUENCY (kHz)
FREQUENCY (kHz)
1000 1000
L = 3.3µH
3 VOUT = 3.3V L = 4.7µH

750 750
2 L = 4.7µH
L = 6.8µH

1 FREQUENCY 500 500

L = 6.8µH
1.5MHz L = 10µH
250kHz
0 250 250
2 2.5 3 3.5 4 4.5 5 5.5 6 7 9 11 13 15 17 19 21 23 25 10 12.5 15 17.5 20 22.5 25
INPUT VOLTAGE (V) INPUT VOLTAGE (V) INPUT VOLTAGE (V)
3501 G27 3501 G28 3501 G29

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 LT3501
Pin Functions
VIN1 (Pin 1): The VIN1 pin powers the internal control SS1/SS2 (Pins 19, 12): The SS1/2 pins control the soft-
circuitry for both channels and is monitored by the under- start and sequence of their respective outputs. A single
voltage lockout comparator. The VIN1 pin is also connected capacitor from the SS pin to ground determines the output
to the collector of channel 1’s on-chip power NPN switch. ramp rate. For soft-start and output tracking/sequencing
The VIN1 pin has high dI/dt edges and must be decoupled details, see the Applications Information section.
to ground close to the pin of the device. VC1/VC2 (Pins 18, 13): The VC pin is the output of the
SW1/SW2 (Pins 2, 9): The SW pin is the emitter of the on- error amplifier and the input to the peak switch current
chip power NPN. At switch-off, the inductor will drive this comparator. It is normally used for frequency compensa-
pin below ground with a high dV/dt. An external Schottky tion, but can also be used as a current clamp or control
catch diode to ground, close to the SW pin and respective loop override. If the error amplifier drives VC above the
VIN decoupling capacitor’s ground, must be used to prevent maximum switch current level, a voltage clamp activates.
this pin from excessive negative voltages. This indicates that the output is overloaded and current is
pulled from the SS pin, reducing the regulation point.
IND1/IND2 (Pins 3, 8): The IND pin is the input to the
on-chip sense resistor that measures current flowing in FB1/FB2 (Pins 17, 14): The FB pin is the negative input
the inductor. When the current in the resistor exceeds to the error amplifier. The output switches regulate this
the current dictated by the VC pin, the SW latch is held in pin to 0.8V, with respect to the exposed ground pad. Bias
reset, disabling the output switch. Bias current flows out current flows out of the FB pin.
of the IND pin when IND is less than 1.6V. SHDN (Pin 15): The shutdown pin is used to turn off both
VOUT1/VOUT2 (Pins 4, 7): The VOUT pin is the output to channels and control circuitry to reduce quiescent current
the on-chip sense resistor that measures current flowing to a typical value of 9µA. The accurate 1.28V threshold and
in the inductor. When the current in the resistor exceeds input current hysteresis can be used as an undervoltage
the current dictated by the VC pin, the SW latch is held in lockout, preventing the regulator from operating until the
reset, disabling the output switch. Bias current flows out input voltage has reached a predetermined level. Force
of the VOUT pin when VOUT is less than 1.6V. the SHDN pin above its threshold or let it float for normal
operation.
PG1/PG2 (Pins 5, 6): The power good pin is an open-col-
lector output that sinks current when the feedback falls RT/SYNC (Pin 16): This RT/SYNC pin provides two modes
below 90% of its nominal regulating voltage. For VIN1 of setting the constant switch frequency.
above 1V, its output state remains true, although during Connecting a resistor from the RT/SYNC pin to ground
shutdown, VIN1 undervoltage lockout or thermal shutdown, will set the RT/SYNC pin to a typical value of 0.975V. The
its current sink capability is reduced. The PG pins can be resultant switching frequency will be set by the resistor
left open circuit or tied together to form a single power value. The minimum value of 15.4k and maximum value of
good signal. 133k sets the switching frequency to 1.5MHz and 250kHz,
VIN2 (Pin 10): The VIN2 pin is the collector of channel 2’s respectively.
on-chip power NPN switch. This pin is independent of VIN1 Driving the RT/SYNC pin with an external clock signal will
and may be connected to the same or a separate supply. In synchronize the switch to the applied frequency. Synchro-
either case, high dI/dt edges are present and decoupling nization occurs on the rising edge of the clock signal after
to ground must be used close to this pin.

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 LT3501
Pin Functions
the clock signal is detected, with switch 1 in phase with BST1/BST2 (Pins 20, 11): The BST pin provides a higher
the synchronization signal. Each rising clock edge initiates than VIN base drive to the power NPN to ensure a low
an oscillator ramp reset. A gain control loop servos the switch drop. A comparator to VIN imposes a minimum
oscillator charging current to maintain a constant oscillator off-time on the SW pin if the BST pin voltage drops too
amplitude. Hence, the slope compensation and channel low. Forcing a SW off-time allows the boost capacitor to
phase relationship remain unchanged. If the clock signal recharge.
is removed, the oscillator reverts to resistor mode and
Exposed Pad (Pin 21): GND. The Exposed Pad GND pin is
reapplies the 0.975V bias to the RT/SYNC pin after the
the only ground connection for the device. The Exposed
synchronization detection circuitry times out. The clock Pad should be soldered to a large copper area to reduce
source impedance should be set such that the current out thermal resistance. The GND pin is common to both chan-
of the RT/SYNC pin in resistor mode generates a frequency nels and also serves as small-signal ground. For ideal
roughly equivalent to the synchronization frequency. operation all small-signal ground paths should connect
to the GND pin at a single point, avoiding any high current
ground returns.

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 LT3501
Block Diagram
RT/SYNC VIN
ONE CHANNEL
R3 VIN1 C
CLK1
INTERNAL OSCILLATOR
REGULATOR AND
AND CLK2
AGC BST
REFERENCE DROPOUT
ENHANCEMENT
3µA
7µA
SLOPE C3
COMPENSATION PRE
– S
DRIVER
SHDN
Σ Q
CIRCUITRY
+ + R SW

+ – D
SHUTDOWN L1
1.28V COMPARATOR IND

POR +
UNDERVOLTAGE D
TSD – VOUT
+
0.8V
C

+ R1
LOWEST FB
VOLTAGE –
VC CLAMP R2
S
R Q
POWER GOOD
3.25mA COMPARATOR PGOOD
– –
+ +
SS CLAMP
+ +
SOFT-START 80mV 0.72V
GND RESET
COMPARATOR

3501 BD

SS VC

Figure 1. Block Diagram (One of Two Switching Regulators Shown)

The LT3501 is dual-channel, constant-frequency, current When the SHDN pin is opened or driven above 1.28V,
mode buck converter with internal 3A switches. Each the internal bias circuits turn on generating an internal
channel is identical with a common shutdown pin, internal regulated voltage, 0.8VFB, 0.975V RT/SYNC references,
regulator, oscillator, undervoltage detect, thermal shutdown and a POR signal which sets the soft-start latch.
and power-on reset.
As the RT/SYNC pin reaches its 0.975V regulation point,
If the SHDN pin is taken below its 1.28V threshold the the internal oscillator will start generating two clock sig-
LT3501 will be placed in a low quiescent current mode. nals 180° out of phase for each regulator at a frequency
In this mode the LT3501 typically draws 9µA from VIN1 determined by the resistor from the RT/SYNC pin to ground.
and <1µA from VIN2. In shutdown mode the PG is active Alternatively, if a synchronization signal is detected by the
with a typical sink capability of 50µA for VIN1 voltage LT3501 at the RT/SYNC pin, clock signals 180° out of phase
greater than 2V.

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 LT3501
Block Diagram
will be generated at the incoming frequency on the rising is turned off. Once the switch is turned off the inductor
edge of the synchronization pulse with switch 1 in phase will drive the voltage at the SW pin low until the external
with the synchronization signal. In addition, the internal Schottky diode starts to conduct, decreasing the current
slope compensation will be automatically adjusted to pre- in the inductor. The cycle is repeated with the start of each
vent subharmonic oscillation during synchronization. clock cycle. However, if the internal sense resistor voltage
exceeds the predetermined level at the start of a clock cycle,
The two regulators are constant-frequency, current mode
the flip-flop will not be set resulting in a further decrease in
step-down converters. Current mode regulators are con-
inductor current. Since the output current is controlled by
trolled by an internal clock and two feedback loops that
the VC voltage, output regulation is achieved by the error
control the duty cycle of the power switch. In addition to
amplifier continually adjusting the VC pin voltage.
the normal error amplifier, there is a current sense amplifier
that monitors switch current on a cycle-by-cycle basis. The error amplifier is a transconductance amplifier that
This technique means that the error amplifier commands compares the FB voltage to the lowest voltage present at
current to be delivered to the output rather than voltage. either the SS pin or an internal 0.8V reference. Compensa-
A voltage fed system will have low phase shift up to the tion of the loop is easily achieved with a simple capacitor
resonant frequency of the inductor and output capacitor, or series resistor/capacitor from the VC pin to ground.
then an abrupt 180°, shift will occur. The current fed sys-
Since the SS pin is driven by a constant current source, a
tem will have 90° phase shift at a much lower frequency,
single capacitor on the soft-start pin will generate controlled
but will not have the additional 90° shift until well beyond
linear ramp on the output voltage.
the LC resonant frequency. This makes it much easier to
frequency compensate the feedback loop and also gives If the current demanded by the output exceeds the maxi-
much quicker transient response. mum current dictated by the VC pin clamp, the SS pin
will be discharged, lowering the regulation point until the
The Block Diagram in Figure 1 shows only one of the
output voltage can be supported by the maximum current.
switching regulators whose operation will be discussed
When overload is removed, the output will soft-start from
below. The additional regulator will operate in a similar
the overload regulation point.
manner with the exception that its clock will be 180° out
of phase with the other regulator. VIN1 undervoltage detection or thermal shutdown will
set the soft-start latch, resulting in a complete soft-start
When, during power-up, the POR signal sets the soft-start
sequence.
latch, both SS pins will be discharged to ground to ensure
proper start-up operation. When the SS pin voltage drops The switch driver operates from either the VIN or BST volt-
below 80mV, the VC pin is driven low disabling switching age. An external diode and capacitor are used to generate
and the soft-start latch is reset. Once the latch is reset the a drive voltage higher than VIN to saturate the output NPN
soft-start capacitor starts to charge with a typical value and maintain high efficiency. If the BST capacitor voltage
of 3.25µA. is sufficient, the switch is allowed to operate to 100% duty
cycle. If the boost capacitor discharges towards a level
As the voltage rises above 80mV on the SS pin, the VC pin
insufficient to drive the output NPN, a BST pin compara-
will be driven high by the error amplifier. When the voltage
tor forces a minimum cycle off-time, allowing the boost
on the VC pin exceeds 0.7V, the clock set-pulse sets the
capacitor to recharge.
driver flip-flop which turns on the internal power NPN
switch. This causes current from VIN, through the NPN A power good comparator with 30mV of hysteresis trips
switch, inductor and internal sense resistor, to increase. at 90% of regulated output voltage. The PG output is an
When the voltage drop across the internal sense resistor open-collector NPN that is off when the output is in regu-
exceeds a predetermined level set by the voltage on the lation allowing a resistor to pull the PG pin to a desired
VC pin, the flip-flop is reset and the internal NPN switch voltage.
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 LT3501
Applications Information
Choosing the Output Voltage 1600 190

1400 185
The output voltage is programmed with a resistor divider FREQUENCY
between the output and the FB pin. Choose the 1% resis- 1200 180

FREQUENCY (kHz)
tors according to: 1000 175

PHASE (DEG)
800 170
V  PHASE
R1= R2 •  OUT – 1 600 165
 0.8V 
400 160

R2 should be 10k or less to avoid bias current errors. Refer- 200 155
ence designators refer to the Block Diagram in Figure 1. 100 150
0 20 40 60 80 100 120 140
RESISTANCE (kΩ)
Choosing the Switching Frequency 3501 F02

The LT3501 switching frequency is set by resistor R3 in Figure 2. Frequency and Phase vs RT/SYNC Resistance
Figure 1. The RT/SYNC pin is internally regulated at 0.975V.
Setting resistor R3 sets the current in the RT/SYNC pin The following example along with the data in Table 1
which determines the oscillator frequency as illustrated illustrates the trade-offs of switch frequency selection.
in Figure 2. Example:
The switching frequency is typically set as high as pos- VIN = 25V, VOUT = 3.3V, IOUT = 2.5A,
sible to reduce overall solution size. The LT3501 employs Temperature = 0°C to 85°C
techniques to enhance dropout at high frequencies but tON(MIN) = 200ns (85°C from Typical Characteristics
efficiency and maximum input voltage decrease due to graph), VD = 0.6V, VSW = 0.4V (85°C)
switching losses and minimum switch on-times. The 3.3 + 0.6 1
maximum recommended frequency can be approximated Max Frequency = • ~ 750 kHz
25 – 0.4 + 0.6 200e-9
by the equation:
VOUT + VD 1 R T /SYNc ~ 42k (Figure 2)
Frequency (Hz) = •
VIN – VSW + VD tON(MIN)
Input Voltage Range
where VD is the forward-voltage drop of the catch diode (D1 Once the switching frequency has been determined, the
Figure 2), VSW is the voltage drop of the internal switch, input voltage range of the regulator can be determined. The
and tON(MIN) in the minimum on-time of the switch, all at minimum input voltage is determined by either the LT3501’s
maximum load current. minimum operating voltage of ~2.8V, or by its maximum

Table 1. Efficiency and Size Comparisons for Different RRT/SYNC Values. 3.3V Output
EFFICIENCY
FREQUENCY RT/SYNC VVIN1/2 = 12V VIN(MAX)† L* C* C+L
1.2MHz 20.5k 79.0% 16 1.5µH 22µH 63mm2
1.0MHz 26.7k 80.9% 18 2.2µH 47µH 66mm2
750kHz 38.3k 81.2% 22 3.3µH 47µF 66mm2
500kHz 61.9k 82.0% 24 4.7µH 47µF 66mm2
250kHz 133k 83.9% 24 10µH 100µF 172mm2
†V
IN(MAX) is defined as the highest input voltage that maintains constant output voltage ripple.
*Inductor and capacitor values chosen for stability and constant ripple current.

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 LT3501
Applications Information
duty cycle. The duty cycle is the fraction of time that the 6.0
VOUT = 3.3V
internal switch is on during a clock cycle. Unlike most 5.5
fixed frequency regulators, the LT3501 will not switch off
at the end of each clock cycle if there is sufficient voltage 5.0

VOLTAGE (V)
across the boost capacitor (C3 in Figure 1) to fully satu- 4.5
START-UP

rate the output switch. Forced switch-off for a minimum

time will only occur at the end of a clock cycle when the 4.0

boost capacitor needs to be recharged. This operation

3.5
has the same effect as lowering the clock frequency for a RUNNING
fixed off-time, resulting in a higher duty cycle and lower 3.0
1 10 100 1000 10000
minimum input voltage. The resultant duty cycle depends CURRENT (mA)
on the charging times of the boost capacitor and can be 3501 F03

approximated by the following equation:

Figure 3. Minimum Input Voltage vs Load Current
1
DcMAX = Example:
1
1+ VOUT = 3.3V, IOUT = 1A, Frequency = 1MHz, Temperature
B
= 25°C
where B is 3A divided by the typical boost current from
VSW = 0.1V, B = 50 (from from boost characteristics
the Electrical Characteristics table.
specification), VD = 0.4V, tON(MIN) = 200ns
This leads to a minimum input voltage of:
1
V +V DcMAX = = 98%
VIN(MIN) = OUT D – VD + VSW 1
DcMAX 1+
50
where VSW is the voltage drop of the internal switch. 3.3 + 0.4
VIN(MIN) = – 0.4 + 0.1= 3.48V
Figure 3 shows a typical graph of minimum input voltage 0.98
vs load current for the 3.3V and 1.8V application on the
DcMIN = tMIN(ON) • f = 0.200
first page of this data sheet. The maximum input voltage
is determined by the absolute maximum ratings of the VIN 3.3 + 0.4
and BST pins and by the frequency and minimum duty VIN(MAX) = – 0.4 + 0.1= 18.2V
0.200
cycle. The minimum duty cycle is defined as :
DCMIN = tON(MIN) • Frequency Inductor Selection and Maximum Output Current
Maximum input voltage as: A good first choice for the inductor value is:

VIN(MAX) =
VOUT + VD
– VD + VSW L=
( VIN – VOUT ) • VOUT
DcMIN VIN • f
Note that the LT3501 will regulate if the input voltage is where f is frequency in MHz and L is in µH.
taken above the calculated maximum voltage as long as
With this value the maximum load current will be ~3A,
maximum ratings of the VIN and BST pins are not violated.
independent of input voltage. The inductor’s RMS current
However operation in this region of input voltage will exhibit
rating must be greater than your maximum load current
pulse skipping behavior.

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 LT3501
Applications Information
and its saturation current should be about 30% higher. To 3.5A over the entire duty cycle range. The maximum output
keep efficiency high, the series resistance (DCR) should current is a function of the chosen inductor value:
be less than 0.05Ω.
∆IL ∆I
IOUT(MAX) = ILIM – = 3.5 – L
For applications with a duty cycle of about 50%, the induc- 2 2
tor value should be chosen to obtain an inductor ripple
current less than 40% of peak switch current. If the inductor value is chosen so that the ripple current
is small, then the available output current will be near the
Of course, such a simple design guide will not always result switch current limit.
in the optimum inductor for your application. A larger value
provides a slightly higher maximum load current, and will One approach to choosing the inductor is to start with the
reduce the output voltage ripple. If your load is lower than simple rule given above, look at the available inductors
2.5A, then you can decrease the value of the inductor and and choose one to meet cost or space goals. Then use
operate with higher ripple current. This allows you to use these equations to check that the LT3501 will be able to
a physically smaller inductor, or one with a lower DCR deliver the required output current. Note again that these
resulting in higher efficiency. equations assume that the inductor current is continuous.
Discontinuous operation occurs when IOUT is less than
The current in the inductor is a triangle wave with an IL/2 as calculated above.
average value equal to the load current. The peak switch
current is equal to the output current plus half the peak-to- Figure 4 illustrates the inductance value needed for a 3.3V
peak inductor ripple current. The LT3501 limits its switch output with a maximum load capability of 3A. Referring
current in order to protect itself and the system from to Figure 4, an inductor value between 3.3µH and 4.7µH
overload faults. Therefore, the maximum output current will be sufficient for a 15V input voltage and a switch
that the LT3501 will deliver depends on the current limit, frequency of 750kHz. There are several graphs in the
the inductor value, switch frequency, and the input and Typical Performance Characteristics section of this data
output voltages. The inductor is chosen based on output sheet that show inductor selection as a function of input
current requirements, output voltage ripple requirements, voltage and switch frequency for several popular output
size restrictions and efficiency goals. voltages and output ripple currents. Also, low inductance
When the switch is off, the inductor sees the output volt- 1500
VOUT = 3.3V
age plus the catch diode drop. This gives the peak-to-peak IRIPPLE = 1A
ripple current in the inductor: 1250
L = 2.2µH
(1– Dc)( VOUT + VD )
FREQUENCY (kHz)

∆IL = 1000
L•f L = 3.3µH

750
where f is the switching frequency of the LT3501 and L L = 4.7µH
is the value of the inductor. The peak inductor and switch
500
current is L = 6.8µH

∆IL 250
ISW (PK ) = ILPK = I OUT + 7 9 11 13 15 17 19 21 23 25
2 INPUT VOLTAGE (V)
3501 F04

To maintain output regulation, this peak current must be

Figure 4. Inductor Values for 3A Maximum Load Current
less than the LT3501’s switch current limit ILIM. ILIM is vs Frequency and Input Voltage

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 LT3501
Applications Information
may result in discontinuous mode operation, which is ments of the input capacitor. Determine the worst-case
okay, but further reduces maximum load current. For condition for input ripple current and then size the input
details of maximum output current and discontinuous capacitor such that it reduces input voltage ripple to an
mode operation, see Linear Technology Application Note acceptable level. Typical values for input capacitors run
44. Finally, for duty cycles greater than 50% (VOUT/VIN from 10µF at low frequencies to 2.2µF at higher frequencies.
> 0.5), there is a minimum inductance required to avoid The combination of small size and low impedance (low
subharmonic oscillations. See Application Note 19 for equivalent series resistance or ESR) of ceramic capacitors
more information. make them the preferred choice. The low ESR results in
very low voltage ripple and the capacitors can handle plenty
Input Capacitor Selection of ripple current. They are also comparatively robust and
Bypass the inputs of the LT3501 circuit with a 4.7µF or can be used in this application at their rated voltage. X5R
higher ceramic capacitor of X7R or X5R type. A lower and X7R types are stable over temperature and applied
value or a less expensive Y5V type can be used if there voltage, and give dependable service. Other types (Y5V and
is additional bypassing provided by bulk electrolytic or Z5U) have very large temperature and voltage coefficients
tantalum capacitors. The following paragraphs describe of capacitance, so they may have only a small fraction of
their nominal capacitance in your application. While they
the input capacitor considerations in more detail.
will still handle the RMS ripple current, the input voltage
Step-down regulators draw current from the input supply in ripple may become fairly large, and the ripple current may
pulses with very fast rise and fall times. The input capaci- end up flowing from your input supply or from other by-
tor is required to reduce the resulting voltage ripple at the pass capacitors in your system, as opposed to being fully
LT3501 and to force this very high frequency switching sourced from the local input capacitor. An alternative to a
current into a tight local loop, minimizing EMI. The input high value ceramic capacitor is a lower value along with
capacitor must have low impedance at the switching fre- a larger electrolytic capacitor, for example a 1µF ceramic
quency to do this effectively, and it must have an adequate capacitor in parallel with a low ESR tantalum capacitor.
ripple current rating. With two switchers operating at the For the electrolytic capacitor, a value larger than 10µF will
same frequency but with different phases and duty cycles, be required to meet the ESR and ripple current require-
calculating the input capacitor RMS current is not simple. ments. Because the input capacitor is likely to see high
However, a conservative value is the RMS input current for surge currents when the input source is applied, tantalum
the channel that is delivering most power (VOUT • IOUT). capacitors should be surge rated. The manufacturer may
This is given by: also recommend operation below the rated voltage of the
capacitor. Be sure to place the 1µF ceramic as close as
IOUT VOUT • ( VIN – VOUT ) IOUT
I cIN(RMS) = < possible to the VIN and GND pins on the IC for optimal
VIN 2 noise immunity.
and is largest when VIN = 2VOUT (50% duty cycle). As When the LT3501’s input supplies are operated at different
the second, lower power channel draws input current, input voltages, an input capacitor sized for that channel
the input capacitor’s RMS current actually decreases as should be placed as close as possible to the respective
the out-of-phase current cancels the current drawn by the VIN pins.
higher power channel. Considering that the maximum load A final caution regarding the use of ceramic capacitors
current from a single channel is ~3A, RMS ripple current at the input. A ceramic input capacitor can combine with
will always be less than 1.5A. stray inductance to form a resonant tank circuit. If power
The frequency, VIN to VOUT ratio, and maximum load cur- is applied quickly (for example by plugging the circuit
rent requirement of the LT3501 along with the input supply into a live power source) this tank can ring, doubling the
source impedance, determine the energy storage require- input voltage and damaging the LT3501. The solution is to
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 LT3501
Applications Information
either clamp the input voltage or dampen the tank circuit The RMS content of this ripple is very low, and the RMS
by adding a lossy capacitor in parallel with the ceramic current rating of the output capacitor is usually not of
capacitor. For details, see Application Note 88. concern.

Output Capacitor Selection Another constraint on the output capacitor is that it must
have greater energy storage than the inductor; if the stored
Typically step-down regulators are easily compensated energy in the inductor is transferred to the output, you
with an output crossover frequency that is one-tenth of would like the resulting voltage step to be small compared
the switching frequency. This means that the time that the to the regulation voltage. For a 5% overshoot, this require-
output capacitor must supply the output load during a tran- ment becomes
sient step is ~2 or 3 switching periods. With an allowable 2
5% drop in output voltage during the step, a good starting  I 
cOUT > 10 L  LIM 
value for the output capacitor can be expressed by:  VOUT 
Max Load Step Finally, there must be enough capacitance for good transient
cVOUT =
Frequency • 0.05 • VOUT performance. The last equation gives a good starting point.
Alternatively, you can start with one of the designs in this
Example: data sheet and experiment to get the desired performance.
VOUT = 3.3V, Frequency = 1MHz, Max Load Step = 3A This topic is covered more thoroughly in the section on
loop compensation.
2
cVOUT = = 12µF The high performance (low ESR), small size and robustness
1e6 • 0.05 • 3.3V
of ceramic capacitors make them the preferred type for
The calculated value is only a suggested starting value. LT3501 applications. However, all ceramic capacitors are
Increase the value if transient response needs improvement not the same. As mentioned above, many of the high value
or reduce the capacitance if size is a priority. capacitors use poor dielectrics with high temperature and
voltage coefficients. In particular, Y5V and Z5U types lose
The output capacitor filters the inductor current to generate
a large fraction of their capacitance with applied voltage
an output with low voltage ripple. It also stores energy in
and temperature extremes. Because the loop stability and
order to satisfy transient loads and to stabilize the LT3501’s
transient response depend on the value of COUT, you may
control loop. The switching frequency of the LT3501 deter-
not be able to tolerate this loss. Use X7R and X5R types.
mines the value of output capacitance required. Also, the
You can also use electrolytic capacitors. The ESRs of most
current mode control loop doesn’t require the presence
aluminum electrolytics are too large to deliver low output
of output capacitor series resistance (ESR). For these
ripple. Tantalum and newer, lower ESR organic electrolytic
reasons, you are free to use ceramic capacitors to achieve
capacitors intended for power supply use, are suitable
very low output ripple and small circuit size.
and the manufacturers will specify the ESR. The choice of
Estimate output ripple with the following equations: capacitor value will be based on the ESR required for low
VRIPPLE = ΔIL/(8f COUT) for ceramic capacitors, ripple. Because the volume of the capacitor determines
its ESR, both the size and the value will be larger than a
and ceramic capacitor that would give you similar ripple per-
VRIPPLE = ΔIL ESR for electrolytic capacitors (tantalum formance. One benefit is that the larger capacitance may
and aluminum) give better transient response for large changes in load
current. Table 2 lists several capacitor vendors.
where ΔIL is the peak-to-peak ripple current in the
inductor.

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 LT3501
Applications Information
Table 2 where IOUT(MAX) is the maximum load current, and
VENDOR TYPE SERIES VBST(MIN) is the minimum boost voltage to fully saturate
Taiyo Yuden Ceramic X5R, X7R the switch.
AVX Ceramic X5R, X7R Figure 5 shows four ways to arrange the boost circuit. The
Tantalum
BST pin must be more than 1.4V above the SW pin for
Kemet Tantalum T491, T494, T495
TA Organic T520
full efficiency. Generally, for outputs of 3.3V and higher
AL Organic A700 the standard circuit (Figure 5a) is the best. For outputs
Sanyo TA/AL Organic POSCAP between 2.8V and 3.3V, replace the D2 with a small Schottky
Panasonic AL Organic SP CAP diode such as the PMEG4005. For lower output voltages
TDK Ceramic X5R, X7R the boost diode can be tied to the input (Figure 5b). The
circuit in Figure 5a is more efficient because the BST
Catch Diode pin current comes from a lower voltage source. Figure
5c shows the boost voltage source from available DC
The diode D1 conducts current only during switch off-time. sources that are greater than 3V. The highest efficiency is
Use a Schottky diode to limit forward-voltage drop to attained by choosing the lowest boost voltage above 3V.
increase efficiency. The Schottky diode must have a peak For example, if you are generating 3.3V and 1.8V and the
reverse voltage that is equal to regulator input voltage and 3.3V is on whenever the 1.8V is on, the 1.8V boost diode
sized for average forward current in normal operation. can be connected to the 3.3V output. In any case, you
Average forward current can be calculated from: must also be sure that the maximum voltage at the BST
IOUT pin is less than the maximum specified in the Absolute
ID(AVG) = • ( VIN – VOUT ) Maximum Ratings section.
VIN
The boost circuit can also run directly from a DC voltage
The only reason to consider a larger diode is the worst- that is higher than the input voltage by more than 3V, as
case condition of a high input voltage and shorted output. in Figure 5d. The diode is used to prevent damage to the
With a shorted condition, diode current will increase to a LT3501 in case VX is held low while VIN is present. The
typical value of 4A, determined by the peak switch current circuit saves several components (both BST pins can be
limit of the LT3501. This is safe for short periods of time, tied to D2). However, efficiency may be lower and dissipa-
but it would be prudent to check with the diode manu- tion in the LT3501 may be higher. Also, if VX is absent, the
facturer if continuous operation under these conditions LT3501 will still attempt to regulate the output, but will do
can be tolerated. so with very low efficiency and high dissipation because
the switch will not be able to saturate, dropping 1.5V to
BST Pin Considerations
2V in conduction.
The capacitor and diode tied to the BST pin generate
The minimum input voltage of an LT3501 application is
a voltage that is higher than the input voltage. In most
limited by the minimum operating voltage (<3V) and by
cases a 0.47µF capacitor and fast switching diode (such
the maximum duty cycle as outlined above. For proper
as the CMDSH-3 or FMMD914) will work well. Almost
start-up, the minimum input voltage is also limited by
any type of film or ceramic capacitor is suitable, but the
the boost circuit. If the input voltage is ramped slowly, or
ESR should be <1Ω to ensure it can be fully recharged
the LT3501 is turned on with its SS pin when the output
during the off-time of the switch. The capacitor value can
is already in regulation, then the boost capacitor may not
be approximated by:
be fully charged. Because the boost capacitor is charged
IOUT(MAX) • Dc with the energy stored in the inductor, the circuit will rely
cBST =
(
B • VOUT – VBST(MIN) • f ) on some minimum load current to get the boost circuit
running properly. This minimum load will depend on
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 LT3501
Applications Information
D2

C3 D2 C3
BST BST
VIN VIN SW VIN VIN SW
LT3501 LT3501

IND IND
VOUT VOUT VOUT VOUT < 3V
VBST – VSW = VOUT GND VBST – VSW = VIN GND
VBST(MAX) = VIN + VOUT VBST(MAX) = 2 • VIN

(5a) (5b)

D2 D2
VX = LOWEST VIN VX > VIN + 3V
OR VOUT > 3V
C3
BST BST
VIN VIN SW VIN VIN SW
LT3501 LT3501

IND IND
VOUT VOUT < 3V VOUT VOUT < 3V
VBST – VSW = VX GND VBST – VSW = VX GND
VBST(MAX) = VIN + VX VBST(MAX) = VX 3501 F05

VX(MIN) = 3V VX(MIN) = VIN + 3V

(5c) (5d)

Figure 5. BST Pin Considerations

input and output voltages, and on the arrangement of the part of the loop compensation but is used to filter noise
boost circuit. The Typical Performance Characteristics at the switching frequency.
section shows plots of the minimum load current to start Loop compensation determines the stability and transient
and to run as a function of input voltage for 3.3V and 5V performance. Designing the compensation network is a bit
outputs. In many cases the discharged output capacitor complicated and the best values depend on the application
will present a load to the switcher which will allow it to and in particular the type of output capacitor. A practical
start. The plots show the worst-case situation where VIN is approach is to start with one of the circuits in this data
ramping very slowly. Use a Schottky diode for the lowest sheet that is similar to your application and tune the com-
start-up voltage. pensation network to optimize the performance. Stability
should then be checked across all operating conditions,
Frequency Compensation including load current, input voltage and temperature.
The LT3501 uses current mode control to regulate the The LT1375 data sheet contains a more thorough discus-
output. This simplifies loop compensation. In particular, the sion of loop compensation and describes how to test the
LT3501 does not require the ESR of the output capacitor stability using a transient load.
for stability so you are free to use ceramic capacitors to
achieve low output ripple and small circuit size. Figure 6 shows an equivalent circuit for the LT3501 control
loop. The error amp is a transconductance amplifier with
Frequency compensation is provided by the components finite output impedance. The power section, consisting of
tied to the VC pin. Generally a capacitor and a resistor in the modulator, power switch and inductor, is modeled as
series to ground determine loop gain. In addition, there a transconductance amplifier generating an output cur-
is a lower value capacitor in parallel. This capacitor is not rent proportional to the voltage at the VC pin. Note that

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 LT3501
Applications Information
LT3501

CURRENT MODE SW
POWER STAGE OUTPUT
gm = 3mho
R1 CPL ESR
gm = 275µmho
– FB
VC
+ C1 C1

RC 3.6M ERROR + TANTALUM

CERAMIC
CF AMP 0.8V R2 OR
POLYMER
CC

3501 F06

Figure 6. Model for Loop Response

the output capacitor integrates this current, and that the VOUT1 VCC
capacitor on the VC pin (CC) integrates the error ampli- LT3501 SYNCHRONIZATION
fier output current, resulting in two poles in the loop. In CIRCUITRY

most cases a zero is required and comes from either the PG1 RT/SYNC CLK

output capacitor ESR or from a resistor in series with CC. 3501 F07

This simple model works well as long as the value of the

inductor is not too high and the loop crossover frequency
is much lower than the switching frequency. A phase lead Figure 7. Synchronous Signal Powered from Regulator’s Output
capacitor (CPL) across the feedback divider may improve
the transient response. time the LT3501 reverts to the free-running frequency
based on the current through RT/SYNC. If the RT/SYNC
Synchronization resistor is held above 1.6V at any time, switching will be
disabled.
The RT/SYNC pin can be used to synchronize the regulators
to an external clock source. Driving the RT/SYNC resistor If the synchronization signal is not present during regula-
with a clock source triggers the synchronization detection tor start-up (for example, the synchronization circuitry is
circuitry. Once synchronization is detected, the rising edge powered from the regulator output) the RT/SYNC pin must
of SW1 will be synchronized to the rising edge of the see an equivalent resistance to ground between 15.4k and
RT/SYNC pin signal. An AGC loop will adjust the internal 133k until the synchronization circuitry is active for proper
oscillators to maintain a 180 degree phase between SW1 start-up operation.
and SW2, and also adjust slope compensation to avoid If the synchronization signal powers up in an undetermined
subharmonic oscillation. state (VOL, VOH, Hi-Z), connect the synchronization clock
The synchronizing clock signal input to the LT3501 must to the LT3501 as shown in Figure 7. The circuit as shown
have a frequency between 250kHz and 1.5MHz, a duty will isolate the synchronization signal when the output
cycle between 20% and 80%, a low state below 0.5V and voltage is below 90% of the regulated output. The LT3501
a high state above 1.6V. Synchronization signals outside will start-up with a switching frequency determined by the
of these parameters will cause erratic switching behavior. resistor from the RT/SYNC pin to ground.
The RT/SYNC resistor should be set such that the free If the synchronization signal powers up in a low impedance
running frequency ((VRT/SYNC – VSYNCLO)/RRT/SYNC) is state (VOL), connect a resistor between the RT/SYNC pin
approximately equal to the synchronization frequency. If and the synchronizing clock. The equivalent resistance
the synchronization signal is halted, the synchronization seen from the RT/SYNC pin to ground will set the start-up
detection circuitry will timeout in typically 10µs at which frequency.
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 LT3501
Applications Information
If the synchronization signal powers up in a high impedance defaults the open-pin condition to be operating (see Typical
state (Hi-Z), connect a resistor from the RT/SYNC pin to Performance Characteristics). Current hysteresis is added
ground. The equivalent resistance seen from the RT/SYNC above the SHDN threshold. This can be used to set voltage
pin to ground will set the start-up frequency. hysteresis of the UVLO using the following:
If the synchronization signal changes between high and VH – VL
low impedance states during power-up (VOL, Hi-Z), connect R1=
7µA
the synchronization circuitry to the LT3501 as shown in
the Typical Applications section. This will allow the LT3501 1.28
R2 =
to start-up with a switching frequency determined by the VH – 1.28
equivalent resistance from the RT/SYNC pin to ground. + 3µA
R1
Shutdown and Undervoltage Lockout VH = Turn-on threshold
Figure 8 shows how to add undervoltage lockout (UVLO) VL = Turn-off threshold
to the LT3501. Typically, UVLO is used in situations where
the input supply is current limited, or has a relatively high Example: switching should not start until the input is above
source resistance. A switching regulator draws constant 4.75V and is to stop if the input falls below 3.75V.
power from the source, so source current increases as VH = 4.75V
source voltage drops. This looks like a negative resistance
load to the source and can cause the source to current limit VL = 3.75V
or latch low under low source voltage conditions. UVLO 4.75 – 3.75
prevents the regulator from operating at source voltages R1= ≅ 143k
7µA
where these problems might occur.
An internal comparator will force the part into shutdown 1.28
R2 = ≅ 47k
below the minimum VIN1 of 2.8V. This feature can be 4.75 – 1.28
+ 3µA
used to prevent excessive discharge of battery-operated 143k
systems.
Keep the connections from the resistors to the SHDN
Since VIN2 supplies the output stage of channel 2 and is pin short and make sure that the interplane or surface
not monitored, care must be taken to insure that VIN2 is capacitance to switching nodes is minimized. If high re-
present before channel 2 is allowed to switch. sistor values are used, the SHDN pin should be bypassed
If an adjustable UVLO threshold is required, the SHDN with a 1nF capacitor to prevent coupling problems from
pin can be used. The threshold voltage of the SHDN the switch node.
pin comparator is 1.28V. A 3µA internal current source
Soft-Start
LT3501 The output of the LT3501 regulates to the lowest voltage
VIN1 > 2.8V
VIN1 present at either the SS pin or an internal 0.8V reference.
– A capacitor from the SS pin to ground is charged by an
+
VIN1 OR VIN2
3µA 7µA 1.28V + internal 3.25µA current source resulting in a linear output
R1
SHDN INTERNAL ramp from 0V to the regulated output whose duration is
REGULATOR
given by:
3501 F08
C1 R2
cSS • 0.8V
tRAMP =
3.25µA
Figure 8. Undervoltage Lockout
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 LT3501
Applications Information
At power-up, a reset signal sets the soft-start latch and threshold is exceeded. The PG pin is active (sink capability
discharges both SS pins to approximately 0V to ensure is reduced in shutdown and undervoltage lockout mode)
proper start-up. When both SS pins are fully discharged as long as the VIN1 pin voltage exceeds 1V.
the latch is reset and the internal 3.25µA current source
starts to charge the SS pin. Output Tracking/Sequencing
When the SS pin voltage is below 50mV, the VC pin is pulled Complex output tracking and sequencing between chan-
low which disables switching. This allows the SS pin to be nels can be implemented using the LT3501’s SS and PG
used as an individual shutdown for each channel. pins. Figure 9 shows several configurations for output
tracking/sequencing for a 3.3V and 1.8V application.
As the SS pin voltage rises above 50mV, the VC pin is re-
leased and the output is regulated to the SS voltage. When Independent soft-start for each channel is shown in
the SS pin voltage exceeds the internal 0.8V reference, the Figure 9a. The output ramp time for each channel is set
output is regulated to the reference. The SS pin voltage by the soft-start capacitor as described in the soft-start
will continue to rise until it is clamped at 2V. section.
In the event of a VIN1 undervoltage lockout, the SHDN Ratiometric tracking is achieved in Figure 9b by connecting
pin driven below 1.28V, or the internal die temperature both SS pins together. In this configuration, the SS pin
exceeding its maximum rating during normal operation, the source current is doubled (6.5µA) which must be taken
soft-start latch is set, triggering a start-up sequence. into account when calculating the output rise time.

In addition, if the load exceeds the maximum output switch By connecting a feedback network from VOUT1 to the SS2
current, the output will start to drop causing the VC pin pin with the same ratio that sets VOUT2 voltage, absolute
clamp to be activated. As long as the VC pin is clamped, tracking shown in Figure 9c is implemented. The minimum
the SS pin will be discharged. As a result, the output will value of the top feedback resistor (R1) should be set such
be regulated to the highest voltage that the maximum that the SS pin can be driven all the way to ground with
output current can support. For example, if a 6V output 700µA of sink current when VOUT1 is at its regulated voltage.
In addition, a small VOUT2 voltage offset will be present
is loaded by 1Ω the SS pin will drop to 0.53V, regulating
due to the SS2 3.25µA source current. This offset can be
the output at 4V (4A • 1Ω ). Once the overload condition
corrected for by slightly reducing the value of R2.
is removed, the output will soft-start from the temporary
voltage level to the normal regulation point. Figure 9d illustrates output sequencing. When VOUT1 is
within 10% of its regulated voltage, PG1 releases the SS2
Since the SS pin is clamped at 2V and has to discharge
soft-start pin allowing VOUT2 to soft-start. In this case PG1
to 0.8V before taking control of regulation, momentary
will be pulled up to 2V by the SS pin. If a greater voltage
overload conditions will be tolerated without a soft- is needed for PG1 logic, a pull-up resistor to VOUT1 can
start recovery. The typical time before the SS pin takes be used. This will decrease the soft-start ramp time and
control is: increase tolerance to momentary shorts.
c • 1.2V
tSS(cONTROL) = SS If precise output ramp up and down is required, drive the
700µA SS pins as shown in Figure 9e. The minimum value of
resistor (R3) should be set such that the SS pin can be
Power Good Indicators driven all the way to ground with 700µA of sink current
The PG pin is the open-collector output of an internal during power-up and fault conditions.
comparator. The comparator compares the FB pin voltage
Multiple Input Voltages
to 90% of the reference voltage with 30mV of hysteresis.
The PG pin has a sink capability of 800µA when the FB pin For applications requiring large inductors due to high VIN
is below the threshold and can withstand 25V when the to VOUT ratios, a 2-stage step-down approach may reduce
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 LT3501
Applications Information
Independent Start-Up Ratiometric Start-Up Absolute Start-Up
VOUT1 VOUT1 VOUT1
0.5V/DIV 0.5V/DIV 0.5V/DIV

PG1 PG1 PG1

VOUT2 VOUT2 VOUT2
0.5V/DIV 0.5V/DIV 0.5V/DIV

PG2 PG2 PG2

5ms/DIV 10ms/DIV 10ms/DIV

SS1 VOUT1 3.3V SS1 VOUT1 3.3V SS1 VOUT1 3.3V

0.1µF LT3501 0.1µF LT3501 0.22µF LT3501
PG1 PG1 PG1

SS2 VOUT2 1.8V SS2 VOUT2 1.8V SS2 VOUT2 1.8V

0.22µF

PG2 PG2 PG2

R1
13.7k

R2
8.08k
(9a) (9b) (9c)

Output Sequencing Controlled Power Up and Down

VOUT1 VOUT1
0.5V/DIV 0.5V/DIV

PG1
VOUT2 VOUT2
0.5V/DIV 0.5V/DIV

PG1
SS1/2
PG2

10ms/DIV 10ms/DIV

R3
25k
SS1 VOUT1 3.3V SS1 VOUT1 3.3V
0.1µF LT3501 EXTERNAL +
SOURCE – LT3501
PG1 PG1

SS2 VOUT2 1.8V SS2 VOUT2 1.8V

0.1µF

PG2 PG2

(9d) (9e)

Figure 9

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 LT3501
Applications Information
VIN
6V TO 24V
4.7µF
PMEG4005

VIN1 VIN2
26.7k
SHDN FSET
BST1 BST2
3.3µH 0.47µF 0.47µF 1µH
SW1 SW2
PMEG4005 B360A B360A
LT3501

IND1 IND2
VOUT1 VOUT2
5V VOUT1 VOUT2
1.2V
47µF 42.3k 100k 4k 47µF
×2
PG1 PG2
FB1 FB2
VC1 VC2 8.06k
8.06k
SS/TRACK1 SS/TRACK2
470pF GND 470pF

10pF 40.2k 0.1µF 0.1µF 32.4k 10pF

3501 F10

Figure 10. 5V and 1.2V 2-Stage Step-Down Converter with Output Sequencing

inductor size by allowing an increase in frequency. A dual Single step-down:

step-down application (Figure 10) steps down the input 1.2 + 0.6
voltage (VIN1) to the highest output voltage then uses that
Frequency (Hz) ≤ 24 – 0.4 + 0.6 = 392kHz
voltage to power the second output (VIN2). VOUT1 must be 190ns
able to provide enough current for its output plus VOUT2
maximum load. Note that the VOUT1 must be above VIN2 L1=
(24 – 5) • 5 ≥ 10µH
minimum input voltage (2V) when the second channel 24 • 392kHz
starts to switch. Delaying channel 2 can be accomplished
by either independent soft-start capacitors or sequencing L2 =
(24 – 1.2) • 1.2 ≥ 2.7µH
with the PG1 output. 24 • 392kHz
For example, assume a maximum input of 24V: 2-Stage Step-Down:
VIN = 24V, VOUT1 = 5V at 1.5A and VOUT2 = 1.2V at 1.5A 5 + 0.6
VOUT + VD Frequency ≤ 24 – 0.4 + 0.6 = 1.2MHz
190ns
V – VSW + VD
Frequency (Hz) ≤ IN
tMIN(ON) Max Frequency = 1.2MHz

( VIN – VOUT ) • VOUT L1=

(24 – 5) • 5 ≥ 3.3µH
L≥
VIN • f 24 • 1.2MHz

L2 =
(5 – 1.2) • 1.2 ≥ 0.76µH
5 • 1.2MHz

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 LT3501
Applications Information
VIN LT3501 SW VIN LT3501 SW VIN LT3501 SW

GND GND GND

(11a) (11b) (11c)

Figure 11. Subtracting the Current When the Switch Is On (11a) from the Current When the Switch is Off (11b) Reveals the Path of the
High Frequency Switching Current (11c). Keep This Loop Small. The Voltage on the SW and BST Traces Will Also Be Switched; Keep
These Traces as Short as Possible. Finally, Make Sure the Circuit Is Shielded with a Local Ground Plane

PCB Layout one location, ideally at the ground terminal of the output
For proper operation and minimum EMI, care must be taken capacitor C2. Additionally, the SW and BST traces should
during printed circuit board (PCB) layout. Figure 11 shows be kept as short as possible. The topside metal from the
the high di/dt paths in the buck regulator circuit. DC964A demonstration board in Figure 12 illustrates proper
component placement and trace routing.
Note that large switched currents flow in the power switch,
the catch diode and the input capacitor. The loop formed Thermal Considerations
by these components should be as small as possible.
These components, along with the inductor and output The PCB must also provide heat sinking to keep the LT3501
capacitor, should be placed on the same side of the circuit cool. The exposed metal on the bottom of the package
board and their connections should be made on that layer. must be soldered to a ground plane. This ground should
Place a local, unbroken ground plane below these com- be tied to other copper layers below with thermal vias;
ponents, and tie this ground plane to system ground at these layers will spread the heat dissipated by the LT3501.

Figure 12. Topside PCB Layout DC964A

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24
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 LT3501
Applications Information
Place additional vias near the catch diodes. Adding more There is one special consideration regarding the 2-phase
copper to the top and bottom layers and tying this copper circuit. When the difference between the input voltage and
to the internal planes with vias can further reduce ther- output voltage is less than 2.5V, then the boost circuits may
mal resistance. With these steps, the thermal resistance prevent the two channels from properly sharing current.
from die (or junction) to ambient can be reduced to qJA If, for example, channel 1 gets started first, it can supply
= 45°C/W. the load current, while channel 2 never switches enough
The power dissipation in the other power components current to get its boost capacitor charged.
such as catch diodes, boost diodes and inductors, cause In this case, channel 1 will supply the load until it reaches
additional copper heating and can further increase what current limit, the output voltage drops, and channel 2 gets
the IC sees as ambient temperature. See the LT1767 data started. Two solutions to this problem are shown in the
sheet’s Thermal Considerations section. Typical Applications section.

Single, Low Ripple 6A Output The single 3.3V/6A output converter generates a boost sup-
ply from either SW that will service both switch pins.
The LT3501 can generate a single, low ripple 6A output
if the outputs of the two switching regulators are tied The synchronized 3.3V/12A output converter utilizes un-
together and share a single output capacitor. By tying the dervoltage lockout to prevent the start-up condition.
two FB pins together and the two VC pins together, the
Other Linear Technology Publications
two channels will share the load current. There are several
advantages to this 2-phase buck regulator. Ripple currents Application notes AN19, AN35 and AN44 contain more
at the input and output are reduced, reducing voltage ripple detailed descriptions and design information for buck
and allowing the use of smaller, less expensive capacitors. regulators and other switching regulators. The LT1376
Although two inductors are required, each will be smaller data sheet has a more extensive discussion of output
than the inductor required for a single-phase regulator. This ripple, loop compensation and stability testing. Design
may be important when there are tight height restrictions Note DN100 shows how to generate a dual (+ and –)
on the circuit. output supply using a buck regulator.

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 LT3501
Typical Applications
5V and 2.5V with Absolute Tracking
VIN
12V
4.7µF
VIN1 VIN2 26.7k
SHDN RT/SYNC
BST1 BST2
3.3µH 0.47µF 0.47µF 2.2µH
SW1 SW2
PMEG4005 B360A PMEG4005
B360A LT3501

IND1 IND2
VOUT1 VOUT2
VOUT1 VOUT2
5V 2.5V
47µF 42.3k 100k 100k 16.9k 47µF

PG1 PG2
FB1 FB2
VC1 VC2
470pF SS/TRACK1 SS/TRACK2 470pF
GND
8.06k 10pF 40.2k 40.2k 10pF 8.06k
0.1µF
16.9k
3501 TA02

7.68k

1.25MHz Single 3.3V/6A Low Ripple Output

VIN 6V TO 25V
4.7µF
VIN1 VIN2
20.5k
SHDN RT/SYNC

BST1 BST2
1.5µH 0.47µF 0.47µF 1.5µH
SW1 SW2

PMEG4005 B360A B360A PMEG4005

LT3501

VOUT1 IND1 IND2

3.3V VOUT1 VOUT2
6A 47µF 24.9k 100k
×2
PG1 PG2
FB1 FB2

8.06k VC1 VC2

SS/TRACK1 SS/TRACK2
1000pF
GND
22pF
17.8k
0.1µF

3501 TA03

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26
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 LT3501
Typical Applications
1.25MHz Single 3.3V/6A Low Ripple Output
VIN 4.5V TO 6V
4.7µF
1µF*
VIN1 VIN2
20.5k
SHDN RT/SYNC
PMEG4005* PMEG4005*
BST1 BST2
1.5µH 0.47µF 0.47µF 1.5µH
SW1 SW2
PMEG4005 B360A B360A PMEG4005
LT3501

VOUT1 IND1 IND2

3.3V VOUT1 VOUT2
6A 47µF 24.9k 100k
×2
PG1 PG2
FB1 FB2
8.06k VC1 VC2
SS/TRACK1 SS/TRACK2
1000pF
GND
22pF
17.8k
0.1µF

3501 TA03

*ADDITIONAL COMPONENTS ADDED TO SHOW THE BOOST VOLTAGE WHEN VIN <6V.
THIS IS REQUIRED TO ENSURE LOAD SHARING BETWEEN THE TWO CHANNELS.

Dual LT3501 Synchronized 3.3V/12A Output, 3MHz Effective Switch Frequency

VIN
5.5V TO 24V
10µF 143k

36.5k VIN1 VIN2

SHDN RT/SYNC
BST1 BST2
3.3µH 0.47µF 0.47µF 3.3µH
SW1 SW2

PMEG4005 B360A B360A PMEG4005

LT3501

IND1 IND2
VOUT1
VOUT1 VOUT2
3.3V 47µF 49.9k
24.9k
×4 PG1 PG2
FB1 FB2 49.9k
8.06k VC1 VC2
SS/TRACK1 SS/TRACK2 V+ OUT1
3300pF GND 133k LTC6908-1
SET
47pF 15.3k 0.1µF MOD
GND OUT2
49.9k

PMEG4005 PMEG4005
VIN1 VIN2
SHDN RT/SYNC
BST1 BST2
3.3µH 0.47µF 0.47µF 3.3µH
SW1 SW2
B360A B360A
LT3501

IND1 IND2
VOUT1 VOUT2
49.9k
PG1 PG2
FB1 FB2
VC1 VC2
SS/TRACK1 SS/TRACK2
GND

3501 TA04

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 LT3501
Package Description
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

FE Package
20-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663 Rev I)
Exposed Pad Variation CB

6.40 – 6.60*
3.86 (.252 – .260)
(.152) 3.86
(.152)
20 1918 17 16 15 14 13 12 11

6.60 ±0.10
2.74
4.50 ±0.10 (.108)
6.40
SEE NOTE 4 2.74 (.252)
(.108) BSC
0.45 ±0.05

1.05 ±0.10

0.65 BSC
RECOMMENDED SOLDER PAD LAYOUT 1 2 3 4 5 6 7 8 9 10
1.20
4.30 – 4.50* (.047)
(.169 – .177) 0.25 MAX
REF
0° – 8°

0.65
0.09 – 0.20 0.50 – 0.75 (.0256) 0.05 – 0.15
(.0035 – .0079) (.020 – .030) BSC (.002 – .006)
0.195 – 0.30
FE20 (CB) TSSOP REV I 0211
(.0077 – .0118)
TYP
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE
MILLIMETERS FOR EXPOSED PAD ATTACHMENT
2. DIMENSIONS ARE IN
(INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
3. DRAWING NOT TO SCALE SHALL NOT EXCEED 0.150mm (.006") PER SIDE

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28
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 LT3501
Revision History (Revision history begins at Rev D)

REV DATE DESCRIPTION PAGE NUMBER

D 6/12 Part Marking clarification 2
Solder pad clarification 28

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29
Information furnished by Linear Technology corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
Downloaded from Arrow.com.
 LT3501
Related Parts
PART NUMBER DESCRIPTION COMMENTS
LT1766 60V, 1.2A (IOUT), 200kHz High Efficiency Step-Down DC/DC VIN: 5.5V to 60V, VOUT(MIN) = 1.20V, IQ = 2.5mA, ISD = 25µA,
Converter 16-Lead TSSOPE Package
LT1933 500mA (IOUT), 500kHz Step-Down Switching Regulator in VIN: 3.6V to 36V, VOUT(MIN) = 1.2V, IQ = 1.6mA, ISD < 1µA,
SOT-23 ThinSOT™ Package
LT1936 36V, 1.4A (IOUT), 500kHz High Efficiency Step-Down DC/DC VIN: 3.6V to 36V, VOUT(MIN) = 1.2V, IQ = 1.9mA, ISD < 1µA,
Converter 8-Lead MS8E Package
LT1940 Dual 25V, 1.4A (IOUT), 1.1MHz High Efficiency Step-Down VIN: 3.6V to 25V, VOUT(MIN) = 1.20V, IQ = 3.8mA, ISD < 30µA,
DC/DC Converter 16-Lead TSSOPE Package
LT1976/LT1977 60V, 1.2A (IOUT), 200kHz/500kHz High Efficiency Step-Down VIN: 3.3V to 60V, VOUT(MIN) = 1.20V, IQ = 100µA, ISD < 1µA,
DC/DC Converters with Burst Mode® Operation 16-Lead TSSOPE Package
LTC 3407/LTC3407-2
®
Dual 600mA/800mA, 1.5MHz/2.25MHz Synchronous VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 40µA, ISD < 1µA,
Step-Down DC/DC Converters 3mm × 3mm DFN and 10-Lead MSE Packages
LT3434/LT3435 60V, 2.4A (IOUT), 200kHz/500kHz High Efficiency Step-Down VIN: 3.3V to 60V, VOUT(MIN) = 1.20V, IQ = 100µA, ISD < 1µA,
DC/DC Converters with Burst Mode Operation 16-Lead TSSOPE Package
LT3437 60V, 400mA (IOUT), Micropower Step-Down DC/DC Converter VIN: 3.3V to 60V, VOUT(MIN) = 1.25V, IQ = 100µA, ISD < 1µA,
with Burst Mode Operation DFN Package
LT3493 36V, 1.4A (IOUT), 750kHz High Efficiency Step-Down DC/DC VIN: 3.6V to 36V, VOUT(MIN) = 0.8V, IQ = 1.9mA, ISD < 1µA,
Converter DFN Package
LT3505 36V, 1.2A (IOUT), 3MHz High Efficiency Step-Down DC/DC VIN: 3.6V to 36V, VOUT(MIN) = 0.78V, IQ = 2mA, ISD < 2µA,
Converter 3mm × 3mm DFN and 8-Lead MSE Packages
LT3506/LT3506A Dual 25V, 1.6A (IOUT), 575kHz/1.1MHz High Efficiency VIN: 3.6V to 25V, VOUT(MIN) = 0.8V, IQ = 3.8mA, ISD < 30µA,
Step-Down DC/DC Converters 4mm × 5mm DFN Package
LT3510 Dual 25V, 3A (IOUT), 1.5MHz High Efficiency Step-Down VIN: 3.3V to 25V, VOUT(MIN) = 0.8V, IQ = 3.5mA, ISD < 1µA,
DC/DC Converter 20-Lead TSSOPE Package
LTC3548 Dual 400mA/800mA, 2.25MHz Synchronous Step-Down VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 40µA, ISD < 1µA,
DC/DC Converters 3mm × 3mm DFN and 10-Lead MSE Packages

3501fd

30 Linear Technology Corporation

LT 0612 REV D • PRINTED IN USA

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com  LINEAR TECHNOLOGY CORPORATION 2006
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