Boolean Algebra and Logic Simplification - General Questions

1. Convert the following SOP expression to an equivalent POS expression.

A.
B.
C.
D.
Answer: Option B

2. Determine the values of A, B, C, and D that make the sum term equal to zero.
A.A = 1, B = 0, C = 0, D = 0
B.A = 1, B = 0, C = 1, D = 0
C.A = 0, B = 1, C = 0, D = 0
D.A = 1, B = 0, C = 1, D = 1
Answer: Option B

3. Which of the following expressions is in the sum-of-products (SOP) form?

A.(A + B)(C + D)
B.(A)B(CD)
C.AB(CD)
D.AB + CD
Answer: Option D

4. Derive the Boolean expression for the logic circuit shown below:

A.
B.

C.
D.
Answer: Option A

5. From the truth table below, determine the standard SOP expression.
 A.
B.
C.
D.
Answer: Option D
.
6. One of De Morgan's theorems states that . Simply stated, this means that logically
there is no difference between:
A.a NOR and an AND gate with inverted inputs
B.a NAND and an OR gate with inverted inputs
C.an AND and a NOR gate with inverted inputs
D.a NOR and a NAND gate with inverted inputs
Answer: Option A

7. The commutative law of Boolean addition states that A + B = A × B.

A.True
B.False
Answer: Option B

8. Applying DeMorgan's theorem to the expression , we get ________.

A.
B.
C.
D.
Answer: Option A

9. The systematic reduction of logic circuits is accomplished by:

A.using Boolean algebra
B.symbolic reduction
C.TTL logic
D.using a truth table
Answer: Option A

10. Which output expression might indicate a product-of-sums circuit construction?

A.
B.
C.
 D.
Answer: Option D
n AND gate with schematic "bubbles" on its inputs performs the same function as a(n)________
gate.
A
NOT
.
B
OR
.
C
NOR
.
D
NAND
.
Answer: Option C

12. For the SOP expression , how many 1s are in the truth table's output
column?
A.1
B.2
C.3
D.5
Answer: Option C

13. A truth table for the SOP expression has how many input combinations?
A.1
B.2
C.4
D.8
Answer: Option D

14. How many gates would be required to implement the following Boolean expression before
simplification? XY + X(X + Z) + Y(X + Z)
A.1
B.2
C.4
D.5
Answer: Option D

15. Determine the values of A, B, C, and D that make the product term equal to 1.
A.A = 0, B = 1, C = 0, D = 1
B.A = 0, B = 0, C = 0, D = 1
C.A = 1, B = 1, C = 1, D = 1
D.A = 0, B = 0, C = 1, D = 0
Answer: Option A
What is the primary motivation for using Boolean algebra to simplify logic expressions?
A
It may make it easier to understand the overall function of the circuit.
.
B
It may reduce the number of gates.
.
C
It may reduce the number of inputs required.
.
D
all of the above
.
Answer: Option D

17. How many gates would be required to implement the following Boolean expression after
simplification? XY + X(X + Z) + Y(X + Z)
A.1
B.2
C.4
D.5
Answer: Option B

18. AC + ABC = AC
A.True
B.False
Answer: Option A

19.
When are the inputs to a NAND gate, according to De Morgan's theorem, the output
expression could be:
A.X = A + B
B.
C.X = (A)(B)
D.
Answer: Option A

20. Which Boolean algebra property allows us to group operands in an expression in any order
without affecting the results of the operation [for example, A + B = B + A]?
A.associative
B.commutative
C.Boolean
D.distributive
Answer: Option B

Applying DeMorgan's theorem to the expression , we get ________

A
.
B
.
C
.
D
.
Answer: Option A

22. When grouping cells within a K-map, the cells must be combined in groups of ________.
A.2s
B.1, 2, 4, 8, etc.
C.4s
D.3s
Answer: Option B

23. Use Boolean algebra to find the most simplified SOP expression
for F = ABD + CD + ACD + ABC + ABCD.
 A.F = ABD + ABC + CD
B.F = CD + AD
C.F = BC + AB
D.F = AC + AD
Answer: Option A
24. Occasionally, a particular logic expression will be of no consequence in the operation of a circuit,
such as a BCD-to-decimal converter. These result in ________terms in the K-map and can be
treated as either ________ or ________, in order to ________ the resulting term.
A.don't care, 1s, 0s, simplify
B.spurious, ANDs, ORs, eliminate
C.duplicate, 1s, 0s, verify
D.spurious, 1s, 0s, simplify
Answer: Option A

25. The NAND or NOR gates are referred to as "universal" gates because either:
A.can be found in almost all digital circuits
B.can be used to build all the other types of gates
C.are used in all countries of the world
D.were the first gates to be integrated
Answer: Option B
Referring to the GAL diagram, which is the correct logic function?

A
.
B
.
C
.
D
.
Answer: Option A
2. The output of an exclusive-NOR gate is 1. Which input combination is correct?
A.A = 1, B = 0
B.A = 0, B = 1
C.A = 0, B = 0
D.none of the above
Answer: Option C

3. The Boolean SOP expression obtained from the truth table below is ________.

A.
B.
C.
D.None of these
Answer: Option C

4. The 8-input XOR circuit shown has an output of Y = 1. Which input combination below (ordered
A – H) is correct?

A.10111100
B.10111000
C.11100111
D.00011101
Answer: Option A
5. Implementing the expression AB + CDE using NAND logic, we get:

(A)
A.

B.(B)
C.(C)
D.(D)
Answer: Option A
Before an SOP implementation, the expression would require a total of how many
gates?
A
1
.
B
2
.
C
4
.
D
5
.
Answer: Option D

7. The following waveform pattern is for a(n) ________.

A.2-input AND gate

B.2-input OR gate
C.Exclusive-OR gate
D.None of the above
Answer: Option B
8.
Implementing the expression with NOR logic, we get:

A.(A)
B.(B)
C.(C)
D.(D)
Answer: Option A

9. A 4-variable AND-OR-Invert circuit produces a 0 at its Y output. Which combination of inputs is

correct?
A.
B.
C.
D.none of the above
Answer: Option C

10. The following waveform pattern is for a(n) ________.

A.2-input AND gate

B.2-input OR gate
C.Exclusive-OR gate
 D.None of the above
Answer: Option C
To implement the expression , it takes one OR gate and ________.
A
three AND gates and three inverters
.
B
three AND gates and four inverters
.
C
three AND gates
.
D
one AND gate
.
Answer: Option A

12. One positive pulse with tw = 75 µs is applied to one of the inputs of an exclusive-OR circuit. A
second positive pulse with tw = 15 µs is applied to the other input beginning 20 µs after the
leading edge of the first pulse. Which statement describes the output in relation to the inputs?
The exclusive-OR output is a 20 s pulse followed by a 40 s pulse, with a separation of 15
A.
s between the pulses.
The exclusive-OR output is a 20 s pulse followed by a 15 s pulse, with a separation of 40
B.
s between the pulses.
C.The exclusive-OR output is a 15 s pulse followed by a 40 s pulse.
*The exclusive-OR output is a 20 s pulse followed by a 15 s pulse, followed by a 40 s
D.
pulse.
Answer: Option D

13. How many AND gates are required to implement the Boolean expression,
?
A.1
B.2
C.3
D.4
Answer: Option C

14. How many NOT gates are required to implement the Boolean expression, ?
A.1
B.2
C.4
D.5
Answer: Option B

15. The inverter can be produced with how many NAND gates?
A.1
B.2
C.3
D.4
Answer: Option A
A 4-variable AND-OR circuit produces a 0 at its Y output. Which combination of inputs is
correct?
A.A = 0, B = 0, C = 1, D = 1
B.A = 1, B = 1, C = 0, D = 0
C.A = 1, B = 1, C = 1, D = 1
D.A = 1, B = 0, C = 1, D = 0
 Answer: Option D

17. A 4-variable AND-OR circuit produces a 1 at its Y output. Which combination of inputs is
correct?
A.A = 0, B = 0, C = 0, D = 0
B.A = 0, B = 1, C = 1, D = 0
C.A = 1, B = 1, C = 0, D = 0
D.A = 1, B = 0, C = 0, D = 0
Answer: Option C

18.
Implementing the expression using NAND logic, we get:

A.(A)
B.(B)
C.(C)
D.(D)
Answer: Option D

19. Implementing the expression using NAND logic, we get:

 A.(A)
B.(B)
C.(C)
D.(D)
Answer: Option B

20. The following waveform pattern is for a(n) ________.

A.2-input AND gate

B.2-input OR gate
C.Exclusive-OR gate
D.None of the above
Answer: Option A
Implementation of the Boolean expression results in ________.
A
three AND gates, one OR gate
.
B
three AND gates, one NOT gate, one OR gate
.
C
three AND gates, one NOT gate, three OR gates
.
D
three AND gates, three OR gates
.
Answer: Option B

22. One possible output expression for an AND-OR-Invert circuit having one AND gate with inputs
A, B, and C and one AND gate with inputs D and E is ________.
A.
B.
C.
D.
Answer: Option C
23. How many 2-input NOR gates does it take to produce a 2-input NAND gate?
A.1
B.2
C.3
D.4
Answer: Option D

24. A logic circuit with an output consists of ________.

A.two AND gates, two OR gates, two inverters
B.three AND gates, two OR gates, one inverter
C.two AND gates, one OR gate, two inverters
D.two AND gates, one OR gate
Answer: Option C
The format used to present the logic output for the various combinations of logic inputs to a gate is
called a(n):
A
truth table.
.
B
input logic function.
.
C
Boolean constant.
.
D
Boolean variable.
.
Answer: Option A

2. What is the basic difference between AHDL and VHDL?

A.ADHL is used in all PLD's.
B.VHDL is used in all PLD's.
C.ADHL is proprietary.
D.VHDL is proprietary.
Answer: Option C

3. A small circle on the output of a logic gate is used to represent the:

A.Comparator operation.
B.OR operation.
C.NOT operation.
D.AND operation.
Answer: Option C

4. For a three-input OR gate, with the input waveforms as shown below, which output waveform is
correct?
 A.a
B.b
C.c
D.d
Answer: Option B

5. Which of the figures given below represents a NOR gate?

A.a
B.b
C.c
D.d
Answer: Option D
Which of the figures (a to d) is the DeMorgan equivalent of Figure (e)?

A
a
.
B
b
.
C
c
.
D
d
.
Answer: Option A

7. Which of the figures in figure (a to d) is equivalent to figure (e)?

 A.a
B.b
C.c
D.d
Answer: Option C

8. In VHDL, the mode of a port does not define:

A.an input.
B.an output.
C.both an input and an output.
D.the TYPE of the bit.
Answer: Option D

9. Which of the following equations would accurately describe a 4-input OR gate when A = 1, B =
1, C = 0, and D = 0?
A.1 + 1 + 0 + 0 = 1
B.1 + 1 + 0 + 0 = 01
C.1 + 1 + 0 + 0 = 0
D.1 + 1 + 0 + 0 = 00
Answer: Option A

10. Which of the examples below expresses the distributive law?

A.(A + B) + C = A + (B + C)
B.A(B + C) = AB + AC
C.A + (B + C) = AB + AC
D.A(BC) = (AB) + C
Answer: Option B
Which of the examples below expresses the associative law of addition:
 A.A + (B + C) = (A + B) + C
B.A + (B + C) = A + (BC)
C.A(BC) = (AB) + C
D.ABC = A + B + C
Answer: Option A

12. How are the statements between BEGIN and END not evaluated in VHDL?
A.Constantly
B.Simultaneously
C.Concurrently
D.Sequentially
Answer: Option D

13. Which logic gate does this truth table describe?

A.AND
B.OR
C.NAND
D.NOR
Answer: Option D

14. For a 3-input NAND gate, with the input waveforms as shown below, which output waveform is
correct?

A.a
B.b
C.c
D.d
Answer: Option C
15. Which of the figures given below represents a NAND gate?

A.a
B.b
C.c
D.d
Answer: Option A
Which timing diagram shown below is correct for an inverter?

A
a
.
B
b
.
C
c
.
D
d
.
Answer: Option B

17. A NOR gate with one HIGH input and one LOW input:
A.will output a HIGH
B.functions as an AND
C.will not function
D.will output a LOW
Answer: Option D

18. A NAND gate has:

A.active-LOW inputs and an active-HIGH output.
B.active-LOW inputs and an active-LOW output.
C.active-HIGH inputs and an active-HIGH output.
D.active-HIGH inputs and an active-LOW output.
Answer: Option D

19. Which of the figures given below represents an OR gate?

 A.a
B.b
C.c
D.d
Answer: Option A

20. Which of the following is a form of DeMorgan's theorem?

A.
B.
C.
D.
Answer: Option C
The logic gate that will have HIGH or "1" at its output when any one of its inputs is HIGH is a(n):
A
NOR gate
.
B
OR gate
.
C
AND gate
.
D
NOT operation
.
Answer: Option B

22. Which of the symbols shown below represents an AND gate?

A.a
B.b
C.c
D.d
Answer: Option D

23. For a three-input AND gate, with the input waveforms as shown below, which output waveform is
correct?
 A.a
B.b
C.c
D.d
Answer: Option C

24. An OR gate with inverted inputs functions as:

A.an AND gate.
B.a NAND gate.
C.a NOR gate.
D.an inverter.
Answer: Option B

25. The special software application that translates from HDL into a grid of 1's and 0's, which can be
loaded into a PLD, is called a:
A.formatter.
B.compiler.
C.programmable wiring.
D.CPU.
Answer: Option B
. The Boolean equation for a NOR function is:
A.
B.
C.
D.
Answer: Option B

27. Which step in this reduction process is using DeMorgan's theorem?

 A.STEP 1
B.STEP 2
C.STEP 3
D.STEP 4
Answer: Option A

28.
Simplify the expression using DeMorgan's theorems.
A.
B.
C.
D.
Answer: Option B

29. For a three-input NOR gate, with the input waveforms as shown below, which output waveform
is correct?

A.a
B.b
C.c
D.d
Answer: Option A
1. Determine the output frequency for a frequency division circuit that contains 12 flip-flops with an
 input clock frequency of 20.48 MHz.
A.10.24 kHz
B.5 kHz
C.30.24 kHz
D.15 kHz
Answer: Option B

2. Which statement BEST describes the operation of a negative-edge-triggered D flip-flop?

A.The logic level at the D input is transferred to Q on NGT of CLK.
B.The Q output is ALWAYS identical to the CLK input if the D input is HIGH.
C.The Q output is ALWAYS identical to the D input when CLK = PGT.
D.The Q output is ALWAYS identical to the D input.
Answer: Option A

3. Propagation delay time, tPLH, is measured from the ________.

A.triggering edge of the clock pulse to the LOW-to-HIGH transition of the output
B.triggering edge of the clock pulse to the HIGH-to-LOW transition of the output
C.preset input to the LOW-to-HIGH transition of the output
D.clear input to the HIGH-to-LOW transition of the output
Answer: Option A

4. How is a J-K flip-flop made to toggle?

A.J = 0, K = 0
B.J = 1, K = 0
C.J = 0, K = 1
D.J = 1, K = 1
Answer: Option D

5. How many flip-flops are in the 7475 IC?

A.1
B.2
C.4
D.8
Answer: Option C

6. How many flip-flops are required to produce a divide-by-128 device?

A.1
B.4
C.6
D.7
Answer: Option D
Which is not an Altera primitive port identifier?
A
clk
.
B
ena
.
C
clr
.
D
prn
.
Answer: Option C

8. The timing network that sets the output frequency of a 555 astable circuit contains ________.
 A.three external resistors are used
B.two external resistors and an external capacitor are used
C.an external resistor and two external capacitors are used
D.no external resistor or capacitor is required
Answer: Option B
9. What is the difference between the enable input of the 7475 and the clock input of the 7474?
A.The 7475 is edge-triggered.
B.The 7474 is edge-triggered.
Answer: Option B

10. The phenomenon of interpreting unwanted signals on J and K while Cp (clock pulse) is HIGH is
called ________.
A.parity error checking
B.ones catching
C.digital discrimination
D.digital filtering
Answer: Option B

11. What is another name for a one-shot?

A.Monostable
B.Multivibrator
C.Bistable
D.Astable
Answer: Option A

12. On a master-slave flip-flop, when is the master enabled?

A.when the gate is LOW
B.when the gate is HIGH
C.both of the above
D.neither of the above
Answer: Option B
3. One example of the use of an S-R flip-flop is as a(n):
A.racer
B.astable oscillator
C.binary storage register
D.transition pulse generator
Answer: Option C
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14. What is the difference between the 7476 and the 74LS76?
A.the 7476 is master-slave, the 74LS76 is master-slave
B.the 7476 is edge-triggered, the 74LS76 is edge-triggered
C.the 7476 is edge-triggered, the 74LS76 is master-slave
D.the 7476 is master-slave, the 74LS76 is edge-triggered
Answer: Option D

15. Which of the following is correct for a gated D flip-flop?

A.The output toggles if one of the inputs is held HIGH.
B.Only one of the inputs can be HIGH at a time.
C.The output complement follows the input when enabled.
D.Q output follows the input D when the enable is HIGH.
Answer: Option D
16. With regard to a D latch, ________.
A.the Q output follows the D input when EN is LOW
B.the Q output is opposite the D input when EN is LOW
C.the Q output follows the D input when EN is HIGH
D.the Q output is HIGH regardless of EN's input state
Answer: Option C

17. How can the cross-coupled NAND flip-flop be made to have active-HIGH S-R inputs?
A.It can't be done.
B.Invert the Q outputs.
C.Invert the S-R inputs.
Answer: Option C

18. When is a flip-flop said to be transparent?

A.when the Q output is opposite the input
B.when the Q output follows the input
C.when you can see through the IC packaging
Answer: Option B
Four positive edge-triggered D flip-flops are used to store a 4-bit binary number as shown below.
Determine if the circuit is functioning properly, and if not, what might be wrong.
 A.The circuit is functioning properly.
B.Q2 is incorrect; the flip-flop is probably bad.
C.The input to flip-flop 3 (D2) is probably wrong; check the source of D2.
D.A bad connection probably exists between FF-3 and FF-4, causing FF-3 not to reset.
Answer: Option B
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20. A 555 operating as a monostable multivibrator has an R1 of 1 M . Determine C1 for a pulse

 width of 2 s.
A.1.8 F
B.18 F
C.18 pF
D.18 nF
Answer: Option A
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21. Master-slave J-K flip-flops are called pulse-triggered or level-triggered devices because input
data is read during the entire time the clock pulse is at a LOW level.
A.True
B.False
Answer: Option B
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22. Which of the following is correct for a D latch?

A.The output toggles if one of the inputs is held HIGH.
B.Q output follows the input D when the enable is HIGH.
C.Only one of the inputs can be HIGH at a time.
D.The output complement follows the input when enabled.
Answer: Option B
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23. A J-K flip-flop is in a "no change" condition when ________.

A.J = 1, K = 1
B.J = 1, K = 0
C.J = 0, K = 1
D.J = 0, K = 0
Answer: Option D
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24. A correct output is achieved from a master-slave J-K flip-flop only if its inputs are stable while
the:
A.clock is LOW
B.slave is transferring
C.flip-flop is reset
D.clock is HIGH
Answer: Option D
Which of the following describes the operation of a positive edge-triggered D flip-flop?
A.If both inputs are HIGH, the output will toggle.
 B.The output will follow the input on the leading edge of the clock.
C.When both inputs are LOW, an invalid state exists.
The input is toggled into the flip-flop on the leading edge of the clock and is passed to the
D.
output on the trailing edge of the clock.
Answer: Option B
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26. What does the triangle on the clock input of a J-K flip-flop mean?
A.level enabled
B.edge-triggered
Answer: Option B
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27. A J-K flip-flop with J = 1 and K = 1 has a 20 kHz clock input. The Q output is ________.
A.constantly LOW
B.constantly HIGH
C.a 20 kHz square wave
D.a 10 kHz square wave
Answer: Option D
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28.
The toggle condition in a master-slave J-K flip-flop means that Q and will switch to their
________ state(s) at the ________.
A.opposite, active clock edge
B.inverted, positive clock edge
C.quiescent, negative clock edge
D.reset, synchronous clock edge
Answer: Option A
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29. An RC circuit used in a nonretriggerable 74121 one-shot has an REXT of 49 k and a CEXT of
0.2 F. The pulse width (tW) is approximately ________.
A.6.9 s
B.6.9 ms
C.69 ms
D.690 ms
Answer: Option B
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30. On a positive edge-triggered S-R flip-flop, the outputs reflect the input condition when ________.
A.the clock pulse is LOW
B.the clock pulse is HIGH
C.the clock pulse transitions from LOW to HIGH
D.the clock pulse transitions from HIGH to LOW
Answer: Option C
. What is the hold condition of a flip-flop?
A.both S and R inputs activated
B.no active S or R input
C.only S is active
D.only R is active
Answer: Option B
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32. If an active-HIGH S-R latch has a 0 on the S input and a 1 on the R input and then the R input
goes to 0, the latch will be ________.
A.SET
B.RESET
C.clear
D.invalid
Answer: Option B
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33. In VHDL, how many inputs will a primitive JK flip-flop have?

A.2
B.3
C.4
D.5
Answer: Option D
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34. A 555 operating as a monostable multivibrator has a C1 = 0.01 F. Determine R1 for a pulse
width of 2 ms.
A.200 k
B.182 k
C.91 k
D.182
Answer: Option B
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35. A D flip-flop utilizing a PGT clock is in the CLEAR state. Which of the following input actions will
cause it to change states?
A.CLK = NGT, D = 0
B.CLK = PGT, D = 0
C.CLOCK NGT, D = 1
D.CLOCK PGT, D = 1
E.CLK = NGT, D = 0, CLOCK NGT, D = 1
Answer: Option D
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36. The symbols on this flip-flop device indicate ________.

A.triggering takes place on the negative-going edge of the CLK pulse

B.triggering takes place on the positive-going edge of the CLK pulse
C.triggering can take place anytime during the HIGH level of the CLK waveform
D.triggering can take place anytime during the LOW level of the CLK waveform
Answer: Option A
n a 555 timer, three 5 k resistors provide a trigger level of ________.
A
1/4 VCC and a threshold level 1/2 VCC
.
B
1/3 VCC and a threshold level 3/4 VCC
.
C
1/3 VCC and a threshold level 2/3 VCC
.
D
1/4 VCC and a threshold level 2/3 VCC
.
Answer: Option C
Explanation:
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38. Does the cross-coupled NOR flip-flop have active-HIGH or active-LOW set and reset inputs?
A.active-HIGH
B.active-LOW
Answer: Option A
Explanation:
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39. The circuit that is primarily responsible for certain flip-flops to be designated as edge-triggered is
the:
A.edge-detection circuit.
B.NOR latch.
C.NAND latch.
D.pulse-steering circuit.
Answer: Option A
Explanation:
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40. With four J-K flip-flops wired as an asynchronous counter, the first output change of divider #4
indicates a count of how many input clock pulses?
A.16
B.8
C.4
D.2
Answer: Option B
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41. What is the significance of the J and K terminals on the J-K flip-flop?
A.There is no known significance in their designations.
The J represents "jump," which is how the Q output reacts whenever the clock goes high and
B.
the Jinput is also HIGH.
C.The letters were chosen in honor of Jack Kilby, the inventory of the integrated circuit.
D.All of the other letters of the alphabet are already in use.
Answer: Option C
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42. Why are the S and R inputs of a gated flip-flop said to be synchronous?
A.They must occur with the gate.
B.They occur independent of the gate.
Answer: Option A