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LHW3

Homework exercises Digital Systems design

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19 views

LHW3

Homework exercises Digital Systems design

Uploaded by

Vignesh Ramachandran
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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ECE 270 Introduction to Digital System Design Spring 2019

Homework 3
Due at the beginning of your scheduled lab period

Last Name (Printed): ___________________________________ Lab Div: _____ Date: ____________

E-mail: __ __ __ __ __ __ __ __ @purdue.edu Signature: ______________________________________

Printed copies of these pages along with your original (hand-annotated, not photocopied) written
solution in the space provided (unless otherwise indicated) are required in order to receive credit. NOTE:
The purpose of homework is to provide an opportunity for practicing the kinds of problems you will be
asked to solve on quizzes and exams – copying the work of someone else does not accomplish this.

1. [8 pts] Assume two logic families have the following D.C. characteristics:

Logic Family “A”


VCC = 5 V VOH = 4.1 V VOL = 0.4 V VIH = 3.3 V VIL = 1.3 V
VTH = (VOH – VOL)/2 IOH = -7.5 mA IOL = 7.5 mA IIH = 0.25 A IIL = -0.25 A

Logic Family “B”


VCC = 5 V VOH = 3.4 V VOL = 0.33 V VIH = 2.7 V VIL = 1.2 V
VTH = (VOH – VOL)/2 IOH = -900 A IOL = 8.8 mA IIH = 13 A IIL = -0.13 mA

(a) [4 pts] Calculate the following (show work):


 (LO 1-14) DCNM AB

 (LO 1-14) DCNM BA

 (LO 1-20) Practical Fanout AB

 (LO 1-20) Practical Fanout BA

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ECE 270 Introduction to Digital System Design Spring 2019

Problem 1, continued…

(b) [2 pts] Draw the circuit and calculate the value of the current limiting resistor
for a Type “A” gate driving an LED to the maximum brightness possible in a
current sourcing configuration. Assume VLED is 1.5V. (LO 1-21)

(c) [2 pts] Draw the circuit and calculate the value of the current limiting resistor
for a Type “B” gate driving an LED to the maximum brightness possible in a
current sinking configuration. Assume VLED is 1.5V. (LO 1-21)

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ECE 270 Introduction to Digital System Design Spring 2019

2. [8 pts] Given that a (5-volt) CMOS gate’s P-channel pull-up has an “on” resistance of
60  and that its N-channel pull-down has an “on” resistance of 30 :

(a) [2 pts] If the desired VOHmin is 4.6 volts and the desired VOLmax is 0.25 volts, what
are the gate’s IOHmax and IOLmax ratings? (LO 1-19)

IOHmax = ______ mA IOLmax = ______ mA

(b) [2 pts] If a DCNM of 1.5 volts is desired for this CMOS gate family, what do its
VIHmin and VILmax specifications need to be, based on the values given in part (a)?
(LO 1-14)

VIHmin = _______ V VILmax = ______ V

(c) [1 pt] If the IIH and IIL specifications for gates in this family are +0.1 mA and -0.1
mA, respectively, what is the practical fan-out for circuits constructed using these
gates, based on values calculated in part (a)? (LO 1-20)

Practical fan-out = _________

(d) [3 pts] Show how an LED (forward voltage VLED = 1.5 V) should be interfaced to
gates in this family to obtain maximum brightness, and calculate the value of the
current limiting resistor required along with its power dissipation. (LO 1-21)

Circuit and calculations:

Current limiting resistor = ______ Resistor power dissipation = _____ mW

3
ECE 270 Introduction to Digital System Design Spring 2019

3. [4 pts] A particular CMOS microcontroller is designed to operate over a supply voltage


range of 1.0 V to 5.0 V and at a maximum clock frequency of 80 MHz (no minimum
clock frequency is specified). The maximum power dissipation over this range of
supply voltage and clock frequency is specified to be 450 milliwatts.

(a) [2 pts] Plot the relationship between power dissipation and supply voltage for this
microcontroller (LO 1-29).

500
Power Dissipation (mW)

400

300

200

100

0
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Supply Voltage (V)

(b) [2 pts] Plot the relationship between power dissipation and clock frequency for this
microcontroller (LO 1-28).
500
Power Dissipation (mW)

400

300

200

100

0
0 10 20 30 40 50 60 70 80 Clock Freq (MHz)

Score: ______ / 20
4

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