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Experiment-06

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9 views

Experiment-06

Uploaded by

Rohit
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Experiment – 06

Aim: To write a hardware description of 4-bit mod 13 counter and test its operation.
Tools Used: Xilinx VIVADO 2024.1 version
Theory:
A Counter is a device which stores (and sometimes displays) the number of times a particular
event or process has occurred, often in relationship to a clock signal. Counters are used in
digital electronics for counting purpose, they can count specific event happening in the circuit.
For example, in UP counter a counter increases count for every rising edge of clock.
They can be asynchronous (ripple) where flip-flops toggle at different times or synchronous
where all flip-flops are triggered simultaneously, making them faster and more accurate.
The modulo, mod in short, number is defined as the number of states that the counter goes
through in each complete cycle before it recycles back to its starting state.
A 4-bit modulo-13 counter counts from 0 to 12 (13 states) and then resets to 0, skipping the

Fig 6.1: Logic diagram of a 4-bit counter


(Source: https://www.geeksforgeeks.org/counters-in-digital-logic/)
binary values from 13 to 15. It typically uses additional logic to detect the count of 13 (1101 in
binary) and trigger a reset to maintain the modulo-13 operation.
akk
Verilog HDL Code:
module jk_ff (
input clk,
input reset,
input J,
input K,
output reg Q
);
always @(posedge clk or posedge reset) begin
if (reset)
Q <= 1'b0;
else begin
case ({J,K})
2'b00: Q <= Q; // No change
2'b01: Q <= 1'b0; // Reset
2'b10: Q <= 1'b1; // Set
2'b11: Q <= ~Q; // Toggle
endcase
end
end
endmodule
module counter (
input clk,
input reset,
output [3:0] count
);
wire [3:0] Q;
wire [3:0] J, K;
// Reset
wire reset_count = (Q == 4'b1101);
// Flip-flop 0 (LSB)
assign J[0] = 1'b1;
assign K[0] = 1'b1;
// Flip-flop 1
assign J[1] = Q[0];
assign K[1] = Q[0];
// Flip-flop 2
assign J[2] = Q[0] & Q[1];
assign K[2] = Q[0] & Q[1];
// Flip-flop 3 (MSB)
assign J[3] = Q[0] & Q[1] & Q[2];
assign K[3] = Q[0] & Q[1] & Q[2];
jk_ff ff0 (.clk(clk), .reset(reset | reset_count), .J(J[0]), .K(K[0]), .Q(Q[0]));
jk_ff ff1 (.clk(clk), .reset(reset | reset_count), .J(J[1]), .K(K[1]), .Q(Q[1]));
jk_ff ff2 (.clk(clk), .reset(reset | reset_count), .J(J[2]), .K(K[2]), .Q(Q[2]));
jk_ff ff3 (.clk(clk), .reset(reset | reset_count), .J(J[3]), .K(K[3]), .Q(Q[3]));
assign count = Q;
endmodule
Testbench code:
module tb_counter;
reg clk;
reg reset;
wire [3:0] count;
counter uut (
.clk(clk),
.reset(reset),
.count(count));
// Clock
always #10 clk = ~clk;
initial begin
clk = 0;
reset = 0;
reset = 1;
#20;
reset = 0;
#200;
reset = 0;
#20;
reset = 0;
#200;
$stop;
end
endmodule
RTL Schematic:

Fig 6.2: RTL Schematic of a 4-bit mod 13 counter


Output waveform:

Fig 6.3: Output waveform for a 4-bit mod 13 counter


Result:
A 4-bit mod-13 counter was successfully described in hardware using Verilog HDL and verified
using the RTL schematic. The counter was designed to count from 0 to 12 (mod-13), after
which it resets to 0.
The counter was simulated using a testbench, and the waveform results were observed.

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