A B C D E

COMPAL CONFIDENTIAL
MODEL NAME :CAZ30/CAZ40
1
Port Map: 1

PCB NO : LA-E112P Kirkwood Port Map as of 2016-04-01

BOM P/N : 431A4831L01

X8 KBL UMA
Kabylake U
2
2016-04-20 2

REV : 0.1 (X00)

@ : Nopop Component
EMC@ : EMI, ESD and RF Component
@EMC@ : EMI, ESD and RF Nopop Component
CXDP@ : XDP Component
CONN@ : Connector Component
3 3

MB PCB
Part Number Description

DAA000CM000 PCB 1S3 LA-E112P REV0 MB AR 3

Layout Dell logo

4 4

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
COPYRIGHT 2015
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
ALL RIGHT RESERVED TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Cover Sheet
REV:X00 BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
PWB: 0.1
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
LA-E112P
Date: Friday, April 22, 2016 Sheet 1 of 58
A B C D E
 A B C D E

Memory Down
Kirkwood 12/13 AR Block Diagram
Memory BUS (LPDDR3)
LPDDR3 x 2
4xSDP/DDP/QDP
4x32b,1866MHz

eDP Lane x 4
1 EDP CONN Trough eDP Cable 1
P31
USB2.0[5]
UF Camera
P31
HDMI 1.4 HDMI
CONN P23
PCIE[1][2][3][4] USB2.0[1] SLGC55544BVTR USB2.0[1]_PS
USB POWER SHARE
P42 USB3.0 Conn
Lef t r ear TypeC USB3.0/USB2.0
DDI[1] INTEL USB
USB3.0[1] PS(Ext Port 1)
P42
P29
AR-DP SW2_DP1 USB2.0[2]
USB3.0/USB2.0 P24-25 To type C USB3.0 Conn
Lef t fr ont TypeC USB3.0[3] (Ext Port 2) P43
P30 DP DeMUX DDI[2]
KABYLAKE_U MCP
PS8338B
P22
USB2.0[6]
PD Solution Card reader
USB2.0/SMBus TPS65982D USB2.0/SMBus SW2_DP2 USB3.0[4] RTS5330 SD4.0
P26-27 To M2 WiGig card P32 P32

2 2

USB2.0[8] Wacom G12T Touchscreen/Pen

SATA[1]/PCIE[8] PCIE[6] PCIE[5]
I2C[0] 10 pin conn(default).
P31
M.2,3042 Key B
Micro SIM M.2,3030 Key A SPI
P34 WWAN/LTE/HCA IPT
PCIex2 for 2nd SSD and 6 pin conn for IPT opt i on.
Optane P34 WLAN+BT/WIGIG P31
P34
USB2.0[4]
USB2.0[7] Accelerometer &
I2C
SW2_DP1
Gyroscope P47
USB/PCIE MUX
Magnetometer/
HD3SS3212 E-Compass P47
P33
Place on Sensor/B
2nd Accelerometer
PCIE[7] USB3.0[2] (LCD) P3
0 ohm LID SWITCH for
PAGE 6~19
Laptop mode P47
0 ohm ALS TSL25911FN
3 HD Audio I/F MEC5105 P3 3
LID SWITCH for
SATA[2]/PCIE[12][11][10][9] 0 ohm Place on RF module Tablet mode P47
SPI
Smart Card TDA8034HN 0 ohm SAR Sensor
W25Q128FVSIQ MEC5105 USH CONN
USH TPM1.2 USB2.0[10] Semtech SX9310 P40
P8
ESPI

BCM58102
SPI 128M 4K sector INT.Speaker
RFID/NFC CPU&PCH XDP Port
W25Q128FVSIQ P36
P14
P8
Fingerprint SPI 128M 4K sector HDA Codec Universal Jack AUTOMATIC POWER
NB-2023-S CONN reserve
ALC3253 P36 P36 SWITCH(APS) P11
USH board P40 TPM2.0
ATTPM20P-G1MA1-ABF Dig. MIC
P40 P32 DC/DC Interface
P58
Co-lay for cont i ngency Trough eDP Cable
Place on PWR/B
TPM1.2 POWER ON/OFF
NPCT650JA0YX P39 SW & LED P45
M.2 2280
4 SSD Conn P41 4

KB/TP CONN
SMSC KBC P44
GPIO expander I2C
MEC5105
ITE IT8306 P38 DELL CONFIDENTIAL/PROPRIETARY
P37 FAN CONN
P38
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Block diagram
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
0.1
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-E112P
Date: Friday, April 22, 2016 Sheet 2 of 58
A B C D E
 5 4 3 2 1

POWER STATES
Signal SLP SLP SLP SLP ALWAYS M SUS RUN CLOCKS
USB3.0 SSIC PCIE SATA DESTINATION USB PORT# DESTINATION
S3# S4# S5# A# PLANE PLANE PLANE PLANE
State USB3.0-1 JUSB1-->Right 1 JUSB1-->Right

S0 (Full ON) / M0 HIGH HIGH HIGH HIGH ON ON ON ON ON

USB3.0-2 SSIC M.2 3042(LTE) 2 JUSB2-->Lef t
USB3.0-3 JUSB2-->Lef t 3 NA
S3 (Suspend to RAM) / M3 LOW HIGH HIGH HIGH ON ON ON OFF OFF
D
USB3.0-4 SD Card Reader 4 M2 3042(WWAN) D

S4 (Suspend to DISK) / M3 LOW LOW HIGH HIGH ON ON OFF OFF OFF USB3.0-5 PCIE-1 5 UF Camera

S5 (SOFT OFF) / M3 LOW LOW LOW HIGH ON ON OFF OFF OFF

USB3.0-6 PCIE-2 6 SD Card Reader
Alpine Ridge-DP
PCIE-3 7 M.2 3030(BT)
S3 (Suspend to RAM) / M-OFF LOW HIGH HIGH LOW ON OFF ON OFF OFF
PCIE-4 8 Touch Screen
S4 (Suspend to DISK) / M-OFF LOW LOW HIGH LOW ON OFF OFF OFF OFF PCIE-5 M.2 3030(WLAN) 9 NA

S5 (SOFT OFF) / M-OFF LOW LOW LOW LOW ON OFF OFF OFF OFF
PCIE-6 M.2 3030(WIGIG) 10 USH
PCIE-7 SATA-0
M.2 3042(SATA Cache or HCA)
PM TABLE PCIE-8 SATA-1

+5V_ALW
PCIE-9
(M-OFF)
+3.3V_ALW PCIE-10 M.2 2280 SSD
+3.3V_ALW_DSW +3.3V_CV2 +5V_RUN (PCIe4 or SATA)
+3.3V_M +3.3V_M PCIE-11 SATA-1*
+3.3V_ALW_PCH +1.2V_MEM +3.3V_RUN
power +VCC_CORE
C plane +RTC_CELL +2.5V_MEM +0.6V_DDR_VTT PCIE-12 SATA-2 C
+VCC_GT
+1.8V_PRIM +1.0V_VCCST +1.8V_RUN
+1.0VS_VCCIO
+1.0V_PRIM
+VCC_SA
+1.0V_PRIM_CORE
+5V_ALW 2
State
+3.3V_ALW2
+3.3V_RTC_LDO
+1.0V_MPHYGT

S0 ON ON ON ON ON

S3 ON ON OFF ON OFF

S5 S4/AC ON OFF OFF ON OFF

S5 S4/AC doesn't exist OFF OFF OFF OFF OFF

B B

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
Port assignment
Size Document Number R ev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 0.1
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-E112P
Date: Friday, April 22, 2016 Sheet 3 of 58
5 4 3 2 1
 5 4 3 2 1

SIO_SLP_SUS# CPU PWR

SIO_SLP_S4#
SIO_SLP_S4# TPS22961 PCH PWR
+1.2V_MEM (UZ26) +VCC_SFR_OC
Peripheral Device PWR
SY8210A
(PU200) TYPE-C Power
0.6V_DDR_VTT_ON RUN_ON
TPS22961 SIO_SLP_S0#
Barrel Type-C +0.6V_DDR_VTT (UZ19) +1.0V_VCCSTG
ADAPTER ADAPTER
SIO_SLP_S4#
TPS22961
(UZ21) +1.0V_VCCST
D D

SIO_SLP_SUS#
SYX196D
(PU301) +1.0V_PRIM

RUN_ON
CHARGER TPS62134C
ISL88738 +PWR_SRC +5V_ALW (PU401) +1.0VS_VCCIO
ALW ON
(PU901) SY8288C
(PU102) TPS62134D SIO_SLP_SUS#

(PU402) +1.0V_PRIM_CORE
+5V_ALW2

RUN_ON 3.3V_TS_EN
EM5209 LP2301
(UZ4) +5V_RUN (QV8) +3.3V_TSP

BATTERY AUD_PWR_EN
EM5209
(@UZ5) +5V_RUN_AUDIO

USB_PWR_SHR_EN#
SY8288B +3.3V_RTC_LDO SLGC55544C
(PU100) (UI3) +5V_USB_CHG_PWR
C C
ALW ON
USB_PWR_EN1#
+3.3V_ALW2 SY6288
(UI1) +USB_EX2_PWR

ISL95857
(PU602) +3.3V_ALW
SIO_SLP_S4#
AP7361C
(PU503) +1.8V_MEM
for LPDDR3

SIO_SLP_SUS# RUN_ON
RT8097ALGE AOZ1336
(PU501) +1.8V_PRIM (UZ8) +1.8V_RUN

ISL95808 CSD97374 CSD97374 AO6405

(PU606) (PU604) (PU603) (QV1) EM5209 AUX_EN_WOWL
(UZ2) +3.3V_WLAN
IMVP_VR_ON

IMVP_VR_ON
IMVP_VR_ON

@SIO_SLP_WLAN#
EN_INVPWR

SIO_SLP_SUS#
+3.3V_ALW_PCH
B EM5209 @PCH_ALW_ON B
(UZ3)
RUN_ON 3.3V_CAM_EN#
+VCC_SA +VCC_GT +VCC_CORE +BL_PWR_SRC LP2301A
+3.3V_RUN (QZ1) +3.3V_CAM

3.3V_WWAN_EN
EM5209
TYPE-C (UZ4) +3.3V_WWAN

AUD_PWR_EN
EM5209
+5V_ALW (@UZ5) +3.3V_RUN_AUDIO
TPS65982D
(UT5,UT11) +TBT_VBUS(5V~20V) G524B1T11U ENVCC_PCH

(UV24) +LCDVDD

TBT_PWR_EN
AOZ1336
+5V_ALW (UT4) +3.3V_TBT
+3.3V_TBT_SX AP2112K
(UT14) AP2204
+5V_TBT_VBUS (UT8,UT12) CV2_ON
TPS22967
(UZ18) +3.3V_CV2
USH/B

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
Power rails
Size Document Number R ev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 0.1
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-XXXXP
Date: Friday, April 22, 2016 Sheet 4 of 58
5 4 3 2 1
 5 4 3 2 1

1K 2.2K
SMBUS Address [0x9a]

1K
+3.3V_ALW_PCH 2.2K
+3.3V_RUN
AW44 MEM_SMBCLK DDR_XDP_WAN_SMBCLK
53
MEM_SMBDATA
DMN66D0LDW-7 DDR_XDP_WAN_SMBDATA
BB43 51 XDP
DMN66D0LDW-7
499
PCH
499
+3.3V_ALW_PCH
D D

AY44 SML0_SMBCLK
SML0_SMBDATA
BB39
AW45 AW42
1K
SML1_SMBDATA

SML1_SMBCLK
+3.3V_ALW_PCH
1K
2.2K
E11 D8 2.2K
+3.3V_ALW 2.2K
+3.3V_TBT_FLASH
03 03 2.2K
00 D7 UPD2_SMBCLK B5
DMN66D0LDW-7 PD
00 E7 UPD2_SMBDAT A5 FW reflash KEYSCAN_SMBDAT
DMN66D0LDW-7
@2.2K 2.2K 2.2K

+3.3V_ALW +3.3V_CV2 +3.3V_RUN

@2.2K 2.2K 2.2K

01 B3 USH_SMBCLK
DMN66D0LDW-7
E5 USH_SMBDAT SAR
01
C DMN66D0LDW-7 C
M9
4.7K USH/B
L9 USH ALS
+3.3V_RUN

KBC 02
02
E10
C12
DAT_TP_SIO_I2C_CLK

DAT_TP_SIO_I2C_DATA
0
0
I2C_1_SCL TP
2.2K 0
2.2K I2C_1_SDA
0
2.2K +3.3V_ALW +3.3V_TBT_FLASH
2.2K

MEC 5105 04 C3 UPD1_SMBCLK

DMN66D0LDW-7 B5
B4 UPD1_SMBDAT PD
04 A5
DMN66D0LDW-7
2.2K

05 F7

05 B6

06 A12
2.2K
B N10 B
06 +3.3V_ALW
2.2K
EXPANDER_GPU_SMCLK
07 M4
M7 EXPANDER_GPU_SMDATA Expander IO
07

08 C5
08 C8

09 F6

09 E9 2.2K
Charger

+3.3V_ALW
2.2K
10
100 ohm 7
N2 PBAT_CHARGER_SMBCLK
100 ohm 6
BATTERY
10 M3 PBAT__CHARGER_SMBDAT CONN
A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
Port assignment
Size Document Number R ev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 0.1
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-E112P
Date: Friday, April 22, 2016 Sheet 5 of 58
5 4 3 2 1
 5 4 3 2 1

+3.3V_RUN
UC1A CPU@ SKL-U

2 1 CPU_DP1_CTRL_CLK E55 C47

RC175 2.2K_0402_5% <24> CPU_DP1_N0 F55 DDI1_TXN[0] EDP_TXN[0] C46 EDP_TXN0 <31>
2 1 CPU_DP1_CTRL_DATA <24> CPU_DP1_P0 E58 DDI1_TXP[0] EDP_TXP[0] D46 EDP_TXP0 <31>
RC178 2.2K_0402_5% <24> CPU_DP1_N1 F58 DDI1_TXN[1] EDP_TXN[1] C45 EDP_TXN1 <31>
2 1 CPU_DP2_CTRL_CLK HDMI <24> CPU_DP1_P1 F53 DDI1_TXP[1] EDP_TXP[1] A45 EDP_TXP1 <31>
D RC176 2.2K_0402_5% <24> CPU_DP1_N2 G53 DDI1_TXN[2] EDP_TXN[2] B45 EDP_TXN2 <31> support QHD D
2 1 CPU_DP2_CTRL_DATA <24> CPU_DP1_P2 F56 DDI1_TXP[2] EDP_TXP[2] A47 EDP_TXP2 <31> +3.3V_RUN
RC177 2.2K_0402_5% <24> CPU_DP1_N3 G56 DDI1_TXN[3] EDP_TXN[3] B47 EDP_TXN3 <31>
<24> CPU_DP1_P3 DDI1_TXP[3] EDP_TXP[3] EDP_TXP3 <31>
C50 E45 CPU_DP1_AUXN 1 2
<22> CPU_DP2_N0 D50 DDI2_TXN[0] DDI EDP EDP_AUXN F45 EDP_AUXN <31>
RC179 100K_0402_5%
<22> CPU_DP2_P0 C52 DDI2_TXP[0] EDP_AUXP EDP_AUXP <31> CPU_DP2_AUXN 1 2
<22> CPU_DP2_N1 D52 DDI2_TXN[1] B52 RC181 100K_0402_5%
PS8338(AR)/ <22> CPU_DP2_P1 A50 DDI2_TXP[1] EDP_DISP_UTIL
PS8348(NON AR) <22> CPU_DP2_N2 B50 DDI2_TXN[2] G50 CPU_DP1_AUXN
<22> CPU_DP2_P2 D51 DDI2_TXP[2] DDI1_AUXN F50 CPU_DP1_AUXP CPU_DP1_AUXN <24>
<22> CPU_DP2_N3 C51 DDI2_TXN[3] DDI1_AUXP E48 CPU_DP1_AUXP <24>
<22> CPU_DP2_P3 DDI2_TXP[3] DDI2_AUXN F48 CPU_DP2_AUXN <22>
DDI2_AUXP G46 CPU_DP3_AUXN CPU_DP2_AUXP <22>
DISPLAY SIDEBANDS DDI3_AUXN F46 CPU_DP3_AUXP PAD~D @ T1 CPU_DP2_AUXP 1 2
CPU_DP1_CTRL_CLK L13 DDI3_AUXP PAD~D @ T2
RC182 100K_0402_5%
<24> CPU_DP1_CTRL_CLK CPU_DP1_CTRL_DATA L12 GPP_E18/DDPB_CTRLCLK L9 CPU_DP1_AUXP 1 2
<24> CPU_DP1_CTRL_DATA GPP_E19/DDPB_CTRLDATA GPP_E13/DDPB_HPD0 L7 CPU_DP1_HPD <24>
RC180 100K_0402_5%
CPU_DP2_CTRL_CLK N7 GPP_E14/DDPC_HPD1 L6 CPU_DP2_HPD <22> EDP_HPD 1 2
<22> CPU_DP2_CTRL_CLK CPU_DP2_CTRL_DATA N8 GPP_E20/DDPC_CTRLCLK GPP_E15/DDPD_HPD2 N9 RC1 100K_0402_5%
<22> CPU_DP2_CTRL_DATA GPP_E21/DDPC_CTRLDATA GPP_E16/DDPE_HPD3 L10 CPU_DP1_HPD 1 2
PCH_SPI_IRQ_TS GPP_E17/EDP_HPD EDP_HPD <31>
<31> TS_SPI_IRQ 0_0402_5% 2 1 RC398 N11 @ RC312 100K_0402_5%
N12 GPP_E22/DDPD_CTRLCLK R12 CPU_DP2_HPD 1 2
<31> I2C0_IRQ_TS GPP_E23/DDPD_CTRLDATA EDP_BKLTEN R11 PANEL_BKLEN <31> RC242 100K_0402_5%
RC2 2 1 24.9_0402_1% EDP_COMP E52 EDP_BKLTCTL U13 EDP_BIA_PWM <31>
+1.0VS_VCCIO EDP_RCOMP EDP_VDDEN ENVDD_PCH <31,37>
1 OF 20
SKL-U_BGA1356
COMPENSATION PU FOR eDP
CAD Note:Trace width=20 mils ,Spacing=25mil, SKL-U Ballout Rev0.71 & INTEL symbol Rev1.0
Max length=100 mils.
C C

SKL_ULT
UC1I CPU@

CSI-2

A36 C37
B36 CSI2_DN0 CSI2_CLKN0 D37
C38 CSI2_DP0 CSI2_CLKP0 C32
D38 CSI2_DN1 CSI2_CLKN1 D32
C36 CSI2_DP1 CSI2_CLKP1 C29
B D36 CSI2_DN2 CSI2_CLKN2 D29 B
A38 CSI2_DP2 CSI2_CLKP2 B26
B38 CSI2_DN3 CSI2_CLKN3 A26
CSI2_DP3 CSI2_CLKP3
C31 E13 CSI2_COMP RC3 1 2 100_0402_1%
D31 CSI2_DN4 CSI2_COMP B7
C33 CSI2_DP4 GPP_D4/FLASHTRIG TBT_FORCE_PWR <24>
D33 CSI2_DN5
A31 CSI2_DP5 EMMC

B31 CSI2_DN6 AP2 MEM_CONFIG0

A33 CSI2_DP6 GPP_F13/EMMC_DATA0 AP1 MEM_CONFIG1
B33 CSI2_DN7 GPP_F14/EMMC_DATA1 AP3 MEM_CONFIG2
CSI2_DP7 GPP_F15/EMMC_DATA2 AN3 MEM_CONFIG3
A29 GPP_F16/EMMC_DATA3 AN1 MEM_CONFIG4
B29 CSI2_DN8 GPP_F17/EMMC_DATA4 AN2
C28 CSI2_DP8 GPP_F18/EMMC_DATA5 AM4
D28 CSI2_DN9 GPP_F19/EMMC_DATA6 AM1
A27 CSI2_DP9 GPP_F20/EMMC_DATA7
B27 CSI2_DN10 AM2
C27 CSI2_DP10 GPP_F21/EMMC_RCLK AM3
D27 CSI2_DN11 GPP_F22/EMMC_CLK AP4
CSI2_DP11 GPP_F12/EMMC_CMD
AT1 EMMC_RCOMP 1 2
EMMC_RCOMP RC4 200_0402_1%
SKL-U_BGA1356 9 OF 20

+1.8V_PRIM

A 1 2 MEM_CONFIG0 1 2 A
@ RC388 10K_0402_5% RC393 10K_0402_5%
1 2 MEM_CONFIG1 1 2
RC389 10K_0402_5% @ RC394 10K_0402_5%
1 2 MEM_CONFIG2 1 2
@ RC390
1 2
10K_0402_5%
MEM_CONFIG3
RC395
1 2
10K_0402_5% DELL CONFIDENTIAL/PROPRIETARY
RC391
1 2
10K_0402_5%
MEM_CONFIG4
@ RC396
1 2
10K_0402_5%
Compal Electronics, Inc.
@ RC392 10K_0402_5% RC397 10K_0402_5% PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
CPU (1/14)
Size Document Number R ev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
0.1
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-E112P
Date: Friday, April 22, 2016 Sheet 6 of 58
5 4 3 2 1
 5 4 3 2 1

For LPDDR3
<20> DDR_A_DQS#[0..7] <21> DDR_B_DQS#[0..7]

<20> DDR_A_D[0..63] <21> DDR_B_D[0..63]

LPDDR3, Ballout for side by side(Non-Interleave) <20> DDR_A_DQS[0..7] <21> DDR_B_DQS[0..7]
D D
<20> DDR_A_CAA[0..9] <21> DDR_B_CAA[0..9]
SKL-U
SKL-U <20> DDR_A_CAB[0..9] <21> DDR_B_CAB[0..9]
UC1B CPU@ UC1C CPU@

AU53 DDR_A_CLK#0
DDR_A_D0 AL71 DDR0_CKN[0] AT53 DDR_A_CLK0 DDR_A_CLK#0 <20> DDR_A_D16 AF65 AN45 DDR_B_CLK#0
DDR_A_D1 AL68 DDR0_DQ[0] DDR0_CKP[0] AU55 DDR_A_CLK#1 DDR_A_CLK0 <20> DDR_A_D17 AF64 DDR1_DQ[0]/DDR0_DQ[16] DDR1_CKN[0] AN46 DDR_B_CLK#1 DDR_B_CLK#0 <21>
DDR_A_D2 AN68 DDR0_DQ[1] DDR0_CKN[1] AT55 DDR_A_CLK1 DDR_A_CLK#1 <20> DDR_A_D18 AK65 DDR1_DQ[1]/DDR0_DQ[17] DDR1_CKN[1] AP45 DDR_B_CLK0 DDR_B_CLK#1 <21>
DDR_A_D3 AN69 DDR0_DQ[2] DDR0_CKP[1] DDR_A_CLK1 <20> DDR_A_D19 AK64 DDR1_DQ[2]/DDR0_DQ[18] DDR1_CKP[0] AP46 DDR_B_CLK1 DDR_B_CLK0 <21>
DDR_A_D4 AL70 DDR0_DQ[3] BA56 DDR_A_CKE0 DDR_A_D20 AF66 DDR1_DQ[3]/DDR0_DQ[19] DDR1_CKP[1] DDR_B_CLK1 <21>
DDR_A_D5 AL69 DDR0_DQ[4] DDR0_CKE[0] BB56 DDR_A_CKE1 DDR_A_CKE0 <20> DDR_A_D21 AF67 DDR1_DQ[4]/DDR0_DQ[20] AN56 DDR_B_CKE0
DDR_A_D6 AN70 DDR0_DQ[5] DDR0_CKE[1] AW56 DDR_A_CKE2 DDR_A_CKE1 <20> DDR_A_D22 AK67 DDR1_DQ[5]/DDR0_DQ[21] DDR1_CKE[0] AP55 DDR_B_CKE1 DDR_B_CKE0 <21>
DDR_A_D7 AN71 DDR0_DQ[6] DDR0_CKE[2] AY56 DDR_A_CKE3 DDR_A_CKE2 <20> DDR_A_D23 AK66 DDR1_DQ[6]/DDR0_DQ[22] DDR1_CKE[1] AN55 DDR_B_CKE2 DDR_B_CKE1 <21>
DDR_A_D8 AR70 DDR0_DQ[7] DDR0_CKE[3] DDR_A_CKE3 <20> DDR_A_D24 AF70 DDR1_DQ[7]/DDR0_DQ[23] DDR1_CKE[2] AP53 DDR_B_CKE3 DDR_B_CKE2 <21>
DDR_A_D9 AR68 DDR0_DQ[8] AU45 DDR_A_CS#0 DDR_A_D25 AF68 DDR1_DQ[8]/DDR0_DQ[24] DDR1_CKE[3] DDR_B_CKE3 <21>
DDR_A_D10 AU71 DDR0_DQ[9] DDR0_CS#[0] AU43 DDR_A_CS#1 DDR_A_CS#0 <20> DDR_A_D26 AH71 DDR1_DQ[9]/DDR0_DQ[25] BB42 DDR_B_CS#0
DDR_A_D11 AU68 DDR0_DQ[10] DDR0_CS#[1] AT45 DDR_A_ODT0 DDR_A_CS#1 <20> DDR_A_D27 AH68 DDR1_DQ[10]/DDR0_DQ[26] DDR1_CS#[0] AY42 DDR_B_CS#1 DDR_B_CS#0 <21>
DDR_A_D12 AR71 DDR0_DQ[11] DDR0_ODT[0] AT43 DDR_A_ODT0 <20> DDR_A_D28 AF71 DDR1_DQ[11]/DDR0_DQ[27] DDR1_CS#[1] BA42 DDR_B_ODT0 DDR_B_CS#1 <21>
DDR_A_D13 AR69 DDR0_DQ[12] DDR0_ODT[1] DDR_A_D29 AF69 DDR1_DQ[12]/DDR0_DQ[28] DDR1_ODT[0] AW42 DDR_B_ODT0 <21>
DDR_A_D14 AU70 DDR0_DQ[13] BA51 DDR_A_CAA0 DDR_A_D30 AH70 DDR1_DQ[13]/DDR0_DQ[29] DDR1_ODT[1]
DDR_A_D15 AU69 DDR0_DQ[14] DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] BB54 DDR_A_CAA1 DDR_A_D31 AH69 DDR1_DQ[14]/DDR0_DQ[30] AY48 DDR_B_CAA0
DDR_A_D32 BB65 DDR0_DQ[15] DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] BA52 DDR_A_CAA2 DDR_A_D48 AT66 DDR1_DQ[15]/DDR0_DQ[31] DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] AP50 DDR_B_CAA1
DDR_A_D33 AW65 DDR0_DQ[16]/DDR0_DQ[32] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] AY52 DDR_A_CAA3 DDR_A_D49 AU66 DDR1_DQ[16]/DDR0_DQ[48] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] BA48 DDR_B_CAA2
DDR_A_D34 AW63 DDR0_DQ[17]/DDR0_DQ[33] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] AW52 DDR_A_CAA4 DDR_A_D50 AP65 DDR1_DQ[17]/DDR0_DQ[49] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] BB48 DDR_B_CAA3
DDR_A_D35 AY63 DDR0_DQ[18]/DDR0_DQ[34] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7] AY55 DDR_A_CAA5 DDR_A_D51 AN65 DDR1_DQ[18]/DDR0_DQ[50] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] AP48 DDR_B_CAA4
DDR_A_D36 BA65 DDR0_DQ[19]/DDR0_DQ[35] DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] AW54 DDR_A_CAA6 DDR_A_D52 AN66 DDR1_DQ[19]/DDR0_DQ[51] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7] AP52 DDR_B_CAA5
DDR_A_D37 AY65 DDR0_DQ[20]/DDR0_DQ[36] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] BA54 DDR_A_CAA7 DDR_A_D53 AP66 DDR1_DQ[20]/DDR0_DQ[52] DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] AN50 DDR_B_CAA6
DDR_A_D38 BA63 DDR0_DQ[21]/DDR0_DQ[37] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11] BA55 DDR_A_CAA8 DDR_A_D54 AT65 DDR1_DQ[21]/DDR0_DQ[53] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] AN48 DDR_B_CAA7
DDR_A_D39 BB63 DDR0_DQ[22]/DDR0_DQ[38] DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# AY54 DDR_A_CAA9 DDR_A_D55 AU65 DDR1_DQ[22]/DDR0_DQ[54] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11] AN53 DDR_B_CAA8
DDR_A_D40 BA61 DDR0_DQ[23]/DDR0_DQ[39] DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1] DDR_A_D56 AT61 DDR1_DQ[23]/DDR0_DQ[55] DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# AN52 DDR_B_CAA9
DDR_A_D41 AW61 DDR0_DQ[24]/DDR0_DQ[40] AU46 DDR_A_CAB0 DDR_A_D57 AU61 DDR1_DQ[24]/DDR0_DQ[56] DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]
C DDR_A_D42 BB59 DDR0_DQ[25]/DDR0_DQ[41] DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13] AU48 DDR_A_CAB1 DDR_A_D58 AP60 DDR1_DQ[25]/DDR0_DQ[57] BA43 DDR_B_CAB0 C
DDR_A_D43 AW59 DDR0_DQ[26]/DDR0_DQ[42] DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15] AT46 DDR_A_CAB2 DDR_A_D59 AN60 DDR1_DQ[26]/DDR0_DQ[58] DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13] AY43 DDR_B_CAB1
DDR_A_D44 BB61 DDR0_DQ[27]/DDR0_DQ[43] DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14] AU50 DDR_A_CAB3 DDR_A_D60 AN61 DDR1_DQ[27]/DDR0_DQ[59] DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15] AY44 DDR_B_CAB2
DDR_A_D45 AY61 DDR0_DQ[28]/DDR0_DQ[44] DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16] AU52 DDR_A_CAB4 DDR_A_D61 AP61 DDR1_DQ[28]/DDR0_DQ[60] DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14] AW44 DDR_B_CAB3
DDR_A_D46 BA59 DDR0_DQ[29]/DDR0_DQ[45] DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0] AY51 DDR_A_CAB5 DDR_A_D62 AT60 DDR1_DQ[29]/DDR0_DQ[61] DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16] BB44 DDR_B_CAB4
DDR_A_D47 AY59 DDR0_DQ[30]/DDR0_DQ[46] DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2] AT48 DDR_A_CAB6 DDR_A_D63 AU60 DDR1_DQ[30]/DDR0_DQ[62] DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0] AY47 DDR_B_CAB5
DDR_B_D0 AY39 DDR0_DQ[31]/DDR0_DQ[47] DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] AT50 DDR_A_CAB7 DDR_B_D16 AU40 DDR1_DQ[31]/DDR0_DQ[63] DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2] BA44 DDR_B_CAB6
DDR_B_D1 AW39 DDR0_DQ[32]/DDR1_DQ[0] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10] BB50 DDR_A_CAB8 DDR_B_D17 AT40 DDR1_DQ[32]/DDR1_DQ[16] DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] AW46 DDR_B_CAB7
DDR_B_D2 AY37 DDR0_DQ[33]/DDR1_DQ[1] DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] AY50 DDR_A_CAB9 DDR_B_D18 AT37 DDR1_DQ[33]/DDR1_DQ[17] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10] AY46 DDR_B_CAB8
DDR_B_D3 AW37 DDR0_DQ[34]/DDR1_DQ[2] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0] BA50 DDR_B_D19 AU37 DDR1_DQ[34]/DDR1_DQ[18] DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] BA46 DDR_B_CAB9
DDR_B_D4 BB39 DDR0_DQ[35]/DDR1_DQ[3] DDR0_MA[3] BB52 DDR_B_D20 AR40 DDR1_DQ[35]/DDR1_DQ[19] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0] BB46
DDR_B_D5 BA39 DDR0_DQ[36]/DDR1_DQ[4] DDR0_MA[4] DDR_B_D21 AP40 DDR1_DQ[36]/DDR1_DQ[20] DDR1_MA[3] BA47
DDR_B_D6 BA37 DDR0_DQ[37]/DDR1_DQ[5] AM70 DDR_A_DQS#0 DDR_B_D22 AP37 DDR1_DQ[37]/DDR1_DQ[21] DDR1_MA[4]
DDR_B_D7 BB37 DDR0_DQ[38]/DDR1_DQ[6] DDR0_DQSN[0] AM69 DDR_A_DQS0 DDR_B_D23 AR37 DDR1_DQ[38]/DDR1_DQ[22] AH66 DDR_A_DQS#2
DDR_B_D8 AY35 DDR0_DQ[39]/DDR1_DQ[7] DDR0_DQSP[0] AT69 DDR_A_DQS#1 DDR_B_D24 AT33 DDR1_DQ[39]/DDR1_DQ[23] DDR1_DQSN[0]/DDR0_DQSN[2] AH65 DDR_A_DQS2
DDR_B_D9 AW35 DDR0_DQ[40]/DDR1_DQ[8] DDR0_DQSN[1] AT70 DDR_A_DQS1 DDR_B_D25 AU33 DDR1_DQ[40]/DDR1_DQ[24] DDR1_DQSP[0]/DDR0_DQSP[2] AG69 DDR_A_DQS#3
DDR_B_D10 AY33 DDR0_DQ[41]/DDR1_DQ[9] DDR0_DQSP[1] BA64 DDR_A_DQS#4 DDR_B_D26 AU30 DDR1_DQ[41]/DDR1_DQ[25] DDR1_DQSN[1]/DDR0_DQSN[3] AG70 DDR_A_DQS3
DDR_B_D11 AW33 DDR0_DQ[42]/DDR1_DQ[10] DDR0_DQSN[2]/DDR0_DQSN[4] AY64 DDR_A_DQS4 DDR_B_D27 AT30 DDR1_DQ[42]/DDR1_DQ[26] DDR1_DQSP[1]/DDR0_DQSP[3] AR66 DDR_A_DQS#6
DDR_B_D12 BB35 DDR0_DQ[43]/DDR1_DQ[11] DDR0_DQSP[2]/DDR0_DQSP[4] AY60 DDR_A_DQS#5 DDR_B_D28 AR33 DDR1_DQ[43]/DDR1_DQ[27] DDR1_DQSN[2]/DDR0_DQSN[6] AR65 DDR_A_DQS6
DDR_B_D13 BA35 DDR0_DQ[44]/DDR1_DQ[12] DDR0_DQSN[3]/DDR0_DQSN[5] BA60 DDR_A_DQS5 DDR_B_D29 AP33 DDR1_DQ[44]/DDR1_DQ[28] DDR1_DQSP[2]/DDR0_DQSP[6] AR61 DDR_A_DQS#7
DDR_B_D14 BA33 DDR0_DQ[45]/DDR1_DQ[13] DDR0_DQSP[3]/DDR0_DQSP[5] BA38 DDR_B_DQS#0 DDR_B_D30 AR30 DDR1_DQ[45]/DDR1_DQ[29] DDR1_DQSN[3]/DDR0_DQSN[7] AR60 DDR_A_DQS7
DDR_B_D15 BB33 DDR0_DQ[46]/DDR1_DQ[14] DDR0_DQSN[4]/DDR1_DQSN[0] AY38 DDR_B_DQS0 DDR_B_D31 AP30 DDR1_DQ[46]/DDR1_DQ[30] DDR1_DQSP[3]/DDR0_DQSP[7] AT38 DDR_B_DQS#2
DDR_B_D32 AY31 DDR0_DQ[47]/DDR1_DQ[15] DDR0_DQSP[4]/DDR1_DQSP[0] AY34 DDR_B_DQS#1 DDR_B_D48 AU27 DDR1_DQ[47]/DDR1_DQ[31] DDR1_DQSN[4]/DDR1_DQSN[2] AR38 DDR_B_DQS2
DDR_B_D33 AW31 DDR0_DQ[48]/DDR1_DQ[32] DDR0_DQSN[5]/DDR1_DQSN[1] BA34 DDR_B_DQS1 DDR_B_D49 AT27 DDR1_DQ[48] DDR1_DQSP[4]/DDR1_DQSP[2] AT32 DDR_B_DQS#3
DDR_B_D34 AY29 DDR0_DQ[49]/DDR1_DQ[33] DDR0_DQSP[5]/DDR1_DQSP[1] BA30 DDR_B_DQS#4 DDR_B_D50 AT25 DDR1_DQ[49] DDR1_DQSN[5]/DDR1_DQSN[3] AR32 DDR_B_DQS3
DDR_B_D35 AW29 DDR0_DQ[50]/DDR1_DQ[34] DDR0_DQSN[6]/DDR1_DQSN[4] AY30 DDR_B_DQS4 DDR_B_D51 AU25 DDR1_DQ[50] DDR1_DQSP[5]/DDR1_DQSP[3] AR25 DDR_B_DQS#6
DDR_B_D36 BB31 DDR0_DQ[51]/DDR1_DQ[35] DDR0_DQSP[6]/DDR1_DQSP[4] AY26 DDR_B_DQS#5 DDR_B_D52 AP27 DDR1_DQ[51] DDR1_DQSN[6] AR27 DDR_B_DQS6
DDR_B_D37 BA31 DDR0_DQ[52]/DDR1_DQ[36] DDR0_DQSN[7]/DDR1_DQSN[5] BA26 DDR_B_DQS5 DDR_B_D53 AN27 DDR1_DQ[52] DDR1_DQSP[6] AR22 DDR_B_DQS#7
DDR_B_D38 BA29 DDR0_DQ[53]/DDR1_DQ[37] DDR0_DQSP[7]/DDR1_DQSP[5] DDR_B_D54 AN25 DDR1_DQ[53] DDR1_DQSN[7] AR21 DDR_B_DQS7
DDR_B_D39 BB29 DDR0_DQ[54]/DDR1_DQ[38] AW50
DDR0_PAR,DDR0_ALERT# for DDR4 DDR_B_D55 AP25 DDR1_DQ[54] DDR1_DQSP[7]
DDR_B_D40 AY27 DDR0_DQ[55]/DDR1_DQ[39] DDR0_ALERT# AT52 PAD~D @ T260 DDR_B_D56 AT22 DDR1_DQ[55] AN43
DDR1_PAR,DDR1_ALERT# for DDR4
DDR_B_D41 AW27 DDR0_DQ[56]/DDR1_DQ[40] DDR0_PAR PAD~D @ T261 DDR_B_D57 AU22 DDR1_DQ[56] DDR1_ALERT# AP43 PAD~D @ T257
B DDR_B_D42 AY25 DDR0_DQ[57]/DDR1_DQ[41] AY67 DDR_B_D58 AU21 DDR1_DQ[57] DDR1_PAR AT13 PAD~D @ T258 B
DDR_B_D43 AW25 DDR0_DQ[58]/DDR1_DQ[42] DDR_VREF_CA AY68
+DDR_VREF_CA DDR_B_D59 AT21 DDR1_DQ[58] DRAM_RESET# AR18 SM_RCOMP0 PAD~D @ T259
DDR_B_D44 DDR0_DQ[59]/DDR1_DQ[43] DDR0_VREF_DQ +DDR_VREF_A_DQ DDR_B_D60 DDR1_DQ[59] DDR_RCOMP[0] SM_RCOMP1
BB27 DDR CH - A BA67 AN22 AT18
DDR_B_D45 DDR0_DQ[60]/DDR1_DQ[44] DDR1_VREF_DQ +DDR_VREF_B_DQ DDR_B_D61 DDR1_DQ[60] DDR CH - B DDR_RCOMP[1] SM_RCOMP2
BA27 AP22 AU18
DDR_B_D46 BA25 DDR0_DQ[61]/DDR1_DQ[45] AW67 DDR_VTT_CTRL DDR_B_D62 AP21 DDR1_DQ[61] DDR_RCOMP[2]
DDR_B_D47 BB25 DDR0_DQ[62]/DDR1_DQ[46] DDR_VTT_CNTL DDR_B_D63 AN21 DDR1_DQ[62]
DDR0_DQ[63]/DDR1_DQ[47] DDR1_DQ[63]

SKL-U_BGA1356 2 OF 20 SKL-U_BGA1356 3 OF 20

+1.2V_MEM LPDDR3 COMPENSATION SIGNALS

UD5
1 5 1 2 SM_RCOMP0 RC5 1 2 200_0402_1%
NC VCC @ CD115 0.1U_0201_10V6K
DDR_VTT_CTRL 2 SM_RCOMP1 RC6 1 2 80.6_0402_1%
A 4
3 Y 0.6V_DDR_VTT_ON <50> SM_RCOMP2 1 2 162_0402_1%
RC7
GND 1 2
+3.3V_RUN
74AUP1G07GW_TSSOP5 RD83 100K_0402_5%

CHECK
CAD Note:
0.6V_DDR_VTT_ON (control 0.6V power EN) Trace width=12~15 mil, Spacing=20 mils
Max trace length= 500 mil
A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
CPU (2/14)
Size Document Number R ev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
0.1
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-E112P
Date: Friday, April 22, 2016 Sheet 7 of 58
5 4 3 2 1
 5 4 3 2 1

+3.3V_RUN
SPI_MOSI= SPI_IO0
SPI_MISO= SPI_IO1
For Kirkwood
PCH EDS R0.7 p.235~236 SKL-U
UC1E CPU@

2
SPI - FLASH
SMBUS, SMLINK
PCH_SPI_CLK AV2 MEM_SMBCLK 6 1
PCH_SPI_D1 AW3 SPI0_CLK R7 MEM_SMBCLK DDR_XDP_WAN_SMBCLK <14>
CXDP@
RC10 1 2 1K_0402_1% PCH_SPI_D0 AV3 SPI0_MISO GPP_C0/SMBCLK R8 MEM_SMBDATA QC2A
<14> PCH_SPI_DO_XDP SPI0_MOSI GPP_C1/SMBDATA

5
RC11 1 2 1K_0402_1% PCH_SPI_D2 AW2 R10 PCH_SMB_ALERT# DMN65D8LDW-7_SOT363-6
<14> PCH_SPI_DO2_XDP CXDP@ PCH_SPI_D3 AU4 SPI0_IO2 GPP_C2/SMBALERT#
PCH_SPI_CS#0 AU3 SPI0_IO3 R9 SML0_SMBCLK MEM_SMBDATA 3 4
D PCH_SPI_CS#1 AU2 SPI0_CS0# GPP_C3/SML0CLK W2 SML0_SMBDATA DDR_XDP_WAN_SMBDAT <14> D
PCH_SPI_CS#2 AU1 SPI0_CS1# GPP_C4/SML0DATA W1 GPP_C5 QC2B
<39> PCH_SPI_CS#2 SPI0_CS2# GPP_C5/SML0ALERT# DMN65D8LDW-7_SOT363-6 +3.3V_RUN
RPC6 W3 SML1_SMBCLK
SPI - TOUCH GPP_C6/SML1CLK V3 SML1_SMBDATA SML1_SMBCLK <37>
1 8 TS_SPI_SI TS_SPI_CLK M2 GPP_C7/SML1DATA AM7 GPP_B23 SML1_SMBDATA <37> DDR_XDP_WAN_SMBDAT1 2
<31> TS_SPI_SI_R TS_SPI_SO TS_SPI_SO GPP_D1/SPI1_CLK GPP_B23/SML1ALERT#/PCHHOT#
2 7 M3 RC318 2.2K_0402_5%
<31> TS_SPI_SO_R TS_SPI_CLK TS_SPI_SI GPP_D2/SPI1_MISO DDR_XDP_WAN_SMBCLK1
3 6 J4 2
<31> TS_SPI_CLK_R TS_SPI_CS# GPP_D3/SPI1_MOSI
4 5 V1 RC319 2.2K_0402_5%
<31> TS_SPI_CS#_R GPP_D21/SPI1_IO2
V2
15_0804_8P4R_5% TS_SPI_CS# M1 GPP_D22/SPI1_IO3 +3.3V_ALW_PCH
LPC
GPP_D0/SPI1_CS# AY13 ESPI_IO0_R RC3661 2 15_0402_5%
GPP_A1/LAD0/ESPI_IO0 BA13 ESPI_IO1_R ESPI_IO0 <37,38> MEM_SMBCLK
RC3671 2 15_0402_5% 1 2
C LINK GPP_A2/LAD1/ESPI_IO1 BB13 ESPI_IO2_R ESPI_IO1 <37,38>
RC3681 2 15_0402_5% ESPI_IO2 <37,38> RC12 1K_0402_5%
G3 GPP_A3/LAD2/ESPI_IO2 AY12 ESPI_IO3_R RC3691 2 15_0402_5% MEM_SMBDATA 1 2
<34> PCH_CL_CLK1 G2 CL_CLK GPP_A4/LAD3/ESPI_IO3 BA12 ESPI_IO3 <37,38>
RC14 1K_0402_5%
<34> PCH_CL_DATA1 G1 CL_DATA GPP_A5/LFRAME#/ESPI_CS# BA11 ESPI_CS# <37,38> SML1_SMBCLK 1 2
<34> PCH_CL_RST1# CL_RST# GPP_A14/SUS_STAT#/ESPI_RESET# ESPI_RESET# <37>
+3.3V_1.8V_ESPI? SML1_SMBDATA
RC15 1K_0402_5%
LPC@ RC13 2 1 10K_0402_5% 1 2
LPC - 3.3V +3.3V_1.8V_ESPI
AW13 AW9 ESPI_CLK EMI@ RC16 1 2 15_0402_5% ESPI_CLK_5105 RC17 1K_0402_5%
ESPI - 1.8V <37> SIO_RCIN# GPP_A0/RCIN# GPP_A9/CLKOUT_LPC0/ESPI_CLK AY9 PCI_CLK_LPC1 ESPI_CLK_5105 <37,38> SML0_SMBCLK
@ RC22 1 2 22_0402_5% 1 2
AY11 GPP_A10/CLKOUT_LPC1 AW11 RC347 499_0402_1%
<37> ESPI_ALERT# GPP_A6/SERIRQ GPP_A8/CLKRUN# CLKRUN# <37> SML0_SMBDATA 1 2
RC21 2 1 8.2K_0402_1% RC348 499_0402_1%
+3.3V_1.8V_ESPI
SKL-U_BGA1356 5 OF 20 CHECK,LPC_CLK FOR DEBUG CARD?
Reserve

C C

RF Request
ESPI_CLK_5105 1 2 +1.8V_RUN
+1.8V?
@RF@ CC316 33P_0402_50V8J

CLKRUN# 1 2
LPC@ RC27 8.2K_0402_5%
SOFTWARE TAA SML0_SMBCLK 1 2
@RF@ CC318 33P_0402_50V8J
SML1_SMBCLK 1 2 +3.3V_ALW_PCH
@RF@ CC319 33P_0402_50V8J

RPC1 MEM_SMBCLK 1 2
@RF@ CC320 33P_0402_50V8J PCH_SMB_ALERT# 1 2
PCH_SPI_D0_R1 1 8 PCH_SPI_D0_0_R RC23 2.2K_0402_5%
+3.3V_SPI <39> PCH_SPI_D0_R1 PCH_SPI_CLK_R1 2 7 PCH_SPI_CLK_0_R
<39> PCH_SPI_CLK_R1 PCH_SPI_D1_R1 3 6 PCH_SPI_D1_0_R
PCH_SPI_CLK_1_R PCH_SPI_CLK_0_R <39> PCH_SPI_D1_R1 PCH_SPI_D3_R1 4 5 PCH_SPI_D3_0_R TLS CONFIDENTIALITY
2 1 PCH_SPI_D2_R1 Place close CPU side HIGH ENABLE
@ RC30 1K_0402_5% 33_0804_8P4R_5%
LOW(DEFAULT) DISABLE
33_0402_5%

33_0402_5%
1

2 1 PCH_SPI_D3_R1
@EMI@

@EMI@

@ RC31 1K_0402_5% WEAK INTERNAL 20K PD

RC28

RC29

2 1 PCH_SPI_D3_R1
@ RC316 1K_0402_5%
2

PCH_SPI_D3_R1 @ RC407 1 2 33_0402_5% PCH_SPI_D3_1_R +3.3V_ALW_PCH

33P_0402_50V8J

33P_0402_50V8J

PCH_SPI_CLK_R1 @ RC408 1 2 33_0402_5% PCH_SPI_CLK_1_R

03/02:follow Intel MOW_2015WW06 PCH_SPI_D0_R1 @ RC409 1 2 33_0402_5% PCH_SPI_D0_1_R
@EMI@

@EMI@
1

B PCH_SPI_D1_R1 @ RC410 1 2 33_0402_5% PCH_SPI_D1_1_R B

GPP_C5 1 2
CC7

CC8

ESPI@RC25 4.7K_0402_5%
2

ACES_50696-0200M-P01
22
21 GND_2
+3.3V_SPI GND_1 EC interface
CC9 2 1 PCH_SPI_CS#1_R1 20
HIGH ESPI
1 2 @RC32 0_0402_5% PCH_SPI_CS#1 19 20 LOW(DEFAULT) LPC
2 1 PCH_SPI_D0_R1 18 19 WEAK INTERNAL 20K PD
128Mb Flash ROM 0.1U_0201_10V6K RC33 0_0402_5% PCH_SPI_D0 17 18
UC5 2 1 PCH_SPI_D1_R1 16 17
PCH_SPI_CS#0_R1 RC37 1 2 0_0402_5% PCH_SPI_CS#0_R2 1 8 RC34 0_0402_5% PCH_SPI_D1 15 16
PCH_SPI_D1_0_R 2 /CS VCC 7 PCH_SPI_D3_0_R 2 1 PCH_SPI_CLK_R1 14 15
PCH_SPI_D2_R1 RC39 1 2 33_0402_5% PCH_SPI_D2_0_R 3 IO1 IO3 6 PCH_SPI_CLK_0_R RC35 0_0402_5% PCH_SPI_CLK 13 14 +3.3V_ALW_PCH
4 IO2 CLK 5 PCH_SPI_D0_0_R 2 1 PCH_SPI_CS#0_R1 12 13
GND IO0 RC36 0_0402_5% PCH_SPI_CS#0 11 12
W25Q128FVSIQ_SO8 2 1 PCH_SPI_D2_R1 10 11
RC38 0_0402_5% PCH_SPI_D2 9 10 GPP_B23 1 2
+3.3V_SPI 2 1 PCH_SPI_D3_R1 8 9 RC317 150K_0402_5%
RC40 0_0402_5% PCH_SPI_D3 7 8
@ CC10 6 7
+3.3V_SPI 6
1 2 5
128Mb Flash ROM +3.3V_ALW_PCH
4 5 EXI BOOT STALL BYPASS
0.1U_0201_10V6K 2 1 3 4
2 3 HIGH ENABLED
@ UC6 RC41 0_0402_5%
PCH_SPI_CS#1_R1 @ RC42 1 2 0_0402_5% PCH_SPI_CS#1_R2 1 8 1 2 LOW(DEFAULT) DIABLED
PCH_SPI_D1_1_R 2 /CS VCC 7 PCH_SPI_D3_1_R 1 WEAK INTERNAL PD
PCH_SPI_D2_R1 @ RC43 1 2 33_0402_5% PCH_SPI_D2_1_R 3 IO1 IO3 6 PCH_SPI_CLK_1_R JSPI1
4 IO2 CLK 5 PCH_SPI_D0_1_R CONN@
GND IO0
A W25Q128FVSIQ_SO8 A

ESPI LPC
RC39 33 ohm 15 ohm DELL CONFIDENTIAL/PROPRIETARY
RPC1 33 ohm 15 ohm Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
RC33,RC34,RC35, 0 ohm 25 ohm BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
CPU (3/14)
Size Document Number R ev
RC36,RC38,RC40 NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
0.1
Need check
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-E112P
Date: Monday, April 25, 2016 Sheet 8 of 58
5 4 3 2 1
 5 4 3 2 1

UC1F CPU@ SKL-U

+3.3V_RUN
LPSS ISH

AN8
ONE_DIMM# AP7 GPP_B15/GSPI0_CS# P2 MEM_INTERLEAVED
D AP8 GPP_B16/GSPI0_CLK GPP_D9 P3 D
3.3V_TS_EN <39> TPM_PIRQ# NRB_BIT GPP_B17/GSPI0_MISO GPP_D10 AR_DET#
2 1 AR7 P4
RC282 100K_0402_5% GPP_B18/GSPI0_MOSI GPP_D11 P1
AM5 GPP_D12
AN7 GPP_B19/GSPI1_CS# M4 ISH_I2C0_SDA
SIO_EXT_SCI# <37> SIO_EXT_SCI# GPP_B20/GSPI1_CLK GPP_D5/ISH_I2C0_SDA ISH_I2C0_SCL ISH_I2C0_SDA <46> +3.3V_RUN
2 1 AP5 N3
RC237 10K_0402_5%
<31> 3.3V_TS_EN GPP_B22 AN5 GPP_B21/GSPI1_MISO
GPP_B22/GSPI1_MOSI
GPP_D6/ISH_I2C0_SCL
N1 ISH_I2C1_SDA
ISH_I2C0_SCL <46>
Only for Kirkwood
2 1 LPSS_UART2_RXD 1 100K_0402_5%GPP_C8 GPP_D7/ISH_I2C1_SDA ISH_I2C1_SCL ISH_I2C1_SDA <46>
@ RC4052 AB1 N2
AB2 GPP_C8/UART0_RXD GPP_D8/ISH_I2C1_SCL ISH_I2C1_SCL <46> ISH_I2C0_SDA 1 2
@ RC402 49.9K_0402_1%
2 1 LPSS_UART2_TXD <38> SBIOS_TX W4 GPP_C9/UART0_TXD AD11 ISH_I2C2_SDA RC358 2.2K_0402_5%
@ RC403 49.9K_0402_1% AB3 GPP_C10/UART0_RTS# GPP_F10/I2C5_SDA/ISH_I2C2_SDA AD12 ISH_I2C2_SCL ISH_I2C2_SDA <34> WWAN ISH_I2C0_SCL 1 2
GPP_C11/UART0_CTS# GPP_F11/I2C5_SCL/ISH_I2C2_SCL ISH_I2C2_SCL <34>
RC359 2.2K_0402_5%
LPSS_UART2_RXD AD1 ISH_I2C1_SDA 1 2
LPSS_UART2_TXD AD2 GPP_C20/UART2_RXD U1
9/24: Reserve for embedded locat i on,r ef er I nt el PDG 0. 9 RC360 1K_0402_5%
AD3 GPP_C21/UART2_TXD GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA U2 ISH_UART0_RXD <34> ISH_I2C1_SCL 1 2
AD4 GPP_C22/UART2_RTS# GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL U3 ISH_UART0_TXD <34>
RC361 1K_0402_5%
GPP_C23/UART2_CTS# GPP_D15/ISH_UART0_RTS# U4 ISH_UART0_RTS# <34> WLAN ISH_I2C2_SDA 1 2
+3.3V_ALW_PCH GPP_D16/ISH_UART0_CTS#/SML0BALERT# ISH_UART0_CTS# <34>
RC363 1K_0402_5%
U7 AC1 ISH_I2C2_SCL 1 2
<31> TS_I2C_SDA U6 GPP_C16/I2C0_SDA GPP_C12/UART1_RXD/ISH_UART1_RXD AC2 SIO_EXT_WAKE# <37>
RC362 1K_0402_5%
<31> TS_I2C_SCL GPP_C17/I2C0_SCL GPP_C13/UART1_TXD/ISH_UART1_TXD AC3 RTD3_CIO_PWR_EN <24> LCD_CBL_DET# 1 2
2 1 SIO_EXT_WAKE# U8 GPP_C14/UART1_RTS#/ISH_UART1_RTS# AB4 LCD_CBL_DET# <31>
RC287 100K_0402_5%
<43> I2C1_SDA_TP U9 GPP_C18/I2C1_SDA GPP_C15/UART1_CTS#/ISH_UART1_CTS#
RC283 10K_0402_5%
2 1 LPSS_UART2_RXD <43> I2C1_SCK_TP GPP_C19/I2C1_SCL AY8 ISH_GP0_D
AH9 GPP_A18/ISH_GP0 BA8 ISH_GP1_D ISH_GP0_D <46>
RC330 49.9K_0402_1%
2 1 LPSS_UART2_TXD AH10 GPP_F4/I2C2_SDA GPP_A19/ISH_GP1 BB7 ISH_GP2_D ISH_GP1_D <46>
GPP_F5/I2C2_SCL GPP_A20/ISH_GP2 BA7 ISH_GP3_D ISH_GP2_D <46>
RC331 49.9K_0402_1%
AH11 GPP_A21/ISH_GP3 AY7 NB_MODE_D ISH_GP3_D <46>
AH12 GPP_F6/I2C3_SDA GPP_A22/ISH_GP4 AW7 LID_CL#_NB_C
GPP_F7/I2C3_SCL GPP_A23/ISH_GP5 AP13 LID_CL#_TAB_C RC5042 1 0_0402_5%
AF11 GPP_A12/BM_BUSY#/ISH_GP6 LID_CL#_NB_D <46>
RC5052 1 0_0402_5%
C AF12 GPP_F8/I2C4_SDA LID_CL#_TAB_D <46> C
GPP_F9/I2C4_SCL
GPP_A GROUP is +1.8V
SKL-U_BGA1356 6 OF 20 ISH_GP0 for Main Accelerometer (LCD Sesnor Board)
ISH_GP1 for 2nd Accelerometer (MB) ISH_GP0_D 1 2
ISH_GP2 for E-Compass (MB) @ RC365 10K_0402_5%
ISH_GP3 for ALS (LCD Sesnor Board) ISH_GP1_D 1 2
ISH_GP4 for EC5105 (Tablet/NB mode) @ RC364 10K_0402_5%
ISH_GP2_D 1 2
@ RC501 10K_0402_5%
+3.3V_RUN ISH_GP3_D 1 2
@ RC502 10K_0402_5%
+3.3V_RUN NB_MODE_D 1 2
2 1 NRB_BIT @ RC349 10K_0402_5%
+1.8V_PRIM
10K_0402_5%

@ RC186 4.7K_0402_5%
2
@ RC267

NB_MODE_D 2 1
NO REBOOT STRAP RC506 10K_0402_5%
+3.3V_ALW
HIGH No REBOOT
1

LOW(DEFAULT) REBOOT ENABLE ONE_DIMM# NB_MODE 2 1

Weak IPD @ RC507 10K_0402_5%
1
10K_0402_5%

1 2 NB_MODE_D
<37> NB_MODE
RC268

DZ106
RB751S40T1G_SOD523-2
2

B +3.3V_ALW_PCH B

DIMM Detect
2 1 GPP_B22
@ RC184 8.2K_0402_5%
HIGH 1 DIMM +3.3V_ALW_PCH +3.3V_ALW_PCH
LOW 2 DIMM

BOOT BIOS Dest i nat i on(Bi t 10

)
HIGH LPC
2

2
LOW(DEFAULT) SPI @ RC371 RC400 @
Internal 20k PD 10K_0402_5% 10K_0402_5%
1

1
MEM_INTERLEAVED AR_DET#
1

1
10K_0402_5% 10K_0402_5%
RC372 RC401
2

2
DIMM TYPE AR_DET#

HIGH Interleave HIGH NON AR

A A
LOW Non-Interleave LOW AR

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
CPU (4/14)
Size Document Number R ev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
0.1
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-E112P
Date: Friday, April 22, 2016 Sheet 9 of 58
5 4 3 2 1
 5 4 3 2 1

For AR, Kirkwood

UC1H CPU@ SKL-U

SSIC / USB3
PCIE/USB3/SATA
H8
USB3_1_RXN G8 USB3_PRX_DTX_N1 <41>
H13 USB3_1_RXP C13 USB3_PRX_DTX_P1 <41>
D <24> PCIE_PRX_DTX_N1 G13 PCIE1_RXN/USB3_5_RXN USB3_1_TXN D13 USB3_PTX_DRX_N1 <41> -----> Ext USB3 Port 1 Charge D
<24> PCIE_PRX_DTX_P1 B17 PCIE1_RXP/USB3_5_RXP USB3_1_TXP USB3_PTX_DRX_P1 <41>
<24> PCIE_PTX_DRX_N1 A17 PCIE1_TXN/USB3_5_TXN J6
<24> PCIE_PTX_DRX_P1 PCIE1_TXP/USB3_5_TXP USB3_2_RXN/SSIC_1_RXN H6 USB3_PRX_DTX_N2 <33>
G11 USB3_2_RXP/SSIC_1_RXP B13 USB3_PRX_DTX_P2 <33>
<24> PCIE_PRX_DTX_N2 F11 PCIE2_RXN/USB3_6_RXN USB3_2_TXN/SSIC_1_TXN A13 USB3_PTX_DRX_N2 <33> -----> M.2 3042(LTE)
<24> PCIE_PRX_DTX_P2 D16 PCIE2_RXP/USB3_6_RXP USB3_2_TXP/SSIC_1_TXP USB3_PTX_DRX_P2 <33>
<24> PCIE_PTX_DRX_N2 C16 PCIE2_TXN/USB3_6_TXN J10
<24> PCIE_PTX_DRX_P2 PCIE2_TXP/USB3_6_TXP USB3_3_RXN/SSIC_2_RXN H10 USB3_PRX_DTX_N3 <42>
AR -----> H16 USB3_3_RXP/SSIC_2_RXP B15 USB3_PRX_DTX_P3 <42>
<24> PCIE_PRX_DTX_N3 G16 PCIE3_RXN USB3_3_TXN/SSIC_2_TXN A15 USB3_PTX_DRX_N3 <42> -----> Ext USB3 Port 2
<24> PCIE_PRX_DTX_P3 D17 PCIE3_RXP USB3_3_TXP/SSIC_2_TXP USB3_PTX_DRX_P3 <42>
<24> PCIE_PTX_DRX_N3 C17 PCIE3_TXN E10
<24> PCIE_PTX_DRX_P3 PCIE3_TXP USB3_4_RXN F10 USB3_PRX_DTX_N4 <32>
G15 USB3_4_RXP C15 USB3_PRX_DTX_P4 <32> -----> Card Reader RTS5330
<24> PCIE_PRX_DTX_N4 F15 PCIE4_RXN USB3_4_TXN D15 USB3_PTX_DRX_N4 <32>
<24> PCIE_PRX_DTX_P4 B19 PCIE4_RXP USB3_4_TXP USB3_PTX_DRX_P4 <32>
<24> PCIE_PTX_DRX_N4 A19 PCIE4_TXN AB9
<24> PCIE_PTX_DRX_P4 PCIE4_TXP USB2N_1 AB10 USB20_N1 <41>
F16 USB2P_1 USB20_P1 <41> -----> Ext USB Port 1 Charge(RIGHT)
<34> PCIE_PRX_DTX_N5 E16 PCIE5_RXN AD6
<34> PCIE_PRX_DTX_P5 C19 PCIE5_RXP USB2N_2 AD7 USB20_N2 <42>
M.2 3030(WLAN) ---> <34> PCIE_PTX_DRX_N5 D19 PCIE5_TXN USB2P_2 USB20_P2 <42> -----> Ext USB Port 2(LEFT)
<34> PCIE_PTX_DRX_P5 PCIE5_TXP AH3
G18 USB2N_3 AJ3
<34> PCIE_PRX_DTX_N6 F18 PCIE6_RXN USB2P_3
<34> PCIE_PRX_DTX_P6 D20 PCIE6_RXP AD9
M.2 3030(WiGig) ---> <34> PCIE_PTX_DRX_N6 C20 PCIE6_TXN USB2N_4 AD10 USB20_N4 <34>
<34> PCIE_PTX_DRX_P6 PCIE6_TXP USB2P_4 USB20_P4 <34> -----> M2 3042(WWAN)
F20 AJ1
<33> PCIE_PRX_DTX_N7 E20 PCIE7_RXN/SATA0_RXN USB2N_5 AJ2 USB20_N5 <31>
<33> PCIE_PRX_DTX_P7 B21 PCIE7_RXP/SATA0_RXP
USB2
USB2P_5 USB20_P5 <31> -----> Camera
C <33> PCIE_PTX_DRX_N7 A21 PCIE7_TXN/SATA0_TXN AF6 C
M.2 3042(SATA Cache <33> PCIE_PTX_DRX_P7 PCIE7_TXP/SATA0_TXP USB2N_6 AF7 USB20_N6 <32>
or/HCA)---> G21 USB2P_6 USB20_P6 <32> -----> Card Reader RTS5330
<34> PCIE_PRX_DTX_N8 F21 PCIE8_RXN/SATA1A_RXN AH1
<34> PCIE_PRX_DTX_P8 D21 PCIE8_RXP/SATA1A_RXP USB2N_7 AH2 USB20_N7 <34>
<34> PCIE_PTX_DRX_N8 C21 PCIE8_TXN/SATA1A_TXN USB2P_7 USB20_P7 <34> -----> M.2 3030(BT)
<34> PCIE_PTX_DRX_P8 PCIE8_TXP/SATA1A_TXP AF8
E22 USB2N_8 AF9 USB20_N8 <31>
<40> PCIE_PRX_DTX_N9 E23 PCIE9_RXN USB2P_8 USB20_P8 <31> -----> LCD Touch
<40> PCIE_PRX_DTX_P9 B23 PCIE9_RXP AG1
<40> PCIE_PTX_DRX_N9 A23 PCIE9_TXN USB2N_9 AG2
<40> PCIE_PTX_DRX_P9 PCIE9_TXP USB2P_9
F25 AH7
<40> PCIE_PRX_DTX_N10 E25 PCIE10_RXN USB2N_10 AH8 USB20_N10 <39>
<40> PCIE_PRX_DTX_P10 D23 PCIE10_RXP USB2P_10 USB20_P10 <39> -----> USH +3.3V_ALW_PCH
<40> PCIE_PTX_DRX_N10 C23 PCIE10_TXN AB6 USBCOMP 1 2 113_0402_1%
RC44
<40> PCIE_PTX_DRX_P10 PCIE10_TXP USB2_COMP AG3 USB2_ID RC337 1 2 0_0402_5%
PCIE_RCOMPN F5 USB2_ID AG4 USB2_VBUSSENSE RC338 1 2 1K_0402_5% 10K_8P4R_5%
RC45 1 2 100_0402_1% PCIE_RCOMPP E5 PCIE_RCOMPN USB2_VBUSSENSE USB_OC1# 1 8
PCIE_RCOMPP A9 USB_OC3# 2 7
D56 GPP_E9/USB2_OC0# C9 USB_OC0# <41> USB_OC0# 3 6
<14> CPU_XDP_PRDY# D61 PROC_PRDY# GPP_E10/USB2_OC1# D9 USB_OC2# USB_OC1# <42> USB_OC2# 4 5
M2 2280 SSD ---> <14> CPU_XDP_PREQ# HDD_FALL_INT BB11 PROC_PREQ# GPP_E11/USB2_OC2# B9 USB_OC3# Reserve
GPP_A7/PIRQA# GPP_E12/USB2_OC3# RPC3
E28 J1
<40> PCIE_PRX_DTX_N11 E27 PCIE11_RXN/SATA1B_RXN GPP_E4/DEVSLP0 J2
<40> PCIE_PRX_DTX_P11 D24 PCIE11_RXP/SATA1B_RXP GPP_E5/DEVSLP1 J3 M3042_DEVSLP <34>
<40> PCIE_PTX_DRX_N11 C24 PCIE11_TXN/SATA1B_TXN GPP_E6/DEVSLP2 M2_DEVSLP <40>
<40> PCIE_PTX_DRX_P11 E30 PCIE11_TXP/SATA1B_TXP H2 HDD_DET#
<40> PCIE_PRX_DTX_N12 F30 PCIE12_RXN/SATA2_RXN GPP_E0/SATAXPCIE0/SATAGP0 H3 M3042_PCIE#_SATA
<40> PCIE_PRX_DTX_P12 A25 PCIE12_RXP/SATA2_RXP GPP_E1/SATAXPCIE1/SATAGP1 G4 m2280_PCIE_SATA# M3042_PCIE#_SATA <37>
NEED DOUBLE CHECK
<40> PCIE_PTX_DRX_N12 B25 PCIE12_TXN/SATA2_TXN GPP_E2/SATAXPCIE2/SATAGP2 m2280_PCIE_SATA# <40>
B <40> PCIE_PTX_DRX_P12 PCIE12_TXP/SATA2_TXP H1 B
SATALED#
GPP_E8/SATALED# SATALED# <34,40,44>

SKL-U_BGA1356 8 OF 20

+3.3V_RUN
10K_8P4R_5%
M2280_PCIE_SATA# 1 8
M3042_PCIE#_SATA 2 7
HDD_DET# 3 6
SATALED# 4 5

RPC4

1.8V?
+1.8V_RUN
HDD_FALL_INT 1 2
@ RC370 10K_0402_5%

12/17:INT1 is PP mode, depop RC370,double check.

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
CPU (5/14)
Size Document Number R ev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
0.1
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-E112P
Date: Friday, April 22, 2016 Sheet 10 of 58
5 4 3 2 1
 5 4 3 2 1

For UMA CONFIG CC21

1 2

15P_0402_50V8J

2
1M_0402_1%

3
4
RC46
UC1J CPU@ SKL_ULT
YC1
CLOCK SIGNALS 24MHZ_12PF_X3G024000DC1H

1
2
D42
<34> CLK_PCIE_N0 C42 CLKOUT_PCIE_N0 XTAL24_IN CC22
<34> CLK_PCIE_P0 CLKOUT_PCIE_P0
WWAN---> RF@RC373 2 1 0_0402_5% CLKREQ_PCIE#0_R AR10 XTAL24_OUT 1 2 XTAL24_OUT_R 1 2
<34> CLKREQ_PCIE#0 2 1 GPP_B5/SRCCLKREQ0#
+3.3V_RUN RC189 10K_0402_5% RC295 0_0402_5%
B42 For Skylake,YC1 24 MHz (50 Ohm ESR) 15P_0402_50V8J
D <34> CLK_PCIE_N1 A42 CLKOUT_PCIE_N1 F43 CLK_ITPXDP_N 1 2 0_0402_5% For Cannonlake,YC1 38.4 MHz (30 Ohm ESR) D
@ RC297
<34> CLK_PCIE_P1 CLKOUT_PCIE_P1 CLKOUT_ITPXDP_N CLK_ITPXDP_N_R <14>
WLAN---> RF@RC374 2 1 0_0402_5% CLKREQ_PCIE#1_R AT7 E43 CLK_ITPXDP_P @ RC298 1 2 0_0402_5% 546765_546765_2014WW48_Skylake_MOW_Rev_1_0
<34> CLKREQ_PCIE#1 2 1 GPP_B6/SRCCLKREQ1# CLKOUT_ITPXDP_P CLK_ITPXDP_P_R <14>
+3.3V_RUN RC47 10K_0402_5%
D41 BA17 SUSCLK
<34> CLK_PCIE_N2 C41 CLKOUT_PCIE_N2 GPD8/SUSCLK SUSCLK <34,40>
CC23
<34> CLK_PCIE_P2 CLKOUT_PCIE_P2
WIGIG---> RF@RC375 2 1 0_0402_5% CLKREQ_PCIE#2_R AT8 E37 XTAL24_IN PCH_RTCX1 1 2
<34> CLKREQ_PCIE#2 2 1 GPP_B7/SRCCLKREQ2# XTAL24_IN E35 XTAL24_OUT PCH_RTCX2
+3.3V_RUN RC50 10K_0402_5%
D40 XTAL24_OUT 15P_0402_50V8J
<40> CLK_PCIE_N3 C40 CLKOUT_PCIE_N3 E42 XCLK_BIASREF 1 2
<40> CLK_PCIE_P3 CLKOUT_PCIE_P3 XCLK_BIASREF +1.0V_CLK5

1
M.2 SDD---> RF@RC376 2 1 0_0402_5% CLKREQ_PCIE#3_R AT10 RC52 2.7K_0402_1%
<40> CLKREQ_PCIE#3 2 1 GPP_B8/SRCCLKREQ3# AM18 PCH_RTCX1 1 2
+3.3V_RUN RC59 10K_0402_5% For Skylake, pop RC52,depop RC324 RC54 YC2
B40 RTCX1 AM20 PCH_RTCX2 @ RC324 59_0402_1% For Cannonlake, pop RC324,depop RC52 32.768KHZ_12.5PF_9H03200042
CLKOUT_PCIE_N4 RTCX2 10M_0402_5%
A40 546765_546765_2014WW48_Skylake_MOW_Rev_1_0 ESR MAX=50k ohm

2
AU8 CLKOUT_PCIE_P4 AN18 SRTCRST# RC56 1 2 20K_0402_5%
LAN---> +RTC_CELL

1
GPP_B9/SRCCLKREQ4# SRTCRST# AM16 CC26
E40 RTCRST# CC24 1 2 1U_0402_6.3V6K 1 2 PCH_RTCX2_R 1 2
<24> CLK_PCIE_N5 E38 CLKOUT_PCIE_N5 RC296 0_0402_5%
<24> CLK_PCIE_P5 1 0_0402_5% CLKREQ_PCIE#5_RAU7 CLKOUT_PCIE_P5 PCH_RTCRST# <37>
AR ---> RF@RC378 2 12P_0402_50V8J
<24> CLKREQ_PCIE#5 GPP_B10/SRCCLKREQ5# PCH_RTCRST#
+3.3V_RUN RC190 2 1 10K_0402_5% RC57 1 2 20K_0402_5%

CC25 1 2 1U_0402_6.3V6K

SKL-U_BGA1356 10 OF 20

1 2 +3.3V_ALW_DSW
1 2 8/21 can change to 10K for merge to RP
PCH_PLTRST#
PCH_BATLOW# 1 2
SHORT PADS~D RC72 8.2K_0402_5%
1 2 @ CMOS1 AC_PRESENT 1 2
PCH_PLTRST#_EC <38>
RC244 0_0402_5% CMOS1 must take care short & touch risk on layout placement RC243 10K_0402_5%
C +3.3V_ALW_PCH +RTC_CELL C

PCH_PLTRST# 1 2
+3.3V_ALW_DSW PLTRST_TPM# <39> 1 2
@ RC60 0_0402_5% INTRUDER#
5

RC69 1M_0402_5%
1 PCH_PLTRST#_AND 1 2
P

2 1 LAN_WAKE# B 4 PCH_PLTRST#_AND RC325 0_0402_5% +3.3V_ALW_PCH

2 O PCH_PLTRST#_AND <24,31,34,39,40>
RC323 10K_0402_5%
A
G

1
UC7 MPHYP_PWR_EN 1 2
2 1 PCH_PCIE_WAKE# TC7SH08FU_SSOP5~D @ RC65 @ RC387 100K_0402_5%
3

RC67 1K_0402_5% 100K_0402_5% VRALERT# 1 2

@ RC73 10K_0402_5%
1 2
2

+1.0V_VCCST @ RC344 10K_0402_5%

2 1 VCCST_PWRGD +3.3V_ALW
RC71 1K_0402_5%
SIO_SLP_LAN# 1 2
+3.3V_ALW_PCH @ RC68 10K_0402_5%

2 1 ME_SUS_PWR_ACK
@ RC74 10K_0402_5% SUSCLK 1 2
10/6 depop, prevent singal step. @ RC48 1K_0402_5%

2 1 PCH_PWROK
@RC411 10K_0402_5% UC1K CPU@ SKL-U

SYSTEM POWER MANAGEMENT

AT11 SIO_SLP_S0#
GPP_B12/SLP_S0# AP15 SIO_SLP_S0# <17,52>
PCH_PLTRST# AN10 GPD4/SLP_S3# BA16 SIO_SLP_S3# <24,37,38>
SYS_RESET# B5 GPP_B13/PLTRST# GPD5/SLP_S4# AY16 SIO_SLP_S4# <17,37,50,53>
B PCH_RSMRST#_ANDAY17 SYS_RESET# GPD10/SLP_S5# SIO_SLP_S5# <37> B
<14,43> PCH_RSMRST#_AND RSMRST# AN15 JAPS1
H_CPUPWRGD_R@ RC77 1 2 1K_0402_5% H_CPUPWRGD A68 SLP_SUS# AW15 SIO_SLP_SUS# <17,37,45,51,52,53> 1
T9 @ PAD~D PROCPWRGD SLP_LAN# SIO_SLP_LAN# <37> +3.3V_ALW_PCH 1
RC78 1 2 60.4_0402_1% VCCST_PWRGD_CPU B65 BB17 SIO_SLP_S3# 2
<14,37,38> VCCST_PWRGD VCCST_PWRGD GPD9/SLP_WLAN# AN16 SIO_SLP_WLAN# <37,45> 3 2
GPD6/SLP_A# SIO_SLP_A# <37> +3.3V_ALW SIO_SLP_S5# 3
B6 4
<14,37> SYS_PWROK PCH_PWROK BA20 SYS_PWROK BA15 SIO_SLP_S4# 5 4
<54> PCH_PWROK BB20 PCH_PWROK GPD3/PWRBTN# AY15 SIO_PWRBTN# <14,37> SIO_SLP_A# 6 5
H_CPUPWRGD VCCST_PWRGD <38> PCH_DPWROK DSW_PWROK GPD1/ACPRESENT AU13 PCH_BATLOW# AC_PRESENT <37> 7 6
GPD0/BATLOW# +3.3V_ALW 7
AR13 8
<37> ME_SUS_PWR_ACK GPP_A13/SUSWARN#/SUSPWRDNACK PCH_RTCRST# 8
100P_0402_50V8J
ESD@ CC300

100P_0402_50V8J
ESD@ CC301

AP11 9
<37> SUSACK# GPP_A15/SUSACK# AU11 10 9
PME#
GPP_A11/PME# PAD~D @ T115 10
1

BB15 AP16 INTRUDER# 11

<37,38> PCH_PCIE_WAKE# AM15 WAKE# INTRUDER# <38,44> POWER_SW#_MB 12 11
<37> LAN_WAKE# AW17 GPD2/LAN_WAKE# AM10 MPHYP_PWR_EN SYS_RESET# 13 12
2

AT15 GPD11/LANPHYPC GPP_B11/EXT_PWR_GATE# AM11 VRALERT# 14 13

<31> 3.3V_CAM_EN# GPD7/RSVD GPP_B2/VRALERT# SIO_SLP_S0# 15 14
connect to VCCMPHYGTAON_1P0 enable pin 16 15
2 1 SKL-U_BGA1356 11 OF 20 17 16
RC311 10K_0402_5% SYS_RESET# 18 17
ESD Request:place near CPU side 18

0.1U_0402_25V6
@ESD@ CC302
19
20 GND
GND

1
1 2 +3.3V_RUN
RC215 RC290 0_0402_5%
CVILU_CF4218FH0R0-05-NH

2
10K_0402_5%

CONN@
POP NO Support Deep sleep
2

DE-POP Support Deep sleep +3.3V_RUN

@RC291

XDP_DBRESET#
PCH_DPWROK 1 2 PCH_RSMRST#_AND <14> XDP_DBRESET#
5

@ RC215 0_0402_5% ESD Request:place near CPU side

1

A +3.3V_RUN 1 A
P

B
1

SYS_RESET#_R 1 SYS_RESET#
0.01UF_0402_25V7K

100K_0402_1%

1 4 2
@ RC75 2 1 ME_RESET# 2 O RC224 1K_0402_5%
A
G
CC266

RC220

10K_0402_5% @ RC225 8.2K_0402_5% @ UC12

2 1 74AHC1G09GW_TSSOP5
DELL CONFIDENTIAL/PROPRIETARY
3

2 @ RC227 8.2K_0402_5%
2

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
if pop UC12, RC291 also need pop(74AHC1G09GW is OD output)
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
CPU (6/14)
Size Document Number R ev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
0.1
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-E112P
Date: Friday, April 22, 2016 Sheet 11 of 58
5 4 3 2 1
 5 4 3 2 1

+1.0V_VCCSTG

PCH_JTAG_TDI 1 2
RC81 51_0402_5%
PCH_JTAG_TDO 1 2
RC82 100_0402_1%
PCH_JTAG_TMS 1 2
UC1D CPU@ SKL-U RC130 51_0402_5%
CPU_XDP_TCLK 2 1 XDP_JTAGX
H_CATERR# D63 RC328 0_0402_5%
A54 CATERR#
D <37> PECI_EC 1 2 H_PROCHOT#_R C65 PECI D
<37,54,57> H_PROCHOT# PROCHOT# JTA G
RC84 499_0402_1% H_THERMTRIP# C63
<38> H_THERMTRIP# A65 THERMTRIP# B61 CPU_XDP_TCLK
SKTOCC# PROC_TCK D60 CPU_XDP_TDI CPU_XDP_TCLK <14>
CPU MISC PROC_TDI CPU_XDP_TDI <14>
C55 A61 CPU_XDP_TDO
<14> XDP_OBS0_R D55 BPM#[0] PROC_TDO C60 CPU_XDP_TMS CPU_XDP_TDO <14>
<14> XDP_OBS1_R XDP_OBS2_R B54 BPM#[1] PROC_TMS B59 CPU_XDP_TRST# CPU_XDP_TMS <14>
T10 @ PAD~D XDP_OBS3_R BPM#[2] PROC_TRST# CPU_XDP_TRST# <14>
C56 1 2
T11 @ PAD~D BPM#[3] PCH_JTAG_TCK
B56 @ RC86 51_0402_5%
+1.0V_VCCST A6 PCH_JTAG_TCK D59 PCH_JTAG_TDI PCH_JTAG_TCK <14>
<37> SIO_EXT_SMI# A7 GPP_E3/CPU_GP0 PCH_JTAG_TDI A56 PCH_JTAG_TDO PCH_JTAG_TDI <14>
2 1 H_CATERR# <31> TOUCH_SCREEN_PD# TOUCHPAD_INTR# BA5 GPP_E7/CPU_GP1 PCH_JTAG_TDO C59 PCH_JTAG_TMS PCH_JTAG_TDO <14>
<37,43> TOUCHPAD_INTR# AY5 GPP_B3/CPU_GP2 PCH_JTAG_TMS C61 CPU_XDP_TRST# PCH_JTAG_TMS <14>
@ RC79 49.9_0402_1%
2 1 H_THERMTRIP# <31> TOUCH_SCREEN_DET# GPP_B4/CPU_GP3 PCH_TRST# A59 XDP_JTAGX 1 2
CPU_POPIRCOMP AT16 JTAGX +1.0V_VCCSTG
RC80 1K_0402_5% @ RC87 1K_0402_5%
PCH_POPIRCOMP AU16 PROC_POPIRCOMP
+1.0V_VCCSTG EDRAM_OPIO_RCOMP H66 PCH_OPIRCOMP
EOPIO_RCOMP H65 OPCE_RCOMP
2 1 H_PROCHOT# OPC_RCOMP

1
49.9_0402_1%

49.9_0402_1%

49.9_0402_1%

49.9_0402_1%
RC83 1K_0402_5%

RC88

RC89

RC90

RC91
SKL-U_BGA1356 4 OF 20
Service Mode Switch:
+3.3V_RUN Add a switch to ME_FWP signal to unlock the ME region and

2
RPC5 allow the ent ir e r egi on of t he SPI f l ash to be updat ed us i ng FP.T
8 1 TOUCHPAD_INTR#
7 2 +3.3V_ALW_PCH
6 3 CAM_MIC_CBL_DET#
5 4 ME_FW_EC 2 1 ME_FWP
@ RC221 0_0402_5%

2
10K_8P4R_5% PT,ST pop RC222 and SW1; MP pop RC221
RC222
C 2 1 CONTACTLESS_DET# 1K_0402_5% C
RC278 10K_0402_5%
2 1 TOUCH_SCREEN_PD# TOUCH_SCREEN_PD# PU changes to Module Side SW1

1
@ RC272 10K_0402_5% (Not confirm yet?) 20160311
2 1 AUD_PWR_EN 1
RC279 10K_0402_5% 2
<37> ME_FW_EC
2 1 IR_CAM_DET# ME_FWP 3
RC345 100K_0402_5%
2 1 HOST_SD_WP# 4 G
RC292 10K_0402_5% 5
G
+3.3V_ALW_PCH ME_FWP PCH has internal 20K PD. SSAL120100_3P
2 1 SIO_EXT_SMI# (suspend power rail)
RC346 10K_0402_5% FLASH DESCRIPTOR SECURITY OVERRIDE
UC1G CPU@ SKL-U
2 1 KB_DET#
RC288 10K_0402_5%
LOW = ENABLE (DEFAULT) -->Pin3 & Pin2 short
AUDIO
HIGH = DISABLE (ME can update) -->Pin1 & Pin2 short
RC92 1 2 33_0402_5% HDA_SYNC BA22
<36> HDA_SYNC_R 1 2 HDA_BIT_CLK AY22 HDA_SYNC/I2S0_SFRM
EMI@ RC93 33_0402_5%
<36> HDA_BIT_CLK_R 1 2 HDA_SDOUT BB22 HDA_BLK/I2S0_SCLK
RC94 33_0402_5% SDIO/SDXC
<36> HDA_SDOUT_R ME_FWP RC223 1 2 BA21 HDA_SDO/I2S0_TXD
1K_0402_5%
<36> HDA_SDIN0 AY21 HDA_SDI0/I2S0_RXD AB11
1 2 33_0402_5% HDA_RST# AW22 HDA_SDI1/I2S1_RXD GPP_G0/SD_CMD AB13 CAM_MIC_CBL_DET# <31>
RC95
<36> HDA_RST#_R J5 HDA_RST#/I2S1_SCLK GPP_G1/SD_DATA0 AB12 TBT_CIO_PLUG_EVENT#
AY20 GPP_D23/I2S_MCLK GPP_G2/SD_DATA1 W12 TBT_CIO_PLUG_EVENT# <24>
AW20 I2S1_SFRM GPP_G3/SD_DATA2 W11 CONTACTLESS_DET# +3.3V_ALW_PCH
HDA_BIT_CLK_R I2S1_TXD GPP_G4/SD_DATA3 W10 HOST_SD_WP# CONTACTLESS_DET# <39>
AK7 GPP_G5/SD_CD# W8 AUD_PWR_EN HOST_SD_WP# <32> PANEL_SIZE_DET 1 2
AK6 GPP_F1/I2S2_SFRM GPP_G6/SD_CLK W7 SPK_DET# AUD_PWR_EN <36>
1 10K_0402_5% RC503
AK9 GPP_F0/I2S2_SCLK GPP_G7/SD_WP SPK_DET# <36>
B @EMI@ CC27 AK10 GPP_F2/I2S2_TXD BA9 B
GPP_F3/I2S2_RXD GPP_A17/SD_PWR_EN#/ISH_GP7 BB9
22P_0402_50V8J GPP_A16/SD_1P8_SEL
2
IR_CAM_DET# H5 AB7 SD_RCOMP RC96 1 2 200_0402_1%
<31> IR_CAM_DET# PANEL_SIZE_DET D7 GPP_D19/DMIC_CLK0 SD_RCOMP
<31> PANEL_SIZE_DET GPP_D20/DMIC_DATA0
Close to RC93
KB_DET# D8 AF13
<43> KB_DET# C8 GPP_D17/DMIC_CLK1 GPP_F23
GPP_D18/DMIC_DATA1
AW5
<36> SPKR GPP_B14/SPKR

SKL-U_BGA1356 7 OF 20
PCH_JTAG_TDO PCH_JTAG_TDI XDP_JTAGX H_THERMTRIP# H_PROCHOT#

0.1U_0402_25V6
@ESD@ CC303

0.1U_0402_25V6
@ESD@ CC304

0.1U_0402_25V6
@ESD@ CC305

0.1U_0402_25V6
@ESD@ CC312

0.1U_0402_25V6
@ESD@ CC310
1

1
2

2
+3.3V_ALW_PCH +3.3V_ALW_PCH

2 1 SPKR 2 1 HDA_SDOUT
@ RC183 8.2K_0402_5% @ RC187 4.7K_0402_5% ESD request,Place near CPU side.

A TOP SWAP STRAP Flash Descriptor Security override A

HIGH ENABLE HIGH DISABLE

LOW(DEFAULT) DISABLE LOW(DEFAULT) ENABLE
Internal 20k PD
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
CPU (7/14)
Size Document Number R ev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
0.1
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-E112P
Date: Friday, April 22, 2016 Sheet 12 of 58
5 4 3 2 1
 5 4 3 2 1

<14> CFG[0..19]

D D

CFG[2][5][6][7] for SKYLAKE-H CPU CFG strap pin

UC1S CPU@ SKL-U
UC1T SKL-U
RESERVED SIGNALS-1
2 1 CFG0 SPARE
@ RC113 10K_0402_1% CFG0 E68 BB68 1/5 2014WW52 MOW reserve to support
2 1 CFG1 B67 CFG[0] RSVD_TP_BB68 BB69 PAD~D @ T12 Cannonlake-U PCH compatibility AW69 F6
CFG2 D65 CFG[1] RSVD_TP_BB69 PAD~D @ T13 AW68 RSVD_AW69 RSVD_F6 E3
@ RC112 10K_0402_1% close UC1.U11/U12 and <400mil
2 1 CFG3 D67 CFG[2] AK13 AU56 RSVD_AW68 RSVD_E3 C11
CFG4 E70 CFG[3] RSVD_TP_AK13 AK12 PAD~D @ T14 +1.8V_PRIM +VCC_1P8 AW48 RSVD_AU56 RSVD_C11 B11
@ RC110 10K_0402_1%
C68 CFG[4] RSVD_TP_AK12 PAD~D @ T15 C7 RSVD_AW48 RSVD_B11 A11
CFG5
CFG6 D68 CFG[5] BB2 1 2 U12 RSVD_C7 RSVD_A11 D12
Stall reset sequence CFG7 C67 CFG[6] RSVD_BB2 BA3 @ RC313 0_0402_5% U11 RSVD_U12 RSVD_D12 C12
CFG[7] RSVD_BA3 RSVD_U11 RSVD_C12

1U_0402_6.3V6K
CFG8 F71 H11 F52
HIGH(DEFAULT) No stall(Normal Operat i on) CFG9 G69 CFG[8] 1 RSVD_H11 RSVD_F52
LOW stall CFG[9]

CC222
CFG10 F70 AU5
CFG11 G68 CFG[10] TP5 AT5 PAD~D @ T128
CFG12 H70 CFG[11] TP6 PAD~D @ T129 2 SKL-U_BGA1356 20 OF 20
CFG13 G71 CFG[12] @
CFG14 H69 CFG[13] D5
CFG15 G70 CFG[14] RSVD_D5 D4
CFG[15] RSVD_D4 B2
CFG16 E63 RSVD_B2 C2
CFG17 F63 CFG[16] RSVD_C2
CFG[17] B3
CFG18 E66 RSVD_B3 A3
CFG19 F66 CFG[18] RSVD_A3
C 2 1 CFG4 CFG[19] AW1 C
RC109 1K_0402_5% 2 1 CFG_RCOMP E60 RSVD_AW1
RC114 49.9_0402_1% CFG_RCOMP E1
2 1 ITP_PMODE E8 RSVD_E1 E2
+1.0V_PRIM_XDP ITP_PMODE RSVD_E2
RC115 1.5K_0402_5%
AY2 BA4
AY1 RSVD_AY2 RSVD_BA4 BB4
<14> ITP_PMODE RSVD_AY1 RSVD_BB4
eDP enable D1 A4
D3 RSVD_D1 RSVD_A4 C4
HIGH(DEFAULT) Disabled RSVD_D3 RSVD_C4
LOW Enabled K46 BB5
K45 RSVD_K46 TP4 PAD~D @ T130
RSVD_K45 A69
AL25 RSVD_A69 B69
AL27 RSVD_AL25 RSVD_B69
RSVD_AL27 AY3
C71 RSVD_AY3
B70 RSVD_C71 D71
RSVD_B70 RSVD_D71 C70
F60 RSVD_C70
RSVD_F60 C54
A52 RSVD_C54 D54
RSVD_A52 RSVD_D54
BA70 AY4
T16 @ PAD~D RSVD_TP_BA70 TP1 PAD~D @ T126
BA68 BB3
T17 @ PAD~D RSVD_TP_BA68 TP2 PAD~D @ T127
J71 AY71
J68 RSVD_J71 VSS_AY71 AR56
RSVD_J68 ZVM#
F65 AW71
ZVM# for SKYLAKE-U 2+3e
G65 VSS_F65 RSVD_TP_AW71 AW70 PAD~D @ T113
B VSS_G65 RSVD_TP_AW70 PAD~D @ T114 B
F61 AP56
E61 RSVD_F61 MSM# C64 1 2
MSM# for SKYLAKE-U 2+3e
RSVD_E61 PROC_SELECT# +1.0V_VCCST
@ RC120 100K_0402_5%

For Skylake , RC120 depop

SKL-U_BGA1356 19 OF 20 For Cannonlake, RC120 pop

546765_546765_2014WW48_Skylake_MOW_Rev_1_0

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
CPU (8/14)
Size Document Number R ev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
0.1
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-E112P
Date: Friday, April 22, 2016 Sheet 13 of 58
5 4 3 2 1
 5 4 3 2 1

+1.0V_PRIM +1.0V_PRIM_XDP

1 2 +1.0V_PRIM_XDP CXDP@
@ RC216 0_0603_1% CPU XDP XDP_PRSNT_PIN1 1
RC121
2 CFG3
0_0402_5%
<13> CFG[0..19]
1 2 +3.3V_RUN
@ RC122 0_0402_5%
+1.0V_PRIM_XDP JXDP1 +1.0V_PRIM_XDP CC30
1 2 2 1
<10> CPU_XDP_PREQ#
CPU_XDP_PREQ# 3 1 2 4 CFG17 UC8
CPU_XDP_PRDY# 5 3 4
0.1U_0201_10V6K

0.1U_0201_10V6K
6 CFG16 0.1U_0201_10V6K
<10> CPU_XDP_PRDY# 7 5 6
@ CC28

@ CC29
1 1 8 14
CFG0 9 7 8 10 CFG8 VCC
CFG1 11 9 10 12 CFG9 TDO_XDP 2 3 CPU_XDP_TDO <12>
13 11 12 14 1A 1B
D 2 2 CFG2 15 13 14 16 CFG10 D
CFG3 17 15 16 18 CFG11 1
19 17 18 20 1OE
CXDP@ RC239 1 2 0_0402_5% XDP_OBS0 21 19 20 22 CFG19 TDI_XDP 5 6 CPU_XDP_TDI <12>
<12> XDP_OBS0_R 1 2 0_0402_5% XDP_OBS1 23 21 22 24 CFG18 2A 2B
CXDP@ RC240
<12> XDP_OBS1_R 25 23 24 26
Place near CFG4 27 25 26 28 CFG12 4
JXDP1 CFG5 29 27 28 30 CFG13 2OE
RC5 need to close to JCPU1 31 29 30 32 XDP_TMS 9 8 CPU_XDP_TMS <12>
CFG6 33 31 32 34 CFG14 3A 3B
@ RC123 1 2 1K_0402_5% CFG7 35 33 34 36 CFG15
<11,37,38> VCCST_PWRGD 37 35 36 38 10
<11,43> PCH_RSMRST#_ANDCXDP@ RC1241 2 H_VCCST_PWRGD_XDP 39 37 38 40 3OE
41 39 40 42 CLK_ITPXDP_P_R <11> TRST#_XDP 12 11
1K_0402_5% CPU_XDP_TRST# <12>
FIVR_EN <11,37> SIO_PWRBTN# 43 41 42 CLK_ITPXDP_N_R <11> 4A 4B
@ RC2171 2 0_0402_5% 44
CFG0 @ RC1261 2 1K_0402_5% FIVR_EN_R 45 43 44 46 ITP_PMODE
RESET_OUT#_R 47 45 46 XDP_DBRESET# ITP_PMODE <13>
CXDP@ RC1281 2 0_0402_5% 48 XDP_DBRESET# <11> 13 7
<8> PCH_SPI_DO_XDP 49 47 48 <37> RUNPWROK 4OE GND
@ RC1291 2 0_0402_5% 50
<11,37> SYS_PWROK 51 49 50 52 TDO_XDP 15
<8> DDR_XDP_WAN_SMBDAT 53 51 52 54 TRST#_XDP GND PAD
<8> DDR_XDP_WAN_SMBCLK 55 53 54 56 TDI_XDP
<12> PCH_JTAG_TCK CPU_XDP_TCLK 57 55 56 58 XDP_TMS
<12> CPU_XDP_TCLK 74CBTLV3126BQ_DHVQFN14_2P5X3
59 57 58 60
61 59 60 PCH_SPI_DO2_XDP <8>
61
62 63
GND GND
E-T_6601K-Y61N-04L
CONN@ +1.0V_VCCSTG
+1.0VS_VCCIO
CPU_XDP_TMS 1 2
2 1 FIVR_EN_R RC131 51_0402_5%
C RC132 150_0402_5% +3.3V_ALW_PCH +3.3V_ALW_DSW CPU_XDP_TDI 1 2 C
+1.0V_VCCST RC134 51_0402_5%

1.5K_0402_5%
1.5K_0402_5%
CPU_XDP_TDO

CXDP@ RC133
1 2
2

2
FIVR_EN

@ RC241
2 1 RC135 100_0402_1%
@ RC218 150_0402_5%

2 1 FIVR_EN CPU_XDP_TRST# 1 2
@ RC219 10K_0402_5% Place near JXDP1.48 @ RC136 51_0402_5%
1

1
CPU_XDP_TCLK 1 2
XDP_DBRESET# SIO_PWRBTN# RC139 51_0402_5%
PCH_SPI_DO_XDP

0.1U_0402_25V6
CXDP@ CC32

0.1U_0402_25V6
RESET_OUT#_R

1
0.1U_0402_25V6

CC269
@
1
+3.3V_RUN Place near JXDP1.41
1

XDP_TMS
@ CC33

1 2
PCH_JTAG_TMS <12>

2
RC228 0_0402_5%

2
2 1 XDP_DBRESET# TDI_XDP 1 2
PCH_JTAG_TDI <12>
2

RC137 1K_0402_5% RC229 0_0402_5%

+1.0V_PRIM_XDP TDO_XDP 1 2
PCH_JTAG_TDO <12>
RC230 0_0402_5%

2 1 CPU_XDP_PREQ#
@ RC138 51_0402_5%
Place near JXDP1.47

TDO_XDP H_VCCST_PWRGD_XDP CPU_XDP_TRST#

B B

0.1U_0402_25V6
@ESD@ CC306

0.1U_0402_25V6
@ESD@ CC307

0.1U_0402_25V6
@ESD@ CC308
1

1
2

2
ESD request,Place near JXDP1 side. ESD request,Place near UC8 side.

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
CPU (9/14)
Size Document Number R ev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
0.1
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-E112P
Date: Friday, April 22, 2016 Sheet 14 of 58
5 4 3 2 1
 5 4 3 2 1

+VCC_CORE: 0.3~1.35V +VCC_CORE +VCC_CORE

PSC(Primary side cap) : Place as close to the package as possible
UC1L CPU@ SKL-U BSC(Backside cap) : Place on secondary side, underneath the package
CPU POWER 1 OF 4

A30 G32
A34 VCC_A30 VCC_G32 G33
Component placement order:
A39 VCC_A34 VCC_G33 G35 Package edge > 0402 caps > 0805 caps > Bulk caps >Power source
A44 VCC_A39 VCC_G35 G37
AK33 VCC_A44 VCC_G37 G38
AK35 VCC_AK33 VCC_G38 G40
AK37 VCC_AK35 VCC_G40 G42
AK38 VCC_AK37 VCC_G42 J30
D AK40 VCC_AK38 VCC_J30 J33 D
AL33 VCC_AK40 VCC_J33 J37
AL37 VCC_AL33 VCC_J37 J40
AL40 VCC_AL37 VCC_J40 K33 +VCC_CORE
AM32 VCC_AL40 VCC_K33 K35
AM33 VCC_AM32 VCC_K35 K37

100_0402_1%
VCC_AM33 VCC_K37

2
AM35 K38

RC140
AM37 VCC_AM35 VCC_K38 K40
AM38 VCC_AM37 VCC_K40 K42
G30 VCC_AM38 VCC_K42 K43
VCC_G30 VCC_K43

1
+VCC_CORE_G0 K32 E32 VCCSENSE
T122@ PAD~D RSVD_K32 VCC_SENSE VCCSENSE <54>
E33 VSSSENSE
+VCC_CORE_G1 AK32 VSS_SENSE VSSSENSE <54>
T123@ PAD~D RSVD_AK32

1
B63 H_CPU_SVIDALRT#

100_0402_1%
AB62 VIDALERT# A63 VIDSCLK
VCCOPC_AB62 VIDSCK VIDSCLK <54>

RC141
P62 D64 VIDSOUT
V62 VCCOPC_P62 VIDSOUT
VCCOPC_V62 G20

2
H63 VCCSTG_G20
VCC_OPC_1P8_H63
G61
Remove (not support 2+3e) VCC_OPC_1P8_G61
20160303 AC63
AE63 VCCOPC_SENSE
VSSOPC_SENSE +1.0V_VCCSTG_R 1 2
+1.0V_VCCSTG
AE62 @ RC143 0_0603_5%
AG62 VCCEOPIO
VCCEOPIO
AL63
AJ62 VCCEOPIO_SENSE
VSSEOPIO_SENSE
C C
RF Request
SKL-U_BGA1356 12 OF 20
VCCOPC,VCCOPC_1P8,VCCEOPIO for SKYLAKE-U 2+3e
(w/ on package cache) VIDSCLK 1 2
@RF@ CC321 33P_0402_50V8J

Place close CPU side

B B

+1.0V_VCCST
SVID ALERT
56_0402_1%
2

RC152

CAD Note: Place the PU resistors close to CPU

RC204 close to CPU 300 - 1500mils
1

2 1 H_CPU_SVIDALRT#
<54> VIDALERT_N
220_0402_5% RC153

+1.0V_VCCST
SVID DATA
2
100_0402_1%

CAD Note: Place the PU resistors close to CPU

RC157

RC208close to CPU 300 - 1500mils

1

A VIDSOUT A
<54> VIDSOUT

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
CPU (10/14)
Size Document Number R ev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
0.1
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-E112P
Date: Friday, April 22, 2016 Sheet 15 of 58
5 4 3 2 1
 5 4 3 2 1

+VCCGT: 0.3~1.35V
+VCCGTX : 0.3~1.35V

+VCC_GT +VCC_GT

UC1M CPU@ SKL-U

D CPU POWER 2 OF 4 D
N70
A48 VCCGT N71
A53 VCCGT VCCGT R63
A58 VCCGT VCCGT R64
A62 VCCGT VCCGT R65
A66 VCCGT VCCGT R66
AA63 VCCGT VCCGT R67
AA64 VCCGT VCCGT R68
AA66 VCCGT VCCGT R69
AA67 VCCGT VCCGT R70
AA69 VCCGT VCCGT R71
AA70 VCCGT VCCGT T62
AA71 VCCGT VCCGT U65
AC64 VCCGT VCCGT U68
AC65 VCCGT VCCGT U71
AC66 VCCGT VCCGT W63
AC67 VCCGT VCCGT W64
AC68 VCCGT VCCGT W65
AC69 VCCGT VCCGT W66
AC70 VCCGT VCCGT W67
AC71 VCCGT VCCGT W68
J43 VCCGT VCCGT W69
J45 VCCGT VCCGT W70
J46 VCCGT VCCGT W71
J48 VCCGT VCCGT Y62
J50 VCCGT VCCGT +VCC_GTUS
J52 VCCGT
J53 VCCGT AK42
J55 VCCGT VCCGTX_AK42 AK43
J56 VCCGT VCCGTX_AK43 AK45
J58 VCCGT VCCGTX_AK45 AK46
C J60 VCCGT VCCGTX_AK46 AK48 C
K48 VCCGT VCCGTX_AK48 AK50
K50 VCCGT VCCGTX_AK50 AK52
K52 VCCGT VCCGTX_AK52 AK53
K53 VCCGT VCCGTX_AK53 AK55
K55 VCCGT VCCGTX_AK55 AK56
K56 VCCGT VCCGTX_AK56 AK58
K58 VCCGT VCCGTX_AK58 AK60
K60 VCCGT VCCGTX_AK60 AK70
L62 VCCGT VCCGTX_AK70 AL43
L63 VCCGT VCCGTX_AL43 AL46
L64 VCCGT VCCGTX_AL46 AL50
L65 VCCGT VCCGTX_AL50 AL53
VCCGTX for SKYLAKE-U 2+3e
L66 VCCGT VCCGTX_AL53 AL56
L67 VCCGT VCCGTX_AL56 AL60
L68 VCCGT VCCGTX_AL60 AM48
+VCC_GT L69 VCCGT VCCGTX_AM48 AM50
L70 VCCGT VCCGTX_AM50 AM52
L71 VCCGT VCCGTX_AM52 AM53
M62 VCCGT VCCGTX_AM53 AM56
100_0402_1%

VCCGT VCCGTX_AM56
2

N63 AM58
RC161

N64 VCCGT VCCGTX_AM58 AU58

N66 VCCGT VCCGTX_AU58 AU63
N67 VCCGT VCCGTX_AU63 BB57
N69 VCCGT VCCGTX_BB57 BB66
1

VCCGT VCCGTX_BB66
VCC_GT_SENSE J70 AK62
<54> VCC_GT_SENSE VSS_GT_SENSE J69 VCCGT_SENSE VCCGTX_SENSE AL61
<54> VSS_GT_SENSE VSSGT_SENSE VSSGTX_SENSE
1

100_0402_1%

SKL-U_BGA1356 13 OF 20
B B
RC163
2

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
CPU (11/14)
Size Document Number R ev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
0.1
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-E112P
Date: Friday, April 22, 2016 Sheet 16 of 58
5 4 3 2 1
 5 4 3 2 1

+1.2V_MEM +VCC_SFR_OC

+VCCPLL_OC source 1 2
@ RZ119 0_0402_5%
+1.2V_MEM_CPUCLK +1.2V_MEM

UZ26
1 2 VDDQ: 8.45A 1
RC231 0_0402_5% +1.2V_MEM 2 1 2 VIN1
CZ102 1U_0402_6.3V6K VIN2
7 6 1 2
D PSC VIN thermal VOUT CZ103 0.1U_0201_10V6K D
3
+5V_ALW VBIAS

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M
1 2 4 5
<17,37,38,45,52> RUN_ON ON GND
1 1 1 1 @ RZ120 0_0402_5%
CC176

CC177

CC178

CC179
+3.3V_ALW TPS22961DNYR_WSON8
+1.0VS_VCCIO @ CZ104
2 2 2 2 UC1N CPU@ SKL-U 1 2
CPU POWER 3 OF 4

5
0.1U_0402_10V7K
AU23 AK28 1

P
AU28 VDDQ_AU23 VCCIO AK30 <11,37,45,51,52,53> SIO_SLP_SUS# B 4
PSC AU35 VDDQ_AU28 VCCIO AL30 2 O
VDDQ_AU35 VCCIO <11,17,37,50,53> SIO_SLP_S4# A

G
AU42 AL42
BB23 VDDQ_AU42 VCCIO AM28 UZ34

3
VDDQ_BB23 VCCIO
22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M BB32 AM30

1 1 1 TC7SH08FU_SSOP5~D
VDDQ_BB32 VCCIO +VCC_SA
CC294

CC295

CC296 BB41 AM42

+1.2V_MEM_CPUCLK BB47 VDDQ_BB41 VCCIO
BB51 VDDQ_BB47 AK23
2 2 2 VDDQ_BB51 VCCSA AK25
PSC VCCSA G23
AM40 VCCSA G25
VDDQC VCCSA G27
VCCSA +1.0VS_VCCIO
10U_0402_6.3V6M

A18 G28
VCCST VCCSA J22
1 VCCSA
CC297

A22 J23
VCCSTG_A22 VCCSA J27

100_0402_1%
VCCSA

2
AL23 K23
2 VCCPLL_OC VCCSA K25

RC165
+1.0V_VCCST K20 VCCSA K27
K21 VCCPLL_K20 VCCSA K28 +1.0VS_VCCIO
C PSC VCCPLL_K21 VCCSA K30 C

1
VCCSA
AM23 VCCIO_SENSE
VCCIO_SENSE AM22 VSSIO_SENSE VCCIO_SENSE <52> PSC
+1.0V_VCCSTG VSSIO_SENSE VSSIO_SENSE <52>
1U_0402_6.3V6K

1
H21
BSC VSSSA_SENSE
CC195

H20
VCCSA_SENSE

1
100_0402_1%

100_0402_1%

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
2 1 1 1 1

RC166

RC167

CC252

CC253

CC250

CC251
SKL-U_BGA1356 14 OF 20
+VCC_SFR_OC
1U_0402_6.3V6K

1 1 2
+VCC_SA 2 2 2 2
CC199

RC168 100_0402_1%

2
+1.0V_VCCST

2@ PSC
1U_0402_6.3V6K

1U_0402_6.3V6K
2.2P_0402_50V8C

1 1
1 VSA_SEN- <54>
CC288

RF@ CC322

VSA_SEN+ <54>
CC202

S0 S0Ix S3
2 2
2
SIO_SLP_S0# HIGH LOW LOW

SIO_SLP_S3# HIGH HIGH LOW

RF Request
AND HIGH LOW LOW

B B

+1.0V_VCCST source +1.0V_VCCSTG source

+1.0V_VCCSTG +1.0V_VCCST

1 2
@ RZ151 0_0603_5%
pop option with UZ19

1
+1.0V_PRIM
PJP2
UZ19 PAD-OPEN1x1m
+1.0V_PRIM PJP1 2 1 1
UZ21 2 1 CZ105 1U_0402_6.3V6K 2 VIN1
+1.0V_VCCST VIN2
2 1 1

2
CZ100 1U_0402_6.3V6K 2 VIN1 +5V_ALW 7 6 +1.0V_VCCSTG_C1 2
VIN2 PAD-OPEN1x1m VIN thermal VOUT CZ106 0.1U_0201_10V6K
+5V_ALW 7 6 +1.0V_VCCST_C 1 2 3
VIN thermal VOUT CZ101 0.1U_0201_10V6K VBIAS
3 +3.3V_ALW 4 5
VBIAS ON GND
4 5
<11,17,37,50,53> SIO_SLP_S4# ON GND TPS22961DNYR_WSON8
4.4mohm/6A

5
TPS22961DNYR_WSON8
1 TR=12.5us@Vin=1.05V

P
<11,52> SIO_SLP_S0# B 4
4.4mohm/6A 2 O
TR=12.5us@Vin=1.05V <17,37,38,45,52> RUN_ON
UZ35 A G
TC7SH08FU_SSOP5~D
3

A A

@ RZ320 1 2 0_0402_5%
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
CPU (12/14)
Size Document Number R ev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
0.1
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-E112P
Date: Friday, April 22, 2016 Sheet 17 of 58
5 4 3 2 1
 5 4 3 2 1

close UC1.AL1 and <120mil +1.0V_MPHYGT

+1.0V_PRIM
+1.0V_MPHYAON +1.0V_PRIM
+1.0VO_DSW +1.0V_PRIM_CORE
close UC1.K17 and <120mil close UC1.AB19 and <400mil
PCH PWR close UC1.Y16 and <400mil +1.0V_SRAM

+3.3V_PGPPB RC309 1 2 0_0603_5%

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
1 1 1 1 close UC1.AG15 and <120mil
+3.3V_PGPPC +3.3V_PGPPE

@ CC205

@ CC206
+1.0V_APLLEBB

CC203

CC204

1U_0402_6.3V6K
1

@ CC265
+1.0V_MPHYAON UC1O CPU@ SKL-U close UC1.T16 and <400mil
2 2 2 2

1U_0402_6.3V6K

1U_0402_6.3V6K
1 1 RC310 1 2 0_0603_5%
CPU POWER 4 OF 4

@ CC207

@ CC208
RC299 1 2 0_0603_5%
D AB19 Must be +1.8V 2 D
AB20 VCCPRIM_1P0 AK15
VCCPRIM_1P0 VCCPGPPA +3.3V_1.8V_PGPPA 2 2
+1.0V_CLK6 P18 AG15
VCCPRIM_1P0 VCCPGPPB Y16 +3.3V_1.8V_PGPPG
close UC1.AF18 and <400mil VCCPGPPC
RC300 1 2 0_0402_5% AF18 Y15 close UC1.AD15 and <400mil
VCCPRIM_CORE VCCPGPPD +3.3V_PGPPD
AF19 T16
VCCPRIM_CORE VCCPGPPE

1U_0402_6.3V6K
V20 AF16 1
VCCPRIM_CORE VCCPGPPF +1.8V_PGPPF +3.3V_ALW_PCH

CC326
+1.0V_DTS V21 AD15
VCCPRIM_CORE VCCPGPPG +3.3V_1.8V_PGPPG
RC301 1 2 0_0402_5% AL1 V19
DCPDSW_1P0 VCCPRIM_3P3_V19 2
+1.8V_PRIM

1U_0402_6.3V6K
K17 T1 1
VCCMPHYAON_1P0 VCCPRIM_1P0_T1 +1.0V_DTS

@ CC209
+1.0V_CLK1 L1
VCCMPHYAON_1P0 AA1
VCCATS_1P8 close UC1.AA1 and <400mil
RC302 1 2 0_0402_5% +1.0V_MPHYGT N15
VCCMPHYGT_1P0_N15 +RTC_CELL 2

1U_0402_6.3V6K
N16 AK17 1
VCCMPHYGT_1P0_N16 VCCRTCPRIM_3P3 +3.3V_ALW_PCH
close UC1.N15 and CC210 <400mil, CC211 <120mil N17 close UC1.V19 and <120mil
VCCMPHYGT_1P0_N17

CC212
+1.0V_CLK3 P15 AK19
P16 VCCMPHYGT_1P0_P15 VCCRTC_AK19 BB14
VCCMPHYGT_1P0_P16 VCCRTC_BB14 close UC1.AK19 and <120mil 2

47U_0805_6.3V6M

1U_0402_6.3V6K

0.1U_0201_10V6K

1U_0402_6.3V6K
RC303 1 2 0_0402_5% 1 1 1 1

@ CC210
K15 BB10 +DCPRTC
+1.0V_AMPHYPLL VCCAMPHYPLL_1P0 DCPRTC

CC211

CC270

CC213
L15 close UC1.BB10 and <120mil
VCCAMPHYPLL_1P0

0.1U_0201_10V6K
A14 1
2 2 VCCCLK1 +1.0V_CLK1 2 2
V15
+1.0V_APLL VCCAPLL_1P0

CC214
K19
+1.8V_PRIM VCCCLK2 +1.0V_CLK2
+1.8V_PGPPF AB17
+1.0V_PRIM VCCPRIM_1P0_AB17 2
Y18 L21
VCCPRIM_1P0_Y18 VCCCLK3 +1.0V_CLK3
RC304 1 2 0_0402_5%
AD17 N20
+3.3V_ALW_DSW VCCDSW_3P3_AD17 VCCCLK4 +1.0V_CLK4
AD18 RF Request
+3.3V_1.8V_PGPPG AJ17 VCCDSW_3P3_AD18 L19 +1.0V_CLK6
VCCDSW_3P3_AJ17 VCCCLK5 +1.0V_CLK5
C @ RC234 1 2 0_0402_5% AJ19 A10 +1.0V_APLL +3.3V_VCCHDA +1.0V_APLLEBB C
+3.3V_VCCHDA VCCHDA VCCCLK6
close UC1.A10 and <120mil
+1.0V_SRAM

1U_0402_6.3V6K
AJ16 AN11 CORE_VID0 <52> 1
+3.3V_ALW_PCH +3.3V_SPI VCCSPI GPP_B0/CORE_VID0

@ CC216
AN13 CORE_VID1 <52>
AF20 GPP_B1/CORE_VID1
close UC1.AF20 and <400mil VCCSRAM_1P0

2.2P_0402_50V8C

2.2P_0402_50V8C

2.2P_0402_50V8C
RC235 1 2 0_0402_5% AF21 1 1 1
+3.3V_ALW_PCH VCCSRAM_1P0 2
1U_0402_6.3V6K

T19
1 VCCSRAM_1P0 Take care!!! Note1 on Page 19
@ CC217

RF@ CC323

RF@ CC324

RF@ CC325
T20
+3.3V_1.8V_PGPPA +1.0V_PRIM VCCSRAM_1P0
AJ21 2 2 2
LPC@ RC211 1 2 0_0402_5% 2 +1.0V_APLLEBB VCCPRIM_3P3_AJ21
AK20
+3.3V_1.8V_ESPI VCCPRIM_1P0_AK20
+1.8V_PRIM N18
PJP4 VCCAPLLEBB
1U_0402_6.3V6K

ESPI@ RC212 1 2 0_0402_5% 1 2 1 close UC1.N18 and <120mil

SKL-U_BGA1356 15 OF 20
CC218

PAD-OPEN1x1m
+3.3V_ALW_PCH +3.3V_PGPPB
2
RC305 1 2 0_0402_5% Must be +1.8V for eSPI I/F
+3.3V_PGPPC

RC306 1 2 0_0402_5%
+1.0V_MPHYGT +1.0V_AMPHYPLL +1.0V_PRIM +1.0V_CLK2 +1.0V_PRIM +1.0V_CLK5 +3.3V_ALW_PCH
close UC1.K15, UC1.L15 and <100mil close UC1.AK17 and <120mil
+3.3V_PGPPD
RC169 1 2 0_0603_5% RC170 1 2 0_0402_5% RC171 1 2 0_0402_5%
RC307 1 2 0_0402_5% close UC1.K15 and <120mil

47U_0805_6.3V6M

47U_0805_6.3V6M
0.1U_0201_10V6K

1U_0402_6.3V6K

0.1U_0201_10V6K

1U_0402_6.3V6K
1 1 1 close UC1.L19 and <100mil 1 1 1
B B

@ CC220

@ CC221

CC223
+3.3V_PGPPE
@ CC281

@ CC264

CC224
2 2
close UC1.K19 and <100mil 2 2 2 2
RC308 1 2 0_0402_5%

8/28 schematic review

+1.0V_PRIM +1.0V_MPHYGT

+3.3V_ALW_PCH +1.0V_PRIM
+1.0V_APLL
+1.0V_PRIM +1.0V_CLK4
+1.0V_MPHYGT source 1
PJP3
2

+3.3V_VCCHDA PAD-OPEN1x3m

LC1 1 2 BLM15GA750SN1D_2P LC2 1 2 BLM15GA750SN1D_2P RC173 1 2 0_0402_5% Pop PJP35 & Depop UZ20/RZ83/CZ84
0.1U_0201_10V6K

0.1U_0201_10V6K
47U_0805_6.3V6M

47U_0805_6.3V6M
1U_0402_6.3V6K

1 1 1 1 close UC1.N20 and <100mil 1

@ CC215

CC313

@ CC225

CC314

@ CC226

2 2 2 2 2

close UC1.AJ19 and <400mil close UC1.V15 and <100mil

+3.3V_ALW +3.3V_ALW_DSW

A RC214 1 2 0_0402_5% A
22U_0603_6.3V6M
@ CC279

22U_0603_6.3V6M
@ CC280

1 1
DELL CONFIDENTIAL/PROPRIETARY
2 2
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
CPU (13/14)
Size Document Number R ev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
0.1
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-E112P
Date: Friday, April 22, 2016 Sheet 18 of 58
5 4 3 2 1
 5 4 3 2 1

Note1: VCCPRIM_CORE Implementat i on wit h PC H C ORE_VI D Rec o mmendat i on

CPU@ CPU@
UC1P SKL-U UC1Q SKL-U CPU@ R1: PR408,PR411 ; R2: PR417,PR418 ; R3,PR419,PR420 ; R4: PR423 ; R5: PR424
UC1R SKL-U
GND 1 OF 3 GND 2 OF 3
GND 3 OF 3
A5 AL65 AT63 BA49 F8 L18
A67 VSS VSS AL66 AT68 VSS VSS BA53 G10 VSS VSS L2
A70 VSS VSS AM13 AT71 VSS VSS BA57 G22 VSS VSS L20
AA2 VSS VSS AM21 AU10 VSS VSS BA6 G43 VSS VSS L4
AA4 VSS VSS AM25 AU15 VSS VSS BA62 G45 VSS VSS L8
D AA65 VSS VSS AM27 AU20 VSS VSS BA66 G48 VSS VSS N10 D
AA68 VSS VSS AM43 AU32 VSS VSS BA71 G5 VSS VSS N13
AB15 VSS VSS AM45 AU38 VSS VSS BB18 G52 VSS VSS N19
AB16 VSS VSS AM46 AV1 VSS VSS BB26 G55 VSS VSS N21
AB18 VSS VSS AM55 AV68 VSS VSS BB30 G58 VSS VSS N6
AB21 VSS VSS AM60 AV69 VSS VSS BB34 G6 VSS VSS N65
AB8 VSS VSS AM61 AV70 VSS VSS BB38 G60 VSS VSS N68
AD13 VSS VSS AM68 AV71 VSS VSS BB43 G63 VSS VSS P17
AD16 VSS VSS AM71 AW10 VSS VSS BB55 G66 VSS VSS P19
AD19 VSS VSS AM8 AW12 VSS VSS BB6 H15 VSS VSS P20
AD20 VSS VSS AN20 AW14 VSS VSS BB60 H18 VSS VSS P21
AD21 VSS VSS AN23 AW16 VSS VSS BB64 H71 VSS VSS R13
AD62 VSS VSS AN28 AW18 VSS VSS BB67 J11 VSS VSS R6
AD8 VSS VSS AN30 AW21 VSS VSS BB70 J13 VSS VSS T15
AE64 VSS VSS AN32 AW23 VSS VSS C1 J25 VSS VSS T17
AE65 VSS VSS AN33 AW26 VSS VSS C25 J28 VSS VSS T18
AE66 VSS VSS AN35 AW28 VSS VSS C5 J32 VSS VSS T2
AE67 VSS VSS AN37 AW30 VSS VSS D10 J35 VSS VSS T21
AE68 VSS VSS AN38 AW32 VSS VSS D11 J38 VSS VSS T4
AE69 VSS VSS AN40 AW34 VSS VSS D14 J42 VSS VSS U10
AF1 VSS VSS AN42 AW36 VSS VSS D18 J8 VSS VSS U63
AF10 VSS VSS AN58 AW38 VSS VSS D22 K16 VSS VSS U64
AF15 VSS VSS AN63 AW41 VSS VSS D25 K18 VSS VSS U66
AF17 VSS VSS AP10 AW43 VSS VSS D26 K22 VSS VSS U67
AF2 VSS VSS AP18 AW45 VSS VSS D30 K61 VSS VSS U69
AF4 VSS VSS AP20 AW47 VSS VSS D34 K63 VSS VSS U70
AF63 VSS VSS AP23 AW49 VSS VSS D39 K64 VSS VSS V16
AG16 VSS VSS AP28 AW51 VSS VSS D44 K65 VSS VSS V17
AG17 VSS VSS AP32 AW53 VSS VSS D45 K66 VSS VSS V18
AG18 VSS VSS AP35 AW55 VSS VSS D47 K67 VSS VSS W13
AG19 VSS VSS AP38 AW57 VSS VSS D48 K68 VSS VSS W6
AG20 VSS VSS AP42 AW6 VSS VSS D53 K70 VSS VSS W9
C AG21 VSS VSS AP58 AW60 VSS VSS D58 K71 VSS VSS Y17 C
AG71 VSS VSS AP63 AW62 VSS VSS D6 L11 VSS VSS Y19
AH13 VSS VSS AP68 AW64 VSS VSS D62 L16 VSS VSS Y20
AH6 VSS VSS AP70 AW66 VSS VSS D66 L17 VSS VSS Y21
AH63 VSS VSS AR11 AW8 VSS VSS D69 VSS VSS
AH64 VSS VSS AR15 AY66 VSS VSS E11
AH67 VSS VSS AR16 B10 VSS VSS E15
AJ15 VSS VSS AR20 B14 VSS VSS E18
AJ18 VSS VSS AR23 B18 VSS VSS E21 SKL-U_BGA1356 18 OF 20
AJ20 VSS VSS AR28 B22 VSS VSS E46
AJ4 VSS VSS AR35 B30 VSS VSS E50
AK11 VSS VSS AR42 B34 VSS VSS E53
AK16 VSS VSS AR43 B39 VSS VSS E56
AK18 VSS VSS AR45 B44 VSS VSS E6
AK21 VSS VSS AR46 B48 VSS VSS E65
AK22 VSS VSS AR48 B53 VSS VSS E71
AK27 VSS VSS AR5 B58 VSS VSS F1
AK63 VSS VSS AR50 B62 VSS VSS F13
AK68 VSS VSS AR52 B66 VSS VSS F2
AK69 VSS VSS AR53 B71 VSS VSS F22
AK8 VSS VSS AR55 BA1 VSS VSS F23
AL2 VSS VSS AR58 BA10 VSS VSS F27
AL28 VSS VSS AR63 BA14 VSS VSS F28
AL32 VSS VSS AR8 BA18 VSS VSS F32
AL35 VSS VSS AT2 BA2 VSS VSS F33
AL38 VSS VSS AT20 BA23 VSS VSS F35
AL4 VSS VSS AT23 BA28 VSS VSS F37
AL45 VSS VSS AT28 BA32 VSS VSS F38
AL48 VSS VSS AT35 BA36 VSS VSS F4
AL52 VSS VSS AT4 F68 VSS VSS F40
AL55 VSS VSS AT42 BA45 VSS VSS F42
AL58 VSS VSS AT56 VSS VSS BA41
B AL64 VSS VSS AT58 VSS B
VSS VSS

SKL-U_BGA1356 16 OF 20 SKL-U_BGA1356 17 OF 20

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
CPU (14/14)
Size Document Number R ev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
0.1
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-E112P
Date: Friday, April 22, 2016 Sheet 19 of 58
5 4 3 2 1
 5 4 3 2 1

UD1 UD2
For LPDDR3
A3 P9 DDR_A_D3 A3 P9 DDR_A_D37 +0.6V_DDR_VTT
+1.8V_MEM VDD1 DQ0 DDR_A_D7 +1.8V_MEM VDD1 DQ0 DDR_A_D36
A4 N9 A4 N9
A5 VDD1 DQ1 N10 DDR_A_D5 A5 VDD1 DQ1 N10 DDR_A_D38 DDR_A_CAA0 RD1 2 1 68_0402_1%
A6 VDD1 DQ2 N11 DDR_A_D2 A6 VDD1 DQ2 N11 DDR_A_D34 DDR_A_CAA1 RD2 2 1 68_0402_1%
A10 VDD1 DQ3 M8 DDR_A_D0 A10 VDD1 DQ3 M8 DDR_A_D32 DDR_A_CAA2 RD3 2 1 68_0402_1%
U3 VDD1 DQ4 M9 DDR_A_D1 U3 VDD1 DQ4 M9 DDR_A_D39 DDR_A_CAA3 RD4 2 1 68_0402_1%
U4 VDD1 DQ5 M10 DDR_A_D4 U4 VDD1 DQ5 M10 DDR_A_D33 DDR_A_CAA4 2 1 <7> DDR_A_DQS#[0..7]
RD5 68_0402_1%
U5 VDD1 DQ6 M11 DDR_A_D6 U5 VDD1 DQ6 M11 DDR_A_D35 DDR_A_CAA5 RD6 2 1 68_0402_1%
VDD1 DQ7 DDR_A_D26 VDD1 DQ7 DDR_A_D42 DDR_A_CAA6 <7> DDR_A_D[0..63]
U6 F11 U6 F11 RD7 2 1 68_0402_1%
U10 VDD1 DQ8 F10 DDR_A_D28 U10 VDD1 DQ8 F10 DDR_A_D43 DDR_A_CAA7 RD8 2 1 68_0402_1%
VDD1 DQ9 DDR_A_D30 VDD1 DQ9 DDR_A_D40 DDR_A_CAA8 <7> DDR_A_DQS[0..7]
F9 F9 RD9 2 1 68_0402_1%
DQ10 F8 DDR_A_D31 DQ10 F8 DDR_A_D44 DDR_A_CAA9 RD10 2 1 68_0402_1%
DQ11 DDR_A_D27 DQ11 DDR_A_D46 DDR_A_CAB0 <7> DDR_A_CAA[0..9]
+1.2V_MEM A8 E11 +1.2V_MEM A8 E11 RD11 2 1 68_0402_1%
D
A9 VDD2 DQ12 E10 DDR_A_D29 A9 VDD2 DQ12 E10 DDR_A_D47 DDR_A_CAB1 RD12 2 1 68_0402_1%
D
D4 VDD2 DQ13 E9 DDR_A_D25 D4 VDD2 DQ13 E9 DDR_A_D41 DDR_A_CAB2 2 1 <7> DDR_A_CAB[0..9]
RD13 68_0402_1%
D5 VDD2 DQ14 D9 DDR_A_D24 D5 VDD2 DQ14 D9 DDR_A_D45 DDR_A_CAB3 RD14 2 1 68_0402_1%
D6 VDD2 DQ15 T8 DDR_A_D9 D6 VDD2 DQ15 T8 DDR_A_D52 DDR_A_CAB4 RD15 2 1 68_0402_1%
G5 VDD2 DQ16 T9 DDR_A_D12 G5 VDD2 DQ16 T9 DDR_A_D48 DDR_A_CAB5 RD16 2 1 68_0402_1%
H5 VDD2 DQ17 T10 DDR_A_D14 H5 VDD2 DQ17 T10 DDR_A_D55 DDR_A_CAB6 RD17 2 1 68_0402_1%
H6 VDD2 DQ18 T11 DDR_A_D15 H6 VDD2 DQ18 T11 DDR_A_D54 DDR_A_CAB7 RD18 2 1 68_0402_1%
H12 VDD2 DQ19 R8 DDR_A_D8 H12 VDD2 DQ19 R8 DDR_A_D53 DDR_A_CAB8 RD19 2 1 68_0402_1%
J5 VDD2 DQ20 R9 DDR_A_D13 J5 VDD2 DQ20 R9 DDR_A_D49 DDR_A_CAB9 RD20 2 1 68_0402_1%
J6 VDD2 DQ21 R10 DDR_A_D11 J6 VDD2 DQ21 R10 DDR_A_D51
K5 VDD2 DQ22 R11 DDR_A_D10 K5 VDD2 DQ22 R11 DDR_A_D50
K6 VDD2 DQ23 C11 DDR_A_D16 K6 VDD2 DQ23 C11 DDR_A_D63 +0.6V_DDR_VTT
K12 VDD2 DQ24 C10 DDR_A_D20 K12 VDD2 DQ24 C10 DDR_A_D62
L5 VDD2 DQ25 C9 DDR_A_D22 L5 VDD2 DQ25 C9 DDR_A_D56 DDR_A_CS#0 RD21 1 2 80.6_0402_1%
P4 VDD2 DQ26 C8 DDR_A_D18 P4 VDD2 DQ26 C8 DDR_A_D60 DDR_A_CS#1 RD22 1 2 80.6_0402_1%
P5 VDD2 DQ27 B11 DDR_A_D17 P5 VDD2 DQ27 B11 DDR_A_D58 DDR_A_ODT0 RD23 1 2 80.6_0402_1%
P6 VDD2 DQ28 B10 DDR_A_D21 P6 VDD2 DQ28 B10 DDR_A_D59 DDR_A_CKE0 RD24 1 2 80.6_0402_1%
U8 VDD2 DQ29 B9 DDR_A_D23 U8 VDD2 DQ29 B9 DDR_A_D61 DDR_A_CKE1 RD25 1 2 80.6_0402_1%
U9 VDD2 DQ30 B8 DDR_A_D19 U9 VDD2 DQ30 B8 DDR_A_D57 DDR_A_CKE2 RD79 1 2 80.6_0402_1%
VDD2 DQ31 VDD2 DQ31 DDR_A_CKE3 RD80 1 2 80.6_0402_1%

A11 R2 DDR_A_CAA0 A11 R2 DDR_A_CAB0

+1.2V_MEM VDDQ CA0 DDR_A_CAA1 +1.2V_MEM VDDQ CA0 DDR_A_CAB1 +0.6V_DDR_VTT
C12 P2 C12 P2
E8 VDDQ CA1 N2 DDR_A_CAA2 E8 VDDQ CA1 N2 DDR_A_CAB2
E12 VDDQ CA2 N3 DDR_A_CAA3 E12 VDDQ CA2 N3 DDR_A_CAB3 DDR_A_CLK#0 RD26 1 2 37.4_0402_1%
G12 VDDQ CA3 M3 DDR_A_CAA4 G12 VDDQ CA3 M3 DDR_A_CAB4 DDR_A_CLK0 RD27 1 2 37.4_0402_1%
H8 VDDQ CA4 F3 DDR_A_CAA5 H8 VDDQ CA4 F3 DDR_A_CAB5
H9 VDDQ CA5 E3 DDR_A_CAA6 H9 VDDQ CA5 E3 DDR_A_CAB6
H11 VDDQ CA6 E2 DDR_A_CAA7 H11 VDDQ CA6 E2 DDR_A_CAB7 +0.6V_DDR_VTT
J9 VDDQ CA7 D2 DDR_A_CAA8 J9 VDDQ CA7 D2 DDR_A_CAB8
J10 VDDQ CA8 C2 DDR_A_CAA9 J10 VDDQ CA8 C2 DDR_A_CAB9 DDR_A_CLK#1 RD30 1 2 37.4_0402_1%
K8 VDDQ CA9 K8 VDDQ CA9 DDR_A_CLK1 RD33 1 2 37.4_0402_1%
K11 VDDQ K11 VDDQ
L12 VDDQ L10 DDR_A_DQS0 L12 VDDQ L10 DDR_A_DQS4
N8
N12
VDDQ
VDDQ
DQS0
DQS1
G10
P10
DDR_A_DQS3
DDR_A_DQS1
N8
N12
VDDQ
VDDQ
DQS0
DQS1
G10
P10
DDR_A_DQS5
DDR_A_DQS6 Follow CRB 544250
C
R12
U11
VDDQ
VDDQ
DQS2
DQS3
D10 DDR_A_DQS2 R12
U11
VDDQ
VDDQ
DQS2
DQS3
D10 DDR_A_DQS7
CA - 68 ohm C
VDDQ
L11 DDR_A_DQS#0
VDDQ
L11 DDR_A_DQS#4
CS/CKE/ODT - 80.6 ohm
+1.2V_MEM
F2
G2 VDDCA
DQS0#
DQS1#
G11
P11
DDR_A_DQS#3
DDR_A_DQS#1 +1.2V_MEM
F2
G2 VDDCA
DQS0#
DQS1#
G11
P11
DDR_A_DQS#5
DDR_A_DQS#6
CLK - 37.4 ohm
VDDCA DQS2# DDR_A_DQS#2 VDDCA DQS2# DDR_A_DQS#7
Total
H3 D11 H3 D11
L2 VDDCA DQS3# L2 VDDCA DQS3# VDD :8x0.1uF,16x1uF,5x10uF
M2 VDDCA M2 VDDCA
For VDD1 VDDCA: 8x1uF,3x10uF
VDDCA VDDCA +1.8V_MEM
DM0
L8
DM0
L8 VDD2:12x1uF,5x10uF
G8 G8 VDD1:8x1uF,5x10uF
A1 DM1 P8 A1 DM1 P8
A2 NC DM2 D8 A2 NC DM2 D8 VTT:8x1uF,2x22uF
A12 NC DM3 A12 NC DM3
NC NC

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K
A13 A13 1 1 1 1 1 1 1
B1 NC B3 RD28 1 2 243_0402_1% B1 NC B3 RD31 1 2 243_0402_1%
NC ZQ0 NC ZQ0

CD41

CD42

CD43

CD52

CD74

CD75

CD76
B13 B4 RD29 1 2 243_0402_1% B13 B4 RD32 1 2 243_0402_1%
C4 NC ZQ1 C4 NC ZQ1
K9 NC K9 NC 2 2 2 2 2 2 2
R3 NC K3 DDR_A_CKE0 R3 NC K3 DDR_A_CKE2
T1 NC CKE0 K4 DDR_A_CKE1 DDR_A_CKE0 <7> T1 NC CKE0 K4 DDR_A_CKE3 DDR_A_CKE2 <7>
NC CKE1 DDR_A_CKE1 <7> NC CKE1 DDR_A_CKE3 <7>
T13 T13
U1 NC U1 NC
U2 NC L3 DDR_A_CS#0 U2 NC L3 DDR_A_CS#0
NC CS0# DDR_A_CS#1 DDR_A_CS#0 <7> NC CS0# DDR_A_CS#1
U12 L4 U12 L4
U13 NC CS1# DDR_A_CS#1 <7> U13 NC CS1#
NC NC
J3 DDR_A_CLK0 J3 DDR_A_CLK1 +1.2V_MEM
CK DDR_A_CLK#0 DDR_A_CLK0 <7> CK DDR_A_CLK#1 DDR_A_CLK1 <7> For VDD2
P3 J2 P3 J2
VSSCA CK# DDR_A_CLK#0 <7> VSSCA CK# DDR_A_CLK#1 <7>
M4 M4
J4 VSSCA J4 VSSCA
G4 VSSCA J8 DDR_A_ODT0 G4 VSSCA J8 DDR_A_ODT0
VSSCA ODT DDR_A_ODT0 <7> VSSCA ODT

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K
G3 G3 1 1 1 1 1 1 1 1 1
F4 VSSCA F4 VSSCA
VSSCA VSSCA

CD31

CD32

CD33

CD30

CD68

CD69

CD70

CD71

CD72
D3 J11 D3 J11
VSSCA Vref_DQ +VREFDQ_A VSSCA Vref_DQ +VREFDQ_A
C3 H4 C3 H4
VSSCA Vref_CA +VREFCA VSSCA Vref_CA +VREFCA 2 2 2 2 2 2 2 2 2

T12 B2 T12 B2
B
T6 VSSQ VSS B5 T6 VSSQ VSS B5 B
R6 VSSQ VSS C5 R6 VSSQ VSS C5
P12 VSSQ VSS E4 P12 VSSQ VSS E4
VSSQ VSS 1 VSSQ VSS 1
N6 E5 CD10 N6 E5 CD11
M12 VSSQ VSS F5 M12 VSSQ VSS F5
M6 VSSQ VSS H2 0.047U_0402_16V7K M6 VSSQ VSS H2 0.047U_0402_16V7K
L9 VSSQ VSS J12 +VREFCA 2 L9 VSSQ VSS J12 +VREFCA 2
K10 VSSQ VSS K2 K10 VSSQ VSS K2
H10 VSSQ VSS L6 +VREFDQ_A H10 VSSQ VSS L6 +VREFDQ_A
VSSQ VSS VSSQ VSS +1.2V_MEM
For VDDCA
G9 M5 1 G9 M5 1
G6 VSSQ VSS N4 CD20 G6 VSSQ VSS N4 CD21
F12 VSSQ VSS N5 F12 VSSQ VSS N5
F6 VSSQ VSS R4 0.047U_0402_16V7K F6 VSSQ VSS R4 0.047U_0402_16V7K
E6 VSSQ VSS R5 2 E6 VSSQ VSS R5 2
VSSQ VSS VSSQ VSS

10U_0402_6.3V6M

10U_0402_6.3V6M

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K
D12 T2 D12 T2 1 1 1 1 1 1
VSSQ VSS VSSQ VSS

CD5

CD6

CD1

CD2

CD3

CD4
C6 T3 C6 T3
B12 VSSQ VSS T4 B12 VSSQ VSS T4
B6 VSSQ VSS T5 B6 VSSQ VSS T5
VSSQ VSS VSSQ VSS 2 2 2 2 2 2

LPDDR3_FBGA178 LPDDR3_FBGA178

+0.6V_DDR_VTT +1.2V_MEM
For VDDQ
+DDR_VREF_CA +1.2V_MEM +VREFCA +DDR_VREF_A_DQ +1.2V_MEM +VREFDQ_A
For VTT
1

22U_0603_6.3V6M

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

0.1U_0201_10V6K

0.1U_0201_10V6K

0.1U_0201_10V6K

0.1U_0201_10V6K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CD55

CD60

CD61

CD62

CD66

CD36

CD37

CD38

CD22

CD23

CD24

CD25

CD26

CD27

CD28

CD29

CD16

CD17

CD18

CD19
RD34 RD35

8.2K_0402_1% 8.2K_0402_1%
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
2

A RD36 RD37 A
1 2 1 2
1 5.11_0402_1% 1 10_0402_1%
CD39 CD40
1

0.022U_0402_25V7K 0.022U_0402_25V7K
2 2 RD39
RD38
1

RD40
8.2K_0402_1%
RD41 8.2K_0402_1% DELL CONFIDENTIAL/PROPRIETARY
2

24.9_0402_1% 24.9_0402_1%
Compal Electronics, Inc.
2

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, LPDDR3
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
0.1
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-E112P
Date: Friday, April 22, 2016 Sheet 20 of 58
5 4 3 2 1
 5 4 3 2 1

UD3 UD4
For LPDDR3
A3 P9 DDR_B_D15 A3 P9 DDR_B_D44
+1.8V_MEM VDD1 DQ0 DDR_B_D11 +1.8V_MEM VDD1 DQ0 DDR_B_D45 +0.6V_DDR_VTT
A4 N9 A4 N9
A5 VDD1 DQ1 N10 DDR_B_D8 A5 VDD1 DQ1 N10 DDR_B_D43
A6 VDD1 DQ2 N11 DDR_B_D9 A6 VDD1 DQ2 N11 DDR_B_D46 DDR_B_CAA0 RD42 2 1 68_0402_1%
A10 VDD1 DQ3 M8 DDR_B_D14 A10 VDD1 DQ3 M8 DDR_B_D41 DDR_B_CAA1 RD43 2 1 68_0402_1%
U3 VDD1 DQ4 M9 DDR_B_D10 U3 VDD1 DQ4 M9 DDR_B_D42 DDR_B_CAA2 RD44 2 1 68_0402_1%
U4 VDD1 DQ5 M10 DDR_B_D12 U4 VDD1 DQ5 M10 DDR_B_D40 DDR_B_CAA3 RD45 2 1 68_0402_1%
U5 VDD1 DQ6 M11 DDR_B_D13 U5 VDD1 DQ6 M11 DDR_B_D47 DDR_B_CAA4 RD46 2 1 68_0402_1%
VDD1 DQ7 DDR_B_D18 VDD1 DQ7 DDR_B_D51 DDR_B_CAA5 <7> DDR_B_DQS#[0..7]
U6 F11 U6 F11 RD47 2 1 68_0402_1%
U10 VDD1 DQ8 F10 DDR_B_D19 U10 VDD1 DQ8 F10 DDR_B_D50 DDR_B_CAA6 RD48 2 1 68_0402_1%
VDD1 DQ9 DDR_B_D21 VDD1 DQ9 DDR_B_D49 DDR_B_CAA7 <7> DDR_B_D[0..63]
F9 F9 RD49 2 1 68_0402_1%
DQ10 F8 DDR_B_D17 DQ10 F8 DDR_B_D53 DDR_B_CAA8 RD50 2 1 68_0402_1%
DQ11 DDR_B_D23 DQ11 DDR_B_D54 DDR_B_CAA9 <7> DDR_B_DQS[0..7]
+1.2V_MEM A8 E11 +1.2V_MEM A8 E11 RD51 2 1 68_0402_1%
D
A9 VDD2 DQ12 E10 DDR_B_D16 A9 VDD2 DQ12 E10 DDR_B_D55 DDR_B_CAB0 RD52 2 1 68_0402_1%
D
D4 VDD2 DQ13 E9 DDR_B_D20 D4 VDD2 DQ13 E9 DDR_B_D52 DDR_B_CAB1 2 1 <7> DDR_B_CAA[0..9]
RD53 68_0402_1%
D5 VDD2 DQ14 D9 DDR_B_D22 D5 VDD2 DQ14 D9 DDR_B_D48 DDR_B_CAB2 RD54 2 1 68_0402_1%
D6 VDD2 DQ15 T8 DDR_B_D3 D6 VDD2 DQ15 T8 DDR_B_D29 DDR_B_CAB3 2 1 <7> DDR_B_CAB[0..9]
RD55 68_0402_1%
G5 VDD2 DQ16 T9 DDR_B_D0 G5 VDD2 DQ16 T9 DDR_B_D24 DDR_B_CAB4 RD56 2 1 68_0402_1%
H5 VDD2 DQ17 T10 DDR_B_D2 H5 VDD2 DQ17 T10 DDR_B_D26 DDR_B_CAB5 RD57 2 1 68_0402_1%
H6 VDD2 DQ18 T11 DDR_B_D4 H6 VDD2 DQ18 T11 DDR_B_D27 DDR_B_CAB6 RD58 2 1 68_0402_1%
H12 VDD2 DQ19 R8 DDR_B_D1 H12 VDD2 DQ19 R8 DDR_B_D25 DDR_B_CAB7 RD59 2 1 68_0402_1%
J5 VDD2 DQ20 R9 DDR_B_D6 J5 VDD2 DQ20 R9 DDR_B_D28 DDR_B_CAB8 RD60 2 1 68_0402_1%
J6 VDD2 DQ21 R10 DDR_B_D5 J6 VDD2 DQ21 R10 DDR_B_D31 DDR_B_CAB9 RD61 2 1 68_0402_1%
K5 VDD2 DQ22 R11 DDR_B_D7 K5 VDD2 DQ22 R11 DDR_B_D30
K6 VDD2 DQ23 C11 DDR_B_D33 K6 VDD2 DQ23 C11 DDR_B_D57
K12 VDD2 DQ24 C10 DDR_B_D38 K12 VDD2 DQ24 C10 DDR_B_D63 +0.6V_DDR_VTT
L5 VDD2 DQ25 C9 DDR_B_D34 L5 VDD2 DQ25 C9 DDR_B_D56
P4 VDD2 DQ26 C8 DDR_B_D37 P4 VDD2 DQ26 C8 DDR_B_D60 DDR_B_CS#0 RD62 1 2 80.6_0402_1%
P5 VDD2 DQ27 B11 DDR_B_D39 P5 VDD2 DQ27 B11 DDR_B_D58 DDR_B_CS#1 RD63 1 2 80.6_0402_1%
P6 VDD2 DQ28 B10 DDR_B_D35 P6 VDD2 DQ28 B10 DDR_B_D59 DDR_B_ODT0 RD64 1 2 80.6_0402_1%
U8 VDD2 DQ29 B9 DDR_B_D32 U8 VDD2 DQ29 B9 DDR_B_D61 DDR_B_CKE0 RD65 1 2 80.6_0402_1%
U9 VDD2 DQ30 B8 DDR_B_D36 U9 VDD2 DQ30 B8 DDR_B_D62 DDR_B_CKE1 RD66 1 2 80.6_0402_1%
VDD2 DQ31 VDD2 DQ31 DDR_B_CKE2 RD81 1 2 80.6_0402_1%
DDR_B_CKE3 RD82 1 2 80.6_0402_1%
A11 R2 DDR_B_CAA0 A11 R2 DDR_B_CAB0
+1.2V_MEM VDDQ CA0 DDR_B_CAA1 +1.2V_MEM VDDQ CA0 DDR_B_CAB1
C12 P2 C12 P2
E8 VDDQ CA1 N2 DDR_B_CAA2 E8 VDDQ CA1 N2 DDR_B_CAB2 +0.6V_DDR_VTT
E12 VDDQ CA2 N3 DDR_B_CAA3 E12 VDDQ CA2 N3 DDR_B_CAB3
G12 VDDQ CA3 M3 DDR_B_CAA4 G12 VDDQ CA3 M3 DDR_B_CAB4 DDR_B_CLK#0 RD67 1 2 37.4_0402_1%
H8 VDDQ CA4 F3 DDR_B_CAA5 H8 VDDQ CA4 F3 DDR_B_CAB5 DDR_B_CLK0 RD68 1 2 37.4_0402_1%
H9 VDDQ CA5 E3 DDR_B_CAA6 H9 VDDQ CA5 E3 DDR_B_CAB6
H11 VDDQ CA6 E2 DDR_B_CAA7 H11 VDDQ CA6 E2 DDR_B_CAB7
J9 VDDQ CA7 D2 DDR_B_CAA8 J9 VDDQ CA7 D2 DDR_B_CAB8 +0.6V_DDR_VTT
J10 VDDQ CA8 C2 DDR_B_CAA9 J10 VDDQ CA8 C2 DDR_B_CAB9
K8 VDDQ CA9 K8 VDDQ CA9 DDR_B_CLK#1 RD69 1 2 37.4_0402_1%
K11 VDDQ K11 VDDQ DDR_B_CLK1 RD74 1 2 37.4_0402_1%
L12 VDDQ L10 DDR_B_DQS1 L12 VDDQ L10 DDR_B_DQS5
N8 VDDQ DQS0 G10 DDR_B_DQS2 N8 VDDQ DQS0 G10 DDR_B_DQS6
N12
R12
VDDQ
VDDQ
DQS1
DQS2
P10
D10
DDR_B_DQS0
DDR_B_DQS4
N12
R12
VDDQ
VDDQ
DQS1
DQS2
P10
D10
DDR_B_DQS3
DDR_B_DQS7 Follow CRB 544250
C U11 VDDQ
VDDQ
DQS3 U11 VDDQ
VDDQ
DQS3
CA - 68 ohm C

F2 DQS0#
L11
G11
DDR_B_DQS#1
DDR_B_DQS#2 F2 DQS0#
L11
G11
DDR_B_DQS#5
DDR_B_DQS#6
CS/CKE/ODT - 80.6 ohm
+1.2V_MEM
G2
H3
VDDCA
VDDCA
DQS1#
DQS2#
P11
D11
DDR_B_DQS#0
DDR_B_DQS#4
+1.2V_MEM
G2
H3
VDDCA
VDDCA
DQS1#
DQS2#
P11
D11
DDR_B_DQS#3
DDR_B_DQS#7
CLK - 37.4 ohm
L2 VDDCA DQS3# L2 VDDCA DQS3#
M2 VDDCA M2 VDDCA
VDDCA L8 VDDCA L8
DM0 G8 DM0 G8
A1 DM1 P8 A1 DM1 P8 +1.8V_MEM
NC DM2 NC DM2 For VDD1
A2 D8 A2 D8
A12 NC DM3 A12 NC DM3
A13 NC A13 NC
B1 NC B3 RD70 1 2 243_0402_1% B1 NC B3 RD72 1 2 243_0402_1%
NC ZQ0 NC ZQ0

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M
@ CD112

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K
B13 B4 RD71 1 2 243_0402_1% B13 B4 RD73 1 2 243_0402_1% 1 1 1 1 1 1 1
NC ZQ1 NC ZQ1

CD111

CD110

CD103

CD104

CD106

CD107
C4 C4
K9 NC K9 NC
R3 NC K3 DDR_B_CKE0 R3 NC K3 DDR_B_CKE2
T1 NC CKE0 K4 DDR_B_CKE1 DDR_B_CKE0 <7> T1 NC CKE0 K4 DDR_B_CKE3 DDR_B_CKE2 <7> 2 2 2 2 2 2 2
NC CKE1 DDR_B_CKE1 <7> NC CKE1 DDR_B_CKE3 <7>
T13 T13
U1 NC U1 NC
U2 NC L3 DDR_B_CS#0 U2 NC L3 DDR_B_CS#0
NC CS0# DDR_B_CS#1 DDR_B_CS#0 <7> NC CS0# DDR_B_CS#1
U12 L4 U12 L4
U13 NC CS1# DDR_B_CS#1 <7> U13 NC CS1#
NC NC
J3 DDR_B_CLK0 J3 DDR_B_CLK1
CK DDR_B_CLK#0 DDR_B_CLK0 <7> CK DDR_B_CLK#1 DDR_B_CLK1 <7>
P3 J2 P3 J2
VSSCA CK# DDR_B_CLK#0 <7> VSSCA CK# DDR_B_CLK#1 <7> +1.2V_MEM
M4 M4 For VDD2
J4 VSSCA J4 VSSCA
G4 VSSCA J8 DDR_B_ODT0 G4 VSSCA J8 DDR_B_ODT0
G3 VSSCA ODT DDR_B_ODT0 <7> G3 VSSCA ODT
F4 VSSCA F4 VSSCA
VSSCA VSSCA

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M
@ CD102

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K
D3 J11 D3 J11 1 1 1 1 1 1 1 1 1
VSSCA Vref_DQ +VREFDQ_B VSSCA Vref_DQ +VREFDQ_B

CD100

CD101

CD98

CD105

CD109

CD108

CD113

CD114
C3 H4 C3 H4
VSSCA Vref_CA +VREFCA VSSCA Vref_CA +VREFCA

T12 B2 T12 B2 2 2 2 2 2 2 2 2 2
B
T6 VSSQ VSS B5 T6 VSSQ VSS B5 B
R6 VSSQ VSS C5 R6 VSSQ VSS C5
P12 VSSQ VSS E4 P12 VSSQ VSS E4
VSSQ VSS 1 VSSQ VSS 1
N6 E5 CD46 N6 E5 CD47
M12 VSSQ VSS F5 M12 VSSQ VSS F5
M6 VSSQ VSS H2 0.047U_0402_16V7K M6 VSSQ VSS H2 0.047U_0402_16V7K
L9 VSSQ VSS J12 +VREFCA 2 L9 VSSQ VSS J12 +VREFCA 2
K10 VSSQ VSS K2 K10 VSSQ VSS K2
H10 VSSQ VSS L6 +VREFDQ_B H10 VSSQ VSS L6 +VREFDQ_B
G9 VSSQ VSS M5 G9 VSSQ VSS M5
VSSQ VSS 1 VSSQ VSS 1
G6 N4 CD53 G6 N4 CD54 For VDDCA
F12 VSSQ VSS N5 F12 VSSQ VSS N5 +1.2V_MEM
F6 VSSQ VSS R4 0.047U_0402_16V7K F6 VSSQ VSS R4 0.047U_0402_16V7K
E6 VSSQ VSS R5 2 E6 VSSQ VSS R5 2
D12 VSSQ VSS T2 D12 VSSQ VSS T2
C6 VSSQ VSS T3 C6 VSSQ VSS T3
VSSQ VSS VSSQ VSS

10U_0402_6.3V6M

10U_0402_6.3V6M
@ CD78

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K
B12 T4 B12 T4 1 1 1 1 1 1
VSSQ VSS VSSQ VSS

CD83

CD81

CD82

CD79

CD80
B6 T5 B6 T5
VSSQ VSS VSSQ VSS

LPDDR3_FBGA178 LPDDR3_FBGA178 2 2 2 2 2 2

+DDR_VREF_B_DQ +1.2V_MEM +VREFDQ_B +0.6V_DDR_VTT For VTT +1.2V_MEM For VDDQ

1

RD75
22U_0603_6.3V6M

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M
@ CD96

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

0.1U_0201_10V6K

0.1U_0201_10V6K

0.1U_0201_10V6K

0.1U_0201_10V6K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CD63

CD56

CD57

CD58

CD64

CD93

CD90

CD99

CD92

CD97

CD89

CD95

CD86

CD91

CD85

CD84

CD87

CD88

CD94
8.2K_0402_1%
2

A RD76 A
1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
1 10_0402_1%
CD67
1

0.022U_0402_25V7K
2 RD77
1

RD78 8.2K_0402_1% DELL CONFIDENTIAL/PROPRIETARY

2

24.9_0402_1%
Compal Electronics, Inc.
2

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, LPDDR3
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
0.1
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-E112P
Date: Friday, April 22, 2016 Sheet 21 of 58
5 4 3 2 1
 5 4 3 2 1

For Steamboat12/14 &Kirkwood

+3.3V_RUN

2 1 SW2_DP1_AUXN CV62 CV61 close to pin30 &57 +3.3V_RUN

D RV70 100K_0402_5% CV66,CV69,CV70 close to pin5,21,51 D
2 1 SW2_DP2_AUXN
Priority : AR -> WIGI

0.01UF_0402_25V7K

0.01UF_0402_25V7K

0.1U_0201_10V6K

0.1U_0201_10V6K

0.1U_0201_10V6K
RV71 100K_0402_5%
2 1 SW2_PS8338_CFG0
1 1 1

CV83

CV84

CV85
RV85 4.7K_0402_5% UV7
SW2_PS8338_SW

CV81

CV82
2 1
@ RV89 4.7K_0402_5% 5

2
2 1 SW2_PS8338_P0 2 2 2 21 VDD33 50
RV95 4.7K_0402_5% 30 VDD33 OUT1_D0p 49 SW2_DP1_P0 <24>
51 VDD33 OUT1_D0n SW2_DP1_N0 <24>
57 VDD33 47
VDD33 OUT1_D1p 46 SW2_DP1_P1 <24>
OUT1_D1n SW2_DP1_N1 <24>
1 2 CPU_DP2_P0_C 6 45
2 1 SW2_DP1_CADET <6> CPU_DP2_P0
CV86 1 CPU_DP2_N0_C
2 0.1U_0201_10V6K 7 IN_D0p OUT1_D2p 44 SW2_DP1_P2 <24> AR
<6> CPU_DP2_N0 IN_D0n OUT1_D2n SW2_DP1_N2 <24>
RV73 1M_0402_5% CV87 0.1U_0201_10V6K
2 1 SW2_DP2_CADET 1 2 CPU_DP2_P1_C 9 42
<6> CPU_DP2_P1 CPU_DP2_N1_C IN_D1p OUT1_D3p SW2_DP1_P3 <24>
RV74 1M_0402_5% CV88 1 2 0.1U_0201_10V6K 10 41
2 1 SW2_DP1_AUXP <6> CPU_DP2_N1 IN_D1n OUT1_D3n SW2_DP1_N3 <24>
CV89 0.1U_0201_10V6K
RV76 100K_0402_5% 1 2 CPU_DP2_P2_C 12
2 1 SW2_DP2_AUXP <6> CPU_DP2_P2 CPU_DP2_N2_C IN_D2p
CV90 1 2 0.1U_0201_10V6K 13 40
<6> CPU_DP2_N2 IN_D2n OUT2_D0p 39 SW2_DP2_P0 <34>
RV77 100K_0402_5% CV91 0.1U_0201_10V6K
1 2 CPU_DP2_P3_C 15 OUT2_D0n SW2_DP2_N0 <34>
<6> CPU_DP2_P3 CPU_DP2_N3_C IN_D3p
CV92 1 2 0.1U_0201_10V6K 16 37
<6> CPU_DP2_N3 IN_D3n OUT2_D1p 36 SW2_DP2_P1 <34>
CV93 0.1U_0201_10V6K
OUT2_D1n SW2_DP2_N1 <34>
Change from 0402 to 0201 due to placement 35 WIGI
+3.3V_RUN 4 OUT2_D2p 34 SW2_DP2_P2 <34>
3 IN_CA_DET OUT2_D2n SW2_DP2_N2 <34>
<6> CPU_DP2_HPD 2 IN_HPD 32
SW2_PS8338_P1 1 I2C_CTL_EN OUT2_D3p 31 SW2_DP2_P3 <34>
SW2_PS8338_P0 60 Pl1/SCL_CTL OUT2_D3n SW2_DP2_N3 <34>
C Pl0/SDA_CTL C
2

2
4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%

@ @ @ @ @ for support TMDS signal need contact SCL/SDA to P22,23 26

22 OUT1_AUXp_SCL 27 SW2_DP1_AUXP <24>
<6> CPU_DP2_CTRL_CLK SW2_DP1_AUXN <24>
RV79

RV81

RV83

RV91

RV87

RV93

23 IN_DDC_SCL OUT1_AUXn_SDA
<6> CPU_DP2_CTRL_DATA 1 2 CPU_DP2_AUXP_C 24 IN_DDC_SDA 28
<6> CPU_DP2_AUXP CPU_DP2_AUXN_C IN_AUXp OUT2_AUXp_SCL SW2_DP2_AUXP <34>
CV94 1 2 0.1U_0201_10V6K 25 29
<6> CPU_DP2_AUXN SW2_DP2_AUXN <34>
1

SW2_PS8338_P1 CV95 0.1U_0201_10V6K IN_AUXn OUT2_AUXn_SDA

SW2_PS8338_CFG0 59 43 SW2_DP1_CADET
SW2_PS8338_PEQ 58 CFG0 OUT1_CA_DET 48
SW2_PS8338_PC10 56 CFG1 OUT1_HPD SW2_DP1_HPD <24>
Change from 0402 to 0201 due to placement
SW2_PS8338_PC10 SW2_PS8338_PC11 55 PC10 33 SW2_DP2_CADET
SW2_PS8338_PC20 54 PC11 OUT2_CA_DET 38
SW2_PS8338_PC11 SW2_PS8338_PC21 53 PC20 OUT2_HPD SW2_DP2_HPD <34>
PC21 18 SW2_PS8338_SW
SW2_PS8338_PC20 11 SW 8 SW2_PS8338_PEQ
19 GND PEQ 14
SW2_PS8338_PC21 52 GND PD 17
GND CEXT
4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%

61 20
PAD(GND) REXT
1

2.2U_0402_6.3V6M
1
4.99K_0402_1%
RV80

RV82

RV84

RV90

RV88

RV94

PS8338BQFN60GTR-A0_QFN60_5X9

1
RV97

CV96
@ @ @ @ @
2

2
2
B Port switching control or priority configuration. Internal pull down ~150KΩ , 3.3V I/O B
For Control Switching Mode (CFG0 = L):
SW = L: Port1 is selected (default)
SW = H: Port2 is selected
For Automatic Switching Mode (CFG0 = H):
SW = L: Port1 has higher priority when both ports are plugged (default)
SW = H: Port2 has higher priority when both ports are plugged

vender sugguest MUX use LLEQ PEQ=M and PI0=H !!

Programmable input equalization levels, Internal pull down at ~150Kohm,3.3V I/O

PEQ =
L: default,LEQ, compensate channel loss up to 11.5dB @HBR2
H: HEQ, compensate channel loss up to 14.5dB @HBR2
M:LLEQ, compensate channel loss up to 8.5dB @HBR2

PI0:Automatic EQ disable, Internal pull down ~150K ohm, 3.3V I/O

PI0 = L: Automatic EQ enable(default)
H: Automatic EQ disable

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
DP SW2 PS8338
Size Document Number R ev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
0.1
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-E112P
Date: Friday, April 22, 2016 Sheet 22 of 58
5 4 3 2 1
 5 4 3
For2 passive level shifter
1
+5V_RUN
from AR

0.1U_0201_10V6K
1

1
CV39
+VHDMI_VCC
2

IN

AP2330W-7_SC59-3
UV2

0.1U_0201_10V6K

10U_0603_10V6M
1

CV41
EMI@ RV24 1 2 5.6_0402_5%

GND

OUT
HDMI_L_TX_P2 @
@EMI@ LV3

CV40
D D

2
2
1 2 HDMI_TX_P2 1 4 EMI@ 2
<24> AR_DP1_P0

3
CV31 0.1U_0402_25V6 1 4 RV26

<24> AR_DP1_N0
1 2 HDMI_TX_N2 2
2 3
3
200_0402_5% HDMI connector
CV32 0.1U_0402_25V6

1
HCM1012GH900BP_4P HDMI_L_TX_N2
1 2
EMI@ RV25 5.6_0402_5% JHDMI1
HDMI_HPD 19
HP_DET
EMI@ RV27 1 2 5.6_0402_5% 18
HDMI_L_TX_P1 17 +5V
@EMI@ LV6 +3.3V_RUN HDMI_CTRL_DATA 16 DDC/CEC_GND
SDA

2
1 2 HDMI_TX_P1 1 4 EMI@ HDMI_CTRL_CLK 15
<24> AR_DP1_P1 1 4 SCL
CV33 0.1U_0402_25V6 RV29 14
2 1 HDMI_CEC 13 Reserved
200_0402_5% CEC
1 2 HDMI_TX_N1 2 3 10K_0402_5% @ RV19 HDMI_L_CLKN 12
<24> AR_DP1_N1 2 3 11 CK-
CV34 0.1U_0402_25V6

1
HCM1012GH900BP_4P HDMI_L_TX_N1 HDMI_L_CLKP 10 CK_shield
1 2 HDMI_L_TX_N0 9 CK+
EMI@ 5.6_0402_5% 8 D0-
RV28
HDMI_L_TX_P0 7 D0_shield
EMI@ RV30 1 2 5.6_0402_5% HDMI_L_TX_N1 6 D0+
HDMI_L_TX_P0 5 D1-
@EMI@ LV9 HDMI_L_TX_P1 4 D1_shield 20
D1+ GND1

2
1 2 HDMI_TX_P0 1 4 EMI@ HDMI_L_TX_N2 3 21
<24> AR_DP1_P2 1 4 D2- GND2
CV35 0.1U_0402_25V6 RV32 2 22
HDMI_L_TX_P2 1 D2_shield GND3 23
200_0402_5% D2+ GND4
1 2 HDMI_TX_N0 2 3
<24> AR_DP1_N2 2 3
CV36 0.1U_0402_25V6 CONCR_099A3AC19JBLCNF

1
HCM1012GH900BP_4P HDMI_L_TX_N0
CONN@
1 2
EMI@ RV31 5.6_0402_5%
LINK CONCR_099A3AC19JBLCNF DONE
EMI@ RV33 1 2 5.6_0402_5%
HDMI_L_CLKP 20160308
HDMI_TX_P2 HDMI_OB Need to chagne new one and same as DC232003400 (20160315)
C @EMI@ LV12 RV10 1 2 470_0402_1%
C

2
2 1 HDMI_CLKP 1 4 EMI@ HDMI_TX_N2 RV11 1 2 470_0402_1%
<24> AR_DP1_P3 0.1U_0402_25V6 1 4 HDMI_TX_P1
CV37 RV35 RV12 1 2 470_0402_1%
HDMI_TX_N1 RV13 1 2 470_0402_1%
200_0402_5%
2 1 HDMI_CLKN 2 3 HDMI_TX_P0 RV14 1 2 470_0402_1%
<24> AR_DP1_N3 0.1U_0402_25V6 2 3 HDMI_TX_N0 1 2
CV38 RV15 470_0402_1%

1
HCM1012GH900BP_4P HDMI_L_CLKN HDMI_CLKP RV16 1 2 470_0402_1%
HDMI_CLKN RV17 1 2 470_0402_1%
1 2
EMI@ RV34 5.6_0402_5%

1
D
RV18 1 2 10K_0402_5% 2 QV4
+3.3V_RUN
G L2N7002WT1G_SC-70-3
S

3
+3.3V_RUN
1M_0402_5%
2
RV20

2
G
1

3 1 HDMI_HPD 1 2
B <24> AR_DP1_HPD RV21 20K_0402_5%
B
S

QV5
L2N7002WT1G_SC-70-3

+3.3V_RUN

QV3A +VHDMI_VCC
2

DMN65D8LDW-7_SOT363-6

1 6 HDMI_CTRL_CLK 1 2
<24> AR_DP1_CTRL_CLK
RV22 2.2K_0402_5%
5

4 3 HDMI_CTRL_DATA 1 2
<24> AR_DP1_CTRL_DATA
RV23 2.2K_0402_5%
QV3B
DMN65D8LDW-7_SOT363-6

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
HDMI CONN
Size Document Number R ev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 0.1
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-E112P
Date: Friday, April 22, 2016 Sheet 23 of 58

5 4 3 2 1
 5 4 3 2 1

+3.3V_TBT_FLASH_R +3.3V_TBT_FLASH_R
+3.3V_TBT_LC For kirkwood
+3.3V_TBT_FLASH_R +3.3V_TBT_LC +3.3V_TBTA_FLASH

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%
2

2
RT5

RT6

RT7

RT8
0_0402_5% 2 1 RT9

0.1U_0201_10V6K

1
2

2
TBT_JTAG_TDI
3.3K_0402_5%

2.2K_0402_5%

2.2K_0402_5%

3.3K_0402_5%
1
TBT_JTAG_TMS

CT1
0_0402_5% 2 1 @ RT10
TBT_JTAG_TCK
TBT_JTAG_TDO
RT1

RT2

RT3

RT4
2
1

1
Rework Debug Pin1 +3.3V_TBT_LC, Pin6 GND
UT2
D 8 1 TBT_ROM_CS# D
TBT_ROM_HOLD# 7 VCC CS# 2 TBT_ROM_DO
TBT_ROM_CLK 6 HOLD#(IO3) DO(IO1) 3 TBT_ROM_WP# +3.3V_TBT
TBT_ROM_DI 5 CLK WP#(IO2) 4
DI(IO0) GND
W25Q80DVSSIG_SO8 TBT_RESET_N_EC @ RT11 1 2 10K_0402_5%

UT1A
CT2 1 2 0.22U_0201_6.3V6K PCIE_PTX_C_DRX_P1 Y23 V23 PCIE_PRX_C_DTX_P1 CT6 1 2 0.22U_0201_6.3V6K
<10> PCIE_PTX_DRX_P1 PCIE_RX0_P PCIE_TX0_P PCIE_PRX_DTX_P1 <10>
CT3 1 2 0.22U_0201_6.3V6K PCIE_PTX_C_DRX_N1 Y22 V22 PCIE_PRX_C_DTX_N1 CT7 1 2 0.22U_0201_6.3V6K AR_DP1_CTRL_DATA RT12 1 2 2.2K_0402_5%
<10> PCIE_PTX_DRX_N1 PCIE_RX0_N PCIE_TX0_N PCIE_PRX_DTX_N1 <10> AR_DP1_CTRL_CLK RT13 1 2 2.2K_0402_5%
CT4 1 2 0.22U_0201_6.3V6K PCIE_PTX_C_DRX_P2 T23 P23 PCIE_PRX_C_DTX_P2 CT8 1 2 0.22U_0201_6.3V6K DPSNK0_DDC_CLK @ RT14 1 2 2.2K_0402_5%

PCIe GEN3
<10> PCIE_PTX_DRX_P2 1 2 0.22U_0201_6.3V6K PCIE_PTX_C_DRX_N2 T22 PCIE_RX1_P PCIE_TX1_P P22 PCIE_PRX_C_DTX_N2 1 2 0.22U_0201_6.3V6K PCIE_PRX_DTX_P2 <10> DPSNK0_DDC_DATA
CT5 CT9 @ RT15 1 2 2.2K_0402_5%
<10> PCIE_PTX_DRX_N2 PCIE_RX1_N PCIE_TX1_N PCIE_PRX_DTX_N2 <10> DPSNK1_DDC_CLK @ RT336 1 2 2.2K_0402_5%
CT123 1 2 0.22U_0201_6.3V6K PCIE_PTX_C_DRX_P3 M23 K23 PCIE_PRX_C_DTX_P3 CT127 1 2 0.22U_0201_6.3V6K SNK0_CONFIG1 @ RT337 1 2 2.2K_0402_5% Need to check 20160310
<10> PCIE_PTX_DRX_P3 1 2 0.22U_0201_6.3V6K PCIE_PTX_C_DRX_N3 M22 PCIE_RX2_P PCIE_TX2_P K22 PCIE_PRX_C_DTX_N3 1 2 0.22U_0201_6.3V6K PCIE_PRX_DTX_P3 <10>
CT124 CT128
<10> PCIE_PTX_DRX_N3 PCIE_RX2_N PCIE_TX2_N PCIE_PRX_DTX_N3 <10>
SNK0_DDC_data/clk – connect to 2k PU only if
CT125 1 2 0.22U_0201_6.3V6K PCIE_PTX_C_DRX_P4 H23 F23 PCIE_PRX_C_DTX_P4 CT129 1 2 0.22U_0201_6.3V6K SRC0 is connected and support HDMI (a.i HDMI
<10> PCIE_PTX_DRX_P4 PCIE_RX3_P PCIE_TX3_P PCIE_PRX_DTX_P4 <10>
CT126 1 2 0.22U_0201_6.3V6K PCIE_PTX_C_DRX_N4 H22 F22 PCIE_PRX_C_DTX_N4 CT130 1 2 0.22U_0201_6.3V6K or DP++ connector). Otherwise can be 100k PD.
<10> PCIE_PTX_DRX_N4 PCIE_RX3_N PCIE_TX3_N PCIE_PRX_DTX_N4 <10>
PCH_PLTRST#_AND SNK1_DDC_data – connect to 100k PD. If SRC0
V19 L4
<11> CLK_PCIE_P5 T19 PCIE_REFCLK_100_IN_P PERST_N PCH_PLTRST#_AND <11,31,34,39,40> support HDMI, connect as SNK0_CFG1 to GPU
<11> CLK_PCIE_N5
AC5 PCIE_REFCLK_100_IN_N N16 TBT_PCIE_RBIAS 1 2
and/or appropriate AUX/DDC demux control
<11> CLKREQ_PCIE#5 PCIE_CLKREQ_N PCIE_RBIAS RT34 3.01K_0402_1% SNK1_DDC_clk – connect to 100k PD.
CT10 1 2 0.1U_0201_10V6K CPU_DP1_P0_C AB7 R2 AR_DP1_P0
<6> CPU_DP1_P0 CPU_DP1_N0_C DPSNK0_ML0_P DPSRC_ML0_P AR_DP1_N0 AR_DP1_P0 <23>
CT11 1 2 0.1U_0201_10V6K AC7 R1
<6> CPU_DP1_N0 DPSNK0_ML0_N DPSRC_ML0_N AR_DP1_N0 <23> AR_DP1_P0 1 2 AR_DP1_N0 +3.3V_TBT_SX
CT12 1 2 0.1U_0201_10V6K CPU_DP1_P1_C AB9 N2 AR_DP1_P1 @ CT201 1P_0201_50V8C
<6> CPU_DP1_P1 CPU_DP1_N1_C DPSNK0_ML1_P DPSRC_ML1_P AR_DP1_N1 AR_DP1_P1 <23> AR_DP1_P1 AR_DP1_N1
CT13 1 2 0.1U_0201_10V6K AC9 N1 1 2

SOURCE PORT 0
<6> CPU_DP1_N1 DPSNK0_ML1_N DPSRC_ML1_N AR_DP1_N1 <23> TBTA_I2C_INT
@ CT202 1P_0201_50V8C RT16 1 2 10K_0402_5%

SINK PORT 0
CT14 1 2 0.1U_0201_10V6K CPU_DP1_P2_C AB11 L2 AR_DP1_P2 AR_DP1_P2 1 2 AR_DP1_N2 TBTB_I2C_INT RT17 1 2 10K_0402_5%
<6> CPU_DP1_P2 CPU_DP1_N2_C DPSNK0_ML2_P DPSRC_ML2_P AR_DP1_N2 AR_DP1_P2 <23>
CT15 1 2 0.1U_0201_10V6K AC11 L1 @ CT203 1P_0201_50V8C
<6> CPU_DP1_N2 DPSNK0_ML2_N DPSRC_ML2_N AR_DP1_N2 <23> AR_DP1_P3 AR_DP1_N3 TBT_I2C_SDA
1 2 RT18 1 2 2.2K_0402_5%
CT16 1 2 0.1U_0201_10V6K CPU_DP1_P3_C AB13 J2 AR_DP1_P3 @ CT204 1P_0201_50V8C TBT_I2C_SCL RT19 1 2 2.2K_0402_5%
<6> CPU_DP1_P3 CPU_DP1_N3_C DPSNK0_ML3_P DPSRC_ML3_P AR_DP1_N3 AR_DP1_P3 <23>
CT17 1 2 0.1U_0201_10V6K AC13 J1
<6> CPU_DP1_N3 DPSNK0_ML3_N DPSRC_ML3_N AR_DP1_N3 <23>
CT18 1 2 0.1U_0201_10V6K CPU_DP1_AUXP_C Y11 W19 Closr UT1 TDOCK_BATLOW# RT20 1 2 10K_0402_5%
<6> CPU_DP1_AUXP CPU_DP1_AUXN_C DPSNK0_AUX_P DPSRC_AUX_P
C <6> CPU_DP1_AUXN CT19 1 2 0.1U_0201_10V6K W11
DPSNK0_AUX_N DPSRC_AUX_N
Y19 Intel Review TBT_SRC_CFG1 C
RT338 1 2 10K_0402_5%
CPU_DP1_HPD AA2 G1 AR_DP1_HPD request
<6> CPU_DP1_HPD DPSNK0_HPD DPSRC_HPD AR_DP1_HPD <23> TBT_CIO_PLUG_EVENT#
1 2 DPSNK0_DDC_CLK Y5 N6 TBT_DP_RBIAS 1 2
20160324 RTD3_CIO_PWR_EN
RT371 1
RT372 1
2 10K_0402_5%
2 10K_0402_5% Intel review request
<6> CPU_DP1_CTRL_CLK DPSNK0_DDC_DATA DPSNK0_DDC_CLK DPSRC_RBIAS
<6> CPU_DP1_CTRL_DATA
1
RT341 2 0_0402_5% R4
DPSNK0_DDC_DATA TBT_I2C_SDA
RT35 14K_0402_1%~D 20160324
RT342 0_0402_5% U1
SW2_DP1_P0_C GPIO_0 TBT_I2C_SCL TBT_I2C_SDA <26,27>
CT186 1 2 0.1U_0201_10V6K AB15 U2
<22> SW2_DP1_P0 SW2_DP1_N0_C DPSNK1_ML0_P GPIO_1 TBT_ROM_WP# TBT_I2C_SCL <26,27> TBTA_LSRX
CT187 1 2 0.1U_0201_10V6K AC15 V1 RT21 1 2 1M_0402_5%

LC GPIO
<22> SW2_DP1_N0 DPSNK1_ML0_N GPIO_2 V2 TBT_TMU_CLK_OUT TBTA_LSTX 1 2
RT22 1M_0402_5%
CT183 1 2 0.1U_0201_10V6K SW2_DP1_P1_C AB17 GPIO_3 W1 PCIE_WAKE# TBTA_HPD RT23 1 2 100K_0402_5%
<22> SW2_DP1_P1 SW2_DP1_N1_C DPSNK1_ML1_P GPIO_4 TBT_CIO_PLUG_EVENT# PCIE_WAKE# <34,38,40> PI3WVR31313A has internal PD 120Kohm CPU_DP1_HPD
CT180 1 2 0.1U_0201_10V6K AC17 W2 @ RT24 1 2 100K_0402_5%
<22> SW2_DP1_N1 DPSNK1_ML1_N GPIO_5 AR_DP1_CTRL_DATA TBT_CIO_PLUG_EVENT# <12> RTD3_CIO_PWR_EN
Y1 @ RT25 1 2 100K_0402_5%
CT185 1 2 0.1U_0201_10V6K SW2_DP1_P2_C AB19 GPIO_6 Y2 AR_DP1_CTRL_CLK AR_DP1_CTRL_DATA <23> RTD3_USB_PWR_EN 1 2
PS8338 RT26 100K_0402_5%
SINK PORT 1
<22> SW2_DP1_P2 SW2_DP1_N2_C DPSNK1_ML2_P GPIO_7 TBT_SRC_CFG1 AR_DP1_CTRL_CLK <23> TBT_FORCE_PWR
CT179 1 2 0.1U_0201_10V6K AC19 AA1 RT27 1 2 10K_0402_5%
<22> SW2_DP1_N2 DPSNK1_ML2_N GPIO_8 TBTA_I2C_INT TBT_TMU_CLK_OUT
J4 RT28 1 2 100K_0402_5%
SW2_DP1_P3_C POC_GPIO_0 TBTB_I2C_INT TBTA_I2C_INT <26> PI3WVR31310 has internal PD 120Kohm SW2_DP1_HPD
CT182 1 2 0.1U_0201_10V6K AB21 E2 @ RT29 1 2 100K_0402_5%
POC GPIO
<22> SW2_DP1_P3 SW2_DP1_N3_C DPSNK1_ML3_P POC_GPIO_1 RTD3_USB_PWR_EN TBTB_I2C_INT <27>
CT181 1 2 0.1U_0201_10V6K AC21 D4
<22> SW2_DP1_N3 DPSNK1_ML3_N POC_GPIO_2 TBT_FORCE_PWR
H4
CT178 1 2 0.1U_0201_10V6K SW2_DP1_AUXP_C Y12 POC_GPIO_3 F2 TDOCK_BATLOW# TBT_FORCE_PWR <6> TBT_SRC_CFG1 @ RT30 1 2 1M_0402_5%
<22> SW2_DP1_AUXP SW2_DP1_AUXN_C DPSNK1_AUX_P POC_GPIO_4 SIO_SLP_S3# TBTB_LSTX
<22> SW2_DP1_AUXN CT184 1 2 0.1U_0201_10V6K W12 D2 RT31 1 2 100K_0402_5%
DPSNK1_AUX_N POC_GPIO_5 F1 RTD3_CIO_PWR_EN SIO_SLP_S3# <11,37,38> TBTB_LSRX RT32 1 2 100K_0402_5%
SW2_DP1_HPD Y6 POC_GPIO_6 RTD3_CIO_PWR_EN <9> TBTB_HPD RT33 1 2 100K_0402_5%
<22> SW2_DP1_HPD DPSNK1_HPD E1 TEST_EN 1 2
DPSNK1_DDC_CLK Y8 TEST_EN RT36 100_0402_5%
Misc

SNK0_CONFIG1 N4 DPSNK1_DDC_CLK AB5 TEST_PWRGD 1 2

DPSNK1_DDC_DATA TEST_PWR_GOOD RT37 100_0402_5%
2 1 DPSNK_RBIAS Y18 F4 TBT_RESET_N_EC
DPSNK_RBIAS RESET_N TBT_RESET_N_EC
<26,27,37> AR_DP1_CTRL_DATA
RT38 14K_0402_1%~D @ RT124 1 2 100K_0402_5%
TBT_JTAG_TDI Y4 D22 XTAL_25_IN AR_DP1_CTRL_CLK @ RT125 1 2 100K_0402_5%
TBT_JTAG_TMS V4 TDI XTAL_25_IN D23 XTAL_25_OUT 1 2 XTAL_25_OUT_R DPSNK0_DDC_CLK @ RT126 1 2 100K_0402_5%
TBT_JTAG_TCK T4 TMS XTAL_25_OUT RT40 0_0402_5% DPSNK0_DDC_DATA @ RT127 1 2 100K_0402_5%
TBT_JTAG_TDO W4 TCK AB3 TBT_ROM_DI DPSNK1_DDC_CLK RT128 1 2
TDO MISC EE_DI TBT_ROM_DO
YT1
SNK0_CONFIG1
100K_0402_5% Need to check 20160310
AC4 3 1 RT129 1 2 100K_0402_5%
1 2 TBT_RBIAS H6 EE_DO AC3 TBT_ROM_CS# OUT IN
RT39 4.75K_0402_1% TBT_RSENSE J6 RBIAS EE_CS_N AB4 TBT_ROM_CLK 4 2
RSENSE EE_CLK GND GND

1
A15 B7 25MHZ_18PF_7V25000034
<29> TBTA_RX2P B15 PA_RX1_P PB_RX1_P A7 TBTB_RX2P <30>
CT20 CT21
<29> TBTA_RX2N PA_RX1_N PB_RX1_N TBTB_RX2N <30>
B 20P_0402_50V8 20P_0402_50V8 B

2
A17 A9
<29> TBTA_TX2P B17 PA_TX1_P PB_TX1_P B9 TBTB_TX2P <30>
<29> TBTA_TX2N PA_TX1_N PB_TX1_N TBTB_TX2N <30>
A19 A11
<29> TBTA_TX1P B19 PA_TX0_P PB_TX0_P B11 TBTB_TX1P <30>
<29> TBTA_TX1N PA_TX0_N PB_TX0_N TBTB_TX1N <30>
TBT PORTS

B21 A13
<29> TBTA_RX1P PA_RX0_P PB_RX0_P TBTB_RX1P <30>
A21 B13
Port A

PORT B

<29> TBTA_RX1N PA_RX0_N PB_RX0_N TBTB_RX1N <30>

Type C Y15 Y16
<26> TBTA_AUXP W15 PA_DPSRC_AUX_P PB_DPSRC_AUX_P W16 TBTB_AUXP <27>
<26> TBTA_AUXN PA_DPSRC_AUX_N PB_DPSRC_AUX_N TBTB_AUXN <27>
E20 E19
<26> TBTA_USB20_P PA_USB2_D_P PB_USB2_D_P TBTB_USB20_P <27>
D20 D19
<26> TBTA_USB20_N PA_USB2_D_N PB_USB2_D_N TBTB_USB20_N <27>
TBTA_LSTX A5 B4 TBTB_LSTX
<26> TBTA_LSTX TBTA_LSRX PA_LSTX PB_LSTX TBTB_LSRX TBTB_LSTX <27>
POC
POC

A4 B5
<26> TBTA_LSRX TBTA_HPD PA_LSRX PB_LSRX TBTB_HPD TBTB_LSRX <27>
M4 G2
<26> TBTA_HPD PA_DPSRC_HPD PB_DPSRC_HPD TBTB_HPD <27>
2 1 TBTA_USB2_RBIAS H19 F19 TBTB_USB2_RBIAS 1 2
RT41 499_0402_1% PA_USB2_RBIAS PB_USB2_RBIAS RT42 499_0402_1%
AC23 D6
AB23 THERMDA MONDC_SVR
THERMDA A23
V18 ATEST_P B23
PCIE_ATEST ATEST_N
AC1 DEBUG E18
TEST_EDM USB2_ATEST
L15 W13
N15 FUSE_VQPS_64 MONDC_DPSNK_0
FUSE_VQPS_128 W18
C23 MONDC_DPSNK_1
C22 MONDC_CIO_0 AB2
MONDC_CIO_1 MONDC_DPSRC
ALPINE-RIDGE_BGA337

A A

DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE:
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
TBT-AR-DP(1/2) DP, PCIE
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 0.1
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-E112P
Date: Monday, April 25, 2016 Sheet 24 of 58
5 4 3 2 1
 A B C D E

For Steamboat 12/14 &kirkwood,For AR

+0.9V_TBT_DP +0.9V_TBT_USB

1U_0201_6.3V6M +3.3V_ALW

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M
PJP6
+3.3V_VDD_PIC @ +3.3V_TBT_SX +3.3V_TBT
1 1 1 1 1 1 1 1 1 1 2 1 2
CT25

CT26

CT27

CT28

CT29

CT30

CT31

CT32

CT33
1 @ RT48 0_0603_5% VCC3P3_SVR:3.3V @ 0.6A max 1
PAD-OPEN1x1m +3.3V_TBT_LC 1 2
@ RT49 0_0603_5%
2 2 2 2 2 2 2 2 2 +3.3V_TBT_S0

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M
CT44

CT45

CT46

CT47
1 1 1 1 1 1 1

CT41

CT42

<BOM Structure> CT43

2 2 2 2 2 2 2

R13
+0.9V_TBT_PCIE +0.9V_TBT_CIO +0.9V_TBT_DP

R6

H9
F8
UT1B
L8 A2 VCC0P9_SVR:0.9V @ 1.8A max

VCC3P3_SX

VCC3P3_S0

VCC3P3A
VCC3P3_LC
L11 VCC0P9_DP VCC3P3_SVR A3
VCC0P9_DP VCC3P3_SVR
Minimum of 4vias must be used
L12 B3
1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M
M8 VCC0P9_DP VCC3P3_SVR +0.9V_TBT_SVR
T11 VCC0P9_DP
1 1 1 1 1 1 1 VCC0P9_DP
CT34

CT35

CT36

CT37

CT38

CT39

CT40
T12 L9

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M
L6 VCC0P9_DP VCC0P9_SVR M9
M6 VCC0P9_ANA_DPSRC VCC0P9_SVR E12
VCC0P9_ANA_DPSRC VCC0P9_SVR_ANA 1 1 1 1 1 1 1
2 2 2 2 2 2 2

CT48

CT49

CT50

CT51

CT52

CT53

CT54
V11 E13
V12 VCC0P9_ANA_DPSNK VCC0P9_SVR_ANA F11
+0.9V_TBT_PCIE V13 VCC0P9_ANA_DPSNK VCC0P9_SVR_ANA F12
VCC0P9_ANA_DPSNK VCC0P9_SVR_ANA F13 2 2 2 2 2 2 2
M13 VCC0P9_SVR_ANA F15
M15 VCC0P9_PCIE VCC0P9_SVR_ANA J9
M16 VCC0P9_PCIE VCC0P9_SVR_SENSE
L19 VCC0P9_PCIE
N19 VCC0P9_ANA_PCIE_1 C1 +TBT_SVR_IND LT1 1 2 0.6UH_MND-04ABIR60M-XGL_20%
L18 VCC0P9_ANA_PCIE_1 SVR_IND C2

47U_0603_6.3V6M

47U_0603_6.3V6M

47U_0603_6.3V6M
VCC0P9_ANA_PCIE_2 SVR_IND

CT55

CT56

CT57
M18 D1 1 1 1
+0.9V_TBT_USB N18 VCC0P9_ANA_PCIE_2 SVR_IND Share Same GND plane

VCC
VCC0P9_ANA_PCIE_2 with SVR_VSS of AR
R15 A1
R16 VCC0P9_USB SVR_VSS B1 2 2 2
+0.9V_TBT_CIO VCC0P9_USB SVR_VSS B2 Intel review request
SVR_VSS
R8
VCC0P9_CIO +0.9V_TBT_LVR_OUT
Change 10U*4 to
R9 SVR_VSS:Minimum of 4 vias must be used.
2
R11 VCC0P9_CIO 47U*3 2
VCC0P9_CIO
R12 F18 20160324

1U_0201_6.3V6M

1U_0201_6.3V6M
VCC0P9_CIO VCC0P9_LVR H18

10U_0402_6.3V6M

10U_0402_6.3V6M
+3.3V_RUN +3.3V_TBT +VCC3V3_ANA_PCIE L16 VCC0P9_LVR J11
+VCC3V3_ANA_USB2 J16 VCC3P3_ANA_PCIE VCC0P9_LVR 1 1 1 1

CT59

CT60

CT61

CT62
H11

1U_0201_6.3V6M

1U_0201_6.3V6M
VCC3P3_ANA_USB2 VCC0P9_LVR_SENSE
@ PJP5 1 1 A6 V5
VSS_ANA VSS_ANA 2 2 2 2

CT63

CT64
2 1 A8 V6
2 1 A10 VSS_ANA VSS_ANA V8
JUMP_43X79 A12 VSS_ANA VSS_ANA V9
2 2 A14 VSS_ANA VSS_ANA V15
A16 VSS_ANA VSS_ANA V16
A18 VSS_ANA VSS_ANA V20
A20 VSS_ANA VSS_ANA W5
A22 VSS_ANA VSS_ANA W6
B6 VSS_ANA VSS_ANA W8
B8 VSS_ANA VSS_ANA W9
B10 VSS_ANA VSS_ANA W20
B12 VSS_ANA VSS_ANA W22
B14 VSS_ANA VSS_ANA W23
B16 VSS_ANA VSS_ANA Y9
B18 VSS_ANA VSS_ANA Y13
B20 VSS_ANA VSS_ANA Y20
B22 VSS_ANA VSS_ANA AA22
D8 VSS_ANA VSS_ANA AA23
D9 VSS_ANA VSS_ANA AB6
D11 VSS_ANA VSS_ANA AB8
D12 VSS_ANA VSS_ANA AB10
D13 VSS_ANA VSS_ANA AB12
D15 VSS_ANA VSS_ANA AB14
D16 VSS_ANA VSS_ANA AB16

GND
D18 VSS_ANA VSS_ANA AB18
E8 VSS_ANA VSS_ANA AB20
E9 VSS_ANA VSS_ANA AB22
E11 VSS_ANA VSS_ANA AC6
E15 VSS_ANA VSS_ANA AC8
E16 VSS_ANA VSS_ANA AC10
E22 VSS_ANA VSS_ANA AC12
E23 VSS_ANA VSS_ANA AC14
3 3
F9 VSS_ANA VSS_ANA AC16
F16 VSS_ANA VSS_ANA AC18
F20 VSS_ANA VSS_ANA AC20
G22 VSS_ANA VSS_ANA AC22
G23 VSS_ANA VSS_ANA D5
+3.3V_TBT_S0 change pn to SHI0000N600 +3.3V_TBT H1 VSS_ANA VSS E4
H2 VSS_ANA VSS E5
1 2 H12 VSS_ANA VSS E6
LT2 1UH_LQM18NN1R0K00D_10% H13 VSS_ANA VSS F5
H15 VSS_ANA VSS F6
47U_0805_6.3V6M

47U_0805_6.3V6M
1U_0402_6.3V6K

VSS_ANA VSS
CT67

1 1 H16 H5
VSS_ANA VSS
1

CT68

CT69

H20 H8
J5 VSS_ANA VSS J8
J18 VSS_ANA VSS J12
2

2 2 J19 VSS_ANA VSS J13

J20 VSS_ANA VSS J15
J22 VSS_ANA VSS L13
J23 VSS_ANA VSS M11
K1 VSS_ANA VSS M12
K2 VSS_ANA VSS N8
L5 VSS_ANA VSS N9
L20 VSS_ANA VSS N11
L22 VSS_ANA VSS N12
L23 VSS_ANA VSS N13
M1 VSS_ANA VSS T6
M2 VSS_ANA VSS T8
M5 VSS_ANA VSS T9
M19 VSS_ANA VSS T13
M20 VSS_ANA VSS T15
N5 VSS_ANA VSS T16
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA

N20 VSS_ANA VSS T18

N22 VSS_ANA VSS AB1
N23 VSS_ANA VSS AC2
VSS_ANA VSS
P1
P2
R5
R18
R19
R20
R22
R23
T1
T2
T5
T20
U22
U23

4 4

DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE:
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
TBT-AR-SP(2/2) PWR,VSS
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 0.1
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-E112P
Date: Monday, April 25, 2016 Sheet 25 of 58
A B C D E
 5 4 3 2 1

+3.3V_TBTA_FLASH +3.3V_TBTA_FLASH
+3.3V_VDD_PIC
For AR port1

2
.1U_0402_16V7K
2

2
3.3K_0402_5%

3.3K_0402_5%

3.3K_0402_5%

3.3K_0402_5%
CT70

1
1 6 UPD1_SMBUS_CLK_Q
<37> UPD1_SMBCLK
RT50

RT51

RT52

RT53
@ QT1A
2 DMN66D0LDW-7_SOT363-6
1

1
RT58 1 2 0_0402_5%
UT6

5
8 1 TBTA_ROM_CS#_PD_R
TBTA_ROM_HOLD#_PD 7 VCC CS# 2 TBTA_ROM_DO_PD_R
TBTA_ROM_CLK_PD_R 6 HOLD#(IO3) DO(IO1) 3 TBTA_ROM_WP#_PD 4 3 UPD1_SMBUS_DAT_Q
TBTA_ROM_DI_PD_R CLK WP#(IO2) <37> UPD1_SMBDAT
5 4
DI(IO0) GND @ QT1B
W25Q80DVSSIG_SO8 DMN66D0LDW-7_SOT363-6
RT59 1 2 0_0402_5%
D D
TBTA_ROM_CLK_PD_R 0_0402_5% 2 1 RT54 TBTA_ROM_CLK_PD
TBTA_ROM_DI_PD_R 0_0402_5% 2 1 RT55 TBTA_ROM_DI_PD
TBTA_ROM_DO_PD_R 0_0402_5% 2 1 RT56 TBTA_ROM_DO_PD RT60 1 2 0_0402_5% UPD1_SMBUS_ALERT#
TBTA_ROM_CS#_PD_R TBTA_ROM_CS#_PD <37> UPD1_ALERT#
0_0402_5% 2 1 RT57

+3.3V_TBTA_FLASH

JDB1
1
1 2 TBTA_ROM_CLK_PD_R
2 3 TBTA_ROM_DI_PD_R
3 4 TBTA_ROM_DO_PD_R
7 4 5 TBTA_ROM_CS#_PD_R
8 GND 5 6
GND 6

ACES_50506-00641-P01
CONN@

+5V_ALW
@ PJP8
TI is 1x47uf+1x0.1uf
2 1

22U_0805_25V6M

22U_0805_25V6M

22U_0805_25V6M

22U_0805_25V6M
PAD-OPEN 1x3m +TBTA_Vbus_1
1 1 1 1

CT75

CT76

CT77

CT78
2 2 2 2

+TBTA_LDO_BMC
+VCC1V8D_TBTA_LDO RT64 @ 1 2 0_0402_5%
+VCC1V8A_TBTA_LDO
C C
RT65 @ 1 2 0_0402_5%
+3.3V_VDD_PIC +3.3V_VDD_PIC_PDA

HV_GATE1_A

HV_GATE2_A
2.2U_0402_16V6K

2.2U_0402_16V6K

2.2U_0402_16V6K

PJP7
1 1 1 @
TI is 3x1uf 1 2
+5V_ALW_PDA
CT71

CT72

CT73

PAD-OPEN1x1m

1U_0402_16V6K
1
2 2 2 2 1

CT74
RT63 0_0402_5%

H10

C11
D11
A11
B11

B10

A10
2

H1

B1

K1

A2

E1

A6
A7
A8
B7

B9

A9
UT5
F1

VIN_3V3

VDDIO

LDO_1V8A

PP_CABLE

PP_5V0
PP_5V0
PP_5V0
PP_5V0

PP_HV
PP_HV
PP_HV
PP_HV

SENSEP

HV_GATE1

HV_GATE2
LDO_1V8D

LDO_BMC

SENSEN
I2C_ADDR
+3.3V_TBTA_FLASH D1
<24,27> TBT_I2C_SDA I2C_SDA1 +TBTA_Vbus_1
D2
+3.3V_TBTA_FLASH <24,27> TBT_I2C_SCL I2C_SCL1
C1
<24> TBTA_I2C_INT I2C_IRQ1_N TI has 1x1uf
2

+3.3V_ALW
3.3K_0402_5% 2 1 RT66 @ UPD1_SMBUS_DAT_Q A5 +3.3V_PDA_VOUT +3.3V_TBTA_FLASH
10K_0402_1% 3.3K_0402_5% 2 1 RT67 @ UPD1_SMBUS_CLK_Q B5 I2C_SDA2 H11
I2C_SCL2 VBUS

1
2 1 RT68 @ UPD1_SMBUS_ALERT# B6 J10

CT82
RT76 10K_0402_5%

1U_0603_25V6K
I2C_IRQ2_N VBUS J11

1U_0402_16V6K

10U_0603_6.3V6M
1 1
1

PD1_GPIO8 VBUS

CT83
0_0402_5% 2 1 @ RT69 B2 K11

2
GPIO0 VBUS

CT84
0_0402_5% 2 1 RT70 C2
<58> EN_PD_HV_1
1

1M_0402_5% 2 1 RT71 D10 GPIO1

RT377 for TI strap pin 0_0402_5% 2 1 RT72 G11 GPIO2 2 2
<57,58> AC1_DISC# GPIO3
43K_0402_1% need double check <24> TBTA_HPD
0_0402_5% 2 1 RT73 C10
0_0402_5% 2 1 @ RT74 E10 GPIO4 H2
0_0402_5% 2 1 @ RT75 G10 GPIO5 VOUT_3V3
2

0_0402_5% 2 1 @ RT339 D7 GPIO6

PD1_GPIO8 H6 GPIO7
GPIO8: USB_TYPEC_FAULT# GPIO8 G1
TBTA_ROM_CLK_PD A3 LDO_3V3
TBTA_ROM_DI_PD B4 SPI_CLK
TBTA_ROM_DO_PD A4 SPI_MOSI
TBTA_ROM_CS#_PD B3 SPI_MISO K6
SPI_SS_N C_USB_TP TBTA_TOP_P <29>
L6
C_USB_TN TBTA_TOP_N <29>
L5
UART_MOSI <24> TBTA_USB20_P USB_RP_P
2 1 K5
<24>
UART_MOSI TBTA_USB20_N USB_RP_N
1M_0402_5% RT81 1 2
<27> UART_MOSI_R
2 1 UART_MISO RT345 0_0402_5% RT83 2 1 0_0402_5% E2 K7
UART_MISO UART_TX C_USB_BP TBTA_BOT_P <29>
B @ 1M_0402_5% RT82 1 2 F2 L7 B
<27> UART_MISO_R UART_RX C_USB_BN TBTA_BOT_N <29>
RT346 0_0402_5%
0_0402_5% 2 1 @ RT84 F4
Reserve Share ROM solution 0_0402_5% 2 1 @ RT85 G4 SWD_DATA TI has 2x220pf
Because TPS65982D has internal ROM SWD_CLK TBTA_CC1 <29>
L9
C_CC1 L10
C_CC2 WHEN CONNECT BUSPOWERZ TO GND,

220P_0402_50V8J

220P_0402_50V8J
TBTA_MRESET TBTA_CC2 <29>
RT86 2 1 1M_0402_5% E11 CONNECT ALSO RPD_Gn to C_CCn 1 1
MRESET
K9 1 2 0_0402_5%

CT85

CT86
RT104
TBTA_LSTX 1 2 TBTA_LSTX_R L4 RPD_G1 K10 RT105 1 2 0_0402_5%
<24> TBTA_LSTX TBTA_LSRX RT87 1 2 0_0402_5% TBTA_LSRX_R K4 TBT_LSTX/R2P RPD_G2 +3.3V_TBTA_FLASH 2 2
<24> TBTA_LSRX RT88 0_0402_5% TBT_LSRX/P2R

TBTA_LSTX 1 2 TBTA_DEBUG3 L3 E4 TBTA_DBG_CTL1 RT106 1 2 10K_0402_5%

TBTA_LSRX @ RT89 1 2 0_0402_5% TBTA_DEBUG4 K3 DIG_AUD_P/DEBUG3 DEBUG_CTL1 D5 TBTA_DBG_CTL2 RT107 1 2 10K_0402_5%
@ RT90 0_0402_5% DIG_AUD_N/DEBUG4 DEBUG_CTL2

UPD1_SMBUS_CLK_Q 1 2 TBTA_DEBUG1 L2
UPD1_SMBUS_DAT_Q RT92 1 2 0_0402_5% TBTA_DEBUG2 K2 DEBUG1
RT93 0_0402_5% DEBUG2
K8 TBTA_SBU1_R 1 2
TBTA_AUXP_C C_SBU1 TBTA_SBU1 <29>
CT80 1 2 0.1U_0201_10V6K J1 RT108 0_0402_5%
<24> TBTA_AUXP TBTA_AUXN_C AUX_P TBTA_SBU2_R
CT81 1 2 0.1U_0201_10V6K J2 L8 1 2
<24> TBTA_AUXN AUX_N C_SBU2 TBTA_SBU2 <29>
RT109 0_0402_5%
+3.3V_TBTA_FLASH
F10
BUSPOWER_N F11 TBTA_RESET_N_EC_R @ RT110 1 2 0_0402_5%
+3.3V_TBTA_FLASH RESET_N TBT_RESET_N_EC <24,27,37>
2 1 TBTA_AUXN_C TBTA_ROSC G2
100K_0402_5% RT95 R_OSC
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

GND
GND
GND
1

15K_0402_1%

SS
2

2 1 TBTA_AUXP_C @
0_0402_5%

RT100

100K_0402_5% RT96 TPS65982_BGA96

A1
D6
E5
E6
E7
F5
G5
H4
H5
B8
D8
E8
F6
F7
F8
G6
G7
G8
H7
H8
L1
L11
RT98

2
1

+VCC1V8D_TBTA_LDO 1 2
@ RT97 0_0402_5%
100K_0402_5%
1

0_0402_5%

1
1

RT101

@ RT103
0_0402_5%

CT87
RT99

A A
0.22U_0402_16V7K
@ 2
2

2
2

Need Link TPS65982D

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
[Type C]PD Controller TI
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. Size Document Number Rev
LA-E112P 0.1

Date: Friday, April 22, 2016 Sheet 26 of 58

5 4 3 2 1
 5 4 3 2 1

For AR port2 kirkwood

+3.3V_VDD_PIC

2
1 6 UPD2_SMBUS_CLK_Q
<37> UPD2_SMBCLK
@ QT2A
DMN66D0LDW-7_SOT363-6
RT150 1 2 0_0402_5%

5
4 3 UPD2_SMBUS_DAT_Q
D <37> UPD2_SMBDAT D
@ QT2B
DMN66D0LDW-7_SOT363-6
RT151 1 2 0_0402_5%

RT156 1 2 0_0402_5% UPD2_SMBUS_ALERT#

<37> UPD2_ALERT#

+5V_ALW

@ PJP10
TI is 1x47uf+1x0.1uf
2 1

22U_0805_25V6M

22U_0805_25V6M

22U_0805_25V6M

22U_0805_25V6M
PAD-OPEN 1x3m
1 1 1 1
+TBTB_Vbus_1

CT142

CT143

CT144

CT145
2 2 2 2

+TBTB_LDO_BMC
+VCC1V8D_TBTB_LDO @RT160 1 2 0_0402_5%
+VCC1V8A_TBTB_LDO
C C
@RT161 1 2 0_0402_5%
+3.3V_VDD_PIC +3.3V_VDD_PIC_PDB

HV_GATE1_B

HV_GATE2_B
2.2U_0402_16V6K

2.2U_0402_16V6K

2.2U_0402_16V6K

PJP9
1 1 1 @
TI is 3x1uf 1 2
+5V_ALW_PDB
CT147

CT148

CT149

PAD-OPEN1x1m

1U_0402_16V6K
1
2 2 2 2 1

CT150
@ RT159 0_0402_5%
+3.3V_TBTA_FLASH

H10

C11
D11
A11
B11

B10

A10
2

H1

B1

K1

A2

E1

A6
A7
A8
B7

B9

A9
UT11
F1

VIN_3V3

VDDIO

LDO_1V8A

PP_CABLE

PP_5V0
PP_5V0
PP_5V0
PP_5V0

PP_HV
PP_HV
PP_HV
PP_HV

SENSEP

HV_GATE1

HV_GATE2
LDO_1V8D

LDO_BMC

SENSEN
I2C_ADDR
2

D1
10K_0402_1% <24,26> TBT_I2C_SDA I2C_SDA1 +TBTB_Vbus_1
D2
+3.3V_TBTB_FLASH <24,26> TBT_I2C_SCL I2C_SCL1
RT172 C1
<24> TBTB_I2C_INT I2C_IRQ1_N TI has 1x1uf
1

PD2_GPIO8 +3.3V_ALW
@ RT162 2 1 3.3K_0402_5% UPD2_SMBUS_DAT_Q A5 +3.3V_PDB_VOUT +3.3V_TBTB_FLASH
1

@ RT163 2 1 3.3K_0402_5% UPD2_SMBUS_CLK_Q B5 I2C_SDA2 H11

I2C_SCL2 VBUS

1
2 1 10K_0402_5% UPD2_SMBUS_ALERT# B6 J10

CT151
RT378 for TI strap pin @ RT164

1U_0603_25V6K
I2C_IRQ2_N VBUS
43K_0402_1% need double check J11

1U_0402_16V6K

10U_0603_6.3V6M
VBUS 1 1
2 1 0_0402_5% B2 K11

CT152
@ RT165

2
2 1 0_0402_5% C2 GPIO0 VBUS

CT153
RT166
<58> EN_PD_HV_2
2

RT167 2 1 1M_0402_5% D10 GPIO1

RT168 2 1 0_0402_5% G11 GPIO2 2 2
<57,58> AC2_DISC# GPIO3
RT169 2 1 0_0402_5% C10
<24> TBTB_HPD GPIO4
@ RT170 2 1 0_0402_5% E10 H2
@ RT171 2 1 0_0402_5% G10 GPIO5 VOUT_3V3
@ RT340 2 1 0_0402_5% D7 GPIO6
PD2_GPIO8 H6 GPIO7
GPIO8: USB_TYPEC_FAULT# GPIO8 G1
RT218 2 1 100K_0402_5% TBTB_ROM_CLK_PD A3 LDO_3V3
RT219 2 1 100K_0402_5% TBTB_ROM_DI_PD B4 SPI_CLK
RT220 2 1 100K_0402_5% TBTB_ROM_DO_PD A4 SPI_MOSI
RT221 2 1 3.3K_0402_0.5% TBTB_ROM_CS#_PD B3 SPI_MISO K6
+3.3V_TBTB_FLASH SPI_SS_N C_USB_TP TBTB_TOP_P <30>
CHECK L6
UART_MOSI_R C_USB_TN TBTB_TOP_N <30>
2 1 L5
<24> TBTB_USB20_P USB_RP_P
1M_0402_5% RT343 K5
UART_MISO_R UART_MISO_R <24> TBTB_USB20_N USB_RP_N
2 1
<26> UART_MISO_R
@ 1M_0402_5% RT344 RT178 2 1 0_0402_5% E2 K7
UART_MOSI_R UART_TX C_USB_BP TBTB_BOT_P <30>
B F2 L7 B
<26> UART_MOSI_R UART_RX C_USB_BN TBTB_BOT_N <30>
@ RT180 2 1 0_0402_5% F4
@ RT181 2 1 0_0402_5% G4 SWD_DATA TI has 2x220pf
SWD_CLK TBTB_CC1 <30>
L9
C_CC1 L10
C_CC2 WHEN CONNECT BUSPOWERZ TO GND,

220P_0402_50V8J

220P_0402_50V8J
TBTB_MRESET TBTB_CC2 <30>
RT182 2 1 1M_0402_5% E11 CONNECT ALSO RPD_Gn to C_CCn 1 1
MRESET
K9 1 2 0_0402_5%

CT154

CT155
RT197
TBTB_LSTX RT183 1 2 0_0402_5% TBTB_LSTX_R L4 RPD_G1 K10 RT198 1 2 0_0402_5%
<24> TBTB_LSTX TBTB_LSRX RT184 1 2 0_0402_5% TBTB_LSRX_R K4 TBT_LSTX/R2P RPD_G2 +3.3V_TBTB_FLASH 2 2
<24> TBTB_LSRX TBT_LSRX/P2R

TBTB_LSTX @ RT185 1 2 0_0402_5% TBTB_DEBUG3 L3 E4 TBTB_DBG_CTL1 RT199 1 2 10K_0402_5%

TBTB_LSRX @ RT186 1 2 0_0402_5% TBTB_DEBUG4 K3 DIG_AUD_P/DEBUG3 DEBUG_CTL1 D5 TBTB_DBG_CTL2 RT200 1 2 10K_0402_5%
DIG_AUD_N/DEBUG4 DEBUG_CTL2

UPD2_SMBUS_CLK_Q 1 2 TBTB_DEBUG1 L2
UPD2_SMBUS_DAT_Q RT188 1 2 0_0402_5% TBTB_DEBUG2 K2 DEBUG1
RT189 0_0402_5% DEBUG2
K8 TBTB_SBU1_R RT201 1 2 0_0402_5%
TBTB_AUXP_C C_SBU1 TBTB_SBU1 <30>
CT156 1 2 0.1U_0201_10V6K J1
<24> TBTB_AUXP TBTB_AUXN_C AUX_P TBTB_SBU2_R
CT157 1 2 0.1U_0201_10V6K J2 L8 RT202 1 2 0_0402_5%
<24> TBTB_AUXN AUX_N C_SBU2 TBTB_SBU2 <30>
+3.3V_TBTB_FLASH
F10
BUSPOWER_N F11 TBTB_RESET_N_EC_R @ RT203 1 2 0_0402_5%
+3.3V_TBTB_FLASH RESET_N TBT_RESET_N_EC <24,26,37>
2 1 TBTB_AUXN_C TBTB_ROSC G2
100K_0402_5% RT204 R_OSC
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

GND
GND
GND
1

15K_0402_1%

SS
2

2 1 TBTB_AUXP_C @
0_0402_5%

RT194

100K_0402_5% RT205 TPS65982_BGA96

A1
D6
E5
E6
E7
F5
G5
H4
H5
B8
D8
E8
F6
F7
F8
G6
G7
G8
H7
H8
L1
L11
RT192

2
1

+VCC1V8D_TBTB_LDO 1 2
@ RT191 0_0402_5%
100K_0402_5%
1

0_0402_5%

1
1

RT195

@ RT196
0_0402_5%

CT158
RT193

A A
0.22U_0402_16V7K
@ 2
2

2
2

Need Link TPS65982D DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
[Type C]PD Controller TI-2
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. Size Document Number Rev
LA-E112P 0.1

Date: Friday, April 22, 2016 Sheet 27 of 58

5 4 3 2 1
 5 4 3 2 1

For kirkwood

+5V_ALW

D D

DT1 +5V_PD_VDD +3.3V_VDD_PIC

2 1
+5V_TBT_VBUS UT7
1N4148WS-7-F_SOD323-2 1 5
DT2 VCC VOUT
2 1 2
@ GND

0.1U_0201_10V6K

1U_0402_10V6K
1N4148WS-7-F_SOD323-2 1 1 3 4
EN ADJ/NC

2.2U_0603_25V6K

0.1U_0402_25V6K
1

1
CT88

CT89
@

CT91

CT92
1 2 AP2112K-3.3TRG1_SOT23-5
2 2 RT111 10K_0402_5%

2
2
1
@
CT90
100P_0402_50V8J
2

+TBTA_VBUS_1

UT8
place near UT7
1
VCC

1U_0603_50V6K
DT3 1
1 2+5V_TBTA_VBUS_D3
VOUT

CT94
2
1N4148WS-7-F_SOD323-2 GND
AP2204R-5.0TRG1_SOT89-3 2
1U_0402_10V6K

1
CT93

C C

2
+TBTB_VBUS_1

UT12
1
VCC

1U_0603_50V6K
DT38 1
1 2 +5V_TBTB_VBUS_D3
VOUT

CT167
2
1N4148WS-7-F_SOD323-2 GND
AP2204R-5.0TRG1_SOT89-3 2

B B

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD [Type C]PD Power-2
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. Size Document Number R ev
LA-E112P 0.1

Date: Friday, April 22, 2016 Sheet 28 of 58

5 4 3 2 1
 5 4 3 2 1

For AR Config

D D

Check ,FROM PWR PAGE

+TBTA_VBUS +TBTA_VBUS

RF Request
JUSBC1 +TBTA_VBUS
A1 B12
GND GND +TBTA_VBUS
CT95 1 2 0.22U_0201_6.3V6K TBTA_TX1P_C A2 B11 TBTA_RX1P
<24> TBTA_TX1P SSTXP1 SSRXP1 TBTA_RX1P <24>
CT96 1 2 0.22U_0201_6.3V6K TBTA_TX1N_C A3 B10 TBTA_RX1N
<24> TBTA_TX1N SSTXN1 SSRXN1 TBTA_RX1N <24>
2 1 A4 B9 1 2
CT99 0.47U_0201_25V VBUS VBUS CT100 0.47U_0201_25V

2
TBTA_CC1 A5 B8 TBTA_SBU2
<26> TBTA_CC1 CC1 SUB2 TBTA_SBU2 <26>
ESD@ DT4
TBTA_TOP_P_R TBTA_BOT_N_R

12P_0402_50V8J
RF@ CT189

82P_0402_50V8J
RF@ CT190
EMI@ RT120 1 2 0_0402_5% A6 B7 EMI@ RT122 1 2 0_0402_5% 1 1 L30ESD24VC3-2_SOT23-3
<26> TBTA_TOP_P TBTA_TOP_N_R DP1 DN2 TBTA_BOT_P_R TBTA_BOT_N <26>
EMI@ RT121 1 2 0_0402_5% A7 B6 EMI@ RT123 1 2 0_0402_5%

Bottom
C <26> TBTA_TOP_N DN1 DP2 TBTA_BOT_P <26> C
TBTA_SBU1 A8 B5 TBTA_CC2

TOP
<26> TBTA_SBU1 SUB1 CC2 TBTA_CC2 <26> 2 2
2 1 A9 B4 1 2
0.47U_0201_25V CT101 VBUS VBUS CT102 0.47U_0201_25V

1
TBTA_RX2N A10 B3 TBTA_TX2N_C 0.22U_0201_6.3V6K 2 1 CT98
<24> TBTA_RX2N TBTA_RX2P A11 SSRXN2 SSTXN2 B2 TBTA_TX2P_C TBTA_TX2N <24>
0.22U_0201_6.3V6K 2 1 CT97
<24> TBTA_RX2P SSRXP2 SSTXP2 TBTA_TX2P <24>
A12 B1
GND GND
1 2
3 GND GND 4
GND GND

JAE_DX07B024XJ1
CONN@

LINK JAE_DX07B024XJ1 DONE

20160321

ESD@ DT5 ESD@ DT13

TBTA_TX1P_C 1 2 TBTA_RX1P 1 2

ESD8011MUT5G_X3DFN2-2 ESD8011MUT5G_X3DFN2-2

B ESD@ DT6 ESD@ DT14 B

TBTA_TX1N_C 1 2 TBTA_RX1N 1 2

ESD8011MUT5G_X3DFN2-2 ESD8011MUT5G_X3DFN2-2

ESD@ DT7 ESD@ DT15

TBTA_CC1 1 2 TBTA_SBU2 1 2

ESD8011MUT5G_X3DFN2-2 ESD8011MUT5G_X3DFN2-2

ESD@ DT8 ESD@ DT16

TBTA_SBU1 1 2 TBTA_CC2 1 2

ESD8011MUT5G_X3DFN2-2 ESD8011MUT5G_X3DFN2-2

ESD@ DT9 ESD@ DT17

TBTA_RX2N 1 2 TBTA_TX2P_C 1 2

ESD8011MUT5G_X3DFN2-2 ESD8011MUT5G_X3DFN2-2

ESD@ DT10 ESD@ DT18

TBTA_RX2P 1 2 TBTA_TX2N_C 1 2

ESD8011MUT5G_X3DFN2-2 ESD8011MUT5G_X3DFN2-2

ESD@ DT11 ESD@ DT19

TBTA_TOP_P_R 1 2 TBTA_BOT_P_R 1 2

ESD8011MUT5G_X3DFN2-2 ESD8011MUT5G_X3DFN2-2

ESD@ DT12 ESD@ DT20

TBTA_TOP_N_R 1 2 TBTA_BOT_N_R 1 2
A A

ESD8011MUT5G_X3DFN2-2 ESD8011MUT5G_X3DFN2-2

PROPRIETARY NOTE: Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, USB 3.0 CONN TYPE C
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
0.1
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-E112P
Date: Friday, April 22, 2016 Sheet 29 of 58
5 4 3 2 1
 5 4 3 2 1

For kirkwood

D D

Check ,FROM PWR PAGE

+TBTB_VBUS +TBTB_VBUS

JUSBC2
A1 B12
GND GND
CT197 1 2 0.22U_0201_6.3V6K TBTB_TX1P_C A2 B11 TBTB_RX1P
<24> TBTB_TX1P TBTB_TX1N_C SSTXP1 SSRXP1 TBTB_RX1N TBTB_RX1P <24>
CT198 1 2 0.22U_0201_6.3V6K A3 B10 RF Request
<24> TBTB_TX1N SSTXN1 SSRXN1 TBTB_RX1N <24> +TBTB_VBUS
2 1 A4 B9 1 2
0.47U_0201_25V CT163 VBUS VBUS CT164 0.47U_0201_25V +TBTB_VBUS
TBTB_CC1 A5 B8 TBTB_SBU2
<27> TBTB_CC1 CC1 SUB2 TBTB_SBU2 <27>
EMI@ RT214 1 2 0_0402_5% TBTB_TOP_P_R A6 B7 TBTB_BOT_N_R EMI@ RT216 1 2 0_0402_5%
<27> TBTB_TOP_P TBTB_TOP_N_R DP1 DN2 TBTB_BOT_P_R TBTB_BOT_N <27>
EMI@ RT215 1 2 0_0402_5% A7 B6 EMI@ RT217 1 2 0_0402_5%

Bottom
C <27> TBTB_TOP_N DN1 DP2 TBTB_BOT_P <27> C

2
TBTB_SBU1 A8 B5 TBTB_CC2

TOP
<27> TBTB_SBU1 SUB1 CC2 TBTB_CC2 <27>
ESD@ DT21

12P_0402_50V8J
RF@ CT191

82P_0402_50V8J
RF@ CT192
2 1 A9 B4 1
2 1 1 L30ESD24VC3-2_SOT23-3
0.47U_0201_25V CT165 VBUS VBUS CT166 0.47U_0201_25V
TBTB_RX2N A10 B3 TBTB_TX2N_C 0.22U_0201_6.3V6K 2 1 CT200
<24> TBTB_RX2N TBTB_RX2P A11 SSRXN2 SSTXN2 B2 TBTB_TX2P_C 0.22U_0201_6.3V6K 2 1 TBTB_TX2N <24>
CT199
<24> TBTB_RX2P SSRXP2 SSTXP2 TBTB_TX2P <24> 2 2
A12 B1
GND GND

1
1 2
3 GND GND 4
GND GND

JAE_DX07B024XJ1
CONN@

LINK JAE_DX07B024XJ1 DONE

20160321

ESD@ DT22 ESD@ DT30

TBTB_TX1P_C 1 2 TBTB_RX1P 1 2

ESD8011MUT5G_X3DFN2-2 ESD8011MUT5G_X3DFN2-2

ESD@ DT23 ESD@ DT31

B
TBTB_TX1N_C 1 2 TBTB_RX1N 1 2 B

ESD8011MUT5G_X3DFN2-2 ESD8011MUT5G_X3DFN2-2

ESD@ DT24 ESD@ DT32

TBTB_CC1 1 2 TBTB_SBU2 1 2

ESD8011MUT5G_X3DFN2-2 ESD8011MUT5G_X3DFN2-2

ESD@ DT25 ESD@ DT33

TBTB_SBU1 1 2 TBTB_CC2 1 2

ESD8011MUT5G_X3DFN2-2 ESD8011MUT5G_X3DFN2-2

ESD@ DT26 ESD@ DT34

TBTB_RX2N 1 2 TBTB_TX2P_C 1 2

ESD8011MUT5G_X3DFN2-2 ESD8011MUT5G_X3DFN2-2

ESD@ DT27 ESD@ DT35

TBTB_RX2P 1 2 TBTB_TX2N_C 1 2

ESD8011MUT5G_X3DFN2-2 ESD8011MUT5G_X3DFN2-2

ESD@ DT28 ESD@ DT36

TBTB_TOP_P_R 1 2 TBTB_BOT_P_R 1 2

ESD8011MUT5G_X3DFN2-2 ESD8011MUT5G_X3DFN2-2

ESD@ DT29 ESD@ DT37

TBTB_TOP_N_R 1 2 TBTB_BOT_N_R 1 2

ESD8011MUT5G_X3DFN2-2 ESD8011MUT5G_X3DFN2-2
A A

PROPRIETARY NOTE: Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, USB 3.0 CONN TYPE C-2
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
0.1
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-E112P
Date: Friday, April 22, 2016 Sheet 30 of 58
5 4 3 2 1
 5 4 3 2 1

JTS2
LINK 50398-04041-001 DONE
JEDP1
1
20160308 1
2
1
2
3
TS_SPI_IRQ
TS_SPI_CS#_R
<6>
<8>
For Kirkwood
1 3 TS_SPI_CLK_R <8>
2 4
2 3 DMIC0 <36> 4 5 TS_SPI_SI_R <8>
3 4 5 6 TS_SPI_SO_R <8>
4 DMIC_CLK0 <36> 6
5 7
5 +3.3V_RUN GND +3.3V_TSP
6 8
6 USB20_N5_R +3.3V_CAM GND Link ACES_50208-0060N-P01 done

100P_0402_50V8J
@EMI@ CA5

100P_0402_50V8J
@EMI@ CA6
7
7 USB20_P5_R
8
8 ACES_50208-0060N-P01 20160315

1
9 TS_I2C_SDA 1 2
9 CAM_MIC_CBL_DET# <12> CONN@
10 +3.3V_TSP RV98 2.2K_0402_5%
10 Pin15: LOOP_BACK TS_I2C_SCL
11 JTS1 1 2

2
11 12 1 RV99 2.2K_0402_5%
12 +BL_PWR_SRC 1
13 2
13 2 PCH_PLTRST#_AND <11,24,34,39,40>
14 3
14 3 TOUCH_SCREEN_PD# <12>
15 4
D
15
16
16 EMI@ LV1 1
DISP_ON
2 BIA_PWM 4
5
5 TS_I2C_SDA
TS_I2C_SCL TS_I2C_SDA <9>
TOUCH_PANEL_PD#:  EXC24CQ900U_4P
D
17 BLM15BB221SN1D_2P EMI Request 6 Close lid >> TP_EN = 0 >> Disable touch events
17 18 6 7 TS_I2C_SCL <9> Open lid >> TP_EN = 1 >> Enable touch events 4 3
18 7 I2C0_IRQ_TS <6> USB20_N8_R USB20_N8 <10>
19 8
19 20 8 9 USB20_P8_R
20 21 9 10 TOUCH_SCREEN_DET# 1 2
21 EDP_HPD <6> +LCDVDD 10 TOUCH_SCREEN_DET# <12> USB20_P8 <10>
22
22 23 LV27 EMI@
23

1
EDP_HPD

10K_0402_5%

AZC199-02SPR7G_SOT23-3
24 1 2 KKW
24 LCD_TST <37>

@ESD@
25 @ RV7 100K_0402_5%
25

RV305
26

3
26 +LCDVDD
27 Reserve for EA
27 28 PANEL_SIZE_DET <12> 11 TS_SPI_CS#_R 1 2

2
28 EDP_AUXN_C CV1 GND

1
29 2 1 0.1U_0402_25V6 12 RF@CV50 33P_0402_50V8J
29 EDP_AUXP_C CV2 EDP_AUXN <6> GND TS_SPI_CLK_R

DV4
30 2 1 0.1U_0402_25V6 1 2
EDP_AUXP <6>

1
30 31 EDP_TXP0_C CV3 2 1 0.1U_0402_25V6 RF@CV51 33P_0402_50V8J
31 EDP_TXN0_C CV4 EDP_TXP0 <6> ACES_50208-01001-P03 TS_SPI_SI_R
32 2 1 0.1U_0402_25V6 1 2
32 33 EDP_TXP1_C CV5 2 1 EDP_TXN0 <6> CONN@
0.1U_0402_25V6 RF@CV52 33P_0402_50V8J
33 34 EDP_TXN1_C CV6 2 1 EDP_TXP1 <6> TS_SPI_SO_R 1 2
0.1U_0402_25V6
34 35 EDP_TXP2_C CV7 2 1 0.1U_0402_25V6
EDP_TXN1 <6> LINK ACES_50208-01001-P03 Done RF@CV53 33P_0402_50V8J
35 EDP_TXN2_C CV8 EDP_TXP2 <6> TS_I2C_SDA
41
42 G1 36
36
37 EDP_TXP3_C CV9
2
2
1
1
0.1U_0402_25V6
EDP_TXN2 <6> 20160321 ESD depop locat i on 1 2
0.1U_0402_25V6 RF@CV54 33P_0402_50V8J
43 G2 37 38 EDP_TXN3_C CV10 2 1 EDP_TXP3 <6> TS_I2C_SCL 1 2
0.1U_0402_25V6
G3 38 EDP_TXN3 <6>
44 39 RF@CV55 33P_0402_50V8J
45 G4 39 40
G5 40 LCD_CBL_DET# <9>
RF Request
ACES_50398-04041-001
CONN@
RF Request
+3.3V_TSP
+BL_PWR_SRC +LCDVDD +3.3V_CAM +3.3V_TSP +3.3V_RUN
+3.3V_RUN
0.1U_0603_50V7K

0.1U_0201_10V6K

0.1U_0201_10V6K

0.1U_0201_10V6K

0.1U_0201_10V6K

10K_0402_5%
1 1 1 1
1

2
@

@ @ @ @

RV8
CV11

CV12

CZ1

CZ2

CA7
JIR1
2

2 2 2 2 +PWR_SRC

12P_0402_50V8J
RF@ CV18

82P_0402_50V8J
RF@ CV19
1 1 1
C 1 IR_CAM_DET# <12> C
2

1
2 3 TOUCH_SCREEN_DET#
3

100P_0402_50V8J
RF@ CZ3
4 1
2 2 4 5
Close to JEDP1.17~19 Close to JEDP1.30~31 Close to JEDP1.11 Close to JEDP1.1 Close to JEDP1.10
5 6
6 +PWR_SRC
7
GND 8 2
DV1 DV2 GND
ACES_50208-0060N-P01
3 EDP_BIA_PWM 3
EDP_BIA_PWM <6> PANEL_BKLEN <6> CONN@
BIA_PWM DISP_ON
RF Request
1 1
2 BIA_PWM_EC 2 Link ACES_50208-0060N-P01 done
BIA_PWM_EC <37> PANEL_BKEN_EC <37>
20160315
1
4.7K_0402_5%

4.7K_0402_5%
1

BAT54CW_SOT323-3 BAT54CW_SOT323-3
RV1

RV2
2

For Touchscreen
2

CHECK Power Rail

+3.3V_RUN +3.3V_TSP +3.3V_RUN

RF Request QV8

10K_0402_5%
LP2301ALT1G_SOT23-3

2
+LCDVDD +3.3V_CAM +BL_PWR_SRC 1 3

RV6

S
G
1

2
12P_0402_50V8J
RF@ CV20

82P_0402_50V8J
RF@ CV21

12P_0402_50V8J
RF@ CV22

82P_0402_50V8J
RF@ CV23

12P_0402_50V8J
RF@ CV24

82P_0402_50V8J
RF@ CV25

1 1 1 1 1 1

L2N7002WT1G_SC-70-3
B B

1
D
2 2 2 2 2 2

QV7
1 2 2
<9> 3.3V_TS_EN
RV306 0_0402_5% G
S

3
LCDVDD POWER +LCDVDD +EDP_VDD

WebCAM Backlight POWER +BL_PWR_SRC

+3.3V_ALW

@
CV16 PJP12 UV24
2 1 1 2 1
+PWR_SRC QV1 VOUT 5
10U_0603_10V6M VIN
+3.3V_CAM +3.3V_RUN 6 PAD-OPEN1x1m 2
D

GND

0.01UF_0402_25V7K
4 5 4
S

EN

@
QZ1 2

CV17
LP2301ALT1G_SOT23-3 1 3
1000P_0402_50V7K

/OC
0.1U_0603_50V7K
G
270K_0402_5%
2

1 3 AO6405_TSOP6 G524B1T11U_SOT23-5
D

CV13

2
2

DV3
RV4

CV15

2
G

<37> LCD_VCC_TEST_EN
2

1 EN_LCDPWR
1

3
<11> 3.3V_CAM_EN# <6,37> ENVDD_PCH

2
BL_PWR_SRC_ON

100K_0402_5%
RV3
QV2 BAT54CW_SOT323-3
L2N7002WT1G_SC-70-3
0.01U_0402_50V7K

1
A A
1 2 1 3
D

S
CV14

RV5 47K_0402_5%
EXC24CQ900U_4P
4 3 USB20_P5_R 2
G

<10> USB20_P5
2

1 2 USB20_N5_R
<10> USB20_N5 <37> EN_INVPWR
LZ1 EMI@ DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, eDP CONN & Touch screen
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
0.1
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-E112P
Date: Friday, April 22, 2016 Sheet 31 of 58
5 4 3 2 1
 A B C D E

RF Request
+3.3V_MMI_IN For USB Interface

12P_0402_50V8J
@RF@ CR25

82P_0402_50V8J
@RF@ CR26
1 1

2 2

1 1

+3.3V_MMI_IN

close to UR1.8 close to UR1.27 close to UR1.11

+3.3V_MMI_IN
4.7U_0603_6.3V6K

0.1U_0201_10V6K

4.7U_0603_6.3V6K

0.1U_0201_10V6K

10U_0402_6.3V6M

0.1U_0201_10V6K
+3.3V_RUN +3.3V_MMI_IN UR1
PJP14
1 1 1 1 11
3V3_IN
1

CR29
1 2 12
CR1

CR3
+3.3V_RUN_CARD
CR2

CR4

CR30
27 SD_3V3
D3V3 13 +1.8V_RUN_CARD
2

2
2 2 2 2 PAD-OPEN1x2m 8 SD40_VDD2
A3V3 14 +SDREG2 1 2
6 SDREG CR15 1U_0402_6.3V6K
+1.2V_LDO +SD40_AV12 AV12
24
VDD_LANE 30 SDWP SD/MMCCLK_R
+DV_12S SD_WP

@EMI@ CR21
21 31 SD/MMCCD#
DV12S SD_CD#

5P_0402_50V8C
+1.2V_LDO 1 2 USB20_P6_R 9
<10> USB20_P6 DP

1
RR20 1 20_0402_5% USB20_N6_R 10 17 SD/MMCCLK EMI@ RR5 1 2 0_0402_5% SD/MMCCLK_R
<10> USB20_N6
close to UR1.6 close to UR1.24 close to UR1.21 RR21 0_0402_5% DM SD_CLK 18 SD/MMCCMD RR6 1 2 0_0402_5% SD/MMCCMD_R
CR31 1 2 0.1U_0402_25V6 USB3_PTX_C_DRX_P4 2 SD_CMD
<10> USB3_PTX_DRX_P4 close to UR1.17

2
Swap TX/RX (Based on Vendor Review) CR32 1 2 0.1U_0402_25V6 USB3_PTX_C_DRX_N4 3 SS_RX+
+SD40_AV12 +DV_12S 20160323 <10> USB3_PTX_DRX_N4 SS_RX-
CR13 1 2 0.1U_0402_25V6 USB3_PRX_C_DTX_P4 4 19 SD/MMCDAT3 RR7 1 2 0_0402_5% SD/MMCDAT3_R
<10> USB3_PRX_DTX_P4 CR14 1 2 0.1U_0402_25V6 USB3_PRX_C_DTX_N4 5 SS_TX+ SD_D3 20 SD/MMCDAT2 RR8 1 2 0_0402_5% SD/MMCDAT2_R
<10> USB3_PRX_DTX_N4 SS_TX- SD_D2 SD/MMCDAT1/RCLK-_R EMI depop locat i on
4.7U_0603_6.3V6K

0.1U_0201_10V6K

1U_0402_6.3V6K

4.7U_0603_6.3V6K

0.1U_0201_10V6K
15 SD/MMCDAT1/RCLK- RR9 1 2 0_0402_5%
29 SD_D1 16 SD/MMCDAT0/RCLK+ RR10 1 2 0_0402_5% SD/MMCDAT0/RCLK+_R
1 1 XTLI SD_D0
1

28
CR5

CR9
CR6

CR10
XTLO
CR8

1 2 SD_GPIO 32 22 SD_UHS2_D1P
+3.3V_MMI_IN
2

2 2 2 GPIO0 SD40_D1+ SD_UHS2_D1N 2

RR3 10K_0402_5% 23
1 SD40_D1- 26 SD_UHS2_D0P
GPIO1 SD40_D0+ 25 SD_UHS2_D0N
1 2 +RREF 7 SD40_D0-
RR4 6.2K_0402_1% RREF 33
EPAD

RTS5330-GR_QFN32_4X4

20160304 CIS Link

3 3

QR1
L2N7002WT1G_SC-70-3
HOST_SD_W P# SDW P_Q SDW P STATUS
SDWP 1 3 SDWP_Q JSD1

S
4
+3.3V_RUN_CARD VDD1
High High Write Protect(SD LOCK) +1.8V_RUN_CARD 15
SD/MMCCMD_R 3 VDD2

G
2
High SD/MMCCLK_R 5 CMD
Low Low Write Enable CLK
<12> HOST_SD_WP#
SD/MMCCD# 9
SDWP_Q 16 CD
High High Write Protect(SD& FW LOCK) SWIO
Low SD/MMCDAT0/RCLK+_R 7
SD/MMCDAT1/RCLK-_R 8 DAT0/RCLK+
Low High Write Protect(FW LOCK) SD/MMCDAT2_R 1 DAT0/RCLK-
+3.3V_RUN_CARD +1.8V_RUN_CARD SD/MMCDAT3_R 2 DAT2
CD/DAT3

SD_UHS2_D0P 18
SD_UHS2_D0N 19 D0+

0.1U_0201_10V6K

0.1U_0201_10V6K
4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
SD_UHS2_D1P 22 D0-
2 2

2
SD_UHS2_D1N 21 D1+

CR17

CR19

CR20
D1-

CR18
10

1
1 1 6 GND1 11
17 VSS1 GND2 12
20 VSS2 GND3 13
23 VSS3 GND4 14
VSS4 GND5
T-SOL_158-1240902600
CR38,CR39 near JSD1.4 CR40,CR41 near JSD1.14 CONN@

LINK T-SOL_158-1240902600 DONE

4
20160329 4

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Card Reader RTS5330
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 0.1
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-E112P
Date: Friday, April 22, 2016 Sheet 32 of 58
A B C D E
 5 4 3 2 1

Only for Kirkwood

PCIE/USB MUX
D
NEED LINK TI HD3SS3212 as main D

+3.3V_WWAN

.1U_0402_16V7K

.1U_0402_16V7K
1 1

CZ154

CZ155
2 2

UZ29
USB3_PRX_DTX_P2 19 1
<10> USB3_PRX_DTX_P2 USB3_PRX_DTX_N2 18 B0+ VDD 6
<10> USB3_PRX_DTX_N2 2 0.1U_0402_10V7K USB3_PTX_C_DRX_P2 B0- VDD
CZ150 1 17 10
<10> USB3_PTX_DRX_P2 B1+ VDD
CZ151 1 2 0.1U_0402_10V7K USB3_PTX_C_DRX_N2 16
<10> USB3_PTX_DRX_N2 B1-
PCIE_PRX_DTX_P7 15 3 PCIE_PRX_SW_DTX_P7
<10> PCIE_PRX_DTX_P7 PCIE_PRX_DTX_N7 C0+ A0+ PCIE_PRX_SW_DTX_N7 PCIE_PRX_SW_DTX_P7 <34>
14 4
<10> PCIE_PRX_DTX_N7 C0- A0- PCIE_PRX_SW_DTX_N7 <34>
CZ152 1 2 0.22U_0402_10V6K PCIE_PTX_C_SW_DRX_P7 13 7 PCIE_PTX_SW_DRX_P7
<10> PCIE_PTX_DRX_P7 C1+ A1+ PCIE_PTX_SW_DRX_P7 <34>
CZ153 1 2 0.22U_0402_10V6K PCIE_PTX_C_SW_DRX_N7 12 8 PCIE_PTX_SW_DRX_N7
<10> PCIE_PTX_DRX_N7 C1- A1- PCIE_PTX_SW_DRX_N7 <34>
SLOT2_CONFIG_1 9 5
<34,37> SLOT2_CONFIG_1 SEL GND 11
2 GND 20
PD GND
21
PGND
C C
PI3PCIE3212ZBEX_TQFN20_2P5X4P5
Function SEL PD
B to A L L
C to A H L
All ports Hi-Z,
IC power down X H

STATE # CONFIG_0 CONFIG_1 CONFIG_2 CONFIG_3 Module Type

0 GND GND GND GND SSD-SATA

1 GND HIGH GND GND SSD-PCIE(2 lane)

8 HIGH GND GND GND WWAN

14 HIGH GND HIGH HIGH HCA-PCIE(1 lane)

15 HIGH HIGH HIGH HIGH NA

B B

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, USB/PCIE MUX
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. Size Document Number R ev
LA-E112P 0.1

Date: Friday, April 22, 2016 Sheet 33 of 58

5 4 3 2 1
 5 4 3 2 1

+3.3V_WWAN
NGFF slot A Key A Only for Kirkwood
NGFF slot B Key B 80148-3221&80148-4221 Footprint the same
+3.3V_WLAN
JNGFF1 CONN@
2 1 W W AN_PW R_EN 1 2
RZ43 47K_0402_5% +3.3V_WWAN USB20_P7_L 3 1 2 4
USB20_N7_L 3 4

100P_0402_50V8J
5 6
5 6

RF@ CZ198
JNGFF2 7
1 2 7
<37> SLOT2_CONFIG_3 GND VCC

1
3 4
5 GND VCC 6 W W AN_PW R_EN
USB20_P4_L 7 GND Full_Card_Power_Off# 8 WWAN_RADIO_DIS#_R 8

2
USB20_N4_L 9 USB_D+ W_DISABLE#1 10 SLOT2_SATA_LED# 1 2 9 8 10
USB_D- LED#1 SATALED# <10,40,44> SW 2_DP2_N3_C 9 10 SW 2_DP2_AUXN_C
11 RN101 0_0402_5% 1 2 11 12 2 1
GND <22> SW2_DP2_N3 11 12 SW2_DP2_AUXN <22>
CV145 1 2 0.1U_0402_25V6 SW 2_DP2_P3_C 13 14 SW 2_DP2_AUXP_C
0.1U_0402_25V6 2 1CV150
<22> SW2_DP2_P3 13 14 SW2_DP2_AUXP <22>
CV146 0.1U_0402_25V6 15 16 0.1U_0402_25V6 CV149
D 1 2 SW 2_DP2_N2_C 17 15 16 18 SW 2_DP2_N1_C 2 1 D
<22> SW2_DP2_N2 17 18 SW2_DP2_N1 <22>
20 CV148 1 2 0.1U_0402_25V6 SW 2_DP2_P2_C 19 20 SW 2_DP2_P1_C0.1U_0402_25V6 2 1CV152
NC <22> SW2_DP2_P2 19 20 SW2_DP2_P1 <22>
21 22 CV147 0.1U_0402_25V6 21 22 0.1U_0402_25V6 CV153
<37> SLOT2_CONFIG_0 NC(CONFIG_0) NC 21 22 SW 2_DP2_N0_C
23 24 23 24 2 1
<37> WWAN_WAKE# P_SENSOR_ACK#_R WAKE_ON_WAN# NC HW _GPS_DISABLE#_R <22> SW2_DP2_HPD 23 24 SW 2_DP2_P0_C0.1U_0402_25V6 SW2_DP2_N0 <22>
2 1 25 26 CZ304 close 25 26 2 1CV156
DRR W_DISABLE#2 PCIE_PTX_C_DRX_P5 25 26 SW2_DP2_P0 <22>
RF@ RZ326 0_0402_5% 27 28 CZ12 1 2 0.1U_0402_25V6 27 28 0.1U_0402_25V6 CV157
PCIE_PRX_L_DTX_N7 29 GND NC 30 UIM_RESET JNGFF2 <10> PCIE_PTX_DRX_P5
CZ13 1 2 0.1U_0402_25V6 PCIE_PTX_C_DRX_N5 29 27 28 30
PCIE_PRX_L_DTX_P7 NC UIM-RESET UIM_CLK <10> PCIE_PTX_DRX_N5 29 30 PCH_CL_RST1# <8>
31 32 RF@ CZ304 1 2 68P_0402_50V8J 31 32
NC UIM-CLK UIM_DATA 31 32 PCH_CL_DATA1 <8>
33 34 33 34
support PCIE & SATA PCIE_PTX_L_DRX_N7 35 GND UIM-DATA 36
+SIM_PWR
WLAN <10> PCIE_PRX_DTX_P5 35 33 34 36 PCH_CL_CLK1 <8>
PCIE_PTX_L_DRX_P7 37 NC UIM-PWR 38 <10> PCIE_PRX_DTX_N5 37 35 36 38
NC NC ISH_I2C2_SCL_R M3042_DEVSLP <10> 37 38
Double check P/N PIN for SATA/PCIE 39 40 2 1 39 40
GND GNSS_SCL ISH_I2C2_SDA_R ISH_I2C2_SCL <9> <11> CLK_PCIE_P1 39 40 W IGIG_32KHZ
41 42 @ RZ76 2 1 0_0402_5% 41 42 2 1
<10> PCIE_PRX_DTX_P8 NC GNSS_SDA ISH_I2C2_SDA <9> <11> CLK_PCIE_N1 41 42 PCH_PLTRST#_AND SUSCLK <11,40>
43 44 @ RZ77 0_0402_5% 43 44 0_0402_5% RZ56
<10> PCIE_PRX_DTX_N8 NC GNSS_IRQ 43 44 BT_RADIO_DIS#_R PCH_PLTRST#_AND <11,24,31,39,40>
45 46 9/24: Reserve for embedded locat i on , r ef er I nt el P DG 0. 9 45 46
GND SYS_CLK(GNSS0) PORT80_DET# <37> <11> CLKREQ_PCIE#1 45 46
CZ10 1 2 0.1U_0402_25V6 PCIE_PTX_C_DRX_N8 47 48 PCIE_W AKE# 47 48 WLAN_WIGIG60GHZ_DIS#_R
<10> PCIE_PTX_DRX_N8 HOST_DEBUG_TX <37,38> <24,38,40> PCIE_WAKE#
CZ11 1 2 0.1U_0402_25V6 PCIE_PTX_C_DRX_P8 49 NC TX_BLANKING(GNSS1) 50 PCH_PLTRST#_AND 49 47 48 50 ISH_UART0_RXD_R 2 1
<10> PCIE_PTX_DRX_P8 NC NC PCIE_PTX_C_DRX_P6 49 50 ISH_UART0_TXD_R @ RZ78 2 ISH_UART0_RXD <9>
51 52 CZ14 1 2 0.1U_0402_25V6 51 52 1 0_0402_5%
GND NC PCIE_W AKE# CLKREQ_PCIE#0 <11> <10> PCIE_PTX_DRX_P6 PCIE_PTX_C_DRX_N6 51 52 ISH_UART0_CTS#_R @ RZ79 2 ISH_UART0_TXD <9>
53 54 CZ15 1 2 0.1U_0402_25V6 53 54 1 0_0402_5%
<11> CLK_PCIE_N0 NC NC <10> PCIE_PTX_DRX_N6 53 54 ISH_UART0_RTS#_R @ RZ80 2 ISH_UART0_CTS# <9>
55 56 55 56 1 0_0402_5%
<11> CLK_PCIE_P0 NC NC 55 56 PCH_PLTRST#_AND @ RZ81 ISH_UART0_RTS# <9>
57 58 57 58 0_0402_5%
2 1 WWAN_ANTCTL0 59 GND NC 60 <10> PCIE_PRX_DTX_P6 59 57 58 60
<35> WWAN_ANTCTL0_R RF@RZ327 2 1 0_0402_5% W W AN_ANTCTL1 61 ANTCTL0 Coex3 62 WIGI <10> PCIE_PRX_DTX_N6 61 59 60 62 PCIE_W AKE# CLKREQ_PCIE#2 <11>
<35> WWAN_ANTCTL1_R RF@RZ328 2 1 0_0402_5% W W AN_ANTCTL2 63 ANTCTL1 Coex2 64 63 61 62 64
<35> WWAN_ANTCTL2_R W W AN_ANTCTL3 ANTCTL2 Coex1 SIM_DET <11> CLK_PCIE_P2 63 64
RF@RZ329 2 1 0_0402_5% 65 66 65 66
9/24: Reserve for embedded locat i on , r ef er I nt el P DG 0. 9
<35> WWAN_ANTCTL3_R ANTCTL3 SIM Detect <11> CLK_PCIE_N2 65 66
RF@RZ330 0_0402_5% PAD~D @ T225 67 68 67
69 RESET# NC 70 67
<33,37> SLOT2_CONFIG_1 GND (CONFIG_1) VCC
71 72
73 GND VCC 74 69 68
GND VCC GND GND
68P_0402_50V8J

68P_0402_50V8J

68P_0402_50V8J

68P_0402_50V8J

75
@RF@ CZ303

@RF@ CZ302

@RF@ CZ301

@RF@ CZ300

<37> SLOT2_CONFIG_2 GND (CONFIG_2) 76

GND 77
GND
1

CONCR_213AAAA32FA
LOTES_APCI0124-P001A
CONN@
2

Wait CIS symbol

C
Wait CIS symbol C

RF Request
+3.3V_WWAN
+3.3V_WWAN
.047U_0402_16V7K

.047U_0402_16V7K

33P_0402_50V8J

33P_0402_50V8J

+3.3V_WLAN
47P_0402_50V8J

100P_0402_50V8J

2200P_0402_50V7K
RF@

WWAN_RADIO_DIS#_R
22U_0603_6.3V6M

RF@ CZ24

100U_B2_6.3VM_R35M
RF@CZ26

1 1 2
RF@ CZ25

<37> WWAN_RADIO_DIS#
1

1
CZ17

CZ18

CZ19

CZ20

CZ21

0.1U_0201_10V6K

.047U_0402_16V7K

.047U_0402_16V7K

0.1U_0201_10V6K

0.1U_0201_10V6K

4.7U_0603_6.3V6K
+ DZ5
WLAN_WIGIG60GHZ_DIS#_R
CZ23

RB751S40T1G_SOD523-2 1 2
<37> WLAN_WIGIG60GHZ_DIS#
2

1 1 1
2

1
2 DZ1 @

CZ27

CZ28

CZ29

CZ30

CZ31

CZ32
RB751S40T1G_SOD523-2
1 2 HW_GPS_DISABLE#_R
<37> HW_GPS_DISABLE#

2
2 2 2
DZ6
RB751S40T1G_SOD523-2

1 2 1 2 BT_RADIO_DIS#_R
<37> BT_RADIO_DIS# RF Request
@RF@ RI27 0_0402_5% +1.8V_RUN
HCM1012GH900BP_4P DZ2 +3.3V_WLAN

1
+3.3V_RUN RB751S40T1G_SOD523-2
1 2 PCIE_PRX_L_DTX_N7 RZ344
<33> PCIE_PRX_SW_DTX_N7 10K_0201_1%

2
PCIE_PRX_L_DTX_P7

15P_0402_50V8J

2.2P_0402_50V8C

12P_0402_50V8J

15P_0402_50V8J
4 3 RF Request

2
<33> PCIE_PRX_SW_DTX_P7

RF@ CZ33

RF@ CZ34

RF@ CZ35

RF@ CZ36
RF@ LI16 1 3 P_SENSOR_ACK#_R 1 2
<38> SAR_DPR#

1
1 2 @RF@ RI49 0_0402_5%

S
@RF@ RI28 0_0402_5%
1 2 DMN65D8LW -7_SOT323-3

2
@RF@ RI29 0_0402_5% Q1
HCM1012GH900BP_4P

1 2 PCIE_PTX_L_DRX_N7
<33> PCIE_PTX_SW_DRX_N7
LI9 RF@
1 2 USB20_N7_L
B <10> USB20_N7 B
4 3 PCIE_PTX_L_DRX_P7
<33> PCIE_PTX_SW_DRX_P7
RF@ LI17 4 3 USB20_P7_L
<10> USB20_P7
1 2 RF Request
@RF@ RI30 0_0402_5% EXC24CQ900U_4P
1 2
SIM Card Push-Push @RF@ RI47 0_0402_5%

+SIM_PWR
@RF@ RI50
1 2
0_0402_5%
Power Rating TBD
JSIM1
4.7U_0402_6.3V6M

1 5 Primary Power Aux Power

UIM_RESET 2 VCC GND 6
RST VPP PWR Voltage
1

UIM_CLK 3 7 UIM_DATA LI8 RF@

CLK I/O USB20_P4_L Rail Tolerance
CZ37

4 8 1 2 Peak Normal Normal

NC NC <10> USB20_P4
2

9
DLSW 10 SIM_DET 4 3 USB20_N4_L
DTSW <10> USB20_N4 +3.3V
11 14 EXC24CQ900U_4P
12 GND GND 15
13 GND GND 16
GND GND 17
GND 1 2
JAE_SF51S006V4B @RF@ RI48 0_0402_5%
CONN@

JAE_SF51S006V4DR1000Q LINK DONE

20160321 (Temp symbol is correct, SP number is wrong on DTSW)

+SIM_PWR

UIM_CLK
@RF@ RZ335
1
15K_0402_5%
47P_0402_50V8J

A A
@RF@ CZ38
1

+SIM_PWR
UIM_DATA UIM_RESET
2

33P_0402_50V8J

33P_0402_50V8J
@RF@ RZ334
1
51_0402_5%

RF@CZ39

RF@CZ40

0.1U_0402_25V6
RF@ CZ41

1 1 1
DELL CONFIDENTIAL/PROPRIETARY
2 2 2 Compal Electronics, Inc.
2

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT NGFF Card
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 0.1
RF Request PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-E112P
Date: Friday, April 22, 2016 Sheet 34 of 58
5 4 3 2 1
 5 4 3 2 1

D D

Only for Kirkwood

+3.3V_WWAN_MAIN

Annt. Control

0.1U_0201_10V6K
1

CZ186
JTUN1 2
RF@RZ331 2 1 0_0402_5% +3.3V_WWAN_MAIN 1
+3.3V_WWAN +3.3V_WWAN_AUX 1
+3.3V_WWAN RF@RZ332 2 1 0_0402_5% 2
WWAN_ANTCTL0_R 3 2
<34> WWAN_ANTCTL0_R WWAN_ANTCTL1_R 3
4
<34> WWAN_ANTCTL1_R WWAN_ANTCTL2_R 4
5
<34> WWAN_ANTCTL2_R WWAN_ANTCTL3_R 5
6
<34> WWAN_ANTCTL3_R 6
7
8 7
C 8 C

9
10 GND +3.3V_WWAN_AUX
GND
ACES_50208-00801-003

0.1U_0201_10V6K
CONN@

Link ACES_50208-00801-003 done

1

20160315

CZ187
RF@CZ180 68P_0402_50V8J
+3.3V_WWAN_MAIN 1 2
RF@CZ181 68P_0402_50V8J 2
+3.3V_WWAN_AUX 1 2
RF@CZ182 68P_0402_50V8J
WWAN_ANTCTL0_R 1 2
RF@CZ183 68P_0402_50V8J
WWAN_ANTCTL1_R 1 2
RF@CZ184 68P_0402_50V8J
WWAN_ANTCTL2_R 1 2
RF@CZ185 68P_0402_50V8J
WWAN_ANTCTL3_R 1 2

B B

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT RF Tunable Conn
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 0.1
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-E112P
Date: Friday, April 22, 2016 Sheet 35 of 58
5 4 3 2 1
 2 1

+3.3V_RUN_AUDIO
SPKR_R
+3.3V_RUN_AUDIO_DVDD

100P_0402_50V8J
2 1

10K_0402_5%
LA14 BLM15PX600SN1D_2P

1
BEEP_R

@ CA72

@ RA51
+1.8V_RUN +3.3V_RUN_AUDIO_IO

0.1U_0201_10V6K

10U_0603_10V6M

100P_0402_50V8J
2 1

10K_0402_5%
1 LA12 BLM15PX600SN1D_2P

2
1

1
+1.8V_RUN_AUDIO

CA10

CA61

0.1U_0201_10V6K

10U_0603_10V6M

@ CA62

@ RA45
1W x 1ch, 4ohm (Transducer spec is 8Ohm/0.5Watt per unit, there are two transducer units in one speaker box.) 1 2 place close to pin16
RA3 0_0603_5% 1
Internal Speakers Header

2
1
10U_0603_10V6M

0.1U_0201_10V6K

CA55

CA56
2

2
2
1

CA58

CA57
40 mils trace keep 20 mil spacing

2
JSPK1 2
INT_SPK_L+ 1 2 INT_SPKR_L+ 1 7
EMI@ LA6 BLM15PX330SN1D_2P need link SM01000NS00

2
INT_SPK_L- EMI@ LA7 1 2 BLM15PX330SN1D_2P INT_SPKR_L- 2 1 G1 2
INT_SPK_R+ EMI@ LA8 1 2 BLM15PX330SN1D_2P INT_SPKR_R+ 3 2 Realtek suggest rated current : 2A
INT_SPK_R- EMI@ LA9 1 2 BLM15PX330SN1D_2P INT_SPKR_R- 4 3
SPK_DET# 5 4 +5V_RUN_AUDIO +5V_RUN_AUDIO
<12> SPK_DET# 5 LA13

L03ESDL5V0CC3-2_SOT23-3

L03ESDL5V0CC3-2_SOT23-3
6 8 LA5 place close to pin41 place close to pin46
6 G2

3
2 1 +VDDA_AVDD1 +5V_RUN_PVDD_L 1 2
place close to pin40

@ESD@

@ESD@
ACES_50278-00601-001 BLM15PX600SN1D_2P FBMA-L11-201209601LMA20T_2P

10U_0603_10V6M

0.1U_0201_10V6K

0.1U_0201_10V6K

10U_0603_10V6M

0.1U_0201_10V6K

10U_0603_10V6M

0.1U_0201_10V6K

10U_0603_10V6M
CONN@ 1 1 1 1 1 1
@EMI@ CA22

@EMI@ CA23

@EMI@ CA19

@EMI@ CA24

CA45

CA47

CA60
1 600 Ohm/2A

1
1000P_0402_50V7K

1000P_0402_50V7K

1000P_0402_50V7K

1000P_0402_50V7K

CA8

CA46

CA48

CA59
@ RA54 1 2 0_0402_5% RF Request
Change to 6pin to support 2 SPK vendor +5V_ALW
1

CA9
2 2 2 2 2 2
Link ACES_50278-00601-001 DONE +5V_RUN_AUDIO

DA6

DA7
RA55 1 2 0_0402_5%
+RTC_CELL

2
2
20160325
2

1
UA1

40

16

21

12

41

46

47
4
+3.3V_RUN

AVDD1

AVDD2

DVDD-IO

PVDD1

PVDD2

5VSTB/AUX MODE
CPVDD

DVDD

12P_0402_50V8J
RF@ CA63

68P_0402_50V8J
RF@ CA64
1 1

1
Close to UA1 AUD_HP_OUT_R HP_OUT_R
2 1 25
RA58 24.9_0402_1% RA8 HP-OUT-R 36
10K_0402_5% AUD_HP_OUT_L 2 1 HP_OUT_L 26 LINE2-L 2 2
24.9_0402_1% RA7 HP-OUT-L 35

2
SPK_DET# 19 LINE2-R
B HP-OUT2-L 34 LINE1_L 1 2 HP_OUT_L B
20 LINE1-L CA43 10U_0603_10V6M AUD_HP_OUT_L/ AUD_HP_OUT_Rplease keep 15 mils trace width
HP-OUT2-R 33 LINE1_R 1 2 HP_OUT_R
LINE1-R CA44 10U_0603_10V6M
Close to UA1 pin6 32 AUD_PC_BEEP 2 1 SPKR_R 1 2
PCBEEP BEEP_R SPKR <12>
15 CA27 2 1 0.1U_0402_25V6 RA12 1 2 1K_0402_5%
HDA_BIT_CLK_R DMIC_CLK0 LINE1-VREFO-R-E/MONO BEEP <37>
30 SLEEVE CA28 0.1U_0402_25V6 RA13 1K_0402_5%
SLEEVE
@EMI@ RA17

@EMI@ CA54

14
LINE1-VREFO-L-E
10P_0402_50V8J

29 RING2 SLEEVE/RING2 please keep 40 mils trace width

RING2
1

1
33_0402_5%

27 +MIC2-VREFO-L 2 1 RING2 RF Request

HDA_BIT_CLK_R 8 MIC2-VREFO-L RA5 2.2K_0402_5%
<12> HDA_BIT_CLK_R
2

BCLK 28 +MIC2-VREFO-R 2 1 SLEEVE +1.8V_RUN_AUDIO +1.8V_RUN

9 MIC2-VREFO-R RA6 2.2K_0402_5%
<12> HDA_SYNC_R
2

SYNC
HDA_SDIN0_R
10P_0402_50V8J
@EMI@ CA33

1 2 10
<12> HDA_SDIN0 RA9 33_0402_5% SDATA-IN 23
place close to UA1 pin6 CBN
1

HDA_SDOUT_R 11
<12> HDA_SDOUT_R Place RA9 close to codec SDATA-OUT Place CA29 close to Codec

RF@ CA69
22 2 1
CBP

33P_0402_50V8J
CA29 1U_0603_10V6K
2

12P_0402_50V8J
RF@ CA65

68P_0402_50V8J
RF@ CA66
1 1 1
2 7
SPDIFO/GPIO2 DC DET/EAPD
5 1 2 2 2 2
<31> DMIC0 GPIO0/DMIC-DATA RA44 100K_0402_5%
DMIC_CLK0 1 2 DMIC_CLK_CODEC 6 39 1 2
<31> DMIC_CLK0 EMI@ RA14 22_0402_5% GPIO1/DMIC-CLK LDO1-CAP CA51 10U_0603_10V6M
17 1 2
LDO2-CAP CA52 10U_0603_10V6M
+3.3V_RUN_AUDIO INT_SPK_L+ 42 13 1 2
SPK-L+ LDO3-CAP CA53 10U_0603_10V6M
INT_SPK_L- 43
Place closely to Pin 14. SPK-L- 1 2
+3.3V_RUN_AUDIO
100K_0402_1% 200K_0402_1%
1

INT_SPK_R- 44 RA18 10K_0402_5%

SPK-R-
RA59

INT_SPK_R+ 45 3 PD# 1 2
SPK-R+ PD CA31 1U_0603_10V6K RF Request
24 1 2
2

AUD_SENSE_A CPVEE CA49 1U_0603_10V6K +3.3V_RUN_AUDIO

AUD_SENSE_A
0.1U_0402_25V6

1 31 1 2
HP1/LINE1 JD MIC2-CAP
1

@ CA41

CA25 10U_0603_10V6M

AVSS2

AVSS1

PGND
48 38 1 2
RA60

HP2/LINE2 JD VREF CA35 2.2U_0402_6.3V6M

2

ALC3253-CG_MQFN48_6X6
2

18

37

49
AUD_HP_NB_SENSE
Add for solve

12P_0402_50V8J
RF@ CA67

68P_0402_50V8J
RF@ CA68
pop noise and 1 1
detect issue
2 2

CLASS-D POWER DOWN CONTROL CIRCUIT

Add this Filter to avoid other HP-Out-Right Nokia-MIC
components/chips be influenced
HP-Out-Lef t iPhone-MIC

1 2
RA48 0_0402_5%
place at AGND and DGND plane

680P_0402_50V7K
@ESD@ CA13
1 2 @ DA8 1 2 1
<37> AUD_NB_MUTE#
RA35 0_0402_5%
RB751S40T1G_SOD523-2 PD#
Global Headset
1 2
1
@ PJP19
2
<12> HDA_RST#_R
1 2 2 Universal Jack
RA36 0_0402_5% @ RA50 0_0402_5%
HDA_Link is 3.3V,no need level shift circuit
PAD-OPEN1x1m JHP1
1 2 7
RA37 0_0402_5% RE313@one control line if DVDD is 3.3V RING2 ESD@ LA10 1 2 BLM15PX330SN1D_2P RING2_R 4 GND
DE2@two control lines1 AUD_HP_OUT_L EMI@ RA52 1 2 0_0402_5% AUD_HP_OUT_L1 1 #4 G/M
#1 L/R Normal
Open
5
#5
A A

AUD_HP_NB_SENSE 6
#6 AGND
AUD_HP_OUT_R EMI@ RA53 1 2 0_0402_5% AUD_HP_OUT_R1 2
SLEEVE ESD@ LA11 1 2 BLM15PX330SN1D_2P SLEEVE_R 3 #2 R/L
@ PJP17 #3 M/G
Power sequence +5V_RUN_AUDIO(501us) > +3.3V_RUN_AUDIO(1204 us) > +1.5V_RUN 1 2

680P_0402_50V7K
+5V_RUN +5V_RUN_AUDIO SINGA_2SJ3095-085111F

ESD@ CA1

EMI@

EMI@

ESD@
ESD@ ESD@ ESD@ CONN@

3
+5V_RUN_AUDIO PAD-OPEN1x2m DA1 DA2 DA3
2.5A Link SINGA_2SJ3095-085111F DONE

2200P_0402_50V7K

2200P_0402_50V7K

680P_0402_50V7K

AZ5123-02S.R7G_SOT23-3

AZ5123-02S.R7G_SOT23-3

680P_0402_50V7K
@ESD@ CA12
2 1 1 1 1
20160308

L03ESDL5V0CC3-2_SOT23-3
Reserve for support D3 cold
1

CA2

CA3

CA4
@ PJP18
@ PJP15 1 2
+3.3V_RUN +3.3V_RUN_AUDIO 1 2 2 2 2
PAD-OPEN1x1m
+5V_RUN PAD-OPEN1x1m
500mA
@ UZ5
2

1
1 14 +5V_RUN_AUDIO_UZ5 1 2
2 VIN1 VOUT1 13 @ CZ125 0.1U_0201_10V6K
VIN1 VOUT1
3 12 1 2
<12> AUD_PWR_EN ON1 CT1 220P_0402_50V7K
@ CZ126
4 11
+5V_ALW
5
VBIAS GND
10 1 2
DELL CONFIDENTIAL/PROPRIETARY
ON2 CT2 @ CZ127 1000P_0402_50V7K
6 9 @ PJP16
+3.3V_RUN VIN2 VOUT2 +3.3V_RUN_AUDIO_UZ5
7 8 1 2
VIN2 VOUT2 +3.3V_RUN_AUDIO
15
GPAD PAD-OPEN1x1m
EM5209VF_SON14_2X3 1 2
@ CZ128 0.1U_0201_10V6K
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Codec ALC3253
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 0.1
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-E112P
Date: Friday, April 22, 2016 Sheet 36 of 58
2 1
 5 4 3 2 1

+3.3V_ALW

+RTC_CELL
RE32
2 1
0_0402_5%
+RTC_CELL_VBAT For KW
UPD1_SMBDAT

0.1U_0201_10V6K
1 1 2

CE11
RE302 2.2K_0402_5%
UPD1_SMBCLK 1 2
+3.3V_ALW_UE1
RE303 2.2K_0402_5%
2 UPD1_ALERT#

0.1U_0201_10V6K

1U_0402_6.3V6K

0.1U_0201_10V6K
PJP22 1 2
+3.3V_ALW 1 2 1 1 RE91 100K_0402_5%

1
UPD2_ALERT#

CE13

CE14

CE23
1 2

10U_0603_6.3V6M
PAD-OPEN1x1m RE92 100K_0402_5%

1
EVT1.0 uses SA00009GL10

2
2 2

CE16
PBAT_CHARGER_SMBDAT
20160323 1 2

2
UE1 RE37 2.2K_0402_5%
F2 TYPEC_ID PBAT_CHARGER_SMBCLK 1 2
GPIO033/RC_ID0 PANEL_ID TYPEC_ID <38>
A2 J10 RE43 2.2K_0402_5%
+3.3V_ALW_UE1 VBAT GPIO034/RC_ID1/SPI0_CLK BOARD_ID PANEL_ID <38>
J13 BOARD_ID <38>
D B7 GPIO036/RC_ID2/SPI0_MISO E7 UPD2_SMBDAT RPE12 D
VTR_ANALOG GPIO003/SMB00_DATA/SPI0_CS# UPD2_SMBCLK UPD2_SMBDAT <27> EXPANDER_GPU_SMDAT
2 1 D7 1 8
+3.3V_ALW_UE1 GPIO004/SMB00_CLK/SPI0_MOSI UPD2_SMBCLK <27> EXPANDER_GPU_SMCLK
0.1U_0201_10V6K

0.1U_0201_10V6K

100_0402_1% RE314 K2 2 7
VREF_ADC UPD2_SMBCLK

22U_0603_6.3V6M

0.1U_0201_10V6K
1 1 1 1 G3 3 6
+3.3V_EC_PLL GPIO057/VCC_PWRGD HW _GPS_DISABLE# RUNPWROK <14> UPD2_SMBDAT
CE19

CE20

@ CE17
F1 H5 4 5
VTR_PLL GPIO060/KBRST/48MHZ_OUT HW_GPS_DISABLE# <34>

CE18
G11
GPIO104/UART0_TX HOST_DEBUG_TX <34,38>
H1 G12 2.2K_0804_8P4R_5%
2 2 2 2 VTR_REG GPIO105/UART0_RX ME_FW_EC <12>
B13
GPIO127/A20M/UART0_CTS# UPD1_ALERT# ME_SUS_PWR_ACK <11>
G8 F10 RPE9
M9 VTR1 GPIO225/UART0_RTS# UPD1_ALERT# <26> SLOT2_CONFIG_1 1 8
+VSS_PLL +3.3V_ALW_UE1 VTR2 PCIE_W AKE#_R SLOT2_CONFIG_2
close to pin G8/M9 +1.8V_3.3V_ALW_VTR3 N5 N13 2 7
VTR3 GPIO025/TIN0/nEM_INT/UART_CLK N12 PCIE_WAKE#_R <38> SLOT2_CONFIG_0 3 6
GPIO026/TIN1 SIO_SLP_S4# <11,17,50,53> SLOT2_CONFIG_3
+3.3V_ALW_UE1
F8 M11 4 5
<38> PCH_DPWROK_EC RUN_ON_EC GPIO020 GPIO027/TIN2 SIO_SLP_A# <11>
RF Request E8 H9
<38> RUN_ON_EC GPIO045 GPIO030/TIN3 SIO_SLP_LAN# <11>
0.1U_0201_10V6K

1 M12 100K_0804_8P4R_5%
+3.3V_ALW <9> SIO_EXT_WAKE# BT_RADIO_DIS# GPIO120
C2 L9
<34> BT_RADIO_DIS# GPIO166 GPIO017/GPTP-IN5 BEEP <36>
CE15

F9 M10 RPE11
<48,57> PBAT_PRES# GPIO175 GPIO151/ICT4 SLOT2_CONFIG_1 <33,34> USB_PW R_EN2#
1 2 N4 N9 1 8
2 <11,17,45,51,52,53> SIO_SLP_SUS# PCH_ALW _ON GPIO230 GPIO152/GPTP-OUT3 SLOT2_CONFIG_0 <34> USB_PW R_SHR_LFT_EN#
RE349 43K_0402_1% M8 2 7
<45> PCH_ALW_ON GPIO231 USB_PW R_EN1#
K8 C11 3 6
<11> AC_PRESENT GPIO233 GPIO156/LED0 BREATH_LED# <44> USB_PW R_SHR_VBUS_EN
D10 4 5
GPIO157/LED1 BAT1_LED# <44>
<8> SML1_SMBDATA
E11 D11
GPIO007/SMB03_DATA/PS2_CLK0B GPIO153/LED2 BAT2_LED# <44>
Close to pin H1 D8 E1 100K_0804_8P4R_5%
<8> SML1_SMBCLK W W AN_W AKE# GPIO010/SMB03_CLK/PS2_DAT0B GPIO226/LED3 LCD_VCC_TEST_EN <31>
12P_0402_50V8J
RF@ CE59

68P_0402_50V8J
RF@ CE60

1 1 M13
<34> WWAN_WAKE# K12 GPIO110/PS2_CLK2 E5 AC_DIS 1 2
<11> SUSACK# W LAN_W IGIG60GHZ_DIS# L13 GPIO111/PS2_DAT2 GPIO005/SMB01_DATA/GPTP-OUT4 USH_SMBDAT <39,46>
B3 @ RE83 100K_0402_5%
<34> WLAN_WIGIG60GHZ_DIS# GPIO112/PS2_CLK1A GPIO006/SMB01_CLK/GPTP-OUT7 EXPANDER_GPU_SMDAT USH_SMBCLK <39,46> HW _GPS_DISABLE#
K11 M7 1 2
2 2 <11,14> SIO_PWRBTN# VCCST_PW RGD_EC K10 GPIO113/PS2_DAT1A GPIO012/SMB07_DATA/TOUT3 EXPANDER_GPU_SMCLK EXPANDER_GPU_SMDAT <38>
1 2 M4 RE12 100K_0402_5%
<11,14,38> VCCST_PWRGD RE308 @ 0_0402_5% N11 GPIO114/PS2_CLK0A/nEC_SCI GPIO013/SMB07_CLK/TOUT2 M3 PBAT_CHARGER_SMBDAT EXPANDER_GPU_SMCLK <38> W LAN_W IGIG60GHZ_DIS# 1 2
<38> LID_CL#_NB GPIO115/PS2_DAT0A GPIO130/SMB10_DATA/TOUT1 PBAT_CHARGER_SMBCLK PBAT_CHARGER_SMBDAT <48,57>
E10 N2 RE8 100K_0402_5%
<43> CLK_TP_SIO_I2C_DAT GPIO154/SMB02_DATA/PS2_CLK1B GPIO131/SMB10_CLK/TOUT0 PBAT_CHARGER_SMBCLK <48,57> W W AN_W AKE#
C12 N10 SLOT2_CONFIG_2 <34> 1 2
<43> DAT_TP_SIO_I2C_CLK GPIO155/SMB02_CLK/PS2_DAT1B GPIO132/SMB06_DATA SYS_LED_MASK#
A12 RE38 10K_0402_5%
JTAG_TDI GPIO140/SMB06_CLK/ICT5 RTCRST_ON SYS_LED_MASK# <44> SYS_LED_MASK#
change to PS2 E9 B6 1 2
<38> JTAG_TDI JTAG_TDO F6 GPIO145/SMB09_DATA/JTAG_TDI GPIO141/SMB05_DATA/SPI1_CLK/UART0_DCD# F7 RE21 10K_0402_5%
<38> JTAG_TDO JTAG_CLK GPIO146/SMB09_CLK/JTAG_TDO GPIO142/SMB05_CLK/SPI1_MOSI/UART0_DSR# UPD1_SMBDAT VOL_UP# <44>
C8 B4 THERMATRIP1# 1 2
<38> JTAG_CLK JTAG_TMS GPIO147/SMB08_DATA/JTAG_CLK GPIO143/SMB04_DATA/SPI1_MISO/UART0_DTR# UPD1_SMBCLK UPD1_SMBDAT <26>
C5 C3 RE301 10K_0402_5%
<38> JTAG_TMS JTAG_RST# GPIO150/SMB08_CLK/JTAG_TMS GPIO144/SMB04_CLK/SPI1_CS#/UART0_RI# UPD1_SMBCLK <26>
G13
JTAG_RST# J4 I_BATT_R RE64 1 2 300_0402_5%
GPIO200/ADC00 I_SYS_R I_BATT <57> PCIE_W AKE#_R
E3 J5 RE312 1 2 300_0402_5% 1 2
<38> FAN1_TACH LCD_TST GPIO050/FAN_TACH0/GTACH0 GPIO201/ADC01 I_SYS <54,57>
D1 J6 RE35 10K_0402_5%
<31> LCD_TST W W AN_RADIO_DIS# GPIO051/FAN_TACH1/GTACH1 GPIO202/ADC02 VOL_DOWN# <44> LID_CL#_TAB
M2 G2 RE318 1 2 0_0402_5% 1 2
<34> WWAN_RADIO_DIS# GPIO052/FAN_TACH2/LRESET# GPIO203/ADC03 PCH_RSMRST#_GPIO204 TOUCHPAD_INTR# <12,43>
L10 H2 RE5 10K_0402_5%
C <38> FAN1_PWM GPIO053/PWM0/GPWM0 GPIO204/ADC04 USB_PW R_SHR_VBUS_EN BC_DAT_ECE1117 C
L11 J2 1 2
<9> NB_MODE SHD_CS# GPIO054/PWM1/GPWM1 GPIO205/ADC05 USB_PW R_SHR_LFT_EN# USB_PWR_SHR_VBUS_EN <41>
M5 J3 RE365 100K_0402_5%
SHD_CLK J8 GPIO055/PWM2/SHD_CS#/(RSMRST#) GPIO206/ADC06 K3 USB_PW R_EN1# USB_PWR_SHR_LFT_EN# <41> WWAN_RADIO_DIS# 1 2
GPIO056/PWM3/SHD_CLK GPIO207/ADC07 USB_PWR_EN1# <42>
<31> BIA_PWM_EC N1 D3 RE10 100K_0402_5%
TBT_RESET_N_EC_R GPIO001/PWM4 GPIO210/ADC08 LOM_CABLE_DETECT# AUX_EN_WOWL <45> BT_RADIO_DIS#
1 2 L8 D2 1 2
<24,26,27> TBT_RESET_N_EC RE506 0_0402_5% T266 @ ACAV_IN_NB N6 GPIO002/PWM5 GPIO211/ADC09 E2 RE11 100K_0402_5%
PAD~D GPIO014/PWM6/GPTP-IN6 GPIO212/ADC10 USB_PW R_EN2# BC_INT#_ECE1117 <43> LOM_CABLE_DETECT#
J9 G5 1 2
<31> PANEL_BKEN_EC VGA_ID H11 GPIO015/PWM7 GPIO213/ADC11 F5 UPD2_ALERT# RE505 100K_0402_5%
GPIO035/PWM8/CTOUT1 GPIO214/ADC12 UPD2_ALERT# <27> PORT80_DET#
PJP20 D9 K4 1 2
<11,45> SIO_SLP_WLAN# AC_DIS GPIO133/PWM9 GPIO215/ADC13 PCH_PCIE_W AKE# PORT80_DET# <34>
1 2 H12 L1 RE512 100K_0402_5%
+1.8V_PRIM +1.8V_3.3V_ALW_VTR3 <57> AC_DIS
G10 GPIO134/PWM10/UART1_RTS# GPIO216/ADC14 L3
PCH_PCIE_WAKE# <11,38> SHD_CLK RE374 1 2 24.9_0402_1% SHD_CLK_R1 +RTC_CELL
1 <39> BCM5882_ALERT# GPIO135/UART1_CTS# GPIO217/ADC15 LAN_WAKE# <11>
PAD-OPEN1x1m MSCLK H10
<38> MSCLK GPIO170/TFDP_CLK/UART1_TX
CE22 MSDATA G9 H8 GPIO162 1 2
<38> MSDATA GPIO171/TFDP_DATA/UART1_RX GPIO222/SER_IRQ SHD_IO0 CV2_ON <37,39> SHD_IO0_R1 RE367 1 LPC@ SHD_IO0_R2
0.1U_0201_10V6K 1 CE21 J7 RE366 1 LPC@ 2 24.9_0402_1% 2 45.3_0402_1% RE507 100K_0402_5%
2 0.1U_0201_10V6K A4 GPIO223/SHD_IO0 L6 SHD_IO1 RE368 1 LPC@ 2 24.9_0402_1% SHD_IO1_R1 RE369 1 LPC@ 2 45.3_0402_1% SHD_IO1_R2 GPIO161 1 2
<36> AUD_NB_MUTE# EN_INVPW R B2 GPIO022/GPTP-IN0 GPIO224/GPTP-IN4/SHD_IO1 L7 SHD_IO2 RE370 1 LPC@ 2 24.9_0402_1% SHD_IO2_R1 RE371 1 LPC@ 2 45.3_0402_1% SHD_IO2_R2 RE508 100K_0402_5%
<31> EN_INVPWR PRIM_PW RGD_GPIO024 GPIO023/GPTP-IN1 GPIO227/SHD_IO2 SHD_IO3 SHD_IO3_R1 RE373 1 LPC@ SHD_IO3_R2
@ PJP21 C1 M6 RE372 1 LPC@ 2 24.9_0402_1% 2 45.3_0402_1%
1 2 2 Close to pin N5 IMVP_VR_ON_EC N7 GPIO024/GPTP-IN2 GPIO016/GPTP-IN7/SHD_IO3/ICT3 Place near UE1 Place near UE9 +3.3V_ALW
+3.3V_ALW <38> IMVP_VR_ON_EC GPIO031/GPTP-OUT1
K9 D6 RE59 close to UE2 at least 250mils
<11,24,38> SIO_SLP_S3# GPIO032/GPTP-OUT0 BGPO0 EC_FPM_EN <39> +PECI_VREF SHD_IO2_R1
PAD-OPEN1x1m N8 C7 2 1 1 2
<11> SIO_SLP_S5# GPI0040/GPTP-OUT2 GPIO164/VCI_OVRD_IN ACAV_IN <57> +1.0V_VCCST
A5 RE59 0_0402_5% LPC@ RE376 1K_0402_5%
P_SENSOR_ACT#_EC VCI_OUT ALWON <49> SHD_IO3_R1

0.1U_0201_10V6K
@ RE509 1 2 0_0402_5% F13 D5
POWER_SW_IN# <38>
1 2
P_SENSOR_ACT# E13 GPIO121/PVT_IO0 GPIO163/VCI_IN0# B5 GPIO162 LPC@ RE377 1K_0402_5%
<57,58> AC_DISC# GPIO124/GPTP-OUT6/PVT_CS# GPIO162/VCI_IN1#

1
SHD_CS#

CE25
C13 D4 GPIO161 1 2
<39> USH_DET# LID_CL#_TAB GPIO125/GPTP-OUT5/PVT_CLK GPIO161/VCI_IN2# POA_W AKE#
RPE10 E12 E4 LPC@ RE98 4.7K_0402_5%
CV2_ON <46> LID_CL#_TAB GPIO126/PVT_IO3 GPIO000/VCI_IN3# POA_WAKE# <39>
8 1
CV2_ON <37,39>

2
7 2 IMVP_VR_ON_EC F11 +3.3V_ALW
6 3 PCH_ALW _ON F12 GPIO122/BCM0_DAT/PVT_IO1 C6 LPC@ UE9
5 4 RUN_ON_EC D12 GPIO123/BCM0_CLK/PVT_IO2 GPIO165/32KHZ_IN/CTOUT0 3.3V_WWAN_EN <45> 8 1 SHD_CS#
<43> BC_DAT_ECE1117 GPIO046/BCM1_DAT 32KHZ_OUT SHD_IO3_R2 VCC CS# SHD_IO1_R2
D13 F3 @ CE54 1 2 10P_0402_50V8J 7 2
<43> BC_CLK_ECE1117 GPIO047/BCM1_CLK GPIO221/GPTP-IN3/32KHZ_OUT SHD_CLK_R1 HOLD#(IO3) DO(IO1) SHD_IO2_R2
100K_0804_8P4R_5% 6 3
F4 SHD_IO0_R2 5 CLK WP#(IO2) 4
<34> SLOT2_CONFIG_3 GPIO041/SYS_SHDN# +PECI_VREF DI(IO0) GND
RE57 2 1 1K_0402_5% B1 J11
+3.3V_ALW2 SIO_EXT_SMI#_EC SYSPWR_PRES GPIO044/VREF_VTT PECI_EC_R
K7 K13 RE60 1 2 43_0402_5% W 25Q80DVSSIG_SO8
PECI_EC <12>
1

SIO_RCIN#_EC N3 GPIO011/nSMI GPIO042/PECI_DAT/SB-TSI_DAT J12

GPIO021/LPCPD# GPIO043/SB-TSI_CLK REM_DIODE1_N M3042_PCIE#_SATA <10>
REM_DIODE1_N
100K_0402_5%

K6 A8 CE24 1 2 2200P_0402_50V7K
<8> ESPI_RESET# GPIO061/LPCPD#/ESPI_RESET# DN1_DP1A REM_DIODE1_P REM_DIODE1_P REM_DIODE1_N <38>
RE58

H7 A7
<8> ESPI_ALERT# GPIO063/SER_IRQ/ESPI_ALERT# DP1_DN1A REM_DIODE2_N REM_DIODE2_N REM_DIODE1_P <38> I_BATT_R
K1 A10 CE26 1 2 2200P_0402_50V7K CE3 1 2 2200P_0402_50V7K
<38> PCH_PLTRST#_5105 ESPI_CLK_5105 GPIO064/LRESET# DN2_DP2A REM_DIODE2_P REM_DIODE2_P REM_DIODE2_N <38>
G7 A9
REM_DIODE2_P <38>
2

<8,38> ESPI_CLK_5105 H6 GPIO065/PCI_CLK/ESPI_CLK DP2_DN2A B9 I_SYS_R CE4 1 2 2200P_0402_50V7K

<8,38> ESPI_CS# K5 GPIO066/LFRAME#/ESPI_CS# DN3_DP3A B8
<8,38> ESPI_IO0 GPIO070/LAD0/ESPI_IO0 DP3_DN3A REM_DIODE4_N REM_DIODE4_N
B L4 A11 CE27 1 2 2200P_0402_50V7K B
<8,38> ESPI_IO1 GPIO071/LAD1/ESPI_IO1 DN4_DP4A REM_DIODE4_P REM_DIODE4_P REM_DIODE4_N <38>
+3.3V_ALW G6 B10
<8,38> ESPI_IO2 GPIO072/LAD2/ESPI_IO2 DP4_DN4A +VR_CAP REM_DIODE4_P <38>
L5 C10
100K_0402_5%

<8,38> ESPI_IO3 CLKRUN#_EC GPIO073/LAD3/ESPI_IO3 VIN VSET_5105 PCH_RSMRST#

L2 C9 VSET_5105 <38>
1 2
GPIO067/CLKRUN# VSET
2

SIO_EXT_SCI#_EC M1 B11 RE342 10K_0402_5%

I_ADP <57>
RE63

SYS_PW ROK G4 GPIO100/nEC_SCI VCP H3 THERMATRIP2# SYS_PW ROK 1 2

VSS_ANALOG
<11,14> SYS_PWROK GPIO106/PWROK GPIO103/THERMTRIP2# THERMATRIP2# <38>
L12 B12 THERMATRIP1# RE56 10K_0402_5%
<6,31> ENVDD_PCH GPIO107/nSMI THERMTRIP1# H_PROCHOT#_R1 I_SYS_R
H13 1 2 1 2
VSS_ADC

VSS_PLL
VR_CAP
MEC_XTAL1 GPIO160/PWM11/PROCHOT# H_PROCHOT# <12,54,57>

@
A1 RE288 100_0402_5% RE313 10K_0402_5%
1

MEC_XTAL2_R A3 XTAL1 LCD_TST 1 2

VSS1

VSS2

VSS3

XTAL2 RE20 100K_0402_5%

JTAG_RST# EN_INVPWR 1 2
MEC5105_W FBGA169_11X11 RE55 100K_0402_5%
A6

A13

E6

H4

1+VR_CAP J1

C4

G1
1U_0402_6.3V6K
1

TBT_RESET_N_EC_R 1 2
1U_0402_6.3V6K

RE95 100K_0402_5%
1

1
@SHORT PADS~D
JTAG1 CONN@

100_0402_1%

+VSS_PLL
1

@ RE65
CE30
2

+RTC_CELL
CE31
2
2
2

For MEC5105 Rev.A:Pop RE361,Depop RE360,RE362

For MEC5105 Rev.B:Depop RE361,Pop RE360,RE362 POA_W AKE# 1 2
+3.3V_RUN RE324 100K_0402_5%
SHD_IO2 1 2 0_0402_5%
@ RE360
1.8V_PRIM_PWRGD <53> For EMI request +3.3V_ALW
2

+3.3V_ALW ESPI_CLK_5105
10K_0402_5% DMN65D8LDW-7_SOT363-6

PRIM_PW RGD_GPIO024 RE361 1 2 49.9K_0402_1%

RE67

RE94 VGA_ID 1 2

33_0402_5%
1
@ RE362 1 2 100K_0402_5% 1 2 RE84 100K_0402_5%

@EMI@
+3.3V_ALW PCH_RTCRST# <11> VGA_ID
75_0402_5% 1 2
100K_0402_5%

RE350
1
2

1
GPIO055 use for SHD_CS# (LPC) or PCH_RSMRST#(eSPI) RUNPWROK D @ RE85 100K_0402_5%
GPIO024 use for SHD_IO2 (LPC) or PRIM_PWRGD(eSPI) RTCRST_ON 2 QE12
RE68

MEC_XTAL2_R G L2N7002W T1G_SC-70-3

2
1
PCH_RSMRST#_GPIO204 LPC@ RE363 1 2 0_0402_5% S

3
PCH_RSMRST# <43>
3

33P_0402_50V8J
RE93
1

QE2B

@EMI@
1

1
SHD_CS# ESPI@ RE364 1 2 0_0402_5% 100K_0201_5%
RUN_ON# 5

CE57
RE290
32 KHz Clock
2

A A
0_0402_5% VGA_ID0

2
DMN65D8LDW-7_SOT363-6

Discrete 0
2

YE1
QE2A

MEC_XTAL1 1 2 MEC_XTAL2 UMA 1

8/28 schematic review
2
<17,38,45,52> RUN_ON
10P_0402_50V8J

10P_0402_50V8J

32.768KHZ_9PF_X1A000141000200
1
1

DELL CONFIDENTIAL/PROPRIETARY
CE28

CE29
2

LPC@ RE337 1 2 0_0402_5% CLKRUN#_EC Compal Electronics, Inc.

<8> CLKRUN# Title
SIO_EXT_SMI#_EC PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
LPC@ RE338 1 2 0_0402_5% TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
<12> SIO_EXT_SMI# LPC@ RE339 1 2 0_0402_5% SIO_RCIN#_EC
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
EC MEC5105
<8> SIO_RCIN# LPC@ RE341 1 2 0_0402_5% SIO_EXT_SCI#_EC Size Document Number Rev
<9> SIO_EXT_SCI# NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 0.1
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-E112P
Date: Friday, April 22, 2016 Sheet 37 of 58
5 4 3 2 1
 5 4 3 2 1

+1.8V_3.3V_ALW_VTR3 +RTC_CELL
PCIE_WAKE# <24,34,40>
+3.3V_ALW

1
100K_0402_5%
UE6

RE31
RE340 @ CE10
1 5 10K_0402_5% 1 2 2 1 1 2
NC VCC <37> PCIE_WAKE#_R PCH_PCIE_WAKE# <11,37>
RE275 0_0402_5% 0_0402_5% @ RE274
2 1U_0402_6.3V6K
<11> PCH_PLTRST#_EC

2
A 4
3 Y PCH_PLTRST#_5105 <37> 1 2
<37> POWER_SW_IN# Stuff RE275 and no stuff RE274 keep E5 design
GND POWER_SW#_MB <11,44> Stuff RE274 and no stuff RE275 to save two GPIOs on EC(PCH_PCIE_WAKE# should be output with OD)
RE33 10K_0402_5%

1U_0402_6.3V6K
74AUP1G07GW_TSSOP5

CE12
2 1

2
0_0402_5% @ RE304

+3.3V_ALW
@ CE53
+3.3V_ALW 1 2
+3.3V_ALW

100K_0402_5%
UE4

1
ESPI LPC

RE25
0.1U_0402_25V6K

5
PAGE
D 1 5 D
IMVP_VR_ON_EC 1 NC VCC
<37> IMVP_VR_ON_EC

P
B 4 IMVP_VR_ON 2
SIO_SLP_S3# 2 O A 4
RE26 <11,24,37,38> SIO_SLP_S3#
LID_CL#_NB

2
A Y VCCST_PWRGD <11,14,37>

G
2 1 UE3 3
<37> LID_CL#_NB LID_CL# <44,46> GND

RC25_10K RC8_15ohm

.047U_0402_16V7K
TC7SH08FU_SSOP5~D

3
8 10_0402_5% 74AUP1G07GW_TSSOP5

CE8
RC13/RC27_8.2K RF Request

2
IMVP_VR_ON <54>
+3.3V_ALW 1 2
0_0402_5% @ RE280

68P_0402_50V8J
1
RUN_ON_EC 2 1

RF@ CE61
<37> RUN_ON_EC RUN_ON <17,37,45,52>
CONN@
JESPI
1
+3.3V_RUN
18 RC212_0ohm RC211_0ohm 2
0_0402_5%

+3.3V_ALW
@ RE292

1
2
3
4
2
3
4
5
ESPI_IO0
ESPI_IO1
ESPI_IO2
<8,37>
<8,37>
<8,37>
0603 0603 @ CE52
1

0.1U_0402_25V6K
2

5
6
6 7 ESPI_IO3 <8,37> 1

P
7 8 20_0402_5% PCH_PLTRST#_EC ESPI_CS# <8,37> B
LPC@ RE375 1 4
11 8 9 2 O
GND 9 A

G
12
GND 10
10
ESPI_CLK_5105 <8,37>
RE337,RE338 UE5
TC7SH08FU_SSOP5~D

3
JXT_FP241AH-010GAAM

RE339,RE340,
31 RE341
0_ohm
+3.3V_ALW

RE2 / RE3
+3.3V_ALW +3.3V_ALW

1
C +3.3V_ALW
UE7
32 0_ohm RE79
240K_0402_5%
RE300
4.3K_0402_5%
C

2
5 1 RE343
PCH_DPWROK <11>

2
VDD RESET BOARD_ID PANEL_ID
1 33K_0402_5% <37> BOARD_ID <37> PANEL_ID
CE6 3 4
MR CT

1
1
2

0.1U_0402_25V6K 2 CE40 CE47

2 GND
1

RE348 4700P_0402_25V7K 4700P_0402_25V7K

2
TYPEC_ID
10K_0402_5% RT9826-30GB CE5
<37> TYPEC_ID
3300P_0402_50V7-K
2
1

RE79 CE40 REV RE300 CE47 PANEL SIZE

1
RE34 1 20_0402_5% TYPEC_ID
<37> PCH_DPWROK_EC CT: 3300 pF ~ 10ms delay L: w/ PD CE62
H: w/o PD 4700P_0402_25V7K * 240K 4700p X00 240K 4700p SB/BR 12"

2
130K 4700p 130K 4700p SB/BR 14"
Reset Threshold Level 3.0V CHECK
62K 4700p 33K 4700p BR 15"
33K 4700p * 4.3K 4700p KW 12/13"
RE343 CE40 REV 8.2K 4700p
240K 4700p Single Port ACE w/o AR 4.3K 4700p
130K 4700p Single Port ACE w/AR 2K 4700p
62K 4700p Dual Port ACE w/o AR 1K 4700p
Dual Port ACE w/AR
PANEL_ID rise t i mei s meas ur ed fr o m5 %~68 %.
33K 4700p
8.2K 4700p Dual Port ACE (w/AR +w/o AR) BOARD_ID rise t i mei s meas ur ed fr o m5 %~68 %.
4.3K 4700p VSET_5105
2K 4700p VSET_5105 <37>

0.1U_0402_25V6
1K 4700p

1
1.58K_0402_1%
1

CE38

RE77
2
+3.3V_ALW

2
1

8
7
6
5
10K_8P4R_5%
49.9_0402_1%
RE71

RPE7
Rest=1.58K , Tp=96 degree???

1
10K_0402_5%

10K_0402_5%

10K_0402_5%

100K_0402_5%
@ RE75
CONN@
Link ACES_50278-0040N-001 DONE

1
2
3
4

RE72

RE73

RE74
B JDEG1 B
+EC_DEBUG_VCC
1
1
2 JTAG_TDI 20160331
JTAG_TDI <37>

2
2 3 JTAG_TMS JFAN1
3 4 JTAG_CLK JTAG_TMS <37> 1
4 5 JTAG_TDO JTAG_CLK <37> 1 2 FAN1_PWM
RE86
5 6 JTAG_TDO <37> 2 3 FAN1_TACH FAN1_PWM <37>
MSCLK 10K_0402_5%
6 7 1 2 +3.3V_RUN 3 4 FAN1_TACH <37>
MSDATA +5V_RUN
7 8 HOST_DEBUG_TX 4
Control Byte 8 DEBUG_TX

10U_0603_6.3V6M

RB751S40T1G_SOD523-2
11 9 5
GND 9 GND

1
12 10 6
GND 10 FAN1_PWM GND

@ DE1
1 2 1 2
<9> SBIOS_TX

CE32
0 1 0 0 0 A1 A0 R/W JXT_FP241AH-010GAAM @ RE306 RE48 10K_0402_5% ACES_50278-0040N-001
0_0402_5% 1 2 FAN1_TACH
CONN@

2
RE51 10K_0402_5%
HOST_DEBUG_TX <34,37>

2
R/W = 0 = Wirte MSDATA <37>
R/W = 1 = Read 1 2 MSCLK <37>
RE30
0_0402_5%
SMBus address 0x40
Thermal diode mapping
+3.3V_ALW 5085 Channel Locat i on
Place under CPU
+3.3V_ALW ITE8306 circuit design DP1/DN1 CPU (QE3) Place CE35 close to the QE3 as possible
1
SA00009YF00 REM_DIODE1_P <37>
1
0.1U_0402_25V6K
UI@ CE501

1U_0402_6.3V6K
UI@ CE502
1

+3.3V_ALW
10K_0402_5%
UI@ RE504

100P_0402_50V8J
DP2/DN2 WiGig (QE5)

1
C
2

@ CE35
2
DN2a/DP2a DDR (QE7) B

1
UE500 E QE3
2

3
14 1 USH_PWR_STATE# <39> LMBT3904WT1G SC70-3
VSTBY GPA0
WRST# 24
VSTBY GPA1
3
6 GPA2
SAR_DPR# <34> DP3/DN3 NA REM_DIODE1_N <37>
2 0.1U_0402_25V6K +VCORE_IT8306 GPA2 PAD~D @ T270
1

1
1U_0402_6.3V6K
UI@ CE500

10K_0402_5%

100K_0402_5%

UI@ CE503 1 4 2 DCIN1_EN <58> DP2/DN2 for WiGig on QE5, place QE5 close
VCORE GPA3
@ RE500

@ RE502

7
12 GPA4 5
VBUS1_ECOK <58> DP4/DN4 CPU VR (QE6) to WiGig and CE37 close to QE5
SATA_LED_EN <44>
2

<37> EXPANDER_GPU_SMCLK SCL/CHIP_CLK GPA5 8

GPA6 DCIN2_EN <58>
13 9 VBUS2_ECOK <58>
<37> EXPANDER_GPU_SMDAT
2

SDA/CHIP_DAT GPA7
WRST# 19 16 GPE0
DP4/DN4 for Skin on
WRST# GPE0 17 GPE2
PAD~D @ T271 CHECK RE69 QE6, place QE6 close to DN2a/DP2a for DDR on QE7, place QE7 close
GPE2 PAD~D @ T272 to DDR and CE46 close to QE7
Vcore VR choke.

0.1U_0402_25V6
10 18 GPE3 @ 1 2
CHIP_ID0 GPE3 PAD~D T273 +1.0VS_VCCIO +3.3V_ALW THERMATRIP2# <37>
23 20 GPE4 @
CHIP_ID1 GPE4 PAD~D T274 REM_DIODE4_P <37> REM_DIODE2_P <37>
21 GPE5 <11,24,37,38>8.2K_0402_5%

LMBT3904WT1G SC70-3
GPE5 PAD~D @ T275 SIO_SLP_S3#

1
LMBT3904WT1G SC70-3

CE36

100P_0402_50V8J
22 GPE6 @ @ QE11
EXPANDER_ALERT# GPE6 PAD~D T276
2

1
100P_0402_50V8J

100P_0402_50V8J

@ CE37
QE7
11 E C
G

T267 @ PAD~D ALERT#/CHIP_CS# MW_1

1

1
100K_0402_5%

10K_0402_5%

@ CE46
25 RE510 2 1 0_0402_5% C C B
2 2

2
GPC0 MW_2

2
QE4

@CE39
A 15 28 RE511 2 1 0_0402_5% 1 3 1 2 2 2 B A

2
VSS GPC1
RE501

RE503

27 GPC2 RE70 2.2K_0402_5% B B C E QE5

D

PAD~D @ T279

3
29 GPC2 26 GPC3 +1.0V_VCCST E E QE6 LMBT3904WT1G SC70-3
PAD~D @ T280

3
EPAD GPC3 L2N7002WT1G_SC-70-3 LMBT3904WT1G SC70-3
2

REM_DIODE2_N <37>
IT8306FN-AX_QFN28_4X4 RE90 1 2 0_0402_5%
<12> H_THERMTRIP# REM_DIODE4_N <37>

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, MEC5085
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Re v
0.1
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-E112P
Date: Friday, April 22, 2016 Sheet 38 of 58
5 4 3 2 1
 5 4 3 2 1

RF Request
+3.3V_ALW
RF Request
+3.3V_TPM
For ATMEL TPM

12P_0402_50V8J
RF@ CZ57

68P_0402_50V8J
RF@ CZ58

12P_0402_50V8J
RF@ CZ59

68P_0402_50V8J
RF@ CZ60
1 1 1 1

D D
2 2 2 2

+3.3V_ALW +3.3V_TPM
PJP23
1 2 +3.3V_TPM

PAD-OPEN1x1m

1 2 TPM_PIRQ#
KW pop RZ8/RZ9 because
RZ69 10K_0402_5% share I2C on USH/SAR/ALS
+3.3V_ALW

1 2 USH_SMBCLK
RZ8 2.2K_0402_5%
1 2 USH_SMBDAT
RZ9 2.2K_0402_5%

+3.3V_TPM 1 2 USH_PWR_STATE#
RZ10 1M_0402_5%
UZ12 1 2
TPM_PIRQ# 7 8 @ CZ53 0.1U_0201_10V6K
<9> TPM_PIRQ# PIRQ# VCC

<8>
<8> PCH_SPI_CS#2
PCH_SPI_CLK_R1
RZ60 1
EMI@ RZ61 1
2 0_0402_5%
2 33_0402_5%
PCH_SPI_CS#2_R
PCH_SPI_CLK_2_R
1
6 SPI_CS# MISO
SPI_CLK MOSI
2
5
PCH_SPI_D1_2_R 33_0402_5% 2
PCH_SPI_D0_2_R 33_0402_5% 2
1 RZ58
1 RZ59 PCH_SPI_D1_R1
PCH_SPI_D0_R1
<8>
<8>
USH CONN
3
<11> PLTRST_TPM# SPI_RST# 4
C GND 9 C
T-PAD JUSH1
ATTPM20P-G1MA1-ABF_UDFN8_2X3 RZ85 1 2 0_0402_5% +PWR_SRC_R 1
+PWR_SRC 1
2
3 2
<37> CV2_ON 4 3
<37> POA_WAKE# 5 4
PCH_SPI_CLK_2_R <37> EC_FPM_EN 6 5
7 6
7
33_0402_5%

8
<10> USB20_N10 8
2

@EMI@

9
<10> USB20_P10 9
RZ63

10
11 10
<37,46> USH_SMBCLK 12 11
<37,46> USH_SMBDAT 13 12
1

<37> BCM5882_ALERT# 13
0.1U_0402_25V6

14
15 14
15
1

@EMI@

16
+3.3V_ALW 16
CZ56

17
18 17
+5V_ALW
2

19 18
+3.3V_RUN 19
20
+5V_RUN USH_RST#_R 20
@ RZ114 1 2 0_0402_5% 21
<11,24,31,34,40> PCH_PLTRST#_AND 22 21
<38> USH_PWR_STATE# 23 22
<12> CONTACTLESS_DET# 24 23
25 24
@ RZ87 1 2 0_0402_5% USH_DET#_R 26 25
<37> USH_DET# 26
DZ7 27
2 1 28 GND1
GND2
B RB751S40T1G_SOD523-2 B
CVILU_CF5026FD0RK-05-NH
CONN@

Link CVILU_CF5026FD0RK-05-NH DONE

20160321
PCH_PLTRST#_AND Close to JUSH1
+5V_ALW +5V_RUN +3.3V_RUN +3.3V_ALW

.047U_0402_16V7K
ESD@ CZ61
1

0.1U_0201_10V6K

0.1U_0201_10V6K

0.1U_0201_10V6K

0.1U_0201_10V6K
1 1 1 1

@
2

CZ64

CZ66

CZ67

CZ68
For ESD solution 2 2 2 2

RF Request
+5V_ALW +5V_RUN +3.3V_RUN +3.3V_ALW
RF Request

68P_0402_50V8J
RF@ CZ69

68P_0402_50V8J
RF@ CZ71

68P_0402_50V8J
RF@ CZ72

68P_0402_50V8J
RF@ CZ73
USH_SMBCLK 1 2 1 1 1 1
@RF@CZ62 68P_0402_50V8J
USH_SMBDAT 1 2
A @RF@CZ63 68P_0402_50V8J 2 2 2 2 A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
USH & TPM
Size Document Number R ev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
0.1
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-E112P
Date: Friday, April 22, 2016 Sheet 39 of 58
5 4 3 2 1
 5 4 3 2 1

For PCIEX4,Kirkwood

RF Request
+3.3V_HDD_M2 +3.3V_HDD_M2
D D

0.1U_0201_10V6K

0.1U_0201_10V6K
68P_0402_50V8J
@RF@CN60

22U_0603_6.3V6M

22U_0603_6.3V6M
1 @ 1

1
CN61

CN62
1

CN63

CN64
2

2
2 2
2
2280 SSD

NGFF slot C Key M

Place near HDD CONN

+3.3V_HDD_M2 2.5A
JNGFF3 CONN@ PJP31
1 2 1 2
Need update! CHECK Kirkwood Port Mapping 3 1 2 4 +3.3V_RUN
PCIE_PRX_DTX_N9 5 3 4 6 PAD-OPEN1x2m
<10> PCIE_PRX_DTX_N9 PCIE_PRX_DTX_P9 7 5 6 8
<10> PCIE_PRX_DTX_P9 9 7 8 10 NVME_LED# 1 2
PCIE_PTX_C_DRX_N9 9 10 12 SATALED# <10,34,44>
CN65 2 1 0.22U_0402_10V6K 11 RN100 0_0402_5%
<10> PCIE_PTX_DRX_N9 PCIE_PTX_C_DRX_P9 11 12 14
CN66 2 1 0.22U_0402_10V6K 13
<10> PCIE_PTX_DRX_P9 15 13 14 16
PCIE_PRX_DTX_N10 17 15 16 18
<10> PCIE_PRX_DTX_N10 PCIE_PRX_DTX_P10 19 17 18 20
<10> PCIE_PRX_DTX_P10 21 19 20 22
C CN67 2 1 0.22U_0402_10V6K PCIE_PTX_C_DRX_N10 23 21 22 24 C
<10> PCIE_PTX_DRX_N10 PCIE_PTX_C_DRX_P10 23 24 26
CN68 2 1 0.22U_0402_10V6K 25
<10> PCIE_PTX_DRX_P10 27 25 26 28
PCIE_PRX_DTX_N11 29 27 28 30
<10> PCIE_PRX_DTX_N11 PCIE_PRX_DTX_P11 31 29 30 32
<10> PCIE_PRX_DTX_P11 33 31 32 34
CN69 2 1 0.22U_0402_10V6K PCIE_PTX_C_DRX_N11 35 33 34 36
<10> PCIE_PTX_DRX_N11 PCIE_PTX_C_DRX_P11 35 36 38
CN70 2 1 0.22U_0402_10V6K 37
<10> PCIE_PTX_DRX_P11 39 37 38 40 M2_DEVSLP <10>
PCIE_PRX_DTX_P12 41 39 40 42
<10> PCIE_PRX_DTX_P12 PCIE_PRX_DTX_N12 43 41 42 44
<10> PCIE_PRX_DTX_N12 45 43 44 46
CN71 2 1 0.22U_0402_10V6K PCIE_PTX_C_DRX_N12 47 45 46 48
<10> PCIE_PTX_DRX_N12 PCIE_PTX_C_DRX_P12 47 48 50
CN72 2 1 0.22U_0402_10V6K 49
<10> PCIE_PTX_DRX_P12 51 49 50 52 PCH_PLTRST#_AND <11,24,31,34,39>
53 51 52 54 PCIE_WAKE# CLKREQ_PCIE#3 <11>
<11> CLK_PCIE_N3 55 53 54 56 PCIE_WAKE# <24,34,38>
<11> CLK_PCIE_P3 57 55 56 58
57 58

+3.3V_HDD_M2

67 68 SUSCLK_R 1 2
1 2 M2_DEVSLP 69 67 68 70 SUSCLK <11,34>
RN99 0_0402_5%
@ RN37 10K_0402_5% <10> m2280_PCIE_SATA# 71 69 70 72
if signal is PCIE GEN3/SATA GEN3 maybe change C value 71 72
or no need for DG0.9 SATA EXPRESS HDD 73 74
75 73 74
75

76
GND 77
GND
B LOTES_YPCI0016-P003A B

Link LOTES_YPCI0016-P003A Done (Key M)

20160315

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
M2 2280 Socket
Size Document Number R ev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
0.1
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-E112P
Date: Friday, April 22, 2016 Sheet 40 of 58
5 4 3 2 1
 5 4 3 2 1

For PWR SW + Charger combine IC

+5V_USB_CHG_PWR

DI4 ESD@ JUSB1

USB3_PRX_DTX_N1 1 1 10 9 USB3_PRX_DTX_N1 1
<10> USB3_PRX_DTX_P1 USB20_N1_R VBUS

150U_B2_6.3VM_R35M
2
USB3_PRX_DTX_P1 USB3_PRX_DTX_P1 USB20_P1_R D-

100U_1206_6.3V6M

0.1U_0201_10V6K
D 2 2 9 8 3 D
@ 4 D+
<10> USB3_PRX_DTX_N1 USB3_PTX_C_DRX_N1 4 4 USB3_PTX_C_DRX_N1 1 1 1 USB3_PRX_DTX_N1 GND

CI17
7 7 5
USB3_PRX_DTX_P1 SSRX-

CI32

CI14

AZC199-02SPR7G_SOT23-3
+ 6 10
SSRX+ GND

2
USB3_PTX_C_DRX_P1 5 6 6 USB3_PTX_C_DRX_P1 7 11
5
2 2 USB3_PTX_C_DRX_N1 GND GND

ESD@ DI5
8 12

2
3 3 2 USB3_PTX_C_DRX_P1 9 SSTX- GND 13
SSTX+ GND

1
8 SANTA_375230-1
CONN@

1
L05ESDL5V0NA-4_SLP2510P8-10-9

LINK 375230-1 DONE

USB3_PTX_C_DRX_P1
<10> USB3_PTX_DRX_P1
CI16
2 1
0.1U_0402_25V6
20160315
2 1 USB3_PTX_C_DRX_N1
<10> USB3_PTX_DRX_N1
CI13 0.1U_0402_25V6

RF Request
+5V_USB_CHG_PWR

LI7 EMI@
SW_USB20_N1 1 2 USB20_N1_R

SW_USB20_P1 4 3 USB20_P1_R

12P_0402_50V8J
RF@ CI43

68P_0402_50V8J
RF@ CI44
1 1
EXC24CQ900U_4P
C C
+5V_ALW
+5V_USB_CHG_PWR 2 2

UI3
1 12
VIN VOUT
2
<10> USB20_N1 3 DM_OUT
<10> USB20_P1 DP_OUT 10 SW_USB20_P1
13 DP_IN 11 SW_USB20_N1
<10> USB_OC0# FAULT# DM_IN
ILIM_SEL 4
ILIM_SEL
5 15
<37> USB_PWR_SHR_VBUS_EN EN ILIM_L 16 2 1
RI14
ILIM_HI 22.1K_0402_1%
6
<37> USB_PWR_SHR_LFT_EN# 7 CTL1 9
8 CTL2 NC 14
CTL3 GND 17
Thermal Pad

+5V_ALW SLGC55544CVTR_TQFN16_3X3

RI13 2 1 ILIM_SEL CIS Link Seligro SA000097E10 20160304

10K_0402_5% MAIN:SLGC55544CVTR

B +5V_ALW B
47U_0603_6.3V6M

47U_0603_6.3V6M

10U_0402_6.3V6M

0.1U_0201_10V6K

1 1 1 1
@ CI34

@ CI33

@ CI31

CI19

2 2 2 2

Place near UI3.1

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
JUSB1+PS
Size Document Number R ev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
0.1
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-E112P
Date: Friday, April 22, 2016 Sheet 41 of 58
5 4 3 2 1
 5 4 3 2 1

For Breckenridge/Steamboat 12&Kirkwood

DI1 ESD@
USB3_PRX_DTX_N3 1 1 USB3_PRX_DTX_N3
10 9
USB3_PRX_DTX_P3 2 2 9 8 USB3_PRX_DTX_P3

USB3_PTX_C_DRX_N3 4 4 7 USB3_PTX_C_DRX_N3 +USB_EX2_PWR

7 RF Request
USB3_PTX_C_DRX_P3 5 5 6 6 USB3_PTX_C_DRX_P3 +USB_EX2_PWR JUSB2
1
3 3 USB20_N2_R 2 VBUS
USB20_P2_R 3 D-
D+

0.1U_0201_10V6K
8 4
USB3_PRX_DTX_N3 GND

100U_1206_6.3V6M
1 5
SSRX-

1
USB3_PRX_DTX_P3

CI3
D
L05ESDL5V0NA-4_SLP2510P8-10-9 6 10 D
SSRX+ GND

CI1

AZC199-02SPR7G_SOT23-3
7 11
<10> USB3_PRX_DTX_P3 GND GND

2
USB3_PTX_C_DRX_N3

12P_0402_50V8J
RF@ CI45

68P_0402_50V8J
RF@ Part Reference
1 1 8 12

2
2 USB3_PTX_C_DRX_P3 SSTX- GND

ESD@ DI2
9 13

2
EXC24CQ900U_4P SSTX+ GND
<10> USB3_PRX_DTX_N3 USB20_P2 4 3 USB20_P2_R SANTA_375230-1
<10> USB20_P2 2 2

1
CONN@

1
USB20_N2 1 2 USB20_N2_R
<10> USB20_N2 LINK 375230-1 DONE
LI3 EMI@
20160315

DFB request:
main SM070003Z00 (INPAQ_MCM1012B900F06BP_4P)
Footprint use 2nd source SM070004400 (PANAS_EXC24CQ900U_4P) +USB_EX2_PWR
Pitch change from 0.5mm to 0.55mm
2 1 USB3_PTX_C_DRX_P3 +5V_ALW
<10> USB3_PTX_DRX_P3
CI4 0.1U_0402_25V6 UI1
1
2 1 USB3_PTX_C_DRX_N3 5 OUT
<10> USB3_PTX_DRX_N3 IN
CI5 0.1U_0402_25V6 2
GND

10U_0603_10V6M

0.1U_0201_10V6K
4
<37> USB_PWR_EN1# EN
1 3 USB_OC1# <10>
OCB

@ CI6

CI7
SY6288D20AAC_SOT23-5

2
2

C C

B B

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
JUSB2
Size Document Number R ev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 0.1
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-E112P
Date: Friday, April 22, 2016 Sheet 42 of 58
5 4 3 2 1
 5 4 3 2 1

RF Request
KB_DET# 1 2
+3.3V_TP RF@ CZ84 68P_0402_50V8J
Touch Pad +3.3V_RUN +3.3V_TP BC_INT#_ECE1117 1
@RF@CZ85
2
68P_0402_50V8J
1
PJP35 RF@CZ83 BC_DAT_ECE1117 1 2
1 2 68P_0402_50V8J @RF@CZ86 68P_0402_50V8J
+3.3V_TP 2
PAD-OPEN1x1m BC_CLK_ECE1117 1 2
@RF@CZ87 68P_0402_50V8J
DAT_TP_SIO_R

4.7K_0402_5%

4.7K_0402_5%
1 2

1
D @RF@CZ88 68P_0402_50V8J D

RZ18

RZ19
CLK_TP_SIO_R 1 2
PS2 @RF@CZ89 68P_0402_50V8J

2
2 1 DAT_TP_SIO_R
<37> DAT_TP_SIO_I2C_CLK
@ RZ22 0_0402_5%
2 1 CLK_TP_SIO_R
<37> CLK_TP_SIO_I2C_DAT
@ RZ23 0_0402_5%

330P_0402_50V8J

330P_0402_50V8J
I2C From EC
Keyboard

1
I2C1_SDA_TP_R JKBTP1 CONN@

CZ80

CZ81
2 1
RZ348 0_0402_5% KB_DET# 1

2
2 1 I2C1_SCK_TP_R <12> KB_DET# 2 1
RZ349 0_0402_5% 3 2
4 3 +3.3V_TP +3.3V_ALW +5V_RUN
5 4
+5V_RUN 5
I2C From EC 6
+3.3V_ALW BC_INT#_ECE1117 6
7
<37> BC_INT#_ECE1117 BC_DAT_ECE1117 7

0.1U_0201_10V6K

0.1U_0201_10V6K

0.1U_0201_10V6K
8 1 1 1
<37> BC_DAT_ECE1117 8

@
9
BC_CLK_ECE1117 9

CZ90

CZ91

CZ92
10
+3.3V_TP +3.3V_TP <37> BC_CLK_ECE1117 11 10
12 11 2 2 2
+3.3V_TP DAT_TP_SIO_R 12
13
CLK_TP_SIO_R 13

10K_0402_5%

10K_0402_5%
14
14

1
4.7K_0402_5%

4.7K_0402_5%
@ @ 15
15

RZ116

RZ117
16
<12,37> TOUCHPAD_INTR# 16

RZ20

RZ21
17
C I2C1_SDA_TP_R 18 17 Place close to JKBTP1 C
I2C1_SCK_TP_R 19 18

2
20 19
2 Link CVILU_CF5020FD0R0-05-NH DONE

2
Reserve for future use 21 20
I2C1_SDA_TP_R GND1
<9> I2C1_SDA_TP
1
RZ26
2
0_0402_5%
22
GND2 20160321
1 2 I2C1_SCK_TP_R CVILU_CF5020FD0R0-05-NH
<9> I2C1_SCK_TP
RZ29 0_0402_5% CHECK PIN DEFINE

I2C From CPU

@ eDP Cable W CAM

@ LED FFC
Part Number Description
Plan is for I2C to be driven by the EC for Win7 and Pre-OS (will utilize Intel I2C drivers for Win7)
Part Number Description
For Win8.1 and 10 the EC will control TP over I2C Pre-OS and then the PCH will drive I2C when in Windows
DC02C007600 H-CONN SET 13D MB-EDP-CAMERA
Route PS2 from EC to the touch pad also for contingency plan if I2C has issues
NBX0001JG00 FFC 10P F P0.5 PAD0.3 172MM MB-LED/B 13D
@ eDP TS Cable W CAM
@ FP FFC
Part Number Description
Part Number Description
DC02C007C00 H-CONN SET 13D MB-EDP-CAMERA-TS
NBX0001JK00 FFC 8P F P0.5 PAD.3 123MM MB-FP VALIDITY
@ eDP Cable W/O CAM
@ TP FFC
Part Number Description
Part Number Description
DC02C007D00 H-CONN SET 13D MB-EDP
NBX0001JI00 FFC 16P F P0.5 PAD=0.3 119MM MB-TP 13D
B @ SATA SPINDLE Cable B
@ USH Board FFC
Part Number Description
Part Number Description
DC02C007500 H-CONN SET 13D MB-SPINDLE HDD
NBX0001JJ00 FFC 26P G P0.5 PAD.3 88MM MB-USH/B 13D

RSMRST circuit @ SATA Cable

Part Number Description @ RTC BATT
DC02C007400 H-CONN SET 13D MB-MSATA HDD Part Number Description

+3.3V_ALW GC02001DS00 BATT CR2032 3V 225MAH PA 5 W/C 30MM

@ DC-IN Cable
@ CZ82
1 2 Part Number Description @ FAN
DC30100Q100 CONN SET 13F DCJACK-MB 2DW1003-041110F Part Number Description
0.1U_0201_10V6K
DC28A000800 FAN SET DAQ20 DC5V AB7405HB-HB3 ADDA
5

@ BATT Cable
1
P

<37> PCH_RSMRST# B Part Number Description

4 @ Speak
O PCH_RSMRST#_AND <11,14>
2
<49> ALW_PWRGD_3V_5V A DC02001X800 H-CONN SET 13D MB-BATT CABLE Part Number Description
G

UZ6 PK230003Q0L SPK PACK ZJX 2.0W 4 OHM FG

3

TC7SH08FU_SSOP5~D

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
Keyboard
Size Document Number R ev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
0.1
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-E112P
Date: Friday, April 22, 2016 Sheet 43 of 58
5 4 3 2 1
 5 4 3 2 1

Bat t er y LE D
HDD LED MUX
means EC can switch battery white led and HDD LED by hot key “ Fn+ H”

<38> SATA_LED_EN
1 2 BATT_WHITE#
BATT_WHITE# <37,44> BAT2_LED#
RZ25 150_0402_5%

1 2 BATT_YELLOW#
<37> BAT1_LED#

5
RZ28 330_0402_5%
D D
4 3 BAT2_LED#_R
<10,34,40> SATALED#
@ QZ2B

3
DMN65D8LDW-7_SOT363-6
R1/R2=10K

+3.3V_ALW DDTA114EUA-7-F_SOT323-3
QZ3 @

1
2
1 6 BAT2_LED#_R
<37,44> BAT2_LED#
1 2
@ QZ2A @ RZ511 150_0402_5%
DMN65D8LDW-7_SOT363-6

LED P/N change to SC50000FL00 from SC50000BA00

Breath LED
POWER & INSTANT ON SWITCH QZ7B

C
For NPI USE <37> BREATH_LED#
DMN65D8LDW-7_SOT363-6
4 3 BREATH_LED#_Q 1
RZ32
2 BREATH_WHITE_LED_SNIFF#
330_0402_5%
C

2 SW3 1

5
<11,38,44> POWER_SW#_MB

MASK_BASE_LEDS#
4 3

SKRBAAE010_4P

+3.3V_ALW

@ CZ93
1 2

0.1U_0201_10V6K
PWR board CONN LED board CONN
5

1
P

<37> SYS_LED_MASK# B MASK_BASE_LEDS# +5V_ALW

4
2 O +5V_ALW JLED1
<38,46> LID_CL# A
G

UZ10
TC7SH08FU_SSOP5~D JPWR1 1
3

1 BATT_YELLOW# 2 1
2 1 BATT_WHITE# 3 2
<11,38,44> POWER_SW#_MB 3 2 4 3
<37> VOL_UP# 4 3 5 4
<37> VOL_DOWN# BREATH_WHITE_LED_SNIFF# 5 4 6 5
6 5 6 7
7 6 GND1 8
8 GND GND2
GND
ACES_50208-0060N-P01 CVILU_CF5006FD0R0-05-NH
CONN@ CONN@
B B

Link ACES_50208-0060N-P01 done

20160321
Link CVILU_CF5006FD0R0-05-NH done
20160325

CLP1 CONN@ CLP2 CONN@ CLP4 CONN@ CLP3 CONN@ CLP6 CONN@ CLP5 CONN@ CLP8 CONN@ CLP7 CONN@
1 1 1 1 1 1 1 1
LED Circuit Control Table P1 P1 P1 P1 P1 P1 P1 P1
Fiducial Mark EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P
@ FD1
1
SYS_LED_MASK# LID_CL#
For JAE JSIM1 boss hole CLP16 CONN@ CLP9 CONN@ CLP11 CONN@ CLP10 CONN@ CLP13 CONN@ CLP12 CONN@ CLP15 CONN@ CLP14 CONN@
FIDUCIAL MARK~D 1 1 1 1 1 1 1 1
P1 P1 P1 P1 P1 P1 P1 P1
@ FD2
Mask All LEDs (Unobtrusive mode) 0 X
1 EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P
Mask Base MB LEDs (Lid Closed) 1 0
FIDUCIAL MARK~D
Do not Mask LEDs (Lid Opened) 1 1 CLP24 CONN@ CLP17 CONN@ CLP19 CONN@ CLP18 CONN@ CLP21 CONN@ CLP20 CONN@ CLP23 CONN@ CLP22 CONN@
@ FD3 1 1 1 1 1 1 1 1
1 P1 P1 P1 P1 P1 P1 P1 P1

FIDUCIAL MARK~D EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P

@ FD4
CPU NGFF EDP screw hole
1 @ H1 @ H2 @ H3 @ H4 @ H5 @ H6 @ H7 @ H8 @ H9 @ H11 @ H12 @ H13 @ H14 @ H16 @ H17 @ H18 @ H19 @ H20 @ ST1 @ ST2 CLP32 CONN@ CLP25 CONN@ CLP27 CONN@ CLP26 CONN@ CLP29 CONN@ CLP28 CONN@ CLP31 CONN@ CLP30 CONN@
H_3P8 H_3P8 H_3P8 H_3P8 H_1P1N H_1P1N H_7P0N H_7P0N H_2P3 H_2P5 H_2P3 H_2P5 H_2P3 H_2P3 H_2P1N H_2P3 H_2P3 H_2P8 CLIP_C3P2 CLIP_C3P2 1 1 1 1 1 1 1 1
FIDUCIAL MARK~D P1 P1 P1 P1 P1 P1 P1 P1

EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P

1

CLP33 CONN@ CLP34 CONN@ CLP35 CONN@ CLP36 CONN@ CLP37 CONN@
1 1 1 1 1
@ H24 @ H26 @ H27 @ H28 @ H29 P1 P1 P1 P1 P1
A H_5P2 H_2P3 H_5P2 H_1P2N H_1P2X1P7N A
EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P
@ H30 @ H31 @ H32 @ H33
H_0P8N H_0P8N H_0P9N H_1P1N
1

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT PAD, LED
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 0.1
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-E112P
Date: Friday, April 22, 2016 Sheet 44 of 58
5 4 3 2 1
 5 4 3 2 1

+3.3V_WLAN/+3.3V_ALW_PCH source +1.8V_RUN source

2A
PJP36
1 2 +3.3V_WLAN
+3.3V_ALW
PAD-OPEN1x2m @ PJP42 0.013A
UZ2 1 2 +1.8V_RUN
1 14 +3.3V_WLAN_UZ2 1 2 +1.8V_PRIM UZ8
1 2 2 VIN1 VOUT1 13 CZ122 0.1U_0201_10V6K PAD-OPEN1x1m
<11,37> SIO_SLP_WLAN# VIN1 VOUT1 1 7
@ RZ71 0_0402_5%
1 2 3 12 1 2 2 VIN VOUT 8 +1.8V_RUN_UZ8 1 2
<37> AUX_EN_WOWL ON1 CT1 VIN VOUT
D
RZ70 0_0402_5% CZ109 470P_0402_50V7K CZ120 0.1U_0201_10V6K D
4 11 1 2 RUN_ON_1.8V 3 6 1 2
+5V_ALW VBIAS GND <17,37,38,45,52> RUN_ON ON CT
RZ345 0_0402_5% CZ121 470P_0402_50V7K
@ RZ65 1 2 0_0402_5% 5 10 1 2
<37> PCH_ALW_ON ON2 CT2
RZ64 1 2 0_0402_5% CZ113 470P_0402_50V7K +5V_ALW
4
<11,17,37,51,52,53> SIO_SLP_SUS# +3.3V_ALW_PCH_UZ3 VBIAS
6 9 1 2 5
7 VIN2 VOUT2 8 CZ112 0.1U_0201_10V6K GND 9
VIN2 VOUT2 GND

1
15 @ CZ197
1 2 AUX_EN_WOWL GPAD AOZ1336_DFN8_2X2
0.63A 470P_0402_50V7K

2
RZ38 100K_0402_5% EM5209VF_SON14_2X3 PJP38
1 2 +3.3V_ALW_PCH
PAD-OPEN1x1m

+3.3V_RUN source
+3.3V_ALW
UZ3
C 1 14 C
2 VIN1 VOUT1 13
VIN1 VOUT1
3 12
ON1 CT1

+5V_ALW
4 11
VBIAS GND
RUN_ON 5 10 1 2
ON2 CT2 CZ114 1000P_0402_50V7K
6 9
7 VIN2 VOUT2 8 +3.3V_RUN_UZ3 1 2
VIN2 VOUT2 CZ115 0.1U_0201_10V6K
15
GPAD
EM5209VF_SON14_2X3 PJP39
1 2 +3.3V_RUN
PAD-OPEN1x3m
3.435A

+5V_RUN/+3.3V_WWAN source
B B

PJP40 2A
1 2 +5V_RUN
+5V_ALW
UZ4 PAD-OPEN1x2m
1 14 +5V_RUN_UZ4 1 2
2 VIN1 VOUT1 13 CZ116 0.1U_0201_10V6K
VIN1 VOUT1
3 12 1 2
<17,37,38,45,52> RUN_ON ON1 CT1 CZ117 470P_0402_50V7K
4 11
VBIAS GND
3.3V_WWAN_EN 5 10 1 2
<37> 3.3V_WWAN_EN ON2 CT2 CZ118 470P_0402_50V7K
6 9 +3.3V_WWAN_UZ4
+3.3V_ALW VIN2 VOUT2
7 8 1 2
1 2 3.3V_WWAN_EN VIN2 VOUT2 CZ119 0.1U_0201_10V6K
RZ40 100K_0402_5% 15
GPAD PJP41
EM5209VF_SON14_2X3 1 2
+3.3V_WWAN

PAD-OPEN1x3m 2.5A

+3.3V_WWAN_UZ4

A 1 A

RF@ CZ124
2200P_0402_50V7K
2

DELL CONFIDENTIAL/PROPRIETARY
RF Request Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
Power control
Size Document Number R ev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 0.1
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-E112P
Date: Friday, April 22, 2016 Sheet 45 of 58
5 4 3 2 1
 5 4 3 2 1

Only for Kirkwood

+3.3V_RUN

Magnetometer/E-Compass 3D accelerometer and Gyro sensor

double check with BIOS for SMB address
1U_0201_6.3V6M

0.1U_0201_10V6K
1 1 +VDD_IO +3.3V_RUN +VDD_IO
CZ160

CZ161

1
2 2 +3.3V_RUN +VDD_IO

10U_0603_10V6M

0.1U_0201_10V6K

0.1U_0201_10V6K
UZ27 @ RZ121

SEN@ CZ168

SEN@ CZ169

SEN@ CZ170
D D
0_0402_5%
6 2
VDDIO RES1

1
5 12

2
VDD RES2 ACC1_SA0
ISH_I2C0_SCL 1 2 MAG_I2C0_SCL 1 4 CZ162 1 2 0.1U_0402_25V6

2
SCL/SPC C1

1
MAG_SA1 RZ125 0_0402_5% 9 8 MAG_DRDY 1 2 UZ37
+VDD_IO ISH_I2C0_SDA 1 2 MAG_I2C0_SDA 11 SD0/SA1 DRDY RZ127 0_0402_5% SEN@ RZ122
RZ126 0_0402_5% SDA/SDI/SDO 10 5 4 ISH_GP1
CS +VDD_IO 0_0402_5% VDDIO INT1
double check with BIOS for SMB address 8 9
VDD INT2
1

3 7 MAG_INT

2
@ RZ123 GND INT
ACC1_SA0 1
0_0402_5% SDO/SA0
LIS3MDLTR_LGA12_2X2
LIS3MDLTR Interrupt active value.Default value:0 2 10
2

MAG_SA1 (0:active low;1:active high) 3 SDx CS_Aux 12

SCx CS +1.8V_RUN
1

ISH_I2C0_SDA 13
RZ124 ISH_I2C0_SCL 14 SCL
SDA
0_0402_5%
11 7
NC GND2 6
2

GND1

LSM6DS3USTR_LGA14_2P5X3 LSM6DS3US Interrupt active value.Default value:0

(0:active high; 1:active low)

+3.3V_WWAN Located on MB

C SAR Sensor Located on motherboard C

2

USH_SMBDAT 6 1 +3.3V_WWAN
<37,39> USH_SMBDAT
1 2
+3.3V_RUN +VDD_IO
QZ13A RZ509 0_0402_5%
5

DMN65D8LDW-7_SOT363-6 1 2
+1.8V_RUN

2
2.2K_0402_5%
@ RZ510 0_0402_5%
USH_SMBCLK 2
2.2K_0402_5%

RZ350
3 4
<37,39> USH_SMBCLK +3.3V_WWAN
RZ351
QZ13B
+3.3V_RUN DMN65D8LDW-7_SOT363-6
1 Detect closed in tablet position Detect clamshell closed
1

I2C from EC
JSAR1
Reserve CPU path
2

1 +3.3V_ALW +3.3V_ALW
1 6 SAR_I2C0_SDA 2 1
<9,46> ISH_I2C0_SDA SAR_I2C0_SCL 2
3 5 UZ28 UZ1
@ QZ10A 4 3 G1 6 2 2
4 G2 VCC VCC
5

0.1U_0201_10V6K

0.1U_0201_10V6K
DMN65D8LDW-7_SOT363-6 1 1
ACES_50208-0040N-001 1 1
GND GND

@ CZ188

@ CZ167
4 3 CONN@
<9,46> ISH_I2C0_SCL 3 3
@ QZ10B 2 <37> LID_CL#_TAB VOUT 2 <38,44> LID_CL# VOUT
DMN65D8LDW-7_SOT363-6 TCS40DLR_SOT23F3 TCS40DLR_SOT23F3

ACES_50208-0040N-001 LINK DONE

RF Request Place CZ1 near UZ1.
+3.3V_WWAN
SAR_I2C0_SDA SAR_I2C0_SCL
20160315
B Hall sensor: SA00009CB00 Hall sensor: SA00009CB00 B

CZ164 1 CZ165 1 CZ166 1

@RF@ @RF@ @RF@
+1.8V_RUN
100P_0402_50V8J

100P_0402_50V8J

100P_0402_50V8J

2 2 2 Level Shift
ISH_GP0_D 1 2
RZ501 10K_0402_5%
ISH_GP0 1 2 ISH_GP0_D ISH_GP1_D 1 2
Located near the WWAN antenna ISH_GP0_D <9> RZ502 10K_0402_5%
DZ100 ISH_GP2_D 1 2
RB751S40T1G_SOD523-2 RZ503 10K_0402_5%
ISH_GP1 1 2 ISH_GP1_D ISH_GP3_D 1 2
+1.8V_RUN +3.3V_RUN ISH_GP1_D <9> RZ504 10K_0402_5%
JSEN2 DZ101 LID_CL#_NB_D 1 2
1 RB751S40T1G_SOD523-2 RZ512 10K_0402_5%
2 1 ISH_GP2 1 2 ISH_GP2_D LID_CL#_TAB_D 1 2
SEN@ RZ137 1 2 0_0402_5% ACC1_I2C0_SCL 3 2 ISH_GP2_D <9> RZ513 10K_0402_5%
JSEN1 ISH_I2C0_SCL SEN@ RZ138 1 2 0_0402_5% ALS_I2C0_SCL 4 3 DZ102
ISH_I2C0_SCL 1 SEN@ RZ140 1 2 0_0402_5% ACC1_I2C0_SDA 5 4 RB751S40T1G_SOD523-2 +3.3V_RUN
<9,46> ISH_I2C0_SCL ISH_I2C0_SDA 2 1 ISH_I2C0_SDA 1 2 ALS_I2C0_SDA 6 5 ISH_GP3 1 2 ISH_GP3_D
<9,46> ISH_I2C0_SDA SEN@ RZ141 0_0402_5%
3 2 ISH_GP0 SEN@ RZ143 1 2 0_0402_5% ACC1_INT1 7 6 ISH_GP3_D <9> ISH_GP0 1 2
<9> ISH_I2C1_SCL 4 3 ISH_GP2 1 2 MAG_INT 8 7
<9> ISH_I2C1_SDA @SEN@ RZ144 0_0402_5% DZ103 @ RZ505 10K_0402_5%
5 4 ISH_GP3 SEN@ RZ145 1 2 0_0402_5% ALS_INT# 9 8 RB751S40T1G_SOD523-2 ISH_GP1 1 2
ISH_GP0_D 6 5 10 9 LID_CL# 1 2 LID_CL#_NB_D @ RZ506 10K_0402_5%
ISH_GP1_D 7 6 10 LID_CL#_NB_D <9> ISH_GP2 1 2
ISH_GP2_D 8 7 DZ104 @ RZ507 10K_0402_5%
ISH_GP3_D 9 8 RB751S40T1G_SOD523-2 ISH_GP3 1 2
10 9 LID_CL#_TAB 1 2 LID_CL#_TAB_D @ RZ508 10K_0402_5%
connect to these pins his ISH GPIOs 11 10 ALS I2C reserve EC solution +3.3V_RUN LID_CL#_TAB_D <9> LID_CL# 1 2
12 11 DZ105 @ RZ514 10K_0402_5%
A 13 12 11 RB751S40T1G_SOD523-2 LID_CL#_TAB 1 2 A
14 13 12 GND @ RZ515 10K_0402_5%
14 GND Device Side CPU side
2

15
16 15
16 USH_SMBCLK ALS_I2C0_SCL ACES_50208-01001-P03
17 6 1
+3.3V_ALW
18 17 CONN@ LINK ACES_50208-01001-P03 Done DELL CONFIDENTIAL/PROPRIETARY
18 @ QZ14A 20160321
5

19
20 GND
DMN65D8LDW-7_SOT363-6
Compal Electronics, Inc.
For Sensor Debug GND USH_SMBDAT 3 4 ALS_I2C0_SDA Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
CVILU_CF4218FH0R0-05-NH
@ QZ14B BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
SENSOR
CONN@ DMN65D8LDW-7_SOT363-6 Size Document Number R ev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
0.1
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-E112P
Date: Friday, April 22, 2016 Sheet 46 of 58
5 4 3 2 1
 5 4 3 2 1

+COINCELL
COIN RTC Battery

2200P_0402_50V7K
1
PR2

1
1K_0402_5%

PC8
+3.3V_RTC_LDO

+Z4012 2

2
@ JRTC1
1
+COINCELL 2 1
2
D D

2
3
+RTC_CELL 4 G1
G2

1
ESD@ PD2 ESD@ PD3
ACES_50278-00201-001
TVNST52302AB0_SOT523-3 TVNST52302AB0_SOT523-3
EMI@ PL2 PD1

1
FBMJ4516HS720NT_2P
+3.3V_ALW BAS40CW SOT-323 1

3
1 2 PC2
Primary Battery Connector 1U_0603_25V6K
EMI@ PL3

1
FBMJ4516HS720NT_2P 2
PBATT+_C
PBATT1
1 2 +PBATT
PR3
1
1 2 100K_0402_5%

2
2 3 PRP1
3 4 PBAT_SMBCLK_C 8 1
2200P_0402_50V7K

4 5 PBAT_SMBDAT_C 7 2
5 PBAT_PRES#_C PBAT_CHARGER_SMBDAT <37,57>
6 6 3
6 PBAT_CHARGER_SMBCLK <37,57> PBAT_PRES# <37,57>
1

7 5 4
EMI@ PC3

7 8
8 9 100_0804_8P4R_5%
2

9 10
10 11
GND 12
GND 13
GND 14
GND

DEREN_40-42507-01001RHF

GND

C C

B B

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D +DCIN
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Size Document Number Rev
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 0.1
LA-E112P
Date: Friday, April 22, 2016 Sheet 48 of 59
5 4 3 2 1
 A B C D E

PR119
0_0402_5%
PGOOD_3V 1 2
ALW_PWRGD_3V_5V <43>
PGOOD_5V 1 2

1 PR120 1
0_0402_5%

PR102
499K_0402_1%
+PWR_SRC ENLDO_3V5V 1 2
PR100
+PWR_SRC
PJP100 PC102

1
3V_VIN BST_3V1

499K_0402_1%
1 2 2 1 2

PR103
PAD-OPEN 1x2m~D 0_0603_5% 0.1U_0603_25V7K

2200P_0402_50V7K

1
PU100

2
10U_0805_25V6K

10U_0805_25V6K
@EMI@ PC100

@EMI@ PC103
0.1U_0402_25V6

BS
IN

IN

IN

IN
1

1
LX_3V 6

PC105

PC104
20 PL100
LX LX 2.2UH_PCMB062D-2R2MS_7A_20%
2

2
7 19 LX_3V 1 2
GND LX +3.3V_ALWP

@EMI@ PR106
8 SY8288BRAC_QFN20_3X3 18
GND GND PR104

4.7_1206_5%

22UF_0805_6.3V6M

22UF_0805_6.3V6M

22UF_0805_6.3V6M

22UF_0805_6.3V6M

22UF_0805_6.3V6M

22UF_0805_6.3V6M
9 17 1 2
PG LDO +3.3V_ALW2

1
0_0402_5%

PC106

PC107

PC108

PC109

PC129

PC110
10 16
NC NC 1 2 +3.3V_RTC_LDO 3VALWP

OUT

2
EN2

EN1
21 PR105

NC
FF
GND
TDC 6.7 A

1 3V_SN 2
PR107 0_0402_5%
Peak Current 9.6 A

11

12

13

14

15

680P_0603_50V7K
100K_0402_5%

@EMI@ PC112
2 1 2 2
+3.3V_ALW 3.3V LDO 150mA~300mA OCP Current 11.5 A

1
ENLDO_3V5V
PC111 Vout is 3.234V~3.366V
4.7U_0603_6.3V6K

2
PGOOD_3V

PJP102
PC113 PR108 +3.3V_ALWP 1 2 +3.3V_ALW
1000P_0402_50V7K 1K_0402_5% 1 2
3V5V_EN 3V_FB 1 2 1 2 JUMP_43X118

+PWR_SRC PJP103
+5V_ALWP 1 2 +5V_ALW
PJP101 1 2
1 2 5V_VIN PR111
PC114 JUMP_43X118
BST_5V 1 2 1 2
PAD-OPEN 1x2m~D
2200P_0402_50V7K

0.1U_0603_25V7K
0_0603_5%
5

1
10U_0805_25V6K

10U_0805_25V6K
@EMI@ PC115

@EMI@ PC116
0.1U_0402_25V6

PU102
1

BS
IN

IN

IN

IN
PC117

PC118

LX_5V 6 20 PL101
2

LX LX 2.2UH_PCMB062D-2R2MS_7A_20%
7 19 LX_5V 1 2
3 GND LX +5V_ALWP 3
8 SY8288CRAC_QFN20_3X3 18
GND GND

1
PR112

680P_0603_50V7K 4.7_1206_5%

22UF_0805_6.3V6M

22UF_0805_6.3V6M

22UF_0805_6.3V6M

22UF_0805_6.3V6M

22UF_0805_6.3V6M

22UF_0805_6.3V6M
PC119

1
@EMI@
9 17 1 2

PC120

PC121

PC122

PC123

PC130

PC124
PG VCC
10 16

2
NC NC 4.7U_0603_6.3V6K

1 5V_SN
OUT

LDO

2
EN2

EN1

21
FF

GND
11

12

13

14

15

PC125
PR113
+5V_ALW2

@EMI@
100K_0402_5%

2
1 2
+3.3V_ALW
ENLDO_3V5V

5V LDO 150mA~300mA
3V5V_EN

PGOOD_5V
PC126
4.7U_0603_6.3V6K

PR114
5VALWP
2

1 2
<37> ALWON
TDC 5.0 A
0_0402_5% Peak Current 7.1 A
3V5V_EN
OCP Current 8.6 A
1M_0402_1%

4.7U_0402_6.3V6M
1

1
PR116

PC128

PC127 PR117
1000P_0402_50V7K 1K_0402_5%
5V_FB 1 2 1 2
2
2

4 4
EN1 and EN2 dont't floating

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL +5V_ALW/3.3V_ALW
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E112P
Date: Friday, April 22, 2016 Sheet 49 of 59
A B C D E
 5 4 3 2 1

D D

+PWR_SRC
PJP202
1 2
@EMI@

@EMI@

PU200
10U_0805_25V6K

10U_0805_25V6K

0.1U_0402_25V6

2200P_0402_50V7K

PAD-OPEN 1x2m~D @EMI@ @EMI@

1

10 19 PR202 PC204
PC200

PC201

+3.3V_ALW
IN OT
PC202

PC203

4.7_1206_5% 680P_0603_50V7K
13 18 1 2 1 2
2

BYP PG

1U_0402_6.3V6K
14 12
PR203
1 2 1
PC205
2
+1.2V_DDRP
VCC BS
1

PC206
C 0_0603_5% 0.1U_0603_16V7K PL201 C

1
LX_DDR

2.2U_0402_6.3V6M
4 11 1 2
VTTGND LX

PC207
1UH_PCMB062D-1R0MS_9A_20%
2

330P_0402_50V7K
2 9 16
PGND FB

1
102K_0402_1%
1
+1.2V_DDRP

PC208

PR204
15 8 PC209
+3.3V_ALW SGND VDDQSNS

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

2200P_0402_50V7K
22U_0603_6.3V6M
R1

100P_0402_50V8J
7 1 2

2
VLDOIN

1
PC210

PC211

PC212

PC213

PC214

PC216

PC217
2
2

@ ILMT_DDR 17 6
PR205 ILMT VTT +0.6VSP

2
The current limit is 0_0402_5% 1 5
S5 VTTSNS
set to 8A, 12A or 16A

1
100K_0402_1%
2 3
1

when this pin is pull S3 VTTREF

22U_0603_6.3V6M

PR206
R2

1
ILMT_DDR

1U_0402_10V6K
PC218
low, floating or pull

PC219
high SY8210AQVC_QFN19_4X3
S5_1.2V

+1.2V_DDR OCP set 8A

2
2

@PR207
0_0402_5% Layout for Pin4,9,15
VTTGND , PGND seperate GND via
1

PGNE Cin_cap shape GND via

PR208
SGND alone GND
0_0402_5%
2 1
B <11,17,37,53> SIO_SLP_S4# B
0.1U_0402_10V7K
1M_0402_5%
1

1
PC221
PR209

+1.2V_DDRP +1.2V_MEM +0.6VSP +0.6V_DDR_VTT

2
@

@ PJP200 @ PJP201
2

JUMP_43X118 JUMP_43X39
1 2 1 2
PR210 1 2 1 2
0_0402_5%
2 1
<7> 0.6V_DDR_VTT_ON
0.1U_0402_10V7K
1M_0402_5%
1

@ PC222

+1.2V_DDR 0.6Volt +/- 5%

PR212

TDC 6.8A TDC 0.007A

2

Mode S3 S5 VOUT VTT Peak Current 9.7A Peak Current 0.01A

Normal H H on on
2

Stadby L H on off OCP Current 11.6A OCP Current 2A (fix)

Shutdown L L off off

Note: S3 - sleep ; S5 - power off

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL +1.2V_MEN/+0.6V_DDR_VTT
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E112P
Date: Friday, April 22, 2016 Sheet 50 of 59
5 4 3 2 1
 5 4 3 2 1

D D

PR312
1 2
SIO_SLP_SUS# <11,17,37,45,52,53>

0_0402_5%

EN_+1VALW P

1
1M_0402_1%
PR302 PJP302
+1VALWP 1 2 +1.0V_PRIM

2
1 2
JUMP_43X118

@EMI@ PR303 @EMI@ PC302

4.7_1206_5% 680P_0603_50V7K
2 SNB_+1VALW P 1
+PWR_SRC PJP301
+1VALW P_B+
PU301
1 2

1 2 2200P_0402_50V7K 8 1 PC304
0.1U_0402_25V6

IN EN PR304
0.1U_0603_25V7K

10U_0603_25V6M

10U_0603_25V6M
PAD-OPEN 1x2m~D 6 BST_+1VALW P 1 2BST_+1VALW
1 P_C 2 PL301
BS
1

1
1UH_PCMB051H-1R0MS_8A_20%
PC305

PC306
9 10 SW _+1VALW P 0_0603_5% 1 2 +1VALWP
@EMI@ PC301

@EMI@ PC303

C C
GND LX
2

22U_0805_6.3VAM

22U_0805_6.3VAM

22U_0805_6.3VAM

22U_0805_6.3VAM
330P_0402_50V7K
1

1
4 FB_+1VALW P
FB

PC307

PC308

PC309

PC310

PC311
21.5K_0402_1%
1
ILMT_+1VALW P 3 7
+3.3V_ALW

2
ILMT BYP

PR306
4.7U_0603_6.3V6K
+3.3V_ALW 2 5

4.7U_0603_6.3V6K
PG LDO

1
PC312

1K_0402_5%
1
SYX196DQNC_QFN10_3X3

PC313

PR308
2
1

2
2
@ PR307

2
0_0402_5%
2

ILMT_+1VALW P

1
1

PR311
31.6K_0402_1%
@ PR310
0_0402_5%

2
+1.0V_PRIM
2

TDC 5 A
Peak Current 7.1 A
OCP Current 8.6 A
B TYP MAX B

Choke DCR 15.0mohm , 17.0mohm

The current limit is set to 6A, 9A or 12A when this pin

is pull low, floating or pull high

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+1VALWP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
LA-E112P
Date: Friday, April 22, 2016 Sheet 51 of 59
5 4 3 2 1
 5 4 3 2 1

+3.3V_ALW
LPM LOGIC VID1 LOGIC VID0 LOGIC OUTPUT VOLTAGE

1
@
PR425 PR404 0 X X 0(LPM)
<11,17,52> SIO_SLP_S0# 1 2 0_0402_5%
0_0402_5% PJP401
TPS62134C 1 0 0 0.80

2
JUMP_43X79 1 0 1 0.95
1 2
PR402 +1VS_VCCIOP 1 2 +1.0VS_VCCIO 1 1 0 1.00
1 2
<17,37,38,45> RUN_ON
1 1 1 1.05

EN_1VS_VCCIO
0.1U_0402_25V6
0_0402_5%

1
@ PC402
PR403
D 1M_0402_1% D

2
2

13

14

15

16

17
PU401
Vin=3~17V
+1.0VS_VCCIO

EN

PGND

PGND

TP
LPM
PJP403
TDC 1.9 A
+5V_ALW 1 2 VIN_1VS_VCCIO 12
PVIN VOS
1
+1VS_VCCIOP Peak Current 2.7 A
PL402 OCP Current 3.3 A

10U_0603_10V6M

10U_0603_10V6M
PAD-OPEN1x1m 1UH_1277AS-H-1R0N-P2_3.3A_30%
TYP MAX

1
LX_1VS_VCCIO
+3.3V_ALW 11 2 1 2
+1VS_VCCIOP

PC403

PC404
PVIN SW
Choke DCR 48.0mohm

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
2

2
TPS62134CRGT_QFN16_3X3

1
10 3

PC406

PC407

PC422
AVIN SW

2
2200P_0402_50V7K

SNUB_1VS_VCCIO
0.1U_0402_25V6
1

1
VID0_VCCIO 9 4

PC408

@EMI@ PC409
VID0 PG @EMI@ PR405
1

AGND
4.7_0603_5%

VID1

FBS
PR413 @ PR414 @EMI@

SS

2
10K_0402_1% 10K_0402_1%
2

5
VID0_VCCIO

1
@EMI@ PC401

SS_1VS_VCCIO
VID1_VCCIO +1VS_VCCIOP
VID1_VCCIO 470P_0402_50V7K

100_0402_1%
2

1
1

PR421
@ PR415 PR416

470P_0402_50V7K
10K_0402_1% 10K_0402_1%
PR422

2
1

1
C

0_0402_5%
C
2

1 2

@ PR427

PC410
VCCIO_SENSE <17>

2
PR412 0_0402_5%

2
1 2
VSSIO_SENSE <17>

0_0402_5%
"R" for SILERGY
+3.3V_ALW

1
PR410
@ PR426 0_0402_5%
1 2
<11,17,52> SIO_SLP_S0#

2
0_0402_5%

PJP402
JUMP_43X79
EN_1.0V_PRIM_COREP

PR406 1 2
<11,17,37,45,51,53> SIO_SLP_SUS# 1 2 +1.0V_PRIM_COREP 1 2 +1.0V_PRIM_CORE
0.1U_0402_25V6

0_0402_5%
1

1
@ PC411

PR407
1M_0402_1%
2
2

13

14

15

16

17

PU402
B Vin=3~17V B
EN

PGND

PGND

TP
LPM

PJP404
VIN_1V_PRIM
+5V_ALW 1 2 12
PVIN VOS
1
+1.0V_PRIM_COREP
+3.3V_ALW PL404
10U_0603_10V6M

10U_0603_10V6M

PAD-OPEN1x1m 1UH_1277AS-H-1R0N-P2_3.3A_30%
1

LX_1V_PRIM
11 2 1 2
+1.0V_PRIM_COREP
PC412

PC413

PVIN SW

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
2

TPS62134DRGT_QFN16_3X3

1
10 3

PC424

PC415

PC416
AVIN SW
Rup
LPM LOGIC VID1 LOGIC VID0 LOGIC OUTPUT VOLTAGE

2
2200P_0402_50V7K
0.1U_0402_25V6
1

9 4
PC417

0 X X 0.7(LPM)
@EMI@ PC418

VID0 PG @EMI@ PR409

1SNUB_1V_PRIM

PR417 PR418 TPS62134D 1 0 0 0.85

2

AGND

10K_0402_1% 10K_0402_1% 4.7_0603_5%

VID0_PRIM_CORE

VID1

FBS
@EMI@

SS

1 0 1 0.90
2

VID0_PRIM_CORE
1 1 0 0.95
8

VID1_PRIM_CORE
@EMI@ PC419 1 1 1 1.00
1

470P_0402_50V7K
VID1_PRIM_CORE

@ PR408
@ PR419 @ PR420 0_0402_5%
SS_1V_PRIM

10K_0402_1% 10K_0402_1% 1 2
<18> CORE_VID0
2

@ PR411
+1.0V_PRIM_CORE
PR423
0_0402_5% TDC 1.8 A
1 2 1 2
<18> CORE_VID1 Peak Current 2.6 A
OCP Current 3.1 A
470P_0402_50V7K

0_0402_5%
1

1M_0402_1%

TYP MAX
1

1
PR428

A A
@ PR424 Choke DCR 48.0mohm
PC420

100K_0402_1%
2

@
2

DELL CONFIDENTIAL/PROPRIETARY
"R" for SILERGY
Compal Electronics, Inc.
Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+1VS_VCCIOP/+1.0V_PRIM_COREP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
LA-E112P
Date: Friday, April 22, 2016 Sheet 52 of 59
5 4 3 2 1
 5 4 3 2 1

PC502 PJP502
22U_0603_6.3V6M
1 2
1 2 +1.8VALWP +1.8V_PRIM
PAD-OPEN1x1m
PJP501
1 2 VIN_1.8VALW
+3.3V_ALW Imax= 2A, Ipeak= 3A
PAD-OPEN1x1m FB=0.6V
D D
PR517 PU501
PL501
2 1 1UH_1277AS-H-1R0N-P2_3.3A_30%
+3.3V_ALW 4 3 LX_1.8VALW 1 2
100K_0402_5% IN LX +1.8VALWP

1
5 2

68P_0402_50V8J
<37> 1.8V_PRIM_PWRGD PG GND @EMI@ PR502

1SNUB_1.8VALW

22U_0603_6.3V6M

22U_0603_6.3V6M
1
6 1

PC503
FB EN

1
4.7_0603_5%

PC501

PC504
PR501

2
RT8097ALGE_SOT23-6
PR504

2
20K_0402_1%
1 2 EN_1.8VALW
<11,17,37,45,51,52> SIO_SLP_SUS# Rup

2
@EMI@ PC506
0_0402_5%

1
680P_0402_50V7K

2
1
PR505 @ PC505

1M_0402_1% 0.1U_0402_16V7K

2
FB_1.8VALW

1
PR506
Rdown +1.8V_PRIM
10K_0402_1% TDC 0.7 A
Note: Peak Current 1.0 A

2
When design Vin=5V, please stuff snubber OCP Current 1.2A
to prevent Vin damage
Vout=0.6V* (1+Rup/Rdown)

C C

B B

+1.8V_MEM
TDC 0.5 A
Peak Current 0.7 A
OCP Current 0.8 A

PU503
PJP505
AP7361C-FGE-7_U-DFN3030-8_3X3 PJP506
1 2 +1.8V_VIN 9
+3.3V_ALW GND 1 1.8V_out 1 2
OUT
+1.8V_MEM
1

8
PAD-OPEN1x1m IN
1

PC514 2
NC PAD-OPEN1x1m

1
4.7U_0603_6.3V6K 7
2

NC 3 PR515 PC515
6 ADJ/NC 12.7K_0402_1% 2 0.01UF_0402_25V7K
NC

1
PR513 4
PC516
2

1 2 EN_1.8V 5 GND
<11,17,37,50> SIO_SLP_S4# EN 22U_0603_6.3V6M

2
0_0402_5%
1

@
PR514 PC513
PR516
2

1M_0402_1% .1U_0402_16V7K 10.2K_0402_1%

2

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+1.8VALWP/1.8V_MEN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
LA-E112P
Date: Friday, April 22, 2016 Sheet 53 of 59
5 4 3 2 1
 5 4 3 2 1

+1.0V_VCCST VCC_SA
TDC 4.0A
Peak Current 4.5A
OCP current 5.4A

0.1U_0402_25V6
1

1
45.3_0402_1%

100_0402_1%
75_0402_1%

PC602
1 2
+5V_ALW Choke DCR 15 m ohm

PR605
PR601

PR604
PR602
0_0402_5%
Local sense put on HW site

2
PJP603

0.22U_0603_25V7K
@ 1 2CPU_B+

1U_0603_10V6K
1 2
D 1 2 PR603 VCCSA_B+ CPU_B+ D
<15> VIDSCLK

1
49.9_0402_1% PR618 0_0402_5%

PC603

PC604
PAD-OPEN1x1m
<15> VIDALERT_N 1 2
0_0402_5% PR625

2
<15> VIDSOUT 1 2
10_0402_1% PR626
PR678 VCCSA_B+

VIDALERT_N_B
<12,37,57> H_PROCHOT#

VIDSOUT_B
VIDSCLK_B
100_0402_1%
1 2 1 2
1 2
PC605 47P_0402_50V8J~D
PR608

10U_0805_25V6K

10U_0805_25V6K
PH601 PR610 78.7K_0402_1%
470K_0402_5% 10K_0402_1% 1 2
1 2 1 2 PR613 1.91K_0402_1% PR612

1
PC612

PC608
84.5K_0402_1% 1 2 PR611
1 2 1 2 +3.3V_RUN 48.7K_0402_1%
PR631 PC613 <11> PCH_PWROK 1 2

2
27.4K_0402_1% 330P_0402_50V8J PR614 0_0402_5%
1 2 1 2
<38> IMVP_VR_ON
PC614 PR617 PR616 0_0402_5%
2200P_0402_50V7K 3.92K_0402_1%
1 2 1 2

40
39
38
37
36
35
34
33
32
31
PU602 SA_UGATE
PC616 PR619 2.2_0603_5%

VR_ENABLE
VR_READY

SCLK

SDA
VCC
VIN
VR_HOT#

ALERT#

PROG1
PROG2
68P_0402_50V8J PR620 1 2
1 2 PC617 PR621 0_0402_5%
1200P_0402_50V7K 316_0402_1% 1 2 1 30 PWM_VSA PU606
<37,57> I_SYS PSYS PWM_C

1
1 2 1 2 2 29 FCCM_VSA S IC ISL95808HRZ-TS2778 DFN MOSFET DRIVE PQ501
<16> VCC_GT_SENSE IMON_B FCCM_C
PR622 3 28 AON7934_DFN3X3A-8-10 PL601

D1

D1

D1

G1
@ PC618 1.91K_0402_1% 4 NTC_B ISUMN_C 27 PC611 1 8 1UH_PCMB051H-1R0MS_8A_20%
COMP_B ISUMP_C UGATE PHASE
0.082U_0402_16V7K

1 2 1 2 5 26 0.22U_0603_16V7K
FB_B RTN_C FB_VSA 9 SA_SW
PC620

6 25 1 2 2 7 10 1 2
RTN_B FB_C BOOT FCCM D1 D2/S1
+VCC_SA
1

330P_0402_50V7K 7 24 COMP_VSA
ISUMP_B COMP_C IMON_VSA PWM_SA

PR627 @EMI@
PC621 PR623 8 23 3 6
C
PC619 680P_0402_50V7K 2K_0402_1% 9 ISUMN_B IMON_C 22 PWM VCC C

G2
S2

S2

S2
2

ISEN1_B PWM_A PWM_IA <55>

1
SA_LGATE

4.7_1206_5%
1 2 @ 1 2 1 2 10 21 4 5
ISEN2_B FCCM_A FCCM_IA <55> GND LGATE

1
0_0402_5%

TP
ISUMN_A
ISUMP_A
PR624

PWM1_B
PWM2_B

COMP_A

8
FCCM_B

PR606
IMON_A
0.01UF_0402_25V7K 41

NTC_A

RTN_A
AGND 3.65K_0603_1%

FB_A

PWM_VSA
<16> VSS_GT_SENSE

1
1

2
PR679

ISUMP_VSA 2
0_0402_5%
+5V_ALW

1SA_SNUB

ISUMN_VSA
11
12
13
14
15
16
17
18
19
20
S IC ISL95857HRTZ-TS2778 TQFN 40P PWM

680P_0603_50V7K
1U_0402_10V6K
<55> ISUMP_GT

2
IMON_IA

FCCM_VSA
FB_IA
<55> FCCM_GT

NTC_IA
COMP_IA
4.42K_0402_1%

PC685

@EMI@ PC622
<55> PWM1_GT

2
1

PR628

PC625
330P_0402_50V7K
10K_0402_5%

2
1 2
PR629
2

0.033U_0402_16V7K

0.01U_0402_25V7K

90.9K_0402_0.1%
1

1
10P_0402_50V8J

7.32K_0402_1%
PC624

1 2

PR630
PH603
1

1
2200P_0402_50V7K

1200P_0402_50V7K
11K_0402_1%

PC626

PR632 PC627 470K_0402_5%

2

1
1

2200P_0402_50V7K
PH602

PR633

PC628
1K_0402_1% 1 2 1 2
1 2 1 2 ISUMP_VSA

2
1.05K_0402_1%
PR647 27.4K_0402_1% PR635 1 2

1
PR638 1 2 10K_0402_1%

2.61K_0402_1%
2

1
PC630

PR640
374_0402_1% PR636 1.24K_0402_1%
2

PC629

PC631
1 2

PR642
<55> ISUMN_GT PR639
2200P_0402_50V7K 3.6K_0402_1% 1 2 1 2

10KB_0402_5%
1 2 1 2

2
.1U_0402_16V7K

0.033U_0402_16V7K
PC632 PR641

2
1

2
1K_0402_1%

11K_0402_1%
PC636 2200P_0402_25V7K 1K_0402_1%

6800P_0402_25V7K
68P_0402_50V8J
PC641

PR643
1

1
PR644

PC633
1 2

PC637
2

1
PC639 PR645 PR646 PC640
B
+5V_ALW B

1
2200P_0402_50V7K 316_0402_1% 1 2 1 2 @

330P_0402_50V7K
1 2 1 2

PH604
316_0402_1% 2200P_0402_50V7K
PR648

2
1 2 PR649

1
130K_0402_1%
1 2

1
1.5K_0402_0.5% PC642 ISUMN_VSA
680P_0402_50V7K 2K_0402_1%

PC643

PR651
0.033U_0402_16V7K 1.62K_0402_1% PC644
1

2K_0402_1%
1 2 .1U_0402_16V7K

2
.1U_0402_16V7K

PR652
1 2

2
1
PR650

PC645
2

1 2
PC646

680P_0402_50V7K
0.01U_0402_25V7K
2

VSA_SEN- <17>
PC647

PC601
1 2

2
1

PC649
0.01UF_0402_25V7K

0.082U_0402_16V7K
1 2
PR656
11K_0402_1%
<15> VCCSENSE

2
PC650
1 2
@ PC652
PR657

1
@ PC651 PH605 @ 330P_0402_50V7K
1 2 4.42K_0402_1% 10KB_0402_5% 1 2
0.082U_0402_16V7K

1 2 1 2
PC653

330P_0402_50V7K
1

VSA_SEN+ <17>
ISUMN_IA <55>
2

PC654 @
A A
1 2
ISUMP_IA <55>
0.01UF_0402_25V7K

<15> VSSSENSE
DELL CONFIDENTIAL/PROPRIETARY
Local sense put on HW site
Compal Electronics, Inc.
Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL PWR_VCORE_ISL95857
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E112P
Date: Friday, April 22, 2016 Sheet 54 of 59
5 4 3 2 1
 5 4 3 2 1

D
+PWR_SRC VCC_core D
PJP601
TDC 21A
1 2
Peak Current 29A
CPU_B+ PAD-OPEN 4x4m OCP current 34.8A
@EMI@ PL602 Choke DCR 2.47 +-5%m ohm
1 2
@EMI@

@EMI@

100U_D_20VM_R55M
2200P_0402_50V7K 9A Z80 10M 1812_2P
10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

0.1U_0402_25V6K~D

1
PC606 +
1

1
PC656

PC657

PC658

PC659

PC660

2
2

VCC_GT
TDC 18A
Peak Current 31A
PU603 OCP current 37.2A
9
PL603
Choke DCR 2.47 +-5%m ohm
PC655 8 PGND2
<54> PWM_IA PWM CORE_SW
1 2 7 4 4 1
BOOT VSW +VCC_CORE
PR663 @EMI@
0.22U_0603_16V7K 3
1 2 6 PGND1 2 3 2
BOOT_R VDD

4.7_1206_5%
PR660 5 1
VIN SKIP#

1
2.2_0603_5% PJP602
0.22UH_MMD-06BD-R22MEV1L_21A_20%

1
1 2
C PR661 GPU_B+ CPU_B+ C
10P_0402_50V8K

CSD97374CQ4M_SON8_3P5X4P5
1

3.65K_0603_1%
5.11K_0402_1%

PAD-OPEN 1x2m~D
1

1U_0402_10V6K
PC686

PR662

PC680
+5V_ALW

2
1

1000P_0402_50V7K
2

2
1
FCCM_IA 0_0402_5%
PR659

PC661

CORE_SNUB
2

<54>

<54>
ISUMP_IA

ISUMN_IA
2

2
2
<54>

GPU_B+
680P_0603_50V7K
1

@EMI@ PC662
2

10U_0805_25V6K

10U_0805_25V6K
1

1
PC672

PC673
2

2
PU604
9
PGND2 PL604
B PC671 8 B
<54> PWM1_GT PWM GT_SW1
1 2 7 4 4 1
BOOT VSW +VCC_GT

PR676 @EMI@
0.22U_0603_16V7K 3
1 2 6 PGND1 2 3 2
BOOT_R VDD

4.7_1206_5%
PR672 5 1

2GT1P
VIN SKIP#

1
2.2_0603_5%
0.22UH_MMD-06BD-R22MEV1L_21A_20%

10P_0402_50V8K
CSD97374CQ4M_SON8_3P5X4P5

1
5.11K_0402_1%
PR674

1U_0402_10V6K
PC688

PR680
PC679

+5V_ALW
3.65K_0603_1%

2
1
1000P_0402_50V7K

0_0402_5%
PC677
2

1
PR671

GT_SNUB1
2

<54>

<54>
ISUMP_GT

ISUMN_GT
2
<54>

680P_0603_50V7K
FCCM_GT

@EMI@ PC678
2
A A

DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL PWR_VCORE_ISL95857
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E112P
Date: Friday, April 22, 2016 Sheet 55 of 59
5 4 3 2 1
 4
3
2
1
+VCC_CORE

A
A

2 1 2 1 2 1

2
1
+
330U_D2_2.5VM_R9M
PC1099 PC1083 PC1076
PC1127
1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1

2
1
+
330U_D2_2.5VM_R9M
PC1095 PC1030 PC1081 PC1078
PC1062
1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1 2 1

@ PC1170 PC1094 PC1031 PC1080 PC1077

22U_0603_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1 2 1
+330u_D2*2 pcs

@ PC1171 PC1096 PC1032 PC1082 PC1079

22U_0603_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1 2 1

@ PC1172 PC1090 PC1033 PC1067 PC1001

22U_0603_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
VCC_CORE Place on CPU

2 1 2 1 2 1 2 1 2 1

@ PC1173 PC1093 PC1034 PC1072 PC1002

22U_0603_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1 2 1

@ PC1174 PC1091 PC1035 PC1069 PC1003

22U_0603_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1

PC1097 PC1036 PC1074 PC1004

1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
22U_0603 * 33 pcs +1U_0201*35 pcs

2 1 2 1 2 1 2 1

B
B

PC1092 PC1037 PC1070 PC1005

1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1

PC1098 PC1038 PC1061 PC1006

1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1

PC1050 PC1039 PC1071 PC1007

1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1

PC1051 PC1084 PC1066 PC1008

1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1

PC1052 PC1086 PC1073 PC1009

1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1

PC1053 PC1085 PC1068 PC1010

1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1

PC1054 PC1088 PC1075 PC1011

1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1

PC1126 PC1087 PC1064 PC1012

1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1

PC1164 PC1089 PC1065 PC1013

C
C

1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M

2 1

PC1125
1U_0201_6.3V6M
+VCC_GT

VCC_SA Place on CPU

2 1 2 1 2 1
2
1
+

330U_D2_2.5VM_R9M
PC1040 PC1133 PC1014
PC1128
1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1
2
1
+

330U_D2_2.5VM_R9M
PC1041 PC1137 PC1015
+330u_D2*2 pcs

PC1063
1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1
+VCC_SA

@ PC1181 PC1042 PC1129 PC1016

22U_0603 * 12 pcs + 1U_0201*7 pcs

22U_0603_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M

2 1 2 1 2 1 2 1

2 1 2 1 @ PC1180 PC1043 PC1132 PC1017

22U_0603_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M

D
D

PC1153 PC1057 2 1 2 1 2 1 2 1
1U_0201_6.3V6M 22U_0603_6.3V6M
2 1 2 1
VCC_GT Place on CPU (U22)

@ PC1177 PC1044 PC1136 PC1018

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
22U_0603_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
PC1147 PC1058 2 1 2 1 2 1 2 1
1U_0201_6.3V6M 22U_0603_6.3V6M
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

2 1 2 1 @ PC1179 PC1045 PC1134 PC1019

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

22U_0603_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

PC1148 PC1059 2 1 2 1 2 1 2 1
1U_0201_6.3V6M 22U_0603_6.3V6M
2 1 2 1
22U_0603 * 26 pcs +1U_0201*12 pcs

@ PC1176 PC1046 PC1135 PC1020

22U_0603_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
PC1149 PC1060 2 1 2 1 2 1 2 1
1U_0201_6.3V6M 22U_0603_6.3V6M
2 1 2 1 @ PC1178 PC1047 PC1138 PC1021
22U_0603_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
PC1150 PC1139 2 1 2 1 2 1 2 1
22U_0603_6.3V6M
Size
Title

1U_0201_6.3V6M
Date:

2 1 2 1 @ PC1175 PC1048 PC1027 PC1022

22U_0603_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
PC1151 PC1140 2 1 2 1 2 1
1U_0201_6.3V6M 22U_0603_6.3V6M
2 1 2 1 PC1049 PC1028 PC1023
1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
+330u_D2*3

PC1152 PC1141 2 1 2 1 2 1
1U_0201_6.3V6M 22U_0603_6.3V6M
2 1 PC1055 PC1130 PC1024
Document Number

1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M

Friday, April 22, 2016

PC1142 2 1 2 1 2 1
22U_0603_6.3V6M
pcs

2 1 PC1056 PC1029 PC1025

1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
PC1143 2 1 2 1
22U_0603_6.3V6M
2 1 PC1131 PC1026
E
E

LA-E112P

22U_0603_6.3V6M 22U_0603_6.3V6M
PC1144
22U_0603_6.3V6M
Sheet

2 1
VCC_GT Place on CPU (U23E)

PC1145
56

22U_0603_6.3V6M
2 1
Compal Electronics, Inc.

of

PC1146
22U_0603_6.3V6M
22U_0603 * 48 pcs +1U_0201*12 pcs

PROCESSOR DECOUPLING

59
DELL CONFIDENTIAL/PROPRIETARY

R ev
0.1
4
3
2
1
 A B C D

+PWR_SRC_AC
+SDC_IN +CHARGER_SRC
PR901 EMI@
0.01_1206_1% PL901
1UH_MMD-05CZ-1R0M-M7L_7A_20%
1 4 2 1

2 3 +PWR_SRC

10U_0603_25V6M

10U_0603_25V6M

15U_B2_25VM_R100M
2200P_0402_50V7K

10U_0603_25V6M

10U_0603_25V6M

15U_B2_25VM_R100M

15U_B2_25VM_R100M
0.1U_0402_25V6
1 1 1
+ + +

PC909
@EMI@ PC902

@EMI@ PC903

PC910

PC951
1

1
PC904

PC906
PC911

PC905
PJP901
1 2
2 2 2

2
1 PAD-OPEN 4x4m 1

10U_0603_25V6M

10U_0603_25V6M
10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M
1

1
PC914

PC916
PC913

PC915

PC917

PC918

PC919

PC920
10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M

2
1

1
PC952

PC953

PC954

PC955
1

1
PR909 PR910

2
1_0402_1% 1_0402_1%

2
CSIN_ISL88738
PC925

CSIP_ISL88738
0.1U_0402_25V6

2200P_0402_50V7K
1 2

0.1U_0402_25V6
0.1U_0402_25V6

0.1U_0402_25V6

1
@EMI@ PC928

@EMI@ PC929
1

1
PC926

PC927

2
2

2
@ @

2
PC930
+SDC_IN
PR943
PD901 0.22U_0603_25V7K

2 1
2 1 2 1 ADP_ISL88738
+PBATT
SDMK0340L-7-F_SOD323-2~D PR914
0_0603_5%
1

0_0603_5%
PD903 PR944
2 1
TBTA_DC_SS 442K_0402_1%

1
2 2
SDMK0340L-7-F_SOD323-2~D
2

BOOT1_ISL88738
ACIN_ISL88738

CSIP_ISL88738

CSIN_ISL88738

UG1_ISL88738

LX1_ISL88738

LG1_ISL88738
PD904
1

2 1
TBTB_DC_SS PR945 PR915
SDMK0340L-7-F_SOD323-2~D 100K_0402_5% 4.7_0402_5%
2

1 2VDD_ISL88738
PR916
2

PU901

16

15

14

13

12

11

10

33
1_0805_5%~D

9
ISL88738HRTZ-T_TQFN32_4X4 PQ905 PQ904
PC931 1U_0603_25V6 CSD87351Q5D_SON8-7 CSD87351Q5D_SON8-7

BOOT1

UGATE1

PHASE1

LGATE1
CSIN

PAD
ADP

CSIP

ASGATE
PC932
1

+VCHGR PQ906

1
1 2 DCIN_ISL88738
17 8 VDDP_ISL88738 2 1 UG1_ISL88738 2 2UG2_ISL88738 PR917 AON7401_DFN8-5
DCIN VDDP
2 1 VDD_ISL88738 18 7 LG2_ISL88738
PL902 0.01_1206_1% 1
2
+PBATT
1UH_PCMB102T-1R0MS_10.8A_20%
VDD LGATE2 1U_0402_6.3V6K
2

7 7 1 4 3 5
PC933 PR918 ACIN_ISL88738 19 6 LX2_ISL88738 LX1_ISL88738
3 6 1 2 6 3 LX2_ISL88738
1U_0402_6.3V6K PR919 ACIN PHASE2 5 5 2 3
100K_0402_1%
1 2 0_0402_5%
OTGEN/CMIN 20 5 UG2_ISL88738 LG1_ISL88738
4 4 LG2_ISL88738
<37,58> AC_DISC#

4
OTGEN/CMIN UGATE2 PC934 PR921
1

ACAV_IN1 1 PR920 2 0_0402_5% 21 4 BOOT2_ISL88738 2 1 2 1

10U_0603_25V6M
10U_0603_25V6M
<37,48> PBAT_CHARGER_SMBDAT SDA BOOT2

1
4.7_1206_5%
4.7_1206_5%
1

@EMI@ PR924
1 PR922 2 0_0402_5% 22 3

@EMI@ PR923
PQ909 0.22U_0603_25V7K 2.2_0603_5%

1000P_0402_25V8J
<37,48> PBAT_CHARGER_SMBCLK

8
SCL VSYS
1

1
D

PC936
PC935
PR925
OTGPG/CMOUT

2
2 1 PR926 2 PROCHOT#_ISL8873823 2 CSOP_ISL88738

PC937
154K_0402_1% <12,37,54> H_PROCHOT# 0_0402_5%
PROCHOT# CSOP
AMON/BMON

<37> AC_DIS G

1SNUB_CHG1 2

1SNUB_CHG2 2

2
1

1 PR928 2 ACOK_ISL88738
24 1 CSON_ISL88738
BATGONE

S
3

1
DMN65D8LW-7_SOT323-3 0_0402_5% ACOK CSON PR929 @

BGATE_ISL88738
BGATE
CMOP
PROG

PSYS

VBAT

0_0402_5%
1 2

680P_0603_50V7K
680P_0603_50V7K
PR927 +PWR_SRC
2

1M_0402_1% @ PR930 PC938

25

26

27

118K_0402_1% 28

29

30

31
BGATE_ISL88738 32

@EMI@ PC941
@EMI@ PC940
100K_0402_1% 10P_0402_50V8J
PR931 1 2 1 2 1 2
2 PR932 1

100K_0402_1%

2
3
1 2 @ PC939 0.1U_0402_25V6 3

<37,48> PBAT_PRES#
VBAT1_ISL88738

PR933
100K_0402_1%
1 2
+3.3V_ALW

COMP_ISL88738

1 2
0_0402_5%
1
PR934

0.1U_0402_25V6
560P_0402_50V7K

@ PC942 0.1U_0402_25V6
20_0402_5%1

1
PC947

0_0402_5%

5.1K_0402_1%
1

1
PR947

PR948

1 2
@ PC943

PR936
0_0402_5%
PR935
2

PC945 PR937
2

0.1U_0402_25V6 1_0402_1%
0.047U_0402_25V7K

2
1
PC944

PR938
2

1 2
2

I_BATT

@ PR950 +3.3V_VDD_PIC
I_ADP

1 2 0_0402_5%
I_SYS <37,54> 1 2
@ PC946 0.1U_0402_25V6
PR939
PD905
0_0402_5% @ PC949
1 2 3 0.1U_0402_10V7K
<26,58> AC1_DISC#
I_BATT <37> 1 2
1 PU903
I_ADP <37> TC7SH08FU_SSOP5

5
+PBATT <27,58> AC2_DISC#
1 2 2
1
PR946
PR941 0_0402_5%

P
B <37> ACAV_IN
2 1 0_0402_5% BAT54CW_SOT323-3 4 1 2
ACAV_IN1 1 2 2 Y
Close to EC ADP_I pin A

G
PR940 PR942
2

4
0_0402_5% 0_0402_5% 4

3
@ PC950
0.1U_0402_25V6
1

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/10/24 Deciphered Date 2015/08/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P47-PWR_CHARGER_ISL9237 (Colay)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E112P
Date: Friday, April 22, 2016 Sheet 57 of 59
A B C D
 5 4 3 2 1

PJP1201
1 2

PAD-OPEN 1x2m~D S2 PD1202

S5 S1 2

SX34_SMA2
1

@ PQ1200 PQ1202 PQ1203 +SDC_IN

AON7401_DFN8-5 AON7401_DFN8-5
TBTA_DC_SS AON7401_DFN8-5
+TBTA_VBUSEMI@ PL1201
+TBTA_VBUS_1 1 1 1
HCB2012KF-121T50_0805 2 2 2
1 2 5 3 3 5 5 3

2
+3.3V_VDD_PIC
100P_0402_50V8J

1000P_0402_50V7K

100P_0402_50V8J

4
1

SI2303CDS-T1-GE3_SOT23-3
PR1202

0.1U_0402_25V6

AO3409 P-CHANNEL SOT-23

PR1277

PR1201
1M_0402_1%
100K_0402_5%

0.022U_0402_25V7K
1

2
PC1283

PC1201

PC1202

@EMI@ PC1203
100K_0402_5%

1
D PR1205 D

1M_0402_5%
100K_0402_5%

1
1

3
S S

PQ1225

PQ1204
PC1206
100K_0402_5%

1500P_0402_50V7K
2

2
1
G
2
G
@ PC1205 2

PR1203

PR1204
1M_0402_5%
EMI@

EMI@

2
@EMI@

PR1206
0.022U_0402_25V7K

1
PC1204
D D

1
1
1

2
PR1279

2
@ 100K_0402_5% PR1207

DMN65D8LW-7_SOT323-3
@ 100K_0402_5%

1
D
PR1208

2
+3.3V_VDD_PIC 2 2 1

PQ1205
0_0402_5% AC_DISC# <58>

1
2
+3.3V_VDD_PIC G

DMN65D8LW-7_SOT323-3
PR1209 S PR1210

3
2

1
D

DMN65D8LDW-7_SOT363-6
PR1284 100K_0402_5% 0_0402_5%

1
@ PR1211 PR1278 PR1212 2

PQ1206
100K_0402_5%

6
G
S5 OVP 100K_0402_5% 100K_0402_5% 100K_0402_5%

1
+3.3V_VDD_PIC +3.3V_VDD_PIC S
<26,58> EN_PD_HV_1 +3.3V_VDD_PIC

3
PQ1224A
1

1
+TBTA_VBUS_1 EN_PD_HV_1#
2
PQ1207A

2
@ PD1201 PC1207 PR1214 DMN66D0LDW-7_SOT363-6

6
0.01U_0402_25V7K 0_0402_5% D

@ PR1213
100K_0402_5%

1
SDMK0340L-7-F_SOD323-2 PR1285 1 2 1 2 2 PQ1207B
1

1
1 2 1M_0402_5% G DMN66D0LDW-7_SOT363-6
150K_0402_1%

100K_0402_1%
1

3
@ PR1217 PR1219 PR1221

100K_0402_5%
0.1U_0402_25V6
5

3
@ PR1218 100K_0402_1% 0_0402_5% D 0_0402_5%
PR1215

PR1216

S <26,58>

1
1

DMN65D8LDW-7_SOT363-6
0_0402_5% @ PQ1201A 1 2 1 5 2 1

PC1208

PR1220

PQ1224B
P
IN1 EN_PD_HV_1 VBUS1_ECOK <38,58>
1 2 @ 2 DMN65D8LDW-7_SOT363-6 4 5 G
2

2
O

3
PU1201A 1 2 2
2

2
G
8

2
@ @ LM393DGKR_VSSOP8 @ PR1223 IN2
S

4
3 0_0402_5% PR1222 PR1224
P

3
+ 1 1 2 5 0_0402_5% PU1202 100K_0402_5%
100P_0402_50V8J

1200P_0402_50V7K
O

0.01UF_0402_25V7K
2 @ PQ1201B SN74AHC1G08DCKR_SC70-5
-
G
1

DMN65D8LDW-7_SOT363-6
100K_0402_1%

200K_0402_1%

100P_0402_50V8J

1
1

1
PC1209

PC1211

PC1212
4
1
PR1225

PR1227

PC1210

PQ1209
2

2
PR1226 DMN65D8LW-7_SOT323-3
2

@ @ @ 0_0402_5%
2

1 2 3

D
@ @ @ 1
DCIN1_EN
DMN65D8LW-7_SOT323-3

@
@ PR1230 (From EC) PT1

G
2
1

1
D
0_0402_5% PAD~D

100K_0402_5%

100K_0402_5%
LPSA_PROTECT#

2
2 1 2
PQ1208

PR1229
G

PR1228
0_0402_5%
1

2
S @ PR1232
3

@ PR1231 0_0402_5%

PR1233
2
@ 10K_0402_5% 1 2
EN_PD_HV_1 <26,58>

1
2

1
C C

+3.3V_VDD_PIC

+3.3V_ALW
PJP1202
1

PAD-OPEN 1x2m~D
2
S4 PD1205

S6 S3
2

SX34_SMA2
1

+SDC_IN
@
PQ1210 PQ1211 TBTB_DC_SS PQ1212
AON7401_DFN8-5 AON7401_DFN8-5 AON7401_DFN8-5
+TBTB_VBUS EMI@ PL1202
+TBTB_VBUS_1 1 1 1
HCB2012KF-121T50_0805 2 2 2
1 2 5 3 3 5 5 3

2
+3.3V_VDD_PIC
100P_0402_50V8J

0.1U_0402_25V6

1000P_0402_50V7K

100P_0402_50V8J

4
1

SI2303CDS-T1-GE3_SOT23-3
AO3409 P-CHANNEL SOT-23
PR1280 PR1235
1500P_0402_50V7K
1

1
PC1213

PC1214

@EMI@ PC1215

PR1234
1M_0402_1%

1M_0402_5%

100K_0402_5% 100K_0402_5%

100K_0402_5%
1

2
PC1284

PC1216

PR1236

0.022U_0402_25V7K
1

1
S
PR1239

PQ1227
PR1237

1M_0402_5%
2

1
1

3
G S
PC1217 2

PQ1213
PC1218

PR1238
100K_0402_5%
2

1
EMI@
@EMI@

G
@ 0.022U_0402_25V7K 2
2

2
EMI@

@ @ +3.3V_VDD_PIC D

1
D

1
1

2
PR1282

1
100K_0402_5% PR1240

DMN65D8LW-7_SOT323-3
PR1283 100K_0402_5%

1
D
<27,58> EN_PD_HV_2 100K_0402_5% PR1241

2
+3.3V_VDD_PIC 2 2 1

PQ1214
+3.3V_VDD_PIC 0_0402_5% AC_DISC# <58>

1
2

2
G

2
2

DMN65D8LW-7_SOT323-3
@ PR1242 PR1244 S PR1243

3
1
D

DMN65D8LDW-7_SOT363-6
100K_0402_5% PR1286 PC1219 100K_0402_5% PR1281 0_0402_5%
0.01U_0402_25V7K 2

PQ1215
1M_0402_5% 100K_0402_5%

6
1 2 G
1

2
PR1245 PQ1216A S

3
5
0_0402_5% PR1248 DMN66D0LDW-7_SOT363-6 PR1246

PQ1226A
EN_PD_HV_2#

6
1 2 1 0_0402_5% D 2
S6 OVP 100K_0402_5%

P
+3.3V_VDD_PIC +3.3V_VDD_PIC IN1 4 1 2 2
1 2 2 O G

1
IN2

G
+TBTB_VBUS_1

100K_0402_5%
0.1U_0402_25V6

DMN65D8LDW-7_SOT363-6
B @ PD1206 PR1247 B

PQ1226B
S
100K_0402_5%

1
2

3
0_0402_5% PU1203
PR1249

PC1220

PR1250
SDMK0340L-7-F_SOD323-2 SN74AHC1G08DCKR_SC70-5 <27,58> PQ1216B
1

3
1 2 D DMN66D0LDW-7_SOT363-6
150K_0402_1%

100K_0402_1%

EN_PD_HV_2

2
1

@ PR1254 5 5 1 2
VBUS2_ECOK <38,58>

1
@ PR1256 100K_0402_1% @ PQ1218 G
PR1252

PR1253

PR1255
0 _0402_5%
1

2
0_0402_5% @ PQ1217A PR1251 DMN65D8LW-7_SOT323-3

4
1 2 @ 2 DMN65D8LDW-7_SOT363-6 0_0402_5% S PR1257
2

4
3

PU1204A 1 2 3
S

1 100K_0402_5%
DCIN2_EN
2

@ @ LM393DGKR_VSSOP8 @ PR1259
1

3 0_0402_5%
P

1
+ 1 1 2 5
G

100K_0402_5%
100P_0402_50V8J

1200P_0402_50V7K

2
0.01UF_0402_25V7K

2 @ PQ1217B
G
1

- DMN65D8LDW-7_SOT363-6 PR1258
100K_0402_1%

200K_0402_1%

100P_0402_50V8J

4
1

+3.3V_ALW +3.3V_ALW
PC1221

PC1223

PC1224

0_0402_5%
100K_0402_5%
4
1

2
PR1261

PR1262

PC1222

PR1260

PR1265
2

1
2

2
@ @ @ +3.3V_ALW +3.3V_ALW
2

@ @ @ PR1263 PR1264
2

+3.3V_VDD_PIC 100K_0402_5% 100K_0402_5%

2
DMN65D8LW-7_SOT323-3

+3.3V_ALW +3.3V_ALW
@

@ PR1266 (From EC) PT2

1
1

D
0_0402_5% PAD~D AC_DISC# <37,57,58> AC_DISC# <37,57,58>
2 1 2 LPSB_PROTECT#
+3.3V_ALW PR1267 PR1268
PQ1219

G 100K_0402_5% 100K_0402_5%
1

6
S @ PR1269 D D
3

1
@ PR1270 0_0402_5% 2 PQ1220A 2 PQ1222A
@ 10K_0402_5% 1 2 PR1271 G DMN66D0LDW-7_SOT363-6 PR1272 G DMN66D0LDW-7_SOT363-6
EN_PD_HV_2 <27,58>
100K_0402_5% 100K_0402_5%

6
D S D S
2

1
2 2
PQ1221B G PQ1223B G
DMN66D0LDW-7_SOT363-6 DMN66D0LDW-7_SOT363-6

3
D S D S

1
1 2 5 PQ1221A 1 2 5 PQ1223A
<38,58> VBUS1_ECOK <38,58> VBUS2_ECOK
G DMN66D0LDW-7_SOT363-6 G DMN66D0LDW-7_SOT363-6
PR1273 PR1274
0_0402_5% 0_0402_5%
4S S

4
3

3
D D
1 2 5 1 2 5
<26,57> AC1_DISC# <27,57> AC2_DISC#
G PQ1220B G PQ1222B
PR1275 PR1276
0_0402_5% DMN66D0LDW-7_SOT363-6 0_0402_5% DMN66D0LDW-7_SOT363-6
S S

4
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/06/10 Deciphered Date 2015/06/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P51 - PWR_DCIN/BATT CONN/OTP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E112P
Date: Friday, April 22, 2016 Sheet 58 of 59
5 4 3 2 1
 5 4 3 2 1

Version Change List ( P. I. R. List )

Item Page# Title Date Request Owner Issue Solution Rev.
Description Description
D D

1.8VALW/+1.2V/ 2016 New add 1.2V_RUN (From 3.3V_RUN) X00

1 55 1.8V_MEN 02/23 Compal by use power regulator SW ,only for HDMI PS8407 modify power rail PU502, change PR508 from 8.87K to 5.1K
EE request

1.8VALW/+1.2V/ 2016
2 55 1.8V_MEN 02/23 Compal For LPDDR3 power , add +1.8v_MEM modify power rail PU503, change PR515 from 21.5K to 12.7K X00

1.8VALW/+1.2V/ 2016
3 55 1.8V_MEN 02/23 Compal PU501 PG connect to +1.8V_RPIM_PWRGD & modify power rail PU501, pull high to 3.3V and X00
Pull high to 3.3V connect netname +1.8V_PRIM_PWRGD

1.8VALW/+1.2V/ 2016
55 1.8V_MEN 03/01 Compal HW dropped PS8407 solution. Remove 1.2V_RUN (PU502) power rail. X00
4

C C

+1.2V_MEM/ 2016
52 +0.6V_DDR 03/07 Compal remove 1.2V_DDR_PG remove 1.2V_DDR_PG,remove PR201
5 X00

6
1Type-C PD 2016 X00
60 Selector 03/17 Compal to add S4 quick turn off 3/14 by chris add PQ1224 PQ1225 PQ1226 PQ1227

7 1Type-C PD 2016 EMI requiest

60 Selector 03/23 Compal add PR1283 PR1284 X00

B B

10

11

12

13

A A
14

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
PWR P.I.R
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number R ev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 0.3
LA-E112P
Date: Friday, April 22, 2016 Sheet 59 of 59
5 4 3 2 1